From nobody Fri Oct 3 21:42:32 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0BA05299A8E for ; Mon, 25 Aug 2025 08:57:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756112233; cv=none; b=p+MejqlShzTvWnbSecJVsbucUTNub0lzSrkVNUYpZFoWMMhyQ4TKEAHgIVIyCp/LHfeB0hMspzb8s0LgODenwgsrdNmSwWmgj1grUCbpQ2TtUK72WOCuP527iKC+0fV3pJgBGcC1AlciWtXu68tiLZJW2JP7Uq8UM3zOrEbQXSs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756112233; c=relaxed/simple; bh=qZJVzvB3RYpOJBlaQE6hqE/Fp8nZMiJrz+TTlwmiAgM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ung8P3KOeW5AB23zG2pUWTAu6EKNIdGAiHnO4Cpl4DMDtQBarmZA1oQtjqgOEd4dxO4MpRYA6Lpuk99hUTkbXpEJxjjVsij9lxWKPl+26Telh9iL7wdzc33HPVn0BuQtpakhteVrSjrHlkN8vpv0EaKgin+sTj8sQ8cLR+Jk/ZE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=mLv63d/+; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="mLv63d/+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1756112230; bh=qZJVzvB3RYpOJBlaQE6hqE/Fp8nZMiJrz+TTlwmiAgM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=mLv63d/+/8+H3yf17N8H6yqChGhHVHwgC7VK3Q4XO+ioqw01iGN8jef7nujur1mrn JR08cMTTaVdOmADo+7ODNRXC2eNTvDG2iIFZYCDoCRgN5o6wnBGpT1Q1sNGgikXsCW qEMewjB7NYR/J14XXCK8g8h8rU+APjkTRrdnolYjRpfhyk/drWHB1kpHucNTKaQZL0 PhxHiVNgR4cMPHVJUrdHi9RmNZITi77Q1hLz8m4LZ8fRQYnsBsIM5UPDiQpNrhvb+J LRVi36dC252sKCbZkduMWbRtosWI66aO8w7+KLwu4Ik6bPJh8KFuJPd0Ruj3fRm0Qn mujoaySQAtAqQ== Received: from localhost (unknown [82.79.138.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 2A72D17E0523; Mon, 25 Aug 2025 10:57:10 +0200 (CEST) From: Cristian Ciocaltea Date: Mon, 25 Aug 2025 11:56:42 +0300 Subject: [PATCH v3 2/6] drm/bridge: dw-hdmi-qp: Fixup timer base setup Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-rk3588-hdmi-cec-v3-2-95324fb22592@collabora.com> References: <20250825-rk3588-hdmi-cec-v3-0-95324fb22592@collabora.com> In-Reply-To: <20250825-rk3588-hdmi-cec-v3-0-95324fb22592@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Dmitry Baryshkov , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 Currently the TIMER_BASE_CONFIG0 register gets initialized to a fixed value as initially found in vendor driver code supporting the RK3588 SoC. As a matter of fact the value matches the rate of the HDMI TX reference clock, which is roughly 428.57 MHz. However, on RK3576 SoC that rate is slightly lower, i.e. 396.00 MHz, and the incorrect register configuration breaks CEC functionality. Set the timer base according to the actual reference clock rate that shall be provided by the platform driver. While at it, also drop the unnecessary empty lines in dw_hdmi_qp_init_hw(). Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 11 ++++++++--- include/drm/bridge/dw_hdmi_qp.h | 1 + 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm= /bridge/synopsys/dw-hdmi-qp.c index 96455b3bb7b6a3f6ad488d10bc9ba90a1b56e4c8..42a90e0383061dad6c8416af21b= 27db7a3ba6d7d 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c @@ -162,6 +162,7 @@ struct dw_hdmi_qp { void *data; } phy; =20 + unsigned long ref_clk_rate; struct regmap *regm; =20 unsigned long tmds_char_rate; @@ -1223,13 +1224,11 @@ static void dw_hdmi_qp_init_hw(struct dw_hdmi_qp *h= dmi) { dw_hdmi_qp_write(hdmi, 0, MAINUNIT_0_INT_MASK_N); dw_hdmi_qp_write(hdmi, 0, MAINUNIT_1_INT_MASK_N); - dw_hdmi_qp_write(hdmi, 428571429, TIMER_BASE_CONFIG0); + dw_hdmi_qp_write(hdmi, hdmi->ref_clk_rate, TIMER_BASE_CONFIG0); =20 /* Software reset */ dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); - dw_hdmi_qp_write(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0); - dw_hdmi_qp_mod(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0); =20 /* Clear DONE and ERROR interrupts */ @@ -1255,6 +1254,11 @@ struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_d= evice *pdev, return ERR_PTR(-ENODEV); } =20 + if (!plat_data->ref_clk_rate) { + dev_err(dev, "Missing ref_clk rate\n"); + return ERR_PTR(-ENODEV); + } + hdmi =3D devm_drm_bridge_alloc(dev, struct dw_hdmi_qp, bridge, &dw_hdmi_qp_bridge_funcs); if (IS_ERR(hdmi)) @@ -1274,6 +1278,7 @@ struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_de= vice *pdev, =20 hdmi->phy.ops =3D plat_data->phy_ops; hdmi->phy.data =3D plat_data->phy_data; + hdmi->ref_clk_rate =3D plat_data->ref_clk_rate; =20 dw_hdmi_qp_init_hw(hdmi); =20 diff --git a/include/drm/bridge/dw_hdmi_qp.h b/include/drm/bridge/dw_hdmi_q= p.h index b4a9b739734ec7b67013b683fe6017551aa19172..76ecf31301997718604a05f70ce= 9eab8695e26b5 100644 --- a/include/drm/bridge/dw_hdmi_qp.h +++ b/include/drm/bridge/dw_hdmi_qp.h @@ -24,6 +24,7 @@ struct dw_hdmi_qp_plat_data { void *phy_data; int main_irq; int cec_irq; + unsigned long ref_clk_rate; }; =20 struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev, --=20 2.50.1