From nobody Fri Oct 3 21:04:31 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75F1D28C866 for ; Mon, 25 Aug 2025 08:57:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756112233; cv=none; b=DFyNiyb9sBP4kGR7kI/S2frc3+rRR5AyoIFCRZ5Z3oOA5z9Bzdla1RGeeCuhge+XNKWfTmYxw9yZ/Vk8KHxapLIde4VwYgH1QJVWScB4+ljLaL7wkFFM3VyHBF5iQEiQPM0S83cjH40xBuV3dtI+EaX9Cu9XYjDBvbEyL79coQs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756112233; c=relaxed/simple; bh=jzmAGuSUKWkNrxhAkqhlRCnweMgPbjMdhH1sCU3MatM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WH+5InL99hJfhY7OWEwS4zh8ilMc6Vcj0w8OXbvVQ045C7c5YU4R1uF1mWVh5Sspphz1dxAdAK+T7spQR5u5JN939ccQYgsmeeUMyCO6rNuARnFdIrC6TOlKg9Bnji5K4VxMrhexpcCkbgHZ+VxxSqzrbJ9+P00K0qs89bwL/n4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=QTvmPbr5; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="QTvmPbr5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1756112229; bh=jzmAGuSUKWkNrxhAkqhlRCnweMgPbjMdhH1sCU3MatM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=QTvmPbr5xeIJO4CEBlCj9ENxEV55Z2gXlLjeBj57tS75C22sNGirnqijcSmn9bSec wAPS4gz85z1afeIcsRih6RJh8iThstHLrMQJdfJZu3AgLFlD1OjbJ08+A4JP0ONRXs LA53tLXfooY+V3u8ZJyEfvmaWVAmamBVR3w9qFwjYcchhNq4wy9thS6Bn5dBASPLq5 iUu2M8Zgrvb196J8DLYGqV2tkCmU0r7WaZjR/8+vp4ySyl/LTKuW/tQ+fMkmrWJMrc GhGQ1U9Nsl3QiIgi+LzGPeasnCM3gLca5E2ARLB7zbigeH8Krg3pmar4lvrXsfytjJ 9OizHzhCr5PbQ== Received: from localhost (unknown [82.79.138.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 4C78B17E0489; Mon, 25 Aug 2025 10:57:09 +0200 (CEST) From: Cristian Ciocaltea Date: Mon, 25 Aug 2025 11:56:41 +0300 Subject: [PATCH v3 1/6] drm/bridge: dw-hdmi-qp: Add CEC support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-rk3588-hdmi-cec-v3-1-95324fb22592@collabora.com> References: <20250825-rk3588-hdmi-cec-v3-0-95324fb22592@collabora.com> In-Reply-To: <20250825-rk3588-hdmi-cec-v3-0-95324fb22592@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Dmitry Baryshkov , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Algea Cao , Derek Foreman X-Mailer: b4 0.14.2 Add support for the CEC interface of the Synopsys DesignWare HDMI QP TX controller. This is based on the downstream implementation, but rewritten on top of the CEC helpers added recently to the DRM HDMI connector framework. Also note struct dw_hdmi_qp_plat_data has been extended to include the CEC IRQ number to be provided by the platform driver. Co-developed-by: Algea Cao Signed-off-by: Algea Cao Co-developed-by: Derek Foreman Signed-off-by: Derek Foreman Reviewed-by: Dmitry Baryshkov Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/bridge/synopsys/Kconfig | 8 + drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 221 +++++++++++++++++++++++= ++++ drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h | 14 ++ include/drm/bridge/dw_hdmi_qp.h | 1 + 4 files changed, 244 insertions(+) diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig b/drivers/gpu/drm/brid= ge/synopsys/Kconfig index f3ab2f985f8ca9dc1eeac3bda6b4a31d355cd51c..99878f051067e65fa3b97d8132b= e8cfa15980966 100644 --- a/drivers/gpu/drm/bridge/synopsys/Kconfig +++ b/drivers/gpu/drm/bridge/synopsys/Kconfig @@ -54,6 +54,14 @@ config DRM_DW_HDMI_QP select DRM_KMS_HELPER select REGMAP_MMIO =20 +config DRM_DW_HDMI_QP_CEC + bool "Synopsis Designware QP CEC interface" + depends on DRM_DW_HDMI_QP + select DRM_DISPLAY_HDMI_CEC_HELPER + help + Support the CEC interface which is part of the Synopsys + Designware HDMI QP block. + config DRM_DW_MIPI_DSI tristate select DRM_KMS_HELPER diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm= /bridge/synopsys/dw-hdmi-qp.c index 39332c57f2c54296f39e27612544f4fbf923863f..96455b3bb7b6a3f6ad488d10bc9= ba90a1b56e4c8 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c @@ -2,6 +2,7 @@ /* * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd. * Copyright (c) 2024 Collabora Ltd. + * Copyright (c) 2025 Amazon.com, Inc. or its affiliates. * * Author: Algea Cao * Author: Cristian Ciocaltea @@ -18,6 +19,7 @@ =20 #include #include +#include #include #include #include @@ -26,6 +28,8 @@ #include #include =20 +#include + #include =20 #include "dw-hdmi-qp.h" @@ -131,12 +135,28 @@ struct dw_hdmi_qp_i2c { bool is_segment; }; =20 +#ifdef CONFIG_DRM_DW_HDMI_QP_CEC +struct dw_hdmi_qp_cec { + struct drm_connector *connector; + int irq; + u32 addresses; + struct cec_msg rx_msg; + u8 tx_status; + bool tx_done; + bool rx_done; +}; +#endif + struct dw_hdmi_qp { struct drm_bridge bridge; =20 struct device *dev; struct dw_hdmi_qp_i2c *i2c; =20 +#ifdef CONFIG_DRM_DW_HDMI_QP_CEC + struct dw_hdmi_qp_cec *cec; +#endif + struct { const struct dw_hdmi_qp_phy_ops *ops; void *data; @@ -965,6 +985,191 @@ static int dw_hdmi_qp_bridge_write_infoframe(struct d= rm_bridge *bridge, } } =20 +#ifdef CONFIG_DRM_DW_HDMI_QP_CEC +static irqreturn_t dw_hdmi_qp_cec_hardirq(int irq, void *dev_id) +{ + struct dw_hdmi_qp *hdmi =3D dev_id; + struct dw_hdmi_qp_cec *cec =3D hdmi->cec; + irqreturn_t ret =3D IRQ_HANDLED; + u32 stat; + + stat =3D dw_hdmi_qp_read(hdmi, CEC_INT_STATUS); + if (stat =3D=3D 0) + return IRQ_NONE; + + dw_hdmi_qp_write(hdmi, stat, CEC_INT_CLEAR); + + if (stat & CEC_STAT_LINE_ERR) { + cec->tx_status =3D CEC_TX_STATUS_ERROR; + cec->tx_done =3D true; + ret =3D IRQ_WAKE_THREAD; + } else if (stat & CEC_STAT_DONE) { + cec->tx_status =3D CEC_TX_STATUS_OK; + cec->tx_done =3D true; + ret =3D IRQ_WAKE_THREAD; + } else if (stat & CEC_STAT_NACK) { + cec->tx_status =3D CEC_TX_STATUS_NACK; + cec->tx_done =3D true; + ret =3D IRQ_WAKE_THREAD; + } + + if (stat & CEC_STAT_EOM) { + unsigned int len, i, val; + + val =3D dw_hdmi_qp_read(hdmi, CEC_RX_COUNT_STATUS); + len =3D (val & 0xf) + 1; + + if (len > sizeof(cec->rx_msg.msg)) + len =3D sizeof(cec->rx_msg.msg); + + for (i =3D 0; i < 4; i++) { + val =3D dw_hdmi_qp_read(hdmi, CEC_RX_DATA3_0 + i * 4); + cec->rx_msg.msg[i * 4] =3D val & 0xff; + cec->rx_msg.msg[i * 4 + 1] =3D (val >> 8) & 0xff; + cec->rx_msg.msg[i * 4 + 2] =3D (val >> 16) & 0xff; + cec->rx_msg.msg[i * 4 + 3] =3D (val >> 24) & 0xff; + } + + dw_hdmi_qp_write(hdmi, 1, CEC_LOCK_CONTROL); + + cec->rx_msg.len =3D len; + cec->rx_done =3D true; + + ret =3D IRQ_WAKE_THREAD; + } + + return ret; +} + +static irqreturn_t dw_hdmi_qp_cec_thread(int irq, void *dev_id) +{ + struct dw_hdmi_qp *hdmi =3D dev_id; + struct dw_hdmi_qp_cec *cec =3D hdmi->cec; + + if (cec->tx_done) { + cec->tx_done =3D false; + drm_connector_hdmi_cec_transmit_attempt_done(cec->connector, + cec->tx_status); + } + + if (cec->rx_done) { + cec->rx_done =3D false; + drm_connector_hdmi_cec_received_msg(cec->connector, &cec->rx_msg); + } + + return IRQ_HANDLED; +} + +static int dw_hdmi_qp_cec_init(struct drm_bridge *bridge, + struct drm_connector *connector) +{ + struct dw_hdmi_qp *hdmi =3D dw_hdmi_qp_from_bridge(bridge); + struct dw_hdmi_qp_cec *cec =3D hdmi->cec; + int ret; + + if (cec->irq < 0) { + dev_err(hdmi->dev, "Invalid cec irq: %d\n", cec->irq); + return -EINVAL; + } + + cec->connector =3D connector; + + dw_hdmi_qp_write(hdmi, 0, CEC_TX_COUNT); + dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR); + dw_hdmi_qp_write(hdmi, 0, CEC_INT_MASK_N); + + ret =3D devm_request_threaded_irq(hdmi->dev, cec->irq, + dw_hdmi_qp_cec_hardirq, + dw_hdmi_qp_cec_thread, IRQF_SHARED, + dev_name(hdmi->dev), hdmi); + if (ret < 0) { + dev_err(hdmi->dev, "Request cec irq thread failed: %d\n", ret); + return ret; + } + + return 0; +} + +static int dw_hdmi_qp_cec_log_addr(struct drm_bridge *bridge, u8 logical_a= ddr) +{ + struct dw_hdmi_qp *hdmi =3D dw_hdmi_qp_from_bridge(bridge); + struct dw_hdmi_qp_cec *cec =3D hdmi->cec; + + if (logical_addr =3D=3D CEC_LOG_ADDR_INVALID) + cec->addresses =3D 0; + else + cec->addresses |=3D BIT(logical_addr) | CEC_ADDR_BROADCAST; + + dw_hdmi_qp_write(hdmi, cec->addresses, CEC_ADDR); + + return 0; +} + +static int dw_hdmi_qp_cec_enable(struct drm_bridge *bridge, bool enable) +{ + struct dw_hdmi_qp *hdmi =3D dw_hdmi_qp_from_bridge(bridge); + unsigned int irqs; + u32 swdisable; + + if (!enable) { + dw_hdmi_qp_write(hdmi, 0, CEC_INT_MASK_N); + dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR); + + swdisable =3D dw_hdmi_qp_read(hdmi, GLOBAL_SWDISABLE); + swdisable =3D swdisable | CEC_SWDISABLE; + dw_hdmi_qp_write(hdmi, swdisable, GLOBAL_SWDISABLE); + } else { + swdisable =3D dw_hdmi_qp_read(hdmi, GLOBAL_SWDISABLE); + swdisable =3D swdisable & ~CEC_SWDISABLE; + dw_hdmi_qp_write(hdmi, swdisable, GLOBAL_SWDISABLE); + + dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR); + dw_hdmi_qp_write(hdmi, 1, CEC_LOCK_CONTROL); + + dw_hdmi_qp_cec_log_addr(bridge, CEC_LOG_ADDR_INVALID); + + irqs =3D CEC_STAT_LINE_ERR | CEC_STAT_NACK | CEC_STAT_EOM | + CEC_STAT_DONE; + dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR); + dw_hdmi_qp_write(hdmi, irqs, CEC_INT_MASK_N); + } + + return 0; +} + +static int dw_hdmi_qp_cec_transmit(struct drm_bridge *bridge, u8 attempts, + u32 signal_free_time, struct cec_msg *msg) +{ + struct dw_hdmi_qp *hdmi =3D dw_hdmi_qp_from_bridge(bridge); + unsigned int i; + u32 val; + + for (i =3D 0; i < msg->len; i++) { + if (!(i % 4)) + val =3D msg->msg[i]; + if ((i % 4) =3D=3D 1) + val |=3D msg->msg[i] << 8; + if ((i % 4) =3D=3D 2) + val |=3D msg->msg[i] << 16; + if ((i % 4) =3D=3D 3) + val |=3D msg->msg[i] << 24; + + if (i =3D=3D (msg->len - 1) || (i % 4) =3D=3D 3) + dw_hdmi_qp_write(hdmi, val, CEC_TX_DATA3_0 + (i / 4) * 4); + } + + dw_hdmi_qp_write(hdmi, msg->len - 1, CEC_TX_COUNT); + dw_hdmi_qp_write(hdmi, CEC_CTRL_START, CEC_TX_CONTROL); + + return 0; +} +#else +#define dw_hdmi_qp_cec_init NULL +#define dw_hdmi_qp_cec_enable NULL +#define dw_hdmi_qp_cec_log_addr NULL +#define dw_hdmi_qp_cec_transmit NULL +#endif /* CONFIG_DRM_DW_HDMI_QP_CEC */ + static const struct drm_bridge_funcs dw_hdmi_qp_bridge_funcs =3D { .atomic_duplicate_state =3D drm_atomic_helper_bridge_duplicate_state, .atomic_destroy_state =3D drm_atomic_helper_bridge_destroy_state, @@ -979,6 +1184,10 @@ static const struct drm_bridge_funcs dw_hdmi_qp_bridg= e_funcs =3D { .hdmi_audio_startup =3D dw_hdmi_qp_audio_enable, .hdmi_audio_shutdown =3D dw_hdmi_qp_audio_disable, .hdmi_audio_prepare =3D dw_hdmi_qp_audio_prepare, + .hdmi_cec_init =3D dw_hdmi_qp_cec_init, + .hdmi_cec_enable =3D dw_hdmi_qp_cec_enable, + .hdmi_cec_log_addr =3D dw_hdmi_qp_cec_log_addr, + .hdmi_cec_transmit =3D dw_hdmi_qp_cec_transmit, }; =20 static irqreturn_t dw_hdmi_qp_main_hardirq(int irq, void *dev_id) @@ -1093,6 +1302,18 @@ struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_d= evice *pdev, hdmi->bridge.hdmi_audio_dev =3D dev; hdmi->bridge.hdmi_audio_dai_port =3D 1; =20 +#ifdef CONFIG_DRM_DW_HDMI_QP_CEC + hdmi->bridge.ops |=3D DRM_BRIDGE_OP_HDMI_CEC_ADAPTER; + hdmi->bridge.hdmi_cec_dev =3D dev; + hdmi->bridge.hdmi_cec_adapter_name =3D dev_name(dev); + + hdmi->cec =3D devm_kzalloc(hdmi->dev, sizeof(*hdmi->cec), GFP_KERNEL); + if (!hdmi->cec) + return ERR_PTR(-ENOMEM); + + hdmi->cec->irq =3D plat_data->cec_irq; +#endif + ret =3D devm_drm_bridge_add(dev, &hdmi->bridge); if (ret) return ERR_PTR(ret); diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h b/drivers/gpu/drm= /bridge/synopsys/dw-hdmi-qp.h index 72987e6c468928f2b998099697a6f32726411557..91a15f82e32acc32eef58f11ec5= ca958337ebb9a 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.h @@ -488,9 +488,23 @@ #define AUDPKT_VBIT_OVR0 0xf24 /* CEC Registers */ #define CEC_TX_CONTROL 0x1000 +#define CEC_CTRL_CLEAR BIT(0) +#define CEC_CTRL_START BIT(0) #define CEC_STATUS 0x1004 +#define CEC_STAT_DONE BIT(0) +#define CEC_STAT_NACK BIT(1) +#define CEC_STAT_ARBLOST BIT(2) +#define CEC_STAT_LINE_ERR BIT(3) +#define CEC_STAT_RETRANS_FAIL BIT(4) +#define CEC_STAT_DISCARD BIT(5) +#define CEC_STAT_TX_BUSY BIT(8) +#define CEC_STAT_RX_BUSY BIT(9) +#define CEC_STAT_DRIVE_ERR BIT(10) +#define CEC_STAT_EOM BIT(11) +#define CEC_STAT_NOTIFY_ERR BIT(12) #define CEC_CONFIG 0x1008 #define CEC_ADDR 0x100c +#define CEC_ADDR_BROADCAST BIT(15) #define CEC_TX_COUNT 0x1020 #define CEC_TX_DATA3_0 0x1024 #define CEC_TX_DATA7_4 0x1028 diff --git a/include/drm/bridge/dw_hdmi_qp.h b/include/drm/bridge/dw_hdmi_q= p.h index e9be6d507ad9cdc55f5c7d6d3ef37eba41f1ce74..b4a9b739734ec7b67013b683fe6= 017551aa19172 100644 --- a/include/drm/bridge/dw_hdmi_qp.h +++ b/include/drm/bridge/dw_hdmi_qp.h @@ -23,6 +23,7 @@ struct dw_hdmi_qp_plat_data { const struct dw_hdmi_qp_phy_ops *phy_ops; void *phy_data; int main_irq; + int cec_irq; }; =20 struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev, --=20 2.50.1 From nobody Fri Oct 3 21:04:31 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0BA05299A8E for ; Mon, 25 Aug 2025 08:57:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756112233; cv=none; b=p+MejqlShzTvWnbSecJVsbucUTNub0lzSrkVNUYpZFoWMMhyQ4TKEAHgIVIyCp/LHfeB0hMspzb8s0LgODenwgsrdNmSwWmgj1grUCbpQ2TtUK72WOCuP527iKC+0fV3pJgBGcC1AlciWtXu68tiLZJW2JP7Uq8UM3zOrEbQXSs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756112233; c=relaxed/simple; bh=qZJVzvB3RYpOJBlaQE6hqE/Fp8nZMiJrz+TTlwmiAgM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ung8P3KOeW5AB23zG2pUWTAu6EKNIdGAiHnO4Cpl4DMDtQBarmZA1oQtjqgOEd4dxO4MpRYA6Lpuk99hUTkbXpEJxjjVsij9lxWKPl+26Telh9iL7wdzc33HPVn0BuQtpakhteVrSjrHlkN8vpv0EaKgin+sTj8sQ8cLR+Jk/ZE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=mLv63d/+; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="mLv63d/+" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1756112230; bh=qZJVzvB3RYpOJBlaQE6hqE/Fp8nZMiJrz+TTlwmiAgM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=mLv63d/+/8+H3yf17N8H6yqChGhHVHwgC7VK3Q4XO+ioqw01iGN8jef7nujur1mrn JR08cMTTaVdOmADo+7ODNRXC2eNTvDG2iIFZYCDoCRgN5o6wnBGpT1Q1sNGgikXsCW qEMewjB7NYR/J14XXCK8g8h8rU+APjkTRrdnolYjRpfhyk/drWHB1kpHucNTKaQZL0 PhxHiVNgR4cMPHVJUrdHi9RmNZITi77Q1hLz8m4LZ8fRQYnsBsIM5UPDiQpNrhvb+J LRVi36dC252sKCbZkduMWbRtosWI66aO8w7+KLwu4Ik6bPJh8KFuJPd0Ruj3fRm0Qn mujoaySQAtAqQ== Received: from localhost (unknown [82.79.138.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 2A72D17E0523; Mon, 25 Aug 2025 10:57:10 +0200 (CEST) From: Cristian Ciocaltea Date: Mon, 25 Aug 2025 11:56:42 +0300 Subject: [PATCH v3 2/6] drm/bridge: dw-hdmi-qp: Fixup timer base setup Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-rk3588-hdmi-cec-v3-2-95324fb22592@collabora.com> References: <20250825-rk3588-hdmi-cec-v3-0-95324fb22592@collabora.com> In-Reply-To: <20250825-rk3588-hdmi-cec-v3-0-95324fb22592@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Dmitry Baryshkov , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 Currently the TIMER_BASE_CONFIG0 register gets initialized to a fixed value as initially found in vendor driver code supporting the RK3588 SoC. As a matter of fact the value matches the rate of the HDMI TX reference clock, which is roughly 428.57 MHz. However, on RK3576 SoC that rate is slightly lower, i.e. 396.00 MHz, and the incorrect register configuration breaks CEC functionality. Set the timer base according to the actual reference clock rate that shall be provided by the platform driver. While at it, also drop the unnecessary empty lines in dw_hdmi_qp_init_hw(). Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c | 11 ++++++++--- include/drm/bridge/dw_hdmi_qp.h | 1 + 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c b/drivers/gpu/drm= /bridge/synopsys/dw-hdmi-qp.c index 96455b3bb7b6a3f6ad488d10bc9ba90a1b56e4c8..42a90e0383061dad6c8416af21b= 27db7a3ba6d7d 100644 --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi-qp.c @@ -162,6 +162,7 @@ struct dw_hdmi_qp { void *data; } phy; =20 + unsigned long ref_clk_rate; struct regmap *regm; =20 unsigned long tmds_char_rate; @@ -1223,13 +1224,11 @@ static void dw_hdmi_qp_init_hw(struct dw_hdmi_qp *h= dmi) { dw_hdmi_qp_write(hdmi, 0, MAINUNIT_0_INT_MASK_N); dw_hdmi_qp_write(hdmi, 0, MAINUNIT_1_INT_MASK_N); - dw_hdmi_qp_write(hdmi, 428571429, TIMER_BASE_CONFIG0); + dw_hdmi_qp_write(hdmi, hdmi->ref_clk_rate, TIMER_BASE_CONFIG0); =20 /* Software reset */ dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); - dw_hdmi_qp_write(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0); - dw_hdmi_qp_mod(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0); =20 /* Clear DONE and ERROR interrupts */ @@ -1255,6 +1254,11 @@ struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_d= evice *pdev, return ERR_PTR(-ENODEV); } =20 + if (!plat_data->ref_clk_rate) { + dev_err(dev, "Missing ref_clk rate\n"); + return ERR_PTR(-ENODEV); + } + hdmi =3D devm_drm_bridge_alloc(dev, struct dw_hdmi_qp, bridge, &dw_hdmi_qp_bridge_funcs); if (IS_ERR(hdmi)) @@ -1274,6 +1278,7 @@ struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_de= vice *pdev, =20 hdmi->phy.ops =3D plat_data->phy_ops; hdmi->phy.data =3D plat_data->phy_data; + hdmi->ref_clk_rate =3D plat_data->ref_clk_rate; =20 dw_hdmi_qp_init_hw(hdmi); =20 diff --git a/include/drm/bridge/dw_hdmi_qp.h b/include/drm/bridge/dw_hdmi_q= p.h index b4a9b739734ec7b67013b683fe6017551aa19172..76ecf31301997718604a05f70ce= 9eab8695e26b5 100644 --- a/include/drm/bridge/dw_hdmi_qp.h +++ b/include/drm/bridge/dw_hdmi_qp.h @@ -24,6 +24,7 @@ struct dw_hdmi_qp_plat_data { void *phy_data; int main_irq; int cec_irq; + unsigned long ref_clk_rate; }; =20 struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev, --=20 2.50.1 From nobody Fri Oct 3 21:04:31 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D064829E11B for ; Mon, 25 Aug 2025 08:57:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756112234; cv=none; b=ZNcRaoUCrkD/K5iGG8T7s5tVeSQkZGckYk7EIyJXrvKSg13e88cCbneP2oysd8bhnTqUY+e1RxXoCneruvjOCQXe0SJ83OHnk2MHeknI1YgsbApophcL2QMJc41/tr0XvXISMizF/UfHyU9blSo2aKWWPODvjmeur58V+MTBw+8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756112234; c=relaxed/simple; bh=WIKih/lv5pN3+A825AnO1OKYgzDPIJjlzykTE0eLhGA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=akgdb0NnJrS3fuue6fjRKVh7v+90l4qT37jj3Y/qL5Qbxv3h7QfYq5c5pXPbs2cP69IdAVKE2oLDJ6TC03m3pmeXT9hU3+QNr9kPQIl5dYhLointwoxuD4ocqXbr6zlT9UOFIy38qtQMB9eZQG7FclB8dCVmvTjlQ3J81TgK1J0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=N4iqcTjB; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="N4iqcTjB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1756112231; bh=WIKih/lv5pN3+A825AnO1OKYgzDPIJjlzykTE0eLhGA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=N4iqcTjB0LjkPpxBf3Vis8ao9PAbSyEXaP5kCIZqa1j/dINPD+bc8AB18qrFyd/Qw tGz2GEIEbiexEhin6paMid2dXM6ifWn4BiFPvnddIpuL4spnizncZHJl1HKhas+ZXo 5NPOfArbfyrQRm6i23p7FoL3Iu6gLihNHHguIbYfXJS0JcpDbrndJzhBpSjGogYOcY fKTUDTHVrCrhB8dqYWefdH5ElDWvGZjGMKfZRUQxqUxvNx6TqQjvmAlBMfCs3BdevU GASEs6qBL0l8/i9SNUF0FzJDn5a2cduiuRVtZA8ulyodsMr6I6nLsH5QpCcLkcexDr ZyAgHkYCdsa8w== Received: from localhost (unknown [82.79.138.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id E899C17E056F; Mon, 25 Aug 2025 10:57:10 +0200 (CEST) From: Cristian Ciocaltea Date: Mon, 25 Aug 2025 11:56:43 +0300 Subject: [PATCH v3 3/6] drm/rockchip: dw_hdmi_qp: Improve error handling with dev_err_probe() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-rk3588-hdmi-cec-v3-3-95324fb22592@collabora.com> References: <20250825-rk3588-hdmi-cec-v3-0-95324fb22592@collabora.com> In-Reply-To: <20250825-rk3588-hdmi-cec-v3-0-95324fb22592@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Dmitry Baryshkov , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 The error handling in dw_hdmi_qp_rockchip_bind() is quite inconsistent, i.e. in some cases the error code is not included in the message, while in some other cases there is no check for -EPROBE_DEFER. Since this is part of the probe path, address the aforementioned issues by switching to dev_err_probe(), which also reduces the code a bit. Signed-off-by: Cristian Ciocaltea Reviewed-by: Daniel Stone --- drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 62 ++++++++++------------= ---- 1 file changed, 24 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/d= rm/rockchip/dw_hdmi_qp-rockchip.c index 7d531b6f4c098c6c548788dad487ce4613a2f32b..4e7794aa2dded4c124963eaa7f5= 158bde9bbbdb6 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -457,10 +457,8 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev= , struct device *master, return -ENODEV; =20 if (!cfg->ctrl_ops || !cfg->ctrl_ops->io_init || - !cfg->ctrl_ops->irq_callback || !cfg->ctrl_ops->hardirq_callback) { - dev_err(dev, "Missing platform ctrl ops\n"); - return -ENODEV; - } + !cfg->ctrl_ops->irq_callback || !cfg->ctrl_ops->hardirq_callback) + return dev_err_probe(dev, -ENODEV, "Missing platform ctrl ops\n"); =20 hdmi->ctrl_ops =3D cfg->ctrl_ops; hdmi->dev =3D &pdev->dev; @@ -473,10 +471,9 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev= , struct device *master, break; } } - if (hdmi->port_id < 0) { - dev_err(hdmi->dev, "Failed to match HDMI port ID\n"); - return hdmi->port_id; - } + if (hdmi->port_id < 0) + return dev_err_probe(hdmi->dev, hdmi->port_id, + "Failed to match HDMI port ID\n"); =20 plat_data.phy_ops =3D cfg->phy_ops; plat_data.phy_data =3D hdmi; @@ -497,39 +494,30 @@ static int dw_hdmi_qp_rockchip_bind(struct device *de= v, struct device *master, =20 hdmi->regmap =3D syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); - if (IS_ERR(hdmi->regmap)) { - dev_err(hdmi->dev, "Unable to get rockchip,grf\n"); - return PTR_ERR(hdmi->regmap); - } + if (IS_ERR(hdmi->regmap)) + return dev_err_probe(hdmi->dev, PTR_ERR(hdmi->regmap), + "Unable to get rockchip,grf\n"); =20 hdmi->vo_regmap =3D syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vo-grf"); - if (IS_ERR(hdmi->vo_regmap)) { - dev_err(hdmi->dev, "Unable to get rockchip,vo-grf\n"); - return PTR_ERR(hdmi->vo_regmap); - } + if (IS_ERR(hdmi->vo_regmap)) + return dev_err_probe(hdmi->dev, PTR_ERR(hdmi->vo_regmap), + "Unable to get rockchip,vo-grf\n"); =20 ret =3D devm_clk_bulk_get_all_enabled(hdmi->dev, &clks); - if (ret < 0) { - dev_err(hdmi->dev, "Failed to get clocks: %d\n", ret); - return ret; - } + if (ret < 0) + return dev_err_probe(hdmi->dev, ret, "Failed to get clocks\n"); =20 hdmi->enable_gpio =3D devm_gpiod_get_optional(hdmi->dev, "enable", GPIOD_OUT_HIGH); - if (IS_ERR(hdmi->enable_gpio)) { - ret =3D PTR_ERR(hdmi->enable_gpio); - dev_err(hdmi->dev, "Failed to request enable GPIO: %d\n", ret); - return ret; - } + if (IS_ERR(hdmi->enable_gpio)) + return dev_err_probe(hdmi->dev, PTR_ERR(hdmi->enable_gpio), + "Failed to request enable GPIO\n"); =20 hdmi->phy =3D devm_of_phy_get_by_index(dev, dev->of_node, 0); - if (IS_ERR(hdmi->phy)) { - ret =3D PTR_ERR(hdmi->phy); - if (ret !=3D -EPROBE_DEFER) - dev_err(hdmi->dev, "failed to get phy: %d\n", ret); - return ret; - } + if (IS_ERR(hdmi->phy)) + return dev_err_probe(hdmi->dev, PTR_ERR(hdmi->phy), + "Failed to get phy\n"); =20 cfg->ctrl_ops->io_init(hdmi); =20 @@ -558,17 +546,15 @@ static int dw_hdmi_qp_rockchip_bind(struct device *de= v, struct device *master, =20 hdmi->hdmi =3D dw_hdmi_qp_bind(pdev, encoder, &plat_data); if (IS_ERR(hdmi->hdmi)) { - ret =3D PTR_ERR(hdmi->hdmi); drm_encoder_cleanup(encoder); - return ret; + return dev_err_probe(hdmi->dev, PTR_ERR(hdmi->hdmi), + "Failed to bind dw-hdmi-qp"); } =20 connector =3D drm_bridge_connector_init(drm, encoder); - if (IS_ERR(connector)) { - ret =3D PTR_ERR(connector); - dev_err(hdmi->dev, "failed to init bridge connector: %d\n", ret); - return ret; - } + if (IS_ERR(connector)) + return dev_err_probe(hdmi->dev, PTR_ERR(connector), + "Failed to init bridge connector\n"); =20 return drm_connector_attach_encoder(connector, encoder); } --=20 2.50.1 From nobody Fri Oct 3 21:04:31 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 77EAD2BDC02 for ; Mon, 25 Aug 2025 08:57:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756112235; cv=none; b=FiSzifVKa5osQxg10O9IYCxgFZjmfz3Xst3HK3tOj8DY4Rnu/Pow5TyRIDXlRouAgu+dj1Tboy24GFC0n5ulNYhXac84RdmKmq08IbdGNIJsoShKHiLIdgo5big/0lC5vpyj9051DMVBi4GfDpzHE9tXWboEkFmrlVPfBug9H4A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756112235; c=relaxed/simple; bh=Dn79h63zUtROM5GLEyGgxHXxWqkWpVUrrxCb6cn+d5M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=a2+NuDBaZ/nY1AXv2dgLtaX1r850XMIfoq4ryvhFEnVPSWY3Bj3Y5lB0IL5IOQ8Ic11e2c1J8g3Pal/CZj0tb/YyQDuNqrwBr8S0xVNJ2Q7uqY76loeoI3G1BpyuMBrCCZJUgbc29sr8ax3rN/pJ9OhPYIlNfPYnuyl1Vb6YzVM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=QsQPQlTW; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="QsQPQlTW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1756112231; bh=Dn79h63zUtROM5GLEyGgxHXxWqkWpVUrrxCb6cn+d5M=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=QsQPQlTWB1XrFKi2B3Oc7vbdrYQHWJ9UwkUTgDSdXi58n/Ne29T7Yk6j+/Kz9IwyT kwVwgxueYk4AM2fHXB9DRVDx/ho1bw6KoDZaLTZHSXqUB+0Wi4Or6mqDQZLcC9+N8q J9JLqQM4CltrPjemu1h/V292ihohJxiWexFFFCuJRbe2sNZXjD8S2u1fXsQpfGYupf jjMVPLzewH9kAQSrhiEDBHGWH4F+OWD7P6zCqAK6RnDWjJ6x4WuA1r6L0TNRcEVSkm qtZcXmDYngKjbgOGo3qcz/lcexSqZoTTgRbg5P/Pi626Q5E7TxKlwHJ5BVNh04CM1J UM3hM8SV+g0VQ== Received: from localhost (unknown [82.79.138.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id A8DEC17E0578; Mon, 25 Aug 2025 10:57:11 +0200 (CEST) From: Cristian Ciocaltea Date: Mon, 25 Aug 2025 11:56:44 +0300 Subject: [PATCH v3 4/6] drm/rockchip: dw_hdmi_qp: Provide CEC IRQ in dw_hdmi_qp_plat_data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-rk3588-hdmi-cec-v3-4-95324fb22592@collabora.com> References: <20250825-rk3588-hdmi-cec-v3-0-95324fb22592@collabora.com> In-Reply-To: <20250825-rk3588-hdmi-cec-v3-0-95324fb22592@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Dmitry Baryshkov , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 In order to support the CEC interface of the DesignWare HDMI QP IP block, setup platform data to include the required IRQ number. Signed-off-by: Cristian Ciocaltea Reviewed-by: Daniel Stone --- drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/d= rm/rockchip/dw_hdmi_qp-rockchip.c index 4e7794aa2dded4c124963eaa7f5158bde9bbbdb6..39b46327afd8e4753d96962fad6= 6792d22b33402 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -527,6 +527,10 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev= , struct device *master, if (plat_data.main_irq < 0) return plat_data.main_irq; =20 + plat_data.cec_irq =3D platform_get_irq_byname(pdev, "cec"); + if (plat_data.cec_irq < 0) + return plat_data.cec_irq; + irq =3D platform_get_irq_byname(pdev, "hpd"); if (irq < 0) return irq; --=20 2.50.1 From nobody Fri Oct 3 21:04:31 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F7352BDC2F for ; Mon, 25 Aug 2025 08:57:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756112236; cv=none; b=EytQfBPQRDNc/Tkn96N+F7a+ABlr+kRwBLuhrgODWguC04KZP3E9b+p8Rlevg89HbvWJfI1H61pdkATlmnVbx9SfyjhsRk+nE1r9wSIhF/1kO3l7phHtrVEkaM420zjUbTp2E57HRUO//hoDZKD2co7rvf3FJvNoEDAfHnhJfwY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756112236; c=relaxed/simple; bh=7+Og7rUGyFk1HcTP8p4Uyc/PYhGejFb5kkEHeMTwBtE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=es57SdwQfeDSdmJF10EZsre0KTQtEii6JzjJ+OCTuu53+ivt/B72stlUPlFCV2oUvRIlzK7IQ5/+VNIK746KoBzf4r5NGfwPX4U0oMiUOYkhd6L9lw1/nNnY5Ha0yarrxcfbg0hddbqaIXiojPzuGeaJLVr2iKkf+feFeF3htU4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=e8t1tZDP; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="e8t1tZDP" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1756112232; bh=7+Og7rUGyFk1HcTP8p4Uyc/PYhGejFb5kkEHeMTwBtE=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=e8t1tZDPcuW161VQWs4w0ue0FAugHx845eecL9ak/QF7jzENLXTW2i1NZ1kuPpOo3 QureLvkUvzB5b7fxs2ahRl3275k+M7fu/ByWkA3i0FVS58OFRshrBmv9Xx+8s1dZQ2 tvq8nGYXON2E0muImZxp1q+NkjOcH07rX9DExONsKx1coznAInXe1YJQv/pVBIc4aQ IUjjFdpj0HyPT0oUs9J7q2j5WcDmbe6KhrdwzYcilOPy722smVYgGYhze7hL06WdIj A+hj7gYWCleSVtkdIvrRVwRDuxfHrKY9g7uPolB7re9Kz5g1YPbNednZJWezpx8sQG 7lWCoUvLQKTcg== Received: from localhost (unknown [82.79.138.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 7752817E059E; Mon, 25 Aug 2025 10:57:12 +0200 (CEST) From: Cristian Ciocaltea Date: Mon, 25 Aug 2025 11:56:45 +0300 Subject: [PATCH v3 5/6] drm/rockchip: dw_hdmi_qp: Provide ref clock rate in dw_hdmi_qp_plat_data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-rk3588-hdmi-cec-v3-5-95324fb22592@collabora.com> References: <20250825-rk3588-hdmi-cec-v3-0-95324fb22592@collabora.com> In-Reply-To: <20250825-rk3588-hdmi-cec-v3-0-95324fb22592@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Dmitry Baryshkov , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 In order to support correct initialization of the timer base in the HDMI QP IP block, setup platform data to include the required reference clock rate. While at it, ensure plat_data is zero-initialized in dw_hdmi_qp_rockchip_bind(). Signed-off-by: Cristian Ciocaltea Reviewed-by: Daniel Stone --- drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/d= rm/rockchip/dw_hdmi_qp-rockchip.c index 39b46327afd8e4753d96962fad66792d22b33402..5280383febe25cf579c306ec164= 2557600595e58 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -431,14 +431,15 @@ static int dw_hdmi_qp_rockchip_bind(struct device *de= v, struct device *master, void *data) { struct platform_device *pdev =3D to_platform_device(dev); + struct dw_hdmi_qp_plat_data plat_data =3D {}; const struct rockchip_hdmi_qp_cfg *cfg; - struct dw_hdmi_qp_plat_data plat_data; struct drm_device *drm =3D data; struct drm_connector *connector; struct drm_encoder *encoder; struct rockchip_hdmi_qp *hdmi; struct resource *res; struct clk_bulk_data *clks; + struct clk *ref_clk; int ret, irq, i; =20 if (!pdev->dev.of_node) @@ -508,6 +509,14 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev= , struct device *master, if (ret < 0) return dev_err_probe(hdmi->dev, ret, "Failed to get clocks\n"); =20 + ref_clk =3D clk_get(hdmi->dev, "ref"); + if (IS_ERR(ref_clk)) + return dev_err_probe(hdmi->dev, PTR_ERR(ref_clk), + "Failed to get ref clock\n"); + + plat_data.ref_clk_rate =3D clk_get_rate(ref_clk); + clk_put(ref_clk); + hdmi->enable_gpio =3D devm_gpiod_get_optional(hdmi->dev, "enable", GPIOD_OUT_HIGH); if (IS_ERR(hdmi->enable_gpio)) --=20 2.50.1 From nobody Fri Oct 3 21:04:31 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 239F42BE051 for ; Mon, 25 Aug 2025 08:57:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756112236; cv=none; b=ZHisOoy+s0BZVWExwCBC87XqC0OYIRFcg6IyD6ItLvaSYVH979wXJjlvE8pXjCnp08wnKncWrTzWupjzVYj7ixpNjpKqCiV3JKYrepLVKNbEzOV9TW1yegq7PlZ0YwrJ3j51pxwjUIm7XNqax5QL9zvt2OOFIlxSbV/vkEAnTQs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756112236; c=relaxed/simple; bh=oAA+CT+px2mYa4L1i6V3uoLfahqbm3emYiVzADVvBxA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=V0chMr1gaejNmXw5/x7ONAkxq30hpSkko54lCfJwmvdt4zdbuctDTxfCZh+xP3WgYmmBCkmEgIlQLbzZ/8kBmkSCZ8gbNBHUcpmNXMnMFZ5fhdALV6sPmgfftkbyQ3IT7cILZF/1eGiqtBz0GYdhtu0eMlfmvU/5kTekdNdDV7A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=AEGBn9W5; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="AEGBn9W5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1756112233; bh=oAA+CT+px2mYa4L1i6V3uoLfahqbm3emYiVzADVvBxA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=AEGBn9W5w/Fk012fJNDdhwflF05mz03s9E2oTVMNXywCVseIvtjxmrxf2jqDSpAlR uCa7anbistRiH1HlvsIXBI5REPHMZa2uQP7QUjSN8tDpSAveY6nMoM7PRur2naEnPH xAidZOD2mdTt1y1c7iXJF7hf6TbY6YoTREUa/u9GP9c4llMLgq1WjfDqmHt6EvxL5V 4mC+a7L9LIqs/aIt8lt33Uw/icibgYKAFbUfBTkw8fVXYFiWTTGMZGNs9upePV5Znv VOd8SKJya6/T+L1kBzIQVvKZU3K8WVRKTc8PP/7WnBpBNxDC+xF2mfZIv8l4Ip6rU1 YVs8CxZrWvVAQ== Received: from localhost (unknown [82.79.138.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 4780517E0478; Mon, 25 Aug 2025 10:57:13 +0200 (CEST) From: Cristian Ciocaltea Date: Mon, 25 Aug 2025 11:56:46 +0300 Subject: [PATCH v3 6/6] arm64: defconfig: Enable DW HDMI QP CEC support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-rk3588-hdmi-cec-v3-6-95324fb22592@collabora.com> References: <20250825-rk3588-hdmi-cec-v3-0-95324fb22592@collabora.com> In-Reply-To: <20250825-rk3588-hdmi-cec-v3-0-95324fb22592@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Dmitry Baryshkov , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Catalin Marinas , Will Deacon Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 Enable support for the CEC interface of the Synopsys DesignWare HDMI QP IP block. This is used by all boards based on RK3588 & RK3576 SoCs. Signed-off-by: Cristian Ciocaltea --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index acb6807d3461384929e84f4c939fcd00c4b509ae..346ef79c1ddd0a317f0b9a8056c= 680c29a4e0baf 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -966,6 +966,7 @@ CONFIG_DRM_CDNS_MHDP8546=3Dm CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE=3Dm CONFIG_DRM_DW_HDMI_AHB_AUDIO=3Dm CONFIG_DRM_DW_HDMI_CEC=3Dm +CONFIG_DRM_DW_HDMI_QP_CEC=3Dy CONFIG_DRM_IMX_DCSS=3Dm CONFIG_DRM_V3D=3Dm CONFIG_DRM_VC4=3Dm --=20 2.50.1