From nobody Fri Oct 3 21:44:12 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F8B62DAFB1 for ; Mon, 25 Aug 2025 10:08:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756116530; cv=none; b=m/dB9eHqmruNVitENK6gsn4JFlF1ji3Lu4T7b0kiLtsyKjgymbz0e0GC8rd0SohErt41ktbgcnKBRhQOqIkDWZibLQPHkpd1/RYL+7NPs6Pji/cStfrWcjvTPMEFT026OiZU4fEBBMrofiYmcJ3nFH/uKWNBHeC6Vi87st3balg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756116530; c=relaxed/simple; bh=qoxTFsHFIVAgWULug32Ze5NgiLmjo1jREPwaJJjIE5I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=j6lEC1ygD9olB7RpY37TiIBNcZXg6Kzyqi7F0yDt53rXZIY4Bo8jtNfuSotFrMCQ0t1mzA7BGRmV3APsdDdosro+gKW8ywNCDaUu34iB0IW19drRgpZjgW/xWujcQjOSu5C0CzIbc5xO4FM5DUz5Hcd8yDPo/rTtfsOLAbeMg24= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=Pi/oMYGf; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="Pi/oMYGf" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1756116526; bh=qoxTFsHFIVAgWULug32Ze5NgiLmjo1jREPwaJJjIE5I=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Pi/oMYGfOTsn0Qm5Cz8h1nACTCYiwQNQV72Ua2K6W+Q774WFQhaimzIkTxY6y4Mj8 uSsUQuyvEnv+AFrO3cyRr0MZWLca4rraGZmR5Dqwt4glZh8nKI1LnpbyppdACCosB7 Xyvx3pHj67Z7wHKwkbBFqleyjMjlS2UUo0huU8NTLhSPEKiEKGFiQaZZC90rCJN1Tc djCNT5k0o82vlb1BU3lOBoheTlPOslkwPsZwdyYqo1I6TRecauuoMk5/nycqg4m91q ETA3rjwXIP3tcOm9seHv6tcn3BE1wNfr8fwxJI+T6pqENVzs8YI+oLVTlE6lBAdIYq IguWOFN6qAdQg== Received: from localhost (unknown [82.79.138.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 98EB517E0963; Mon, 25 Aug 2025 12:08:46 +0200 (CEST) From: Cristian Ciocaltea Date: Mon, 25 Aug 2025 13:08:36 +0300 Subject: [PATCH v2 5/5] drm/rockchip: dw_hdmi_qp: Add high color depth support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-rk3588-10bpc-v2-5-955622d16985@collabora.com> References: <20250825-rk3588-10bpc-v2-0-955622d16985@collabora.com> In-Reply-To: <20250825-rk3588-10bpc-v2-0-955622d16985@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 Since both RK3576 and RK3588 SoCs are capable of handling 10 bpc color depth, introduce a pair of new helpers to program the necessary registers, as well as passing bpc at PHY configuration level. Note max_bpc is unconditionally set to 10 before initializing the QP bridge library, as there is no need to adjust it dynamically, i.e. per SoC variant, for now. While setting up .enc_init() callbacks of rockchip_hdmi_qp_ctrl_ops, also replace the unnecessary whitespace chars before .irq_callback() assignments. Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 59 ++++++++++++++++++++++= ++-- 1 file changed, 56 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/d= rm/rockchip/dw_hdmi_qp-rockchip.c index 0f2b421134af9f935758266af45c5779407b4144..81f106ac7b561110b4be39d58e9= 9a225af7786f2 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -7,6 +7,7 @@ * Author: Cristian Ciocaltea */ =20 +#include #include #include #include @@ -68,6 +69,12 @@ #define RK3588_HDMI1_LEVEL_INT BIT(24) #define RK3588_GRF_VO1_CON3 0x000c #define RK3588_GRF_VO1_CON6 0x0018 +#define RK3588_COLOR_DEPTH_MASK GENMASK(7, 4) +#define RK3588_8BPC 0x0 +#define RK3588_10BPC 0x6 +#define RK3588_COLOR_FORMAT_MASK GENMASK(3, 0) +#define RK3588_RGB 0x0 +#define RK3588_YUV420 0x3 #define RK3588_SCLIN_MASK BIT(9) #define RK3588_SDAIN_MASK BIT(10) #define RK3588_MODE_MASK BIT(11) @@ -96,6 +103,7 @@ struct rockchip_hdmi_qp { =20 struct rockchip_hdmi_qp_ctrl_ops { void (*io_init)(struct rockchip_hdmi_qp *hdmi); + void (*enc_init)(struct rockchip_hdmi_qp *hdmi, struct rockchip_crtc_stat= e *state); irqreturn_t (*irq_callback)(int irq, void *dev_id); irqreturn_t (*hardirq_callback)(int irq, void *dev_id); }; @@ -110,9 +118,16 @@ static struct rockchip_hdmi_qp *to_rockchip_hdmi_qp(st= ruct drm_encoder *encoder) static void dw_hdmi_qp_rockchip_encoder_enable(struct drm_encoder *encoder) { struct rockchip_hdmi_qp *hdmi =3D to_rockchip_hdmi_qp(encoder); + struct drm_crtc *crtc =3D encoder->crtc; =20 /* Unconditionally switch to TMDS as FRL is not yet supported */ gpiod_set_value(hdmi->enable_gpio, 1); + + if (!crtc || !crtc->state) + return; + + if (hdmi->ctrl_ops->enc_init) + hdmi->ctrl_ops->enc_init(hdmi, to_rockchip_crtc_state(crtc->state)); } =20 static int @@ -125,16 +140,19 @@ dw_hdmi_qp_rockchip_encoder_atomic_check(struct drm_e= ncoder *encoder, union phy_configure_opts phy_cfg =3D {}; int ret; =20 - if (hdmi->tmds_char_rate =3D=3D conn_state->hdmi.tmds_char_rate) + if (hdmi->tmds_char_rate =3D=3D conn_state->hdmi.tmds_char_rate && + s->output_bpc =3D=3D conn_state->hdmi.output_bpc) return 0; =20 phy_cfg.hdmi.tmds_char_rate =3D conn_state->hdmi.tmds_char_rate; + phy_cfg.hdmi.bpc =3D conn_state->hdmi.output_bpc; =20 ret =3D phy_configure(hdmi->phy, &phy_cfg); if (!ret) { hdmi->tmds_char_rate =3D conn_state->hdmi.tmds_char_rate; s->output_mode =3D ROCKCHIP_OUT_MODE_AAAA; s->output_type =3D DRM_MODE_CONNECTOR_HDMIA; + s->output_bpc =3D conn_state->hdmi.output_bpc; } else { dev_err(hdmi->dev, "Failed to configure phy: %d\n", ret); } @@ -373,15 +391,49 @@ static void dw_hdmi_qp_rk3588_io_init(struct rockchip= _hdmi_qp *hdmi) regmap_write(hdmi->regmap, RK3588_GRF_SOC_CON2, val); } =20 +static void dw_hdmi_qp_rk3576_enc_init(struct rockchip_hdmi_qp *hdmi, + struct rockchip_crtc_state *state) +{ + u32 val; + + if (state->output_bpc =3D=3D 10) + val =3D HIWORD_UPDATE(FIELD_PREP(RK3576_COLOR_DEPTH_MASK, RK3576_10BPC), + RK3576_COLOR_DEPTH_MASK); + else + val =3D HIWORD_UPDATE(FIELD_PREP(RK3576_COLOR_DEPTH_MASK, RK3576_8BPC), + RK3576_COLOR_DEPTH_MASK); + + regmap_write(hdmi->vo_regmap, RK3576_VO0_GRF_SOC_CON8, val); +} + +static void dw_hdmi_qp_rk3588_enc_init(struct rockchip_hdmi_qp *hdmi, + struct rockchip_crtc_state *state) +{ + u32 val; + + if (state->output_bpc =3D=3D 10) + val =3D HIWORD_UPDATE(FIELD_PREP(RK3588_COLOR_DEPTH_MASK, RK3588_10BPC), + RK3588_COLOR_DEPTH_MASK); + else + val =3D HIWORD_UPDATE(FIELD_PREP(RK3588_COLOR_DEPTH_MASK, RK3588_8BPC), + RK3588_COLOR_DEPTH_MASK); + + regmap_write(hdmi->vo_regmap, + hdmi->port_id ? RK3588_GRF_VO1_CON6 : RK3588_GRF_VO1_CON3, + val); +} + static const struct rockchip_hdmi_qp_ctrl_ops rk3576_hdmi_ctrl_ops =3D { .io_init =3D dw_hdmi_qp_rk3576_io_init, - .irq_callback =3D dw_hdmi_qp_rk3576_irq, + .enc_init =3D dw_hdmi_qp_rk3576_enc_init, + .irq_callback =3D dw_hdmi_qp_rk3576_irq, .hardirq_callback =3D dw_hdmi_qp_rk3576_hardirq, }; =20 static const struct rockchip_hdmi_qp_ctrl_ops rk3588_hdmi_ctrl_ops =3D { .io_init =3D dw_hdmi_qp_rk3588_io_init, - .irq_callback =3D dw_hdmi_qp_rk3588_irq, + .enc_init =3D dw_hdmi_qp_rk3588_enc_init, + .irq_callback =3D dw_hdmi_qp_rk3588_irq, .hardirq_callback =3D dw_hdmi_qp_rk3588_hardirq, }; =20 @@ -474,6 +526,7 @@ static int dw_hdmi_qp_rockchip_bind(struct device *dev,= struct device *master, =20 plat_data.phy_ops =3D cfg->phy_ops; plat_data.phy_data =3D hdmi; + plat_data.max_bpc =3D 10; =20 encoder =3D &hdmi->encoder.encoder; encoder->possible_crtcs =3D drm_of_find_possible_crtcs(drm, dev->of_node); --=20 2.50.1