From nobody Fri Oct 3 21:44:12 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DE9BB2D9787 for ; Mon, 25 Aug 2025 10:08:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756116528; cv=none; b=aZ7kGlxZHxkGwnt8Ono18nezAdd1UzP+x5MA2DCAyE+Mkn5lF4ih9gEU9CyZDpfSIPZG+uhkH7l24Si0jpFTDySZLezfmeGwsj6rX88EwtuSEoOxxqsZa5ITtnTDyg3dWWEoMD3qgJDtuBABtdXboj1hZRvMEvmJ1fIaBSajX5I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756116528; c=relaxed/simple; bh=9xiHC2hMHQhX5mp7mX3NwaloWJOeXf9/yzi4dN1d7LA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZN4x4tkAt+jaZkXrGrNEZYzbci3jKc3ZUYN1RiUARpuZVMGDJQkglqmccV8jXL5FH9pYccELsj4RQjf/lbl8g8U/ULpQq8r4t03A7PIULIm7wFKeqXpoe/RJqvlmcTW/276qLFOJ5kloc1qECr7oiNXtzZuZQlBDqQao0ktqZLI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=P7QlWWa/; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="P7QlWWa/" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1756116525; bh=9xiHC2hMHQhX5mp7mX3NwaloWJOeXf9/yzi4dN1d7LA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=P7QlWWa/0jhNTr6hsCWE+fxw1Is0KM37/TnYpl7Kj+X84Ho4UjPbQ/g5sD0kwFd/f 8raBQSOd57203T4JjcE5PKYBXXSvY7g9+oENDtEzIUhMly027XaCJ+mKx+lNpEroz+ uGzRH2mRXxU2uHB+SlLANCvQBcRk8nidKof6cT0kTqc8aaacx9zeBc/p50JnFG2x2T zzhdD93tIoMq1KY3avNd1DswitHkqs2rA5flBhDQhJVDVaqOdKmlB/vxYO9ccKCAAm XIIGwBD1FXpY1VOm+BTdlvNkmp5hOlzdPiyMkg1Bsg/H+ezokQjhjc52zwaBX6NjDC bMopHD2LIUnPQ== Received: from localhost (unknown [82.79.138.60]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 05AE917E08E3; Mon, 25 Aug 2025 12:08:44 +0200 (CEST) From: Cristian Ciocaltea Date: Mon, 25 Aug 2025 13:08:34 +0300 Subject: [PATCH v2 3/5] drm/rockchip: dw_hdmi_qp: Switch to phy_configure() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-rk3588-10bpc-v2-3-955622d16985@collabora.com> References: <20250825-rk3588-10bpc-v2-0-955622d16985@collabora.com> In-Reply-To: <20250825-rk3588-10bpc-v2-0-955622d16985@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 Stop relying on phy_set_bus_width() based workaround to setup the TMDS character rate and, instead, use the recently introduced HDMI PHY configuration API. This is also a prerequisite to enable high color depth and FRL support. Additionally, move the logic to ->atomic_check() callback where the current mode rate is already provided by the connector state. As a matter of fact this is actually necessary to ensure the link rate is configured before VOP2 attempts to use the PHY PLL as a DCLK source in vop2_crtc_atomic_enable(). The rationale is to restrict any changes of the PHY rate via CCF and, instead, prefer the PHY configuration API for this purpose. Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c | 37 +++++++++++++---------= ---- 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c b/drivers/gpu/d= rm/rockchip/dw_hdmi_qp-rockchip.c index 5280383febe25cf579c306ec1642557600595e58..6f2006e7999b540f29841ec4ef6= 79a3ab1e8f497 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi_qp-rockchip.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include =20 @@ -95,6 +96,7 @@ struct rockchip_hdmi_qp { struct delayed_work hpd_work; int port_id; const struct rockchip_hdmi_qp_ctrl_ops *ctrl_ops; + unsigned long long tmds_char_rate; }; =20 struct rockchip_hdmi_qp_ctrl_ops { @@ -113,24 +115,9 @@ static struct rockchip_hdmi_qp *to_rockchip_hdmi_qp(st= ruct drm_encoder *encoder) static void dw_hdmi_qp_rockchip_encoder_enable(struct drm_encoder *encoder) { struct rockchip_hdmi_qp *hdmi =3D to_rockchip_hdmi_qp(encoder); - struct drm_crtc *crtc =3D encoder->crtc; - unsigned long long rate; =20 /* Unconditionally switch to TMDS as FRL is not yet supported */ gpiod_set_value(hdmi->enable_gpio, 1); - - if (crtc && crtc->state) { - rate =3D drm_hdmi_compute_mode_clock(&crtc->state->adjusted_mode, - 8, HDMI_COLORSPACE_RGB); - /* - * FIXME: Temporary workaround to pass pixel clock rate - * to the PHY driver until phy_configure_opts_hdmi - * becomes available in the PHY API. See also the related - * comment in rk_hdptx_phy_power_on() from - * drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c - */ - phy_set_bus_width(hdmi->phy, div_u64(rate, 100)); - } } =20 static int @@ -138,12 +125,26 @@ dw_hdmi_qp_rockchip_encoder_atomic_check(struct drm_e= ncoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { + struct rockchip_hdmi_qp *hdmi =3D to_rockchip_hdmi_qp(encoder); struct rockchip_crtc_state *s =3D to_rockchip_crtc_state(crtc_state); + union phy_configure_opts phy_cfg =3D {}; + int ret; =20 - s->output_mode =3D ROCKCHIP_OUT_MODE_AAAA; - s->output_type =3D DRM_MODE_CONNECTOR_HDMIA; + if (hdmi->tmds_char_rate =3D=3D conn_state->hdmi.tmds_char_rate) + return 0; =20 - return 0; + phy_cfg.hdmi.tmds_char_rate =3D conn_state->hdmi.tmds_char_rate; + + ret =3D phy_configure(hdmi->phy, &phy_cfg); + if (!ret) { + hdmi->tmds_char_rate =3D conn_state->hdmi.tmds_char_rate; + s->output_mode =3D ROCKCHIP_OUT_MODE_AAAA; + s->output_type =3D DRM_MODE_CONNECTOR_HDMIA; + } else { + dev_err(hdmi->dev, "Failed to configure phy: %d\n", ret); + } + + return ret; } =20 static const struct --=20 2.50.1