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Split these two parts into prepare/enable APIs, to support MST bridges_enable insert the MST payloads funcs between enable stream_clks and program register. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 51 ++++++++++------ drivers/gpu/drm/msm/dp/dp_ctrl.h | 3 +- drivers/gpu/drm/msm/dp/dp_display.c | 113 ++++++++++++++++++++++++--------= ---- drivers/gpu/drm/msm/dp/dp_display.h | 1 + 4 files changed, 113 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 4cf269b98029a55e6cbdfb297587de320019b833..6bfd8faa1e212c3a25964677a44= 62e7a3a162fa4 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2446,27 +2446,19 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ct= rl_private *ctrl, msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID, nvid); } =20 -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link= _train) +int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train) { int ret =3D 0; - bool mainlink_ready =3D false; struct msm_dp_ctrl_private *ctrl; - unsigned long pixel_rate; - unsigned long pixel_rate_orig; =20 if (!msm_dp_ctrl) return -EINVAL; =20 ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 - pixel_rate =3D pixel_rate_orig =3D ctrl->panel->msm_dp_mode.drm_mode.cloc= k; - - if (msm_dp_ctrl->wide_bus_en || ctrl->panel->msm_dp_mode.out_fmt_is_yuv_4= 20) - pixel_rate >>=3D 1; - - drm_dbg_dp(ctrl->drm_dev, "rate=3D%d, num_lanes=3D%d, pixel_rate=3D%lu\n", + drm_dbg_dp(ctrl->drm_dev, "rate=3D%d, num_lanes=3D%d\n", ctrl->link->link_params.rate, - ctrl->link->link_params.num_lanes, pixel_rate); + ctrl->link->link_params.num_lanes); =20 drm_dbg_dp(ctrl->drm_dev, "core_clk_on=3D%d link_clk_on=3D%d stream_clk_on=3D%d\n", @@ -2476,10 +2468,39 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_d= p_ctrl, bool force_link_train ret =3D msm_dp_ctrl_enable_mainlink_clocks(ctrl); if (ret) { DRM_ERROR("Failed to start link clocks. ret=3D%d\n", ret); - goto end; + return ret; } } =20 + if (force_link_train || !msm_dp_ctrl_channel_eq_ok(ctrl)) + msm_dp_ctrl_link_retrain(ctrl); + + /* stop txing train pattern to end link training */ + msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); + + return ret; +} + +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl) +{ + int ret =3D 0; + bool mainlink_ready =3D false; + struct msm_dp_ctrl_private *ctrl; + unsigned long pixel_rate; + unsigned long pixel_rate_orig; + + if (!msm_dp_ctrl) + return -EINVAL; + + ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); + + pixel_rate =3D pixel_rate_orig =3D ctrl->panel->msm_dp_mode.drm_mode.cloc= k; + + if (msm_dp_ctrl->wide_bus_en || ctrl->panel->msm_dp_mode.out_fmt_is_yuv_4= 20) + pixel_rate >>=3D 1; + + drm_dbg_dp(ctrl->drm_dev, "pixel_rate=3D%lu\n", pixel_rate); + ret =3D clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); if (ret) { DRM_ERROR("Failed to set pixel clock rate. ret=3D%d\n", ret); @@ -2497,12 +2518,6 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp= _ctrl, bool force_link_train ctrl->stream_clks_on =3D true; } =20 - if (force_link_train || !msm_dp_ctrl_channel_eq_ok(ctrl)) - msm_dp_ctrl_link_retrain(ctrl); - - /* stop txing train pattern to end link training */ - msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); - /* * Set up transfer unit values and set controller state to send * video. diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index f68bee62713f1650354b37edb8e1d76134d8d395..1497f1a8fc2f00991356663c19c= 87eb9fad48a73 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -17,7 +17,8 @@ struct msm_dp_ctrl { struct phy; =20 int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link= _train); +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl); +int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train); void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 632a1191e4e48fecd7dbda2f6ec6b8ed0aeebc93..36a12150925246b168acbabf77d= 1206a1ef8eff5 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -674,7 +674,42 @@ static int msm_dp_display_set_mode(struct msm_dp *msm_= dp_display, return 0; } =20 -static int msm_dp_display_enable(struct msm_dp_display_private *dp, bool f= orce_link_train) +static int msm_dp_display_prepare(struct msm_dp_display_private *dp) +{ + int rc =3D 0; + struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; + bool force_link_train =3D false; + + drm_dbg_dp(dp->drm_dev, "sink_count=3D%d\n", dp->link->sink_count); + + rc =3D pm_runtime_resume_and_get(&msm_dp_display->pdev->dev); + if (rc) { + DRM_ERROR("failed to pm_runtime_resume\n"); + return rc; + } + + if (dp->link->sink_count =3D=3D 0) + return rc; + + if (msm_dp_display->link_ready && !msm_dp_display->power_on) { + msm_dp_display_host_phy_init(dp); + force_link_train =3D true; + } + + rc =3D msm_dp_ctrl_on_link(dp->ctrl); + if (rc) { + DRM_ERROR("Failed link training (rc=3D%d)\n", rc); + msm_dp_display->connector->state->link_status =3D DRM_LINK_STATUS_BAD; + } + + rc =3D msm_dp_ctrl_prepare_stream_on(dp->ctrl, force_link_train); + if (!rc) + msm_dp_display->prepared =3D true; + + return rc; +} + +static int msm_dp_display_enable(struct msm_dp_display_private *dp) { int rc =3D 0; struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; @@ -685,7 +720,7 @@ static int msm_dp_display_enable(struct msm_dp_display_= private *dp, bool force_l return 0; } =20 - rc =3D msm_dp_ctrl_on_stream(dp->ctrl, force_link_train); + rc =3D msm_dp_ctrl_on_stream(dp->ctrl); if (!rc) msm_dp_display->power_on =3D true; =20 @@ -715,13 +750,10 @@ static int msm_dp_display_post_enable(struct msm_dp *= msm_dp_display) return 0; } =20 -static int msm_dp_display_disable(struct msm_dp_display_private *dp) +static void msm_dp_display_audio_notify_disable(struct msm_dp_display_priv= ate *dp) { struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; =20 - if (!msm_dp_display->power_on) - return 0; - /* wait only if audio was enabled */ if (msm_dp_display->audio_enabled) { /* signal the disconnect event */ @@ -732,6 +764,14 @@ static int msm_dp_display_disable(struct msm_dp_displa= y_private *dp) } =20 msm_dp_display->audio_enabled =3D false; +} + +static int msm_dp_display_disable(struct msm_dp_display_private *dp) +{ + struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; + + if (!msm_dp_display->power_on) + return 0; =20 if (dp->link->sink_count =3D=3D 0) { /* @@ -1395,44 +1435,34 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge = *drm_bridge, struct drm_atomic_state *state) { struct msm_dp_bridge *msm_dp_bridge =3D to_dp_bridge(drm_bridge); - struct msm_dp *dp =3D msm_dp_bridge->msm_dp_display; + struct msm_dp *msm_dp_display =3D msm_dp_bridge->msm_dp_display; int rc =3D 0; - struct msm_dp_display_private *msm_dp_display; - bool force_link_train =3D false; - - msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); - - if (dp->is_edp) - msm_dp_hpd_plug_handle(msm_dp_display, 0); - - if (pm_runtime_resume_and_get(&dp->pdev->dev)) { - DRM_ERROR("failed to pm_runtime_resume\n"); - return; - } + struct msm_dp_display_private *dp; =20 - if (msm_dp_display->link->sink_count =3D=3D 0) - return; + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - if (dp->link_ready && !dp->power_on) { - msm_dp_display_host_phy_init(msm_dp_display); - force_link_train =3D true; - } + if (msm_dp_display->is_edp) + msm_dp_hpd_plug_handle(dp, 0); =20 - rc =3D msm_dp_ctrl_on_link(msm_dp_display->ctrl); + rc =3D msm_dp_display_prepare(dp); if (rc) { - DRM_ERROR("Failed link training (rc=3D%d)\n", rc); - dp->connector->state->link_status =3D DRM_LINK_STATUS_BAD; + DRM_ERROR("DP display prepare failed, rc=3D%d\n", rc); + return; } =20 - msm_dp_display_enable(msm_dp_display, force_link_train); + if (msm_dp_display->prepared) { + rc =3D msm_dp_display_enable(dp); + if (rc) + DRM_ERROR("DP display enable failed, rc=3D%d\n", rc); =20 - rc =3D msm_dp_display_post_enable(dp); - if (rc) { - DRM_ERROR("DP display post enable failed, rc=3D%d\n", rc); - msm_dp_display_disable(msm_dp_display); + rc =3D msm_dp_display_post_enable(msm_dp_display); + if (rc) { + DRM_ERROR("DP display post enable failed, rc=3D%d\n", rc); + msm_dp_display_disable(dp); + } } =20 - drm_dbg_dp(dp->drm_dev, "type=3D%d Done\n", dp->connector_type); + drm_dbg_dp(msm_dp_display->drm_dev, "type=3D%d Done\n", msm_dp_display->c= onnector_type); } =20 void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, @@ -1447,6 +1477,15 @@ void msm_dp_bridge_atomic_disable(struct drm_bridge = *drm_bridge, msm_dp_ctrl_push_idle(msm_dp_display->ctrl); } =20 +static void msm_dp_display_unprepare(struct msm_dp_display_private *dp) +{ + struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; + + pm_runtime_put_sync(&msm_dp_display->pdev->dev); + + msm_dp_display->prepared =3D false; +} + void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, struct drm_atomic_state *state) { @@ -1462,11 +1501,13 @@ void msm_dp_bridge_atomic_post_disable(struct drm_b= ridge *drm_bridge, if (!dp->link_ready) drm_dbg_dp(dp->drm_dev, "type=3D%d is disconnected\n", dp->connector_typ= e); =20 + msm_dp_display_audio_notify_disable(msm_dp_display); + msm_dp_display_disable(msm_dp_display); =20 - drm_dbg_dp(dp->drm_dev, "type=3D%d Done\n", dp->connector_type); + msm_dp_display_unprepare(msm_dp_display); =20 - pm_runtime_put_sync(&dp->pdev->dev); + drm_dbg_dp(dp->drm_dev, "type=3D%d Done\n", dp->connector_type); } =20 void msm_dp_bridge_mode_set(struct drm_bridge *drm_bridge, diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index 60094061c1029bc7a06ffaa80d9403b40aa07eb1..2fbf16f27842bb7639efaa2baec= ac7bdf8908432 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -20,6 +20,7 @@ struct msm_dp { bool link_ready; bool audio_enabled; bool power_on; + bool prepared; unsigned int connector_type; bool is_edp; bool internal_hpd; --=20 2.34.1