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a=ed25519-sha256; t=1756131418; l=8479; i=yongxing.mou@oss.qualcomm.com; s=20241121; h=from:subject:message-id; bh=pW1C/FAkrELsv2lywujfPr2WEDZOqzKrkIRTRgn3JOM=; b=Ia/lzZCIgQkRmB3T8DJay/JEg5rDHt/HDMS4jdDjAYuIMpU3DmbMpB68swR6oxY4h2hftlCb5 0qRF/LIxER/D25ZS3c90EB5PHZjBHIiIdU0liObXziKmAzkQ2YWv6Oz X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=zeCnFRUqtOQMeFvdwex2M5o0Yf67UHYfwCyBRQ3kFbU= X-Proofpoint-GUID: o5F0zb40NyKf3KitVJzxLgtYr_sofi_M X-Proofpoint-ORIG-GUID: o5F0zb40NyKf3KitVJzxLgtYr_sofi_M X-Authority-Analysis: v=2.4 cv=JJo7s9Kb c=1 sm=1 tr=0 ts=68ac706c cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=Uz3yg00KUFJ2y2WijEJ4bw==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=s5ODlx4LKU-xjoPD000A:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODIzMDAzMSBTYWx0ZWRfXxy1pcfkVZcP7 xDrCqQwiSxLaivkABkLxgXvs2oH+lxYQOg0lhmKvcxjNBcmnVLz6pilE3HNLwt60aa2e6MOhK7j 8ZwwkIHS84C6O8aqEQeurPmIPog48c8WHbqhwgcv+mW1mWum93TxtHz9poNeTc8jwmxmH+8E3Y1 RaCuzEJQRJy8zTtbBpZQw47Ys15i1+xcOJOhHMTpS7gOkk7qQEXn+NLJH4VgTwgATHFg0jdXs9T AqDD/elBWKqKxLdNA+fjnvsQYWaBWm82UXg0o0lVtC4/Ly1vb7QmMvB8eMcUNKIwXBvT3ZJw0XJ bB9La8ODNRsxjZ1FlXBHpctf+b/Gr94cnqp/cWJ5ASwNLPewj6p+VcGwHhicNP4tVSvGGtw4IJT rsZDM+In X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-25_06,2025-08-20_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 bulkscore=0 spamscore=0 impostorscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508230031 The cached drm_edid in msm_dp_panel was redundant and led to unnecessary state management complexity. This change removes the drm_edid member from the panel structure and refactors related functions to use locally read EDID data instead. - Replaces msm_dp_panel_read_sink_caps() with msm_dp_panel_read_link_caps() - Updates msm_dp_panel_handle_sink_request() to accept drm_edid as input - Removes msm_dp_panel_get_modes() and drm_edid caching logic - Cleans up unused drm_edid_free() calls This simplifies EDID handling and avoids stale data issues. Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 28 +++++++++++++++------- drivers/gpu/drm/msm/dp/dp_panel.c | 47 ++++-----------------------------= ---- drivers/gpu/drm/msm/dp/dp_panel.h | 9 +++---- 3 files changed, 26 insertions(+), 58 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 6d81950627a073baca9809690134a711e965035f..dadf31bc37763c4f07f68b76fbb= e33fb77b20850 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -282,6 +282,7 @@ static int msm_dp_display_process_hpd_high(struct msm_d= p_display_private *dp) const struct drm_display_info *info =3D &connector->display_info; int rc =3D 0; u8 dpcd[DP_RECEIVER_CAP_SIZE]; + const struct drm_edid *drm_edid; =20 rc =3D drm_dp_read_dpcd_caps(dp->aux, dpcd); if (rc) @@ -289,7 +290,20 @@ static int msm_dp_display_process_hpd_high(struct msm_= dp_display_private *dp) =20 dp->link->lttpr_count =3D msm_dp_display_lttpr_init(dp, dpcd); =20 - rc =3D msm_dp_panel_read_sink_caps(dp->panel, connector); + rc =3D msm_dp_panel_read_link_caps(dp->panel, connector); + if (rc) + goto end; + + drm_edid =3D drm_edid_read_ddc(connector, &dp->aux->ddc); + drm_edid_connector_update(connector, drm_edid); + + if (!drm_edid) { + DRM_ERROR("panel edid read failed\n"); + /* check edid read fail is due to unplug */ + if (!msm_dp_aux_is_link_connected(dp->aux)) + return -ETIMEDOUT; + } + if (rc) goto end; =20 @@ -306,7 +320,7 @@ static int msm_dp_display_process_hpd_high(struct msm_d= p_display_private *dp) dp->msm_dp_display.psr_supported =3D dp->panel->psr_cap.version && psr_en= abled; =20 dp->audio_supported =3D info->has_audio; - msm_dp_panel_handle_sink_request(dp->panel); + msm_dp_panel_handle_sink_request(dp->panel, drm_edid); =20 /* * set sink to normal operation mode -- D0 @@ -565,7 +579,6 @@ static int msm_dp_irq_hpd_handle(struct msm_dp_display_= private *dp, u32 data) static void msm_dp_display_deinit_sub_modules(struct msm_dp_display_privat= e *dp) { msm_dp_audio_put(dp->audio); - msm_dp_panel_put(dp->panel); msm_dp_aux_put(dp->aux); } =20 @@ -616,7 +629,7 @@ static int msm_dp_init_sub_modules(struct msm_dp_displa= y_private *dp) rc =3D PTR_ERR(dp->ctrl); DRM_ERROR("failed to initialize ctrl, rc =3D %d\n", rc); dp->ctrl =3D NULL; - goto error_ctrl; + goto error_link; } =20 dp->audio =3D msm_dp_audio_get(dp->msm_dp_display.pdev, dp->link_base); @@ -624,13 +637,11 @@ static int msm_dp_init_sub_modules(struct msm_dp_disp= lay_private *dp) rc =3D PTR_ERR(dp->audio); pr_err("failed to initialize audio, rc =3D %d\n", rc); dp->audio =3D NULL; - goto error_ctrl; + goto error_link; } =20 return rc; =20 -error_ctrl: - msm_dp_panel_put(dp->panel); error_link: msm_dp_aux_put(dp->aux); error: @@ -794,8 +805,7 @@ int msm_dp_display_get_modes(struct msm_dp *dp) =20 msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); =20 - return msm_dp_panel_get_modes(msm_dp_display->panel, - dp->connector); + return drm_edid_connector_add_modes(msm_dp_display->panel->connector); } =20 bool msm_dp_display_check_video_test(struct msm_dp *dp) diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index 15b7f6c7146e1176a80b5c9d25896b1c8ede3aed..eae125972934bb2fb3b716dc47a= e71cd0421bd1a 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -159,7 +159,7 @@ static u32 msm_dp_panel_get_supported_bpp(struct msm_dp= _panel *msm_dp_panel, return min_supported_bpp; } =20 -int msm_dp_panel_read_sink_caps(struct msm_dp_panel *msm_dp_panel, +int msm_dp_panel_read_link_caps(struct msm_dp_panel *msm_dp_panel, struct drm_connector *connector) { int rc, bw_code; @@ -201,25 +201,6 @@ int msm_dp_panel_read_sink_caps(struct msm_dp_panel *m= sm_dp_panel, =20 rc =3D drm_dp_read_downstream_info(panel->aux, msm_dp_panel->dpcd, msm_dp_panel->downstream_ports); - if (rc) - return rc; - - drm_edid_free(msm_dp_panel->drm_edid); - - msm_dp_panel->drm_edid =3D drm_edid_read_ddc(connector, &panel->aux->ddc); - - drm_edid_connector_update(connector, msm_dp_panel->drm_edid); - - if (!msm_dp_panel->drm_edid) { - DRM_ERROR("panel edid read failed\n"); - /* check edid read fail is due to unplug */ - if (!msm_dp_aux_is_link_connected(panel->aux)) { - rc =3D -ETIMEDOUT; - goto end; - } - } - -end: return rc; } =20 @@ -246,20 +227,6 @@ u32 msm_dp_panel_get_mode_bpp(struct msm_dp_panel *msm= _dp_panel, return bpp; } =20 -int msm_dp_panel_get_modes(struct msm_dp_panel *msm_dp_panel, - struct drm_connector *connector) -{ - if (!msm_dp_panel) { - DRM_ERROR("invalid input\n"); - return -EINVAL; - } - - if (msm_dp_panel->drm_edid) - return drm_edid_connector_add_modes(connector); - - return 0; -} - static u8 msm_dp_panel_get_edid_checksum(const struct edid *edid) { edid +=3D edid->extensions; @@ -267,7 +234,8 @@ static u8 msm_dp_panel_get_edid_checksum(const struct e= did *edid) return edid->checksum; } =20 -void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel) +void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel, + const struct drm_edid *drm_edid) { struct msm_dp_panel_private *panel; =20 @@ -280,7 +248,7 @@ void msm_dp_panel_handle_sink_request(struct msm_dp_pan= el *msm_dp_panel) =20 if (panel->link->sink_request & DP_TEST_LINK_EDID_READ) { /* FIXME: get rid of drm_edid_raw() */ - const struct edid *edid =3D drm_edid_raw(msm_dp_panel->drm_edid); + const struct edid *edid =3D drm_edid_raw(drm_edid); u8 checksum; =20 if (edid) @@ -736,10 +704,3 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *d= ev, struct drm_dp_aux *aux return msm_dp_panel; } =20 -void msm_dp_panel_put(struct msm_dp_panel *msm_dp_panel) -{ - if (!msm_dp_panel) - return; - - drm_edid_free(msm_dp_panel->drm_edid); -} diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index d2cf401506dcbaf553192d5e18c87207337664ab..618d0253b525308b392b9282098= e8ca78bf32f1c 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -33,7 +33,6 @@ struct msm_dp_panel { u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; =20 struct msm_dp_link_info link_info; - const struct drm_edid *drm_edid; struct drm_connector *connector; struct msm_dp_display_mode msm_dp_mode; struct msm_dp_panel_psr psr_cap; @@ -50,13 +49,12 @@ struct msm_dp_panel { int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel); int msm_dp_panel_deinit(struct msm_dp_panel *msm_dp_panel); int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp_panel, bool wide_b= us_en); -int msm_dp_panel_read_sink_caps(struct msm_dp_panel *msm_dp_panel, +int msm_dp_panel_read_link_caps(struct msm_dp_panel *msm_dp_panel, struct drm_connector *connector); u32 msm_dp_panel_get_mode_bpp(struct msm_dp_panel *msm_dp_panel, u32 mode_= max_bpp, u32 mode_pclk_khz); -int msm_dp_panel_get_modes(struct msm_dp_panel *msm_dp_panel, - struct drm_connector *connector); -void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel); +void msm_dp_panel_handle_sink_request(struct msm_dp_panel *msm_dp_panel, + const struct drm_edid *drm_edid); void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enabl= e); 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Remove this two level passing and directly populate the panel's dp_display_mode instead. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 66 ++++++++++++++-------------------= ---- 1 file changed, 24 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index dadf31bc37763c4f07f68b76fbbe33fb77b20850..632a1191e4e48fecd7dbda2f6ec= 6b8ed0aeebc93 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -60,7 +60,6 @@ struct msm_dp_display_private { struct msm_dp_panel *panel; struct msm_dp_ctrl *ctrl; =20 - struct msm_dp_display_mode msm_dp_mode; struct msm_dp msm_dp_display; =20 /* wait for audio signaling */ @@ -649,16 +648,29 @@ static int msm_dp_init_sub_modules(struct msm_dp_disp= lay_private *dp) } =20 static int msm_dp_display_set_mode(struct msm_dp *msm_dp_display, - struct msm_dp_display_mode *mode) + const struct drm_display_mode *adjusted_mode, + struct msm_dp_panel *msm_dp_panel) { - struct msm_dp_display_private *dp; + u32 bpp; =20 - dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); + drm_mode_copy(&msm_dp_panel->msm_dp_mode.drm_mode, adjusted_mode); + + if (msm_dp_display_check_video_test(msm_dp_display)) + bpp =3D msm_dp_display_get_test_bpp(msm_dp_display); + else + bpp =3D msm_dp_panel->connector->display_info.bpc * 3; + + msm_dp_panel->msm_dp_mode.bpp =3D bpp ? bpp : 24; /* Default bpp */ =20 - drm_mode_copy(&dp->panel->msm_dp_mode.drm_mode, &mode->drm_mode); - dp->panel->msm_dp_mode.bpp =3D mode->bpp; - dp->panel->msm_dp_mode.out_fmt_is_yuv_420 =3D mode->out_fmt_is_yuv_420; - msm_dp_panel_init_panel_info(dp->panel); + msm_dp_panel->msm_dp_mode.v_active_low =3D + !!(adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC); + msm_dp_panel->msm_dp_mode.h_active_low =3D + !!(adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC); + msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420 =3D + drm_mode_is_420_only(&msm_dp_panel->connector->display_info, adjusted_mo= de) && + msm_dp_panel->vsc_sdp_supported; + + msm_dp_panel_init_panel_info(msm_dp_panel); return 0; } =20 @@ -1328,7 +1340,7 @@ bool msm_dp_wide_bus_available(const struct msm_dp *m= sm_dp_display) =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - if (dp->msm_dp_mode.out_fmt_is_yuv_420) + if (dp->panel->msm_dp_mode.out_fmt_is_yuv_420) return false; =20 return dp->wide_bus_supported; @@ -1389,10 +1401,6 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge *= drm_bridge, bool force_link_train =3D false; =20 msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); - if (!msm_dp_display->msm_dp_mode.drm_mode.clock) { - DRM_ERROR("invalid params\n"); - return; - } =20 if (dp->is_edp) msm_dp_hpd_plug_handle(msm_dp_display, 0); @@ -1405,12 +1413,6 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge *= drm_bridge, if (msm_dp_display->link->sink_count =3D=3D 0) return; =20 - rc =3D msm_dp_display_set_mode(dp, &msm_dp_display->msm_dp_mode); - if (rc) { - DRM_ERROR("Failed to perform a mode set, rc=3D%d\n", rc); - return; - } - if (dp->link_ready && !dp->power_on) { msm_dp_display_host_phy_init(msm_dp_display); force_link_train =3D true; @@ -1479,31 +1481,11 @@ void msm_dp_bridge_mode_set(struct drm_bridge *drm_= bridge, msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); msm_dp_panel =3D msm_dp_display->panel; =20 - memset(&msm_dp_display->msm_dp_mode, 0x0, sizeof(struct msm_dp_display_mo= de)); - - if (msm_dp_display_check_video_test(dp)) - msm_dp_display->msm_dp_mode.bpp =3D msm_dp_display_get_test_bpp(dp); - else /* Default num_components per pixel =3D 3 */ - msm_dp_display->msm_dp_mode.bpp =3D dp->connector->display_info.bpc * 3; - - if (!msm_dp_display->msm_dp_mode.bpp) - msm_dp_display->msm_dp_mode.bpp =3D 24; /* Default bpp */ - - drm_mode_copy(&msm_dp_display->msm_dp_mode.drm_mode, adjusted_mode); - - msm_dp_display->msm_dp_mode.v_active_low =3D - !!(msm_dp_display->msm_dp_mode.drm_mode.flags & DRM_MODE_FLAG_NVSYNC); - - msm_dp_display->msm_dp_mode.h_active_low =3D - !!(msm_dp_display->msm_dp_mode.drm_mode.flags & DRM_MODE_FLAG_NHSYNC); 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Split these two parts into prepare/enable APIs, to support MST bridges_enable insert the MST payloads funcs between enable stream_clks and program register. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 51 ++++++++++------ drivers/gpu/drm/msm/dp/dp_ctrl.h | 3 +- drivers/gpu/drm/msm/dp/dp_display.c | 113 ++++++++++++++++++++++++--------= ---- drivers/gpu/drm/msm/dp/dp_display.h | 1 + 4 files changed, 113 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 4cf269b98029a55e6cbdfb297587de320019b833..6bfd8faa1e212c3a25964677a44= 62e7a3a162fa4 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2446,27 +2446,19 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ct= rl_private *ctrl, msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID, nvid); } =20 -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link= _train) +int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train) { int ret =3D 0; - bool mainlink_ready =3D false; struct msm_dp_ctrl_private *ctrl; - unsigned long pixel_rate; - unsigned long pixel_rate_orig; =20 if (!msm_dp_ctrl) return -EINVAL; =20 ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 - pixel_rate =3D pixel_rate_orig =3D ctrl->panel->msm_dp_mode.drm_mode.cloc= k; - - if (msm_dp_ctrl->wide_bus_en || ctrl->panel->msm_dp_mode.out_fmt_is_yuv_4= 20) - pixel_rate >>=3D 1; - - drm_dbg_dp(ctrl->drm_dev, "rate=3D%d, num_lanes=3D%d, pixel_rate=3D%lu\n", + drm_dbg_dp(ctrl->drm_dev, "rate=3D%d, num_lanes=3D%d\n", ctrl->link->link_params.rate, - ctrl->link->link_params.num_lanes, pixel_rate); + ctrl->link->link_params.num_lanes); =20 drm_dbg_dp(ctrl->drm_dev, "core_clk_on=3D%d link_clk_on=3D%d stream_clk_on=3D%d\n", @@ -2476,10 +2468,39 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_d= p_ctrl, bool force_link_train ret =3D msm_dp_ctrl_enable_mainlink_clocks(ctrl); if (ret) { DRM_ERROR("Failed to start link clocks. ret=3D%d\n", ret); - goto end; + return ret; } } =20 + if (force_link_train || !msm_dp_ctrl_channel_eq_ok(ctrl)) + msm_dp_ctrl_link_retrain(ctrl); + + /* stop txing train pattern to end link training */ + msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); + + return ret; +} + +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl) +{ + int ret =3D 0; + bool mainlink_ready =3D false; + struct msm_dp_ctrl_private *ctrl; + unsigned long pixel_rate; + unsigned long pixel_rate_orig; + + if (!msm_dp_ctrl) + return -EINVAL; + + ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); + + pixel_rate =3D pixel_rate_orig =3D ctrl->panel->msm_dp_mode.drm_mode.cloc= k; + + if (msm_dp_ctrl->wide_bus_en || ctrl->panel->msm_dp_mode.out_fmt_is_yuv_4= 20) + pixel_rate >>=3D 1; + + drm_dbg_dp(ctrl->drm_dev, "pixel_rate=3D%lu\n", pixel_rate); + ret =3D clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); if (ret) { DRM_ERROR("Failed to set pixel clock rate. ret=3D%d\n", ret); @@ -2497,12 +2518,6 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp= _ctrl, bool force_link_train ctrl->stream_clks_on =3D true; } =20 - if (force_link_train || !msm_dp_ctrl_channel_eq_ok(ctrl)) - msm_dp_ctrl_link_retrain(ctrl); - - /* stop txing train pattern to end link training */ - msm_dp_ctrl_clear_training_pattern(ctrl, DP_PHY_DPRX); - /* * Set up transfer unit values and set controller state to send * video. diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index f68bee62713f1650354b37edb8e1d76134d8d395..1497f1a8fc2f00991356663c19c= 87eb9fad48a73 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -17,7 +17,8 @@ struct msm_dp_ctrl { struct phy; =20 int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, bool force_link= _train); +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl); +int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train); void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 632a1191e4e48fecd7dbda2f6ec6b8ed0aeebc93..36a12150925246b168acbabf77d= 1206a1ef8eff5 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -674,7 +674,42 @@ static int msm_dp_display_set_mode(struct msm_dp *msm_= dp_display, return 0; } =20 -static int msm_dp_display_enable(struct msm_dp_display_private *dp, bool f= orce_link_train) +static int msm_dp_display_prepare(struct msm_dp_display_private *dp) +{ + int rc =3D 0; + struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; + bool force_link_train =3D false; + + drm_dbg_dp(dp->drm_dev, "sink_count=3D%d\n", dp->link->sink_count); + + rc =3D pm_runtime_resume_and_get(&msm_dp_display->pdev->dev); + if (rc) { + DRM_ERROR("failed to pm_runtime_resume\n"); + return rc; + } + + if (dp->link->sink_count =3D=3D 0) + return rc; + + if (msm_dp_display->link_ready && !msm_dp_display->power_on) { + msm_dp_display_host_phy_init(dp); + force_link_train =3D true; + } + + rc =3D msm_dp_ctrl_on_link(dp->ctrl); + if (rc) { + DRM_ERROR("Failed link training (rc=3D%d)\n", rc); + msm_dp_display->connector->state->link_status =3D DRM_LINK_STATUS_BAD; + } + + rc =3D msm_dp_ctrl_prepare_stream_on(dp->ctrl, force_link_train); + if (!rc) + msm_dp_display->prepared =3D true; + + return rc; +} + +static int msm_dp_display_enable(struct msm_dp_display_private *dp) { int rc =3D 0; struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; @@ -685,7 +720,7 @@ static int msm_dp_display_enable(struct msm_dp_display_= private *dp, bool force_l return 0; } =20 - rc =3D msm_dp_ctrl_on_stream(dp->ctrl, force_link_train); + rc =3D msm_dp_ctrl_on_stream(dp->ctrl); if (!rc) msm_dp_display->power_on =3D true; =20 @@ -715,13 +750,10 @@ static int msm_dp_display_post_enable(struct msm_dp *= msm_dp_display) return 0; } =20 -static int msm_dp_display_disable(struct msm_dp_display_private *dp) +static void msm_dp_display_audio_notify_disable(struct msm_dp_display_priv= ate *dp) { struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; =20 - if (!msm_dp_display->power_on) - return 0; - /* wait only if audio was enabled */ if (msm_dp_display->audio_enabled) { /* signal the disconnect event */ @@ -732,6 +764,14 @@ static int msm_dp_display_disable(struct msm_dp_displa= y_private *dp) } =20 msm_dp_display->audio_enabled =3D false; +} + +static int msm_dp_display_disable(struct msm_dp_display_private *dp) +{ + struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; + + if (!msm_dp_display->power_on) + return 0; =20 if (dp->link->sink_count =3D=3D 0) { /* @@ -1395,44 +1435,34 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge = *drm_bridge, struct drm_atomic_state *state) { struct msm_dp_bridge *msm_dp_bridge =3D to_dp_bridge(drm_bridge); - struct msm_dp *dp =3D msm_dp_bridge->msm_dp_display; + struct msm_dp *msm_dp_display =3D msm_dp_bridge->msm_dp_display; int rc =3D 0; - struct msm_dp_display_private *msm_dp_display; - bool force_link_train =3D false; - - msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); - - if (dp->is_edp) - msm_dp_hpd_plug_handle(msm_dp_display, 0); - - if (pm_runtime_resume_and_get(&dp->pdev->dev)) { - DRM_ERROR("failed to pm_runtime_resume\n"); - return; - } + struct msm_dp_display_private *dp; =20 - if (msm_dp_display->link->sink_count =3D=3D 0) - return; + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - if (dp->link_ready && !dp->power_on) { - msm_dp_display_host_phy_init(msm_dp_display); - force_link_train =3D true; - } + if (msm_dp_display->is_edp) + msm_dp_hpd_plug_handle(dp, 0); =20 - rc =3D msm_dp_ctrl_on_link(msm_dp_display->ctrl); + rc =3D msm_dp_display_prepare(dp); if (rc) { - DRM_ERROR("Failed link training (rc=3D%d)\n", rc); - dp->connector->state->link_status =3D DRM_LINK_STATUS_BAD; + DRM_ERROR("DP display prepare failed, rc=3D%d\n", rc); + return; } =20 - msm_dp_display_enable(msm_dp_display, force_link_train); + if (msm_dp_display->prepared) { + rc =3D msm_dp_display_enable(dp); + if (rc) + DRM_ERROR("DP display enable failed, rc=3D%d\n", rc); =20 - rc =3D msm_dp_display_post_enable(dp); - if (rc) { - DRM_ERROR("DP display post enable failed, rc=3D%d\n", rc); - msm_dp_display_disable(msm_dp_display); + rc =3D msm_dp_display_post_enable(msm_dp_display); + if (rc) { + DRM_ERROR("DP display post enable failed, rc=3D%d\n", rc); + msm_dp_display_disable(dp); + } } =20 - drm_dbg_dp(dp->drm_dev, "type=3D%d Done\n", dp->connector_type); + drm_dbg_dp(msm_dp_display->drm_dev, "type=3D%d Done\n", msm_dp_display->c= onnector_type); } =20 void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, @@ -1447,6 +1477,15 @@ void msm_dp_bridge_atomic_disable(struct drm_bridge = *drm_bridge, msm_dp_ctrl_push_idle(msm_dp_display->ctrl); } =20 +static void msm_dp_display_unprepare(struct msm_dp_display_private *dp) +{ + struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; + + pm_runtime_put_sync(&msm_dp_display->pdev->dev); + + msm_dp_display->prepared =3D false; +} + void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, struct drm_atomic_state *state) { @@ -1462,11 +1501,13 @@ void msm_dp_bridge_atomic_post_disable(struct drm_b= ridge *drm_bridge, if (!dp->link_ready) drm_dbg_dp(dp->drm_dev, "type=3D%d is disconnected\n", dp->connector_typ= e); =20 + msm_dp_display_audio_notify_disable(msm_dp_display); + msm_dp_display_disable(msm_dp_display); =20 - drm_dbg_dp(dp->drm_dev, "type=3D%d Done\n", dp->connector_type); + msm_dp_display_unprepare(msm_dp_display); =20 - pm_runtime_put_sync(&dp->pdev->dev); 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However with a slight rework this can still be handled by keeping common paths same for regular and special case. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 19 +------------------ drivers/gpu/drm/msm/dp/dp_ctrl.h | 3 ++- drivers/gpu/drm/msm/dp/dp_display.c | 10 +++++++++- 3 files changed, 12 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 6bfd8faa1e212c3a25964677a4462e7a3a162fa4..e1ff4c6bb4f0eed2e1ff931f12b= a891cf81feffb 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2549,7 +2549,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl) return ret; } =20 -void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_dp_ctrl) { struct msm_dp_ctrl_private *ctrl; struct phy *phy; @@ -2557,23 +2557,6 @@ void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl = *msm_dp_ctrl) ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); phy =3D ctrl->phy; =20 - msm_dp_panel_disable_vsc_sdp(ctrl->panel); - - /* set dongle to D3 (power off) mode */ - msm_dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true); - - msm_dp_ctrl_mainlink_disable(ctrl); - - if (ctrl->stream_clks_on) { - clk_disable_unprepare(ctrl->pixel_clk); - ctrl->stream_clks_on =3D false; - } - - dev_pm_opp_set_rate(ctrl->dev, 0); - msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); - - phy_power_off(phy); - /* aux channel down, reinit phy */ phy_exit(phy); phy_init(phy); diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index 1497f1a8fc2f00991356663c19c87eb9fad48a73..93747c0a9b3f049bc877f347f05= d42b66ad0dddf 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -19,7 +19,6 @@ struct phy; int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl); int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train); -void msm_dp_ctrl_off_link_stream(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl); @@ -46,4 +45,6 @@ void msm_dp_ctrl_core_clk_disable(struct msm_dp_ctrl *msm= _dp_ctrl); void msm_dp_ctrl_enable_irq(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_ctrl); =20 +void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_dp_ctrl); + #endif /* _DP_CTRL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 36a12150925246b168acbabf77d1206a1ef8eff5..4c74eb2915fd620868f658ccafc= 32030b1c208c6 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -773,12 +773,20 @@ static int msm_dp_display_disable(struct msm_dp_displ= ay_private *dp) if (!msm_dp_display->power_on) return 0; =20 + msm_dp_panel_disable_vsc_sdp(dp->panel); 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Currently, msm_dp_ctrl_config_ctrl() configures all of them together, which makes it harder to support MST. This patch separates the configuration into two functions: - msm_dp_ctrl_config_ctrl_link(): handles link-related fields - msm_dp_ctrl_config_ctrl_streams(): handles stream-specific fields It also moves the link-related configuration out of msm_dp_ctrl_configure_source_params(). Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 49 +++++++++++++++++++++++++-----------= ---- 1 file changed, 31 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index e1ff4c6bb4f0eed2e1ff931f12ba891cf81feffb..45d6c9a7f7ddaa049443253cbf4= c6fc5feda3177 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -380,26 +380,41 @@ void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp= _ctrl) drm_dbg_dp(ctrl->drm_dev, "mainlink off\n"); } =20 -static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctrl_private *ctrl) +static void msm_dp_ctrl_config_ctrl_streams(struct msm_dp_ctrl_private *ct= rl, + struct msm_dp_panel *msm_dp_panel) { u32 config =3D 0, tbd; + + config =3D msm_dp_read_link(ctrl, REG_DP_CONFIGURATION_CTRL); + + if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) + config |=3D DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */ + + tbd =3D msm_dp_link_get_test_bits_depth(ctrl->link, + msm_dp_panel->msm_dp_mode.bpp); + + config |=3D tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT; + + if (msm_dp_panel->psr_cap.version) + config |=3D DP_CONFIGURATION_CTRL_SEND_VSC; + + drm_dbg_dp(ctrl->drm_dev, "stream DP_CONFIGURATION_CTRL=3D0x%x\n", config= ); + + msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); +} + +static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl) +{ + u32 config =3D 0; const u8 *dpcd =3D ctrl->panel->dpcd; =20 /* Default-> LSCLK DIV: 1/4 LCLK */ config |=3D (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT); =20 - if (ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420) - config |=3D DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */ - /* Scrambler reset enable */ if (drm_dp_alternate_scrambler_reset_cap(dpcd)) config |=3D DP_CONFIGURATION_CTRL_ASSR; =20 - tbd =3D msm_dp_link_get_test_bits_depth(ctrl->link, - ctrl->panel->msm_dp_mode.bpp); - - config |=3D tbd << DP_CONFIGURATION_CTRL_BPC_SHIFT; - /* Num of Lanes */ config |=3D ((ctrl->link->link_params.num_lanes - 1) << DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT); @@ -413,10 +428,7 @@ static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctrl= _private *ctrl) config |=3D DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN; config |=3D DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK; =20 - if (ctrl->panel->psr_cap.version) - config |=3D DP_CONFIGURATION_CTRL_SEND_VSC; - - drm_dbg_dp(ctrl->drm_dev, "DP_CONFIGURATION_CTRL=3D0x%x\n", config); + drm_dbg_dp(ctrl->drm_dev, "link DP_CONFIGURATION_CTRL=3D0x%x\n", config); =20 msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); } @@ -439,10 +451,7 @@ static void msm_dp_ctrl_configure_source_params(struct= msm_dp_ctrl_private *ctrl { u32 colorimetry_cfg, test_bits_depth, misc_val; =20 - msm_dp_ctrl_lane_mapping(ctrl); - msm_dp_setup_peripheral_flush(ctrl); - - msm_dp_ctrl_config_ctrl(ctrl); + msm_dp_ctrl_config_ctrl_streams(ctrl, ctrl->panel); =20 test_bits_depth =3D msm_dp_link_get_test_bits_depth(ctrl->link, ctrl->pan= el->msm_dp_mode.bpp); colorimetry_cfg =3D msm_dp_link_get_colorimetry_config(ctrl->link); @@ -1614,7 +1623,7 @@ static int msm_dp_ctrl_link_train(struct msm_dp_ctrl_= private *ctrl, u8 assr; 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To improve code clarity and modularity, this patch refactors the related code into a new helper function: msm_dp_ctrl_config_misc1_misc0(). This separation also prepares the codebase for future MST stream programming support. Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 45d6c9a7f7ddaa049443253cbf4c6fc5feda3177..6bfb639c1ebd33f1103c5b68dfb= 40701738fa267 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -447,13 +447,13 @@ static void msm_dp_ctrl_lane_mapping(struct msm_dp_ct= rl_private *ctrl) ln_mapping); } =20 -static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private= *ctrl) +static void msm_dp_ctrl_config_misc1_misc0(struct msm_dp_ctrl_private *ctr= l, + struct msm_dp_panel *msm_dp_panel) { u32 colorimetry_cfg, test_bits_depth, misc_val; =20 - msm_dp_ctrl_config_ctrl_streams(ctrl, ctrl->panel); - - test_bits_depth =3D msm_dp_link_get_test_bits_depth(ctrl->link, ctrl->pan= el->msm_dp_mode.bpp); + test_bits_depth =3D msm_dp_link_get_test_bits_depth(ctrl->link, + msm_dp_panel->msm_dp_mode.bpp); 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However with MST, the cached panel represents the fixed link and not the sinks which are hotplugged. Allow the stream related APIs to work on the panel which is passed to them rather than the cached one. For SST cases, this shall continue to use the cached dp_panel. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 21 +++++++++++---------- drivers/gpu/drm/msm/dp/dp_ctrl.h | 2 +- drivers/gpu/drm/msm/dp/dp_display.c | 2 +- 3 files changed, 13 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 6bfb639c1ebd33f1103c5b68dfb40701738fa267..261907446135904a9e479f18051= 974f5fea88ef1 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -469,13 +469,14 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm= _dp_ctrl_private *ctrl, msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0, misc_val); } =20 -static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private= *ctrl) +static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private= *ctrl, + struct msm_dp_panel *msm_dp_panel) { - msm_dp_ctrl_config_ctrl_streams(ctrl, ctrl->panel); + msm_dp_ctrl_config_ctrl_streams(ctrl, msm_dp_panel); =20 - msm_dp_ctrl_config_misc1_misc0(ctrl, ctrl->panel); + msm_dp_ctrl_config_misc1_misc0(ctrl, msm_dp_panel); =20 - msm_dp_panel_timing_cfg(ctrl->panel, ctrl->msm_dp_ctrl.wide_bus_en); + msm_dp_panel_timing_cfg(msm_dp_panel, ctrl->msm_dp_ctrl.wide_bus_en); } =20 /* @@ -2497,7 +2498,7 @@ int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl = *msm_dp_ctrl, bool force_li return ret; } =20 -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl) +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_p= anel *msm_dp_panel) { int ret =3D 0; bool mainlink_ready =3D false; @@ -2510,9 +2511,9 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl) =20 ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 - pixel_rate =3D pixel_rate_orig =3D ctrl->panel->msm_dp_mode.drm_mode.cloc= k; + pixel_rate =3D pixel_rate_orig =3D msm_dp_panel->msm_dp_mode.drm_mode.clo= ck; =20 - if (msm_dp_ctrl->wide_bus_en || ctrl->panel->msm_dp_mode.out_fmt_is_yuv_4= 20) + if (msm_dp_ctrl->wide_bus_en || msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_= 420) pixel_rate >>=3D 1; =20 drm_dbg_dp(ctrl->drm_dev, "pixel_rate=3D%lu\n", pixel_rate); @@ -2544,14 +2545,14 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_d= p_ctrl) msm_dp_setup_peripheral_flush(ctrl); msm_dp_ctrl_config_ctrl_link(ctrl); =20 - msm_dp_ctrl_configure_source_params(ctrl); + msm_dp_ctrl_configure_source_params(ctrl, msm_dp_panel); =20 msm_dp_ctrl_config_msa(ctrl, ctrl->link->link_params.rate, pixel_rate_orig, - ctrl->panel->msm_dp_mode.out_fmt_is_yuv_420); + msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420); =20 - msm_dp_panel_clear_dsc_dto(ctrl->panel); + msm_dp_panel_clear_dsc_dto(msm_dp_panel); =20 msm_dp_ctrl_setup_tr_unit(ctrl); =20 diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index 93747c0a9b3f049bc877f347f05d42b66ad0dddf..78406c757eccf95e82f1a9d4437= ebdbbc4f8ea46 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -17,7 +17,7 @@ struct msm_dp_ctrl { struct phy; =20 int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); 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Move it into individual helpers so that the helpers can be called wherever necessary. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 77 +++++++++++++++++++++---------------= ---- 1 file changed, 41 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 261907446135904a9e479f18051974f5fea88ef1..c0001b93a194821927507028f39= 2877db585fd2c 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2162,6 +2162,42 @@ static bool msm_dp_ctrl_send_phy_test_pattern(struct= msm_dp_ctrl_private *ctrl) return success; } =20 +static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctrl_private *ctrl, unsi= gned long pixel_rate) +{ + int ret; + + ret =3D clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); + if (ret) { + DRM_ERROR("Failed to set pixel clock rate. ret=3D%d\n", ret); + return ret; + } + + if (ctrl->stream_clks_on) { + drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); + } else { + ret =3D clk_prepare_enable(ctrl->pixel_clk); + if (ret) { + DRM_ERROR("Failed to start pixel clocks. ret=3D%d\n", ret); + return ret; + } + ctrl->stream_clks_on =3D true; + } + + return ret; +} + +static void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl) +{ + struct msm_dp_ctrl_private *ctrl; + + ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); + + if (ctrl->stream_clks_on) { + clk_disable_unprepare(ctrl->pixel_clk); + ctrl->stream_clks_on =3D false; + } +} + static int msm_dp_ctrl_process_phy_test_request(struct msm_dp_ctrl_private= *ctrl) { int ret; @@ -2187,22 +2223,7 @@ static int msm_dp_ctrl_process_phy_test_request(stru= ct msm_dp_ctrl_private *ctrl } =20 pixel_rate =3D ctrl->panel->msm_dp_mode.drm_mode.clock; - ret =3D clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); - if (ret) { - DRM_ERROR("Failed to set pixel clock rate. ret=3D%d\n", ret); - return ret; - } - - if (ctrl->stream_clks_on) { - drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); - } else { - ret =3D clk_prepare_enable(ctrl->pixel_clk); - if (ret) { - DRM_ERROR("Failed to start pixel clocks. ret=3D%d\n", ret); - return ret; - } - ctrl->stream_clks_on =3D true; - } + ret =3D msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); =20 msm_dp_ctrl_send_phy_test_pattern(ctrl); =20 @@ -2518,21 +2539,10 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_d= p_ctrl, struct msm_dp_panel * =20 drm_dbg_dp(ctrl->drm_dev, "pixel_rate=3D%lu\n", pixel_rate); =20 - ret =3D clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); + ret =3D msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); if (ret) { - DRM_ERROR("Failed to set pixel clock rate. ret=3D%d\n", ret); - goto end; - } - - if (ctrl->stream_clks_on) { - drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); - } else { - ret =3D clk_prepare_enable(ctrl->pixel_clk); - if (ret) { - DRM_ERROR("Failed to start pixel clocks. ret=3D%d\n", ret); - goto end; - } - ctrl->stream_clks_on =3D true; + DRM_ERROR("failed to enable pixel clk\n"); + return ret; } =20 /* @@ -2566,7 +2576,6 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, struct msm_dp_panel * drm_dbg_dp(ctrl->drm_dev, "mainlink %s\n", mainlink_ready ? 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Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 8 ++++---- drivers/gpu/drm/msm/dp/dp_ctrl.h | 3 ++- drivers/gpu/drm/msm/dp/dp_display.c | 6 ++++-- 3 files changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index c0001b93a194821927507028f392877db585fd2c..b25eb2fa2835f660073b5109496= ac9f2f4e038d2 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2186,7 +2186,7 @@ static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctr= l_private *ctrl, unsigned l return ret; } =20 -static void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl) { struct msm_dp_ctrl_private *ctrl; =20 @@ -2214,7 +2214,8 @@ static int msm_dp_ctrl_process_phy_test_request(struc= t msm_dp_ctrl_private *ctrl * running. Add the global reset just before disabling the * link clocks and core clocks. */ - msm_dp_ctrl_off(&ctrl->msm_dp_ctrl); + msm_dp_ctrl_off_pixel_clk(&ctrl->msm_dp_ctrl); + msm_dp_ctrl_off_link(&ctrl->msm_dp_ctrl); =20 ret =3D msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl); if (ret) { @@ -2595,7 +2596,7 @@ void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_d= p_ctrl) phy, phy->init_count, phy->power_count); } =20 -void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl) { struct msm_dp_ctrl_private *ctrl; struct phy *phy; @@ -2609,7 +2610,6 @@ void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl) =20 msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); =20 - msm_dp_ctrl_off_pixel_clk(msm_dp_ctrl); dev_pm_opp_set_rate(ctrl->dev, 0); msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); =20 diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index 78406c757eccf95e82f1a9d4437ebdbbc4f8ea46..6ff3e9d9fa6ff0afa325a7a6f72= a15009635f340 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -19,7 +19,8 @@ struct phy; int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_p= anel *msm_dp_panel); int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train); -void msm_dp_ctrl_off(struct msm_dp_ctrl *msm_dp_ctrl); +void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl); +void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_handle_sink_request(struct msm_dp_ctrl *msm_dp_ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index d07bb40f848e0e13a0fa32aa70ffb1621edca159..c5c502e51b94a6ac4b9a893b43e= b88e87a0c0d46 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -784,7 +784,8 @@ static int msm_dp_display_disable(struct msm_dp_display= _private *dp) =20 /* set dongle to D3 (power off) mode */ msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); 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Rather than doing it in a roundabout way, directly pass the dp_display object to these helpers so that the MST bridge can also re-use the same helpers. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 34 ++++++++----------------- drivers/gpu/drm/msm/dp/dp_display.h | 9 +++++++ drivers/gpu/drm/msm/dp/dp_drm.c | 49 +++++++++++++++++++++++++++++++++= +++- drivers/gpu/drm/msm/dp/dp_drm.h | 12 --------- 4 files changed, 67 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index c5c502e51b94a6ac4b9a893b43eb88e87a0c0d46..8e95cfb98bd08088a707ffb5643= a5021a288095f 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -806,24 +806,21 @@ static int msm_dp_display_disable(struct msm_dp_displ= ay_private *dp) =20 /** * msm_dp_bridge_mode_valid - callback to determine if specified mode is v= alid - * @bridge: Pointer to drm bridge structure + * @dp: Pointer to dp display structure * @info: display info * @mode: Pointer to drm mode structure * Returns: Validity status for specified mode */ -enum drm_mode_status msm_dp_bridge_mode_valid(struct drm_bridge *bridge, - const struct drm_display_info *info, - const struct drm_display_mode *mode) +enum drm_mode_status msm_dp_display_mode_valid(struct msm_dp *dp, + const struct drm_display_info *info, + const struct drm_display_mode *mode) { const u32 num_components =3D 3, default_bpp =3D 24; struct msm_dp_display_private *msm_dp_display; struct msm_dp_link_info *link_info; u32 mode_rate_khz =3D 0, supported_rate_khz =3D 0, mode_bpp =3D 0; - struct msm_dp *dp; int mode_pclk_khz =3D mode->clock; =20 - dp =3D to_dp_bridge(bridge)->msm_dp_display; - if (!dp || !mode_pclk_khz || !dp->connector) { DRM_ERROR("invalid params\n"); return -EINVAL; @@ -1441,11 +1438,8 @@ int msm_dp_modeset_init(struct msm_dp *msm_dp_displa= y, struct drm_device *dev, return 0; } =20 -void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, - struct drm_atomic_state *state) +void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display) { - struct msm_dp_bridge *msm_dp_bridge =3D to_dp_bridge(drm_bridge); - struct msm_dp *msm_dp_display =3D msm_dp_bridge->msm_dp_display; int rc =3D 0; struct msm_dp_display_private *dp; =20 @@ -1475,11 +1469,8 @@ void msm_dp_bridge_atomic_enable(struct drm_bridge *= drm_bridge, drm_dbg_dp(msm_dp_display->drm_dev, "type=3D%d Done\n", msm_dp_display->c= onnector_type); } =20 -void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, - struct drm_atomic_state *state) +void msm_dp_display_atomic_disable(struct msm_dp *dp) { - struct msm_dp_bridge *msm_dp_bridge =3D to_dp_bridge(drm_bridge); - struct msm_dp *dp =3D msm_dp_bridge->msm_dp_display; struct msm_dp_display_private *msm_dp_display; =20 msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); @@ -1496,11 +1487,8 @@ static void msm_dp_display_unprepare(struct msm_dp_d= isplay_private *dp) msm_dp_display->prepared =3D false; } =20 -void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridge, - struct drm_atomic_state *state) +void msm_dp_display_atomic_post_disable(struct msm_dp *dp) { - struct msm_dp_bridge *msm_dp_bridge =3D to_dp_bridge(drm_bridge); - struct msm_dp *dp =3D msm_dp_bridge->msm_dp_display; struct msm_dp_display_private *msm_dp_display; =20 msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); @@ -1520,12 +1508,10 @@ void msm_dp_bridge_atomic_post_disable(struct drm_b= ridge *drm_bridge, drm_dbg_dp(dp->drm_dev, "type=3D%d Done\n", dp->connector_type); } =20 -void msm_dp_bridge_mode_set(struct drm_bridge *drm_bridge, - const struct drm_display_mode *mode, - const struct drm_display_mode *adjusted_mode) +void msm_dp_display_mode_set(struct msm_dp *dp, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode) { - struct msm_dp_bridge *msm_dp_bridge =3D to_dp_bridge(drm_bridge); - struct msm_dp *dp =3D msm_dp_bridge->msm_dp_display; struct msm_dp_display_private *msm_dp_display; struct msm_dp_panel *msm_dp_panel; =20 diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index 2fbf16f27842bb7639efaa2baecac7bdf8908432..e12496ac73f853a2bc120e68eeb= 84e5a2de6aabe 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -36,5 +36,14 @@ void msm_dp_display_signal_audio_start(struct msm_dp *ms= m_dp_display); void msm_dp_display_signal_audio_complete(struct msm_dp *msm_dp_display); void msm_dp_display_set_psr(struct msm_dp *dp, bool enter); void msm_dp_display_debugfs_init(struct msm_dp *msm_dp_display, struct den= try *dentry, bool is_edp); +void msm_dp_display_atomic_post_disable(struct msm_dp *dp_display); +void msm_dp_display_atomic_disable(struct msm_dp *dp_display); +void msm_dp_display_atomic_enable(struct msm_dp *dp_display); +void msm_dp_display_mode_set(struct msm_dp *dp, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode); +enum drm_mode_status msm_dp_display_mode_valid(struct msm_dp *dp, + const struct drm_display_info *info, + const struct drm_display_mode *mode); =20 #endif /* _DP_DISPLAY_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_dr= m.c index f935093c4df4681770ab487916584cc76834b0d0..b6b77ee96c30ca60e31cf76569e= 262a237493aeb 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_drm.c @@ -81,6 +81,53 @@ static void msm_dp_bridge_debugfs_init(struct drm_bridge= *bridge, struct dentry msm_dp_display_debugfs_init(dp, root, false); } =20 +static void msm_dp_bridge_atomic_enable(struct drm_bridge *drm_bridge, + struct drm_atomic_state *state) +{ + struct msm_dp_bridge *dp_bridge =3D to_dp_bridge(drm_bridge); + struct msm_dp *dp =3D dp_bridge->msm_dp_display; + + msm_dp_display_atomic_enable(dp); +} + +static void msm_dp_bridge_atomic_disable(struct drm_bridge *drm_bridge, + struct drm_atomic_state *state) +{ + struct msm_dp_bridge *dp_bridge =3D to_dp_bridge(drm_bridge); + struct msm_dp *dp =3D dp_bridge->msm_dp_display; + + msm_dp_display_atomic_disable(dp); +} + +static void msm_dp_bridge_atomic_post_disable(struct drm_bridge *drm_bridg= e, + struct drm_atomic_state *state) +{ + struct msm_dp_bridge *dp_bridge =3D to_dp_bridge(drm_bridge); + struct msm_dp *dp =3D dp_bridge->msm_dp_display; + + msm_dp_display_atomic_post_disable(dp); +} + +static void msm_dp_bridge_mode_set(struct drm_bridge *drm_bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode) +{ + struct msm_dp_bridge *dp_bridge =3D to_dp_bridge(drm_bridge); + struct msm_dp *dp =3D dp_bridge->msm_dp_display; + + msm_dp_display_mode_set(dp, mode, adjusted_mode); +} + +static enum drm_mode_status msm_dp_bridge_mode_valid(struct drm_bridge *dr= m_bridge, + const struct drm_display_info *info, + const struct drm_display_mode *mode) +{ + struct msm_dp_bridge *dp_bridge =3D to_dp_bridge(drm_bridge); + struct msm_dp *dp =3D dp_bridge->msm_dp_display; + + return msm_dp_display_mode_valid(dp, info, mode); +} + static const struct drm_bridge_funcs msm_dp_bridge_ops =3D { .atomic_duplicate_state =3D drm_atomic_helper_bridge_duplicate_state, .atomic_destroy_state =3D drm_atomic_helper_bridge_destroy_state, @@ -149,7 +196,7 @@ static void msm_edp_bridge_atomic_enable(struct drm_bri= dge *drm_bridge, return; } =20 - msm_dp_bridge_atomic_enable(drm_bridge, state); + msm_dp_display_atomic_enable(dp); } =20 static void msm_edp_bridge_atomic_disable(struct drm_bridge *drm_bridge, diff --git a/drivers/gpu/drm/msm/dp/dp_drm.h b/drivers/gpu/drm/msm/dp/dp_dr= m.h index 0d026bc9becf777aee192b9200197f477012bf8f..1066bb181a50b462203647618db= 6386e72a8eb32 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.h +++ b/drivers/gpu/drm/msm/dp/dp_drm.h @@ -26,18 +26,6 @@ int msm_dp_bridge_init(struct msm_dp *msm_dp_display, st= ruct drm_device *dev, bool yuv_supported); =20 enum drm_connector_status msm_dp_bridge_detect(struct drm_bridge *bridge, = struct drm_connector *connector); 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Hence separate it into its own API. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 16 ++++++++++++---- drivers/gpu/drm/msm/dp/dp_display.h | 1 + drivers/gpu/drm/msm/dp/dp_drm.c | 2 ++ 3 files changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 8e95cfb98bd08088a707ffb5643a5021a288095f..78d932bceb581ee54116926506b= 1025bd159108f 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -1438,7 +1438,7 @@ int msm_dp_modeset_init(struct msm_dp *msm_dp_display= , struct drm_device *dev, return 0; } =20 -void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display) +void msm_dp_display_atomic_prepare(struct msm_dp *msm_dp_display) { int rc =3D 0; struct msm_dp_display_private *dp; @@ -1449,10 +1449,18 @@ void msm_dp_display_atomic_enable(struct msm_dp *ms= m_dp_display) msm_dp_hpd_plug_handle(dp, 0); =20 rc =3D msm_dp_display_prepare(dp); - if (rc) { + if (rc) DRM_ERROR("DP display prepare failed, rc=3D%d\n", rc); - return; - } + + return; +} + +void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display) +{ + struct msm_dp_display_private *dp; + int rc =3D 0; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 if (msm_dp_display->prepared) { rc =3D msm_dp_display_enable(dp); diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index e12496ac73f853a2bc120e68eeb84e5a2de6aabe..37c6e87db90ce951274cdae61f2= 6d76dc9ef3840 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -38,6 +38,7 @@ void msm_dp_display_set_psr(struct msm_dp *dp, bool enter= ); void msm_dp_display_debugfs_init(struct msm_dp *msm_dp_display, struct den= try *dentry, bool is_edp); void msm_dp_display_atomic_post_disable(struct msm_dp *dp_display); void msm_dp_display_atomic_disable(struct msm_dp *dp_display); +void msm_dp_display_atomic_prepare(struct msm_dp *dp_display); void msm_dp_display_atomic_enable(struct msm_dp *dp_display); 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Most platforms support 2 or 4 MST streams, while platforms without MST support default to a single stream (`DEFAULT_STREAM_COUNT =3D 1`). This change also accounts for platforms with asymmetric stream support, e.g., DP0 supporting 4 streams and DP1 supporting 2. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 21 +++++++++++++++++++++ drivers/gpu/drm/msm/dp/dp_display.h | 1 + 2 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 78d932bceb581ee54116926506b1025bd159108f..a8477a0a180137f15cbb1401c39= 64636aa32626c 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -33,6 +33,7 @@ module_param(psr_enabled, bool, 0); MODULE_PARM_DESC(psr_enabled, "enable PSR for eDP and DP displays"); =20 #define HPD_STRING_SIZE 30 +#define DEFAULT_STREAM_COUNT 1 =20 enum { ISR_DISCONNECTED, @@ -52,6 +53,7 @@ struct msm_dp_display_private { bool core_initialized; bool phy_initialized; bool audio_supported; + bool mst_supported; =20 struct drm_device *drm_dev; =20 @@ -84,12 +86,15 @@ struct msm_dp_display_private { =20 void __iomem *p0_base; size_t p0_len; + + int max_stream; }; =20 struct msm_dp_desc { phys_addr_t io_start; unsigned int id; bool wide_bus_supported; + int mst_streams; }; =20 static const struct msm_dp_desc msm_dp_desc_sa8775p[] =3D { @@ -1213,6 +1218,15 @@ static int msm_dp_display_get_io(struct msm_dp_displ= ay_private *display) return 0; } =20 +int msm_dp_get_mst_max_stream(struct msm_dp *msm_dp_display) +{ + struct msm_dp_display_private *dp; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); + + return dp->max_stream; +} + static int msm_dp_display_probe(struct platform_device *pdev) { int rc =3D 0; @@ -1239,6 +1253,13 @@ static int msm_dp_display_probe(struct platform_devi= ce *pdev) dp->msm_dp_display.is_edp =3D (dp->msm_dp_display.connector_type =3D=3D DRM_MODE_CONNECTOR_eDP); dp->hpd_isr_status =3D 0; + dp->max_stream =3D DEFAULT_STREAM_COUNT; + dp->mst_supported =3D FALSE; + + if (desc->mst_streams > DEFAULT_STREAM_COUNT) { + dp->max_stream =3D desc->mst_streams; + dp->mst_supported =3D TRUE; + } =20 rc =3D msm_dp_display_get_io(dp); if (rc) diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index 37c6e87db90ce951274cdae61f26d76dc9ef3840..7727cf325a89b4892d2370a5616= c4fa76fc88485 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -29,6 +29,7 @@ struct msm_dp { bool psr_supported; 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a=ed25519-sha256; t=1756131420; l=12337; i=yongxing.mou@oss.qualcomm.com; s=20241121; h=from:subject:message-id; bh=8mqJWU084vDxzCM+Kcn603L6BY3TiY78EJVx8yyw1MM=; b=ufHWehrJK/WfU/3m4tznClnPqHyNs67vJ3ZIVkpU5r6KGcSbNBOJidQk4EhrorYYqA5cWB5RC 2Soq7FwFV+RDt+ksCITiXA3hpyKI0yBNMugKXFpnYzmgJuUAS7g0qSD X-Developer-Key: i=yongxing.mou@oss.qualcomm.com; a=ed25519; pk=zeCnFRUqtOQMeFvdwex2M5o0Yf67UHYfwCyBRQ3kFbU= X-Authority-Analysis: v=2.4 cv=KOlaDEFo c=1 sm=1 tr=0 ts=68ac709c cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=Uz3yg00KUFJ2y2WijEJ4bw==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=3Q5v3ENETf2jWLhp-IIA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: kzPa7XQkjWT7Zq1SqvRkaOL-NBmp2XHT X-Proofpoint-ORIG-GUID: kzPa7XQkjWT7Zq1SqvRkaOL-NBmp2XHT X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODIzMDAzMyBTYWx0ZWRfX2s/N3jGMMzoL Oog48KNHmThqUjR3ZiY+n3kUIdNM6hIzhEnmvDrHgRPT/85rAOePwa/mxTfz3qL2QsFyYUVNEWT ZPLoi9Rb0LVBTFYvheeHt5Ntqhsmlay1US7FySMbSUupNx/vLWPoHK1mcjg1tId15Uw3TIy0zDH VW/EaQgiPt49cE/gmRtXx8YLkDEtNh1uVrIOmNE4IunZTSweVI3iH2XdTqD3LyO4+uTbUoCtsOQ jn/u588TJ9eaVOK1ngcHRVgqqiS3nRj98VMM1NfAvG5DG60MutywFuZozqOs0ODkXUwUceu+5q4 hKA/kZxqJBtD8ZW7zH8qWlP3OFvl69z76x65kgYbyywGdLizHXrOD4jsrVFMCcXtFYp0dbDO2a6 oH8u2ohV X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-25_07,2025-08-20_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 bulkscore=0 adultscore=0 phishscore=0 impostorscore=0 spamscore=0 suspectscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508230033 From: Abhinav Kumar With MST, each DP controller can handle multiple streams. There shall be one dp_panel for each stream but the dp_display object shall be shared among them. To represent this abstraction, create a stream_id for each DP panel which shall be set by the MST stream. For SST, default this to stream 0. Use the stream ID to control the pixel clock of that respective stream by extending the clock handles and state tracking of the DP pixel clock to an array of max supported streams. The maximum streams currently is 4. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 58 ++++++++++++++++++++++-----------= ---- drivers/gpu/drm/msm/dp/dp_ctrl.h | 3 +- drivers/gpu/drm/msm/dp/dp_display.c | 27 +++++++++++++++-- drivers/gpu/drm/msm/dp/dp_display.h | 2 ++ drivers/gpu/drm/msm/dp/dp_panel.h | 11 +++++++ 5 files changed, 73 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index b25eb2fa2835f660073b5109496ac9f2f4e038d2..d4a74c6b70fb182ad8a0a786f85= a0f50982d3858 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -127,7 +127,7 @@ struct msm_dp_ctrl_private { unsigned int num_link_clks; struct clk_bulk_data *link_clks; =20 - struct clk *pixel_clk; + struct clk *pixel_clk[DP_STREAM_MAX]; =20 union phy_configure_opts phy_opts; =20 @@ -139,7 +139,7 @@ struct msm_dp_ctrl_private { =20 bool core_clks_on; bool link_clks_on; - bool stream_clks_on; + bool stream_clks_on[DP_STREAM_MAX]; }; =20 static inline u32 msm_dp_read_ahb(const struct msm_dp_ctrl_private *ctrl, = u32 offset) @@ -2162,39 +2162,40 @@ static bool msm_dp_ctrl_send_phy_test_pattern(struc= t msm_dp_ctrl_private *ctrl) return success; } =20 -static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctrl_private *ctrl, unsi= gned long pixel_rate) +static int msm_dp_ctrl_on_pixel_clk(struct msm_dp_ctrl_private *ctrl, unsi= gned long pixel_rate, + enum msm_dp_stream_id stream_id) { int ret; =20 - ret =3D clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); + ret =3D clk_set_rate(ctrl->pixel_clk[stream_id], pixel_rate * 1000); if (ret) { DRM_ERROR("Failed to set pixel clock rate. ret=3D%d\n", ret); return ret; } =20 - if (ctrl->stream_clks_on) { + if (ctrl->stream_clks_on[stream_id]) { drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); } else { - ret =3D clk_prepare_enable(ctrl->pixel_clk); + ret =3D clk_prepare_enable(ctrl->pixel_clk[stream_id]); if (ret) { DRM_ERROR("Failed to start pixel clocks. ret=3D%d\n", ret); return ret; } - ctrl->stream_clks_on =3D true; + ctrl->stream_clks_on[stream_id] =3D true; } =20 return ret; } =20 -void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl, enum msm_d= p_stream_id stream_id) { struct msm_dp_ctrl_private *ctrl; =20 ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 - if (ctrl->stream_clks_on) { - clk_disable_unprepare(ctrl->pixel_clk); - ctrl->stream_clks_on =3D false; + if (ctrl->stream_clks_on[stream_id]) { + clk_disable_unprepare(ctrl->pixel_clk[stream_id]); + ctrl->stream_clks_on[stream_id] =3D false; } } =20 @@ -2214,7 +2215,7 @@ static int msm_dp_ctrl_process_phy_test_request(struc= t msm_dp_ctrl_private *ctrl * running. Add the global reset just before disabling the * link clocks and core clocks. */ - msm_dp_ctrl_off_pixel_clk(&ctrl->msm_dp_ctrl); + msm_dp_ctrl_off_pixel_clk(&ctrl->msm_dp_ctrl, ctrl->panel->stream_id); msm_dp_ctrl_off_link(&ctrl->msm_dp_ctrl); =20 ret =3D msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl); @@ -2224,7 +2225,7 @@ static int msm_dp_ctrl_process_phy_test_request(struc= t msm_dp_ctrl_private *ctrl } =20 pixel_rate =3D ctrl->panel->msm_dp_mode.drm_mode.clock; - ret =3D msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); + ret =3D msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate, ctrl->panel->stream_id= ); =20 msm_dp_ctrl_send_phy_test_pattern(ctrl); =20 @@ -2499,9 +2500,8 @@ int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl = *msm_dp_ctrl, bool force_li ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes); =20 - drm_dbg_dp(ctrl->drm_dev, - "core_clk_on=3D%d link_clk_on=3D%d stream_clk_on=3D%d\n", - ctrl->core_clks_on, ctrl->link_clks_on, ctrl->stream_clks_on); + drm_dbg_dp(ctrl->drm_dev, "core_clk_on=3D%d link_clk_on=3D%d\n", + ctrl->core_clks_on, ctrl->link_clks_on); =20 if (!ctrl->link_clks_on) { /* link clk is off */ ret =3D msm_dp_ctrl_enable_mainlink_clocks(ctrl); @@ -2540,7 +2540,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, struct msm_dp_panel * =20 drm_dbg_dp(ctrl->drm_dev, "pixel_rate=3D%lu\n", pixel_rate); =20 - ret =3D msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate); + ret =3D msm_dp_ctrl_on_pixel_clk(ctrl, pixel_rate, msm_dp_panel->stream_i= d); if (ret) { DRM_ERROR("failed to enable pixel clk\n"); return ret; @@ -2604,8 +2604,6 @@ void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_= ctrl) ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); phy =3D ctrl->phy; =20 - msm_dp_panel_disable_vsc_sdp(ctrl->panel); - msm_dp_ctrl_mainlink_disable(ctrl); =20 msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); @@ -2677,10 +2675,11 @@ static const char *ctrl_clks[] =3D { "ctrl_link_iface", }; =20 -static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *msm_dp_ctrl) +static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *msm_dp_ctrl, int max_s= tream) { struct msm_dp_ctrl_private *ctrl; struct device *dev; + char stream_id_str[15]; int i, rc; =20 ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); @@ -2710,9 +2709,19 @@ static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *= msm_dp_ctrl) if (rc) return rc; =20 - ctrl->pixel_clk =3D devm_clk_get(dev, "stream_pixel"); - if (IS_ERR(ctrl->pixel_clk)) - return PTR_ERR(ctrl->pixel_clk); + ctrl->pixel_clk[DP_STREAM_0] =3D devm_clk_get(dev, "stream_pixel"); + if (IS_ERR(ctrl->pixel_clk[DP_STREAM_0])) + return PTR_ERR(ctrl->pixel_clk[DP_STREAM_0]); + + for (i =3D DP_STREAM_1; i < max_stream; i++) { + sprintf(stream_id_str, "stream_%d_pixel", i); + ctrl->pixel_clk[i] =3D devm_clk_get(dev, stream_id_str); + + if (IS_ERR(ctrl->pixel_clk[i])) { + DRM_DEBUG_DP("failed to get stream %d pixel clock", i); + break; + } + } =20 return 0; } @@ -2720,6 +2729,7 @@ static int msm_dp_ctrl_clk_init(struct msm_dp_ctrl *m= sm_dp_ctrl) struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_link= *link, struct msm_dp_panel *panel, struct drm_dp_aux *aux, struct phy *phy, + int max_stream, void __iomem *ahb_base, void __iomem *link_base) { @@ -2762,7 +2772,7 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *de= v, struct msm_dp_link *link ctrl->ahb_base =3D ahb_base; ctrl->link_base =3D link_base; =20 - ret =3D msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl); + ret =3D msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl, max_stream); if (ret) { dev_err(dev, "failed to init clocks\n"); return ERR_PTR(ret); diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index 6ff3e9d9fa6ff0afa325a7a6f72a15009635f340..32ff1455caf0e7fcb1bd74b1f31= 92c6c3c03ee74 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -20,7 +20,7 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_p= anel *msm_dp_panel); int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train); void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl); -void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl); +void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl, enum msm_d= p_stream_id stream_id); void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_handle_sink_request(struct msm_dp_ctrl *msm_dp_ctrl); @@ -29,6 +29,7 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct msm_dp_panel *panel, struct drm_dp_aux *aux, struct phy *phy, + int max_stream, void __iomem *ahb_base, void __iomem *link_base); =20 diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index a8477a0a180137f15cbb1401c3964636aa32626c..3422f18bdec71a99407edfe943d= 31957d0e8847a 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -628,7 +628,7 @@ static int msm_dp_init_sub_modules(struct msm_dp_displa= y_private *dp) } =20 dp->ctrl =3D msm_dp_ctrl_get(dev, dp->link, dp->panel, dp->aux, - phy, dp->ahb_base, dp->link_base); + phy, dp->max_stream, dp->ahb_base, dp->link_base); if (IS_ERR(dp->ctrl)) { rc =3D PTR_ERR(dp->ctrl); DRM_ERROR("failed to initialize ctrl, rc =3D %d\n", rc); @@ -789,7 +789,7 @@ static int msm_dp_display_disable(struct msm_dp_display= _private *dp) =20 /* set dongle to D3 (power off) mode */ msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); - msm_dp_ctrl_off_pixel_clk(dp->ctrl); + msm_dp_ctrl_off_pixel_clk(dp->ctrl, dp->panel->stream_id); msm_dp_ctrl_off_link(dp->ctrl); /* re-init the PHY so that we can listen to Dongle disconnect */ msm_dp_ctrl_reinit_phy(dp->ctrl); @@ -798,7 +798,7 @@ static int msm_dp_display_disable(struct msm_dp_display= _private *dp) * unplugged interrupt * dongle unplugged out of DUT */ - msm_dp_ctrl_off_pixel_clk(dp->ctrl); + msm_dp_ctrl_off_pixel_clk(dp->ctrl, dp->panel->stream_id); msm_dp_ctrl_off_link(dp->ctrl); msm_dp_display_host_phy_exit(dp); } @@ -809,6 +809,25 @@ static int msm_dp_display_disable(struct msm_dp_displa= y_private *dp) return 0; } =20 +int msm_dp_display_set_stream_id(struct msm_dp *dp, + struct msm_dp_panel *panel, enum msm_dp_stream_id stream_id) +{ + int rc =3D 0; + struct msm_dp_display_private *msm_dp_display; + + msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); + + if (!msm_dp_display) { + DRM_ERROR("invalid input\n"); + return -EINVAL; + } + + if (panel) + panel->stream_id =3D stream_id; + + return rc; +} + /** * msm_dp_bridge_mode_valid - callback to determine if specified mode is v= alid * @dp: Pointer to dp display structure @@ -1483,6 +1502,8 @@ void msm_dp_display_atomic_enable(struct msm_dp *msm_= dp_display) =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 + msm_dp_display_set_stream_id(msm_dp_display, dp->panel, 0); + if (msm_dp_display->prepared) { rc =3D msm_dp_display_enable(dp); if (rc) diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index 7727cf325a89b4892d2370a5616c4fa76fc88485..a839d0a3941eac3e277185e42fd= dea15ca05a17f 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -47,5 +47,7 @@ void msm_dp_display_mode_set(struct msm_dp *dp, enum drm_mode_status msm_dp_display_mode_valid(struct msm_dp *dp, const struct drm_display_info *info, const struct drm_display_mode *mode); +int msm_dp_display_set_stream_id(struct msm_dp *dp, + struct msm_dp_panel *panel, enum msm_dp_stream_id stream_id); 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This patch adds support for the additional pixel register blocks (p1, p2, p3), enabling multi-stream configurations. To reduce code duplication, introduce helper functions msm_dp_read_pn and msm_dp_write_pn. All pixel clocks (PCLKs) share the same register layout, but use different base addresses. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 39 +++++++++++++-------- drivers/gpu/drm/msm/dp/dp_panel.c | 68 ++++++++++++++++++---------------= ---- 2 files changed, 59 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 3422f18bdec71a99407edfe943d31957d0e8847a..935a0c57a928b15a1e9a6f1fab2= 576b7b09acb8e 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -84,8 +84,8 @@ struct msm_dp_display_private { void __iomem *link_base; size_t link_len; =20 - void __iomem *p0_base; - size_t p0_len; + void __iomem *pixel_base[DP_STREAM_MAX]; + size_t pixel_len; =20 int max_stream; }; @@ -619,7 +619,7 @@ static int msm_dp_init_sub_modules(struct msm_dp_displa= y_private *dp) goto error_link; } =20 - dp->panel =3D msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, dp-= >p0_base); + dp->panel =3D msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, dp-= >pixel_base); if (IS_ERR(dp->panel)) { rc =3D PTR_ERR(dp->panel); DRM_ERROR("failed to initialize panel, rc =3D %d\n", rc); @@ -937,8 +937,8 @@ void msm_dp_snapshot(struct msm_disp_state *disp_state,= struct msm_dp *dp) msm_dp_display->aux_base, "dp_aux"); msm_disp_snapshot_add_block(disp_state, msm_dp_display->link_len, msm_dp_display->link_base, "dp_link"); - msm_disp_snapshot_add_block(disp_state, msm_dp_display->p0_len, - msm_dp_display->p0_base, "dp_p0"); + msm_disp_snapshot_add_block(disp_state, msm_dp_display->pixel_len, + msm_dp_display->pixel_base[0], "dp_p0"); } =20 void msm_dp_display_set_psr(struct msm_dp *msm_dp_display, bool enter) @@ -1181,12 +1181,13 @@ static void __iomem *msm_dp_ioremap(struct platform= _device *pdev, int idx, size_ #define DP_DEFAULT_AUX_SIZE 0x0200 #define DP_DEFAULT_LINK_OFFSET 0x0400 #define DP_DEFAULT_LINK_SIZE 0x0C00 -#define DP_DEFAULT_P0_OFFSET 0x1000 -#define DP_DEFAULT_P0_SIZE 0x0400 +#define DP_DEFAULT_PIXEL_OFFSET 0x1000 +#define DP_DEFAULT_PIXEL_SIZE 0x0400 =20 static int msm_dp_display_get_io(struct msm_dp_display_private *display) { struct platform_device *pdev =3D display->msm_dp_display.pdev; + int i; =20 display->ahb_base =3D msm_dp_ioremap(pdev, 0, &display->ahb_len); if (IS_ERR(display->ahb_base)) @@ -1206,7 +1207,7 @@ static int msm_dp_display_get_io(struct msm_dp_displa= y_private *display) * reg is specified, so fill in the sub-region offsets and * lengths based on this single region. */ - if (display->ahb_len < DP_DEFAULT_P0_OFFSET + DP_DEFAULT_P0_SIZE) { + if (display->ahb_len < DP_DEFAULT_PIXEL_OFFSET + DP_DEFAULT_PIXEL_SIZE) { DRM_ERROR("legacy memory region not large enough\n"); return -EINVAL; } @@ -1216,8 +1217,10 @@ static int msm_dp_display_get_io(struct msm_dp_displ= ay_private *display) display->aux_len =3D DP_DEFAULT_AUX_SIZE; display->link_base =3D display->ahb_base + DP_DEFAULT_LINK_OFFSET; display->link_len =3D DP_DEFAULT_LINK_SIZE; - display->p0_base =3D display->ahb_base + DP_DEFAULT_P0_OFFSET; - display->p0_len =3D DP_DEFAULT_P0_SIZE; + for (i =3D DP_STREAM_0; i < display->max_stream; i++) + display->pixel_base[i] =3D display->ahb_base + + (i+1) * DP_DEFAULT_PIXEL_OFFSET; + display->pixel_len =3D DP_DEFAULT_PIXEL_SIZE; =20 return 0; } @@ -1228,10 +1231,18 @@ static int msm_dp_display_get_io(struct msm_dp_disp= lay_private *display) return PTR_ERR(display->link_base); } =20 - display->p0_base =3D msm_dp_ioremap(pdev, 3, &display->p0_len); - if (IS_ERR(display->p0_base)) { - DRM_ERROR("unable to remap p0 region: %pe\n", display->p0_base); - return PTR_ERR(display->p0_base); + display->pixel_base[0] =3D msm_dp_ioremap(pdev, 3, &display->pixel_len); + if (IS_ERR(display->pixel_base[0])) { + DRM_ERROR("unable to remap p0 region: %pe\n", display->pixel_base[0]); + return PTR_ERR(display->pixel_base[0]); + } + + for (i =3D DP_STREAM_1; i < display->max_stream; i++) { + /* pixels clk reg index start from 3*/ + display->pixel_base[i] =3D msm_dp_ioremap(pdev, i + 3, &display->pixel_l= en); + if (IS_ERR(display->pixel_base[i])) + DRM_DEBUG_DP("unable to remap p%d region: %pe\n", i, + display->pixel_base[i]); } =20 return 0; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index eae125972934bb2fb3b716dc47ae71cd0421bd1a..e8c1cf0c7dab7217b8bfe7ecd58= 6af33d7547ca9 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -26,7 +26,7 @@ struct msm_dp_panel_private { struct drm_dp_aux *aux; struct msm_dp_link *link; void __iomem *link_base; - void __iomem *p0_base; + void __iomem *pixel_base[DP_STREAM_MAX]; bool panel_on; }; =20 @@ -45,24 +45,24 @@ static inline void msm_dp_write_link(struct msm_dp_pane= l_private *panel, writel(data, panel->link_base + offset); } =20 -static inline void msm_dp_write_p0(struct msm_dp_panel_private *panel, +static inline void msm_dp_write_pn(struct msm_dp_panel_private *panel, u32 offset, u32 data) { /* * To make sure interface reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, panel->p0_base + offset); + writel(data, panel->pixel_base[panel->msm_dp_panel.stream_id] + offset); } =20 -static inline u32 msm_dp_read_p0(struct msm_dp_panel_private *panel, +static inline u32 msm_dp_read_pn(struct msm_dp_panel_private *panel, u32 offset) { /* * To make sure interface reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - return readl_relaxed(panel->p0_base + offset); + return readl_relaxed(panel->pixel_base[panel->msm_dp_panel.stream_id] + o= ffset); } =20 static void msm_dp_panel_read_psr_cap(struct msm_dp_panel_private *panel) @@ -297,33 +297,33 @@ static void msm_dp_panel_tpg_enable(struct msm_dp_pan= el *msm_dp_panel, display_hctl =3D (hsync_end_x << 16) | hsync_start_x; =20 =20 - msm_dp_write_p0(panel, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); - msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * + msm_dp_write_pn(panel, MMSS_DP_INTF_HSYNC_CTL, hsync_ctl); + msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period); - msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * + msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0, v_sync_width * hsync_period); - msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_HCTL, 0); - msm_dp_write_p0(panel, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); - msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); - msm_dp_write_p0(panel, MMSS_INTF_DISPLAY_V_START_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); - msm_dp_write_p0(panel, MMSS_DP_INTF_POLARITY_CTL, 0); - - msm_dp_write_p0(panel, MMSS_DP_TPG_MAIN_CONTROL, + msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PERIOD_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_DISPLAY_HCTL, display_hctl); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_HCTL, 0); + msm_dp_write_pn(panel, MMSS_INTF_DISPLAY_V_START_F0, display_v_start); + msm_dp_write_pn(panel, MMSS_DP_INTF_DISPLAY_V_END_F0, display_v_end); + msm_dp_write_pn(panel, MMSS_INTF_DISPLAY_V_START_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_DISPLAY_V_END_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_START_F0, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_END_F0, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_START_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_ACTIVE_V_END_F1, 0); + msm_dp_write_pn(panel, MMSS_DP_INTF_POLARITY_CTL, 0); + + msm_dp_write_pn(panel, MMSS_DP_TPG_MAIN_CONTROL, DP_TPG_CHECKERED_RECT_PATTERN); - msm_dp_write_p0(panel, MMSS_DP_TPG_VIDEO_CONFIG, + msm_dp_write_pn(panel, MMSS_DP_TPG_VIDEO_CONFIG, DP_TPG_VIDEO_CONFIG_BPP_8BIT | DP_TPG_VIDEO_CONFIG_RGB); - msm_dp_write_p0(panel, MMSS_DP_BIST_ENABLE, + msm_dp_write_pn(panel, MMSS_DP_BIST_ENABLE, DP_BIST_ENABLE_DPBIST_EN); - msm_dp_write_p0(panel, MMSS_DP_TIMING_ENGINE_EN, + msm_dp_write_pn(panel, MMSS_DP_TIMING_ENGINE_EN, DP_TIMING_ENGINE_EN_EN); drm_dbg_dp(panel->drm_dev, "%s: enabled tpg\n", __func__); } @@ -333,9 +333,9 @@ static void msm_dp_panel_tpg_disable(struct msm_dp_pane= l *msm_dp_panel) struct msm_dp_panel_private *panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); =20 - msm_dp_write_p0(panel, MMSS_DP_TPG_MAIN_CONTROL, 0x0); - msm_dp_write_p0(panel, MMSS_DP_BIST_ENABLE, 0x0); - msm_dp_write_p0(panel, MMSS_DP_TIMING_ENGINE_EN, 0x0); + msm_dp_write_pn(panel, MMSS_DP_TPG_MAIN_CONTROL, 0x0); + msm_dp_write_pn(panel, MMSS_DP_BIST_ENABLE, 0x0); + msm_dp_write_pn(panel, MMSS_DP_TIMING_ENGINE_EN, 0x0); } =20 void msm_dp_panel_tpg_config(struct msm_dp_panel *msm_dp_panel, bool enabl= e) @@ -369,7 +369,7 @@ void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *ms= m_dp_panel) struct msm_dp_panel_private *panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); =20 - msm_dp_write_p0(panel, MMSS_DP_DSC_DTO, 0x0); + msm_dp_write_pn(panel, MMSS_DP_DSC_DTO, 0x0); } =20 static void msm_dp_panel_send_vsc_sdp(struct msm_dp_panel_private *panel, = struct dp_sdp *vsc_sdp) @@ -559,7 +559,7 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp= _panel, bool wide_bus_en) msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blankin= g); msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER, msm_dp_active); =20 - reg =3D msm_dp_read_p0(panel, MMSS_DP_INTF_CONFIG); + reg =3D msm_dp_read_pn(panel, MMSS_DP_INTF_CONFIG); if (wide_bus_en) reg |=3D DP_INTF_CONFIG_DATABUS_WIDEN; else @@ -567,7 +567,7 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp= _panel, bool wide_bus_en) =20 drm_dbg_dp(panel->drm_dev, "wide_bus_en=3D%d reg=3D%#x\n", wide_bus_en, r= eg); =20 - msm_dp_write_p0(panel, MMSS_DP_INTF_CONFIG, reg); + msm_dp_write_pn(panel, MMSS_DP_INTF_CONFIG, reg); =20 if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) msm_dp_panel_setup_vsc_sdp_yuv_420(msm_dp_panel); @@ -673,7 +673,7 @@ static int msm_dp_panel_parse_dt(struct msm_dp_panel *m= sm_dp_panel) struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_au= x *aux, struct msm_dp_link *link, void __iomem *link_base, - void __iomem *p0_base) + void __iomem *pixel_base[]) { struct msm_dp_panel_private *panel; struct msm_dp_panel *msm_dp_panel; @@ -692,7 +692,7 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *de= v, struct drm_dp_aux *aux panel->aux =3D aux; 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Stream 1 share the same link clk with stream 0 with different reg offset. Also add additional register defines for stream 1. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 24 ++++++++++--- drivers/gpu/drm/msm/dp/dp_panel.c | 72 +++++++++++++++++++++++++++--------= ---- drivers/gpu/drm/msm/dp/dp_reg.h | 9 +++++ 3 files changed, 79 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index d4a74c6b70fb182ad8a0a786f85a0f50982d3858..b8b6a09966aed96f705bdd54cb1= 6ea63e5f0141f 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -384,6 +384,7 @@ static void msm_dp_ctrl_config_ctrl_streams(struct msm_= dp_ctrl_private *ctrl, struct msm_dp_panel *msm_dp_panel) { u32 config =3D 0, tbd; + u32 reg_offset =3D 0; =20 config =3D msm_dp_read_link(ctrl, REG_DP_CONFIGURATION_CTRL); =20 @@ -400,7 +401,8 @@ static void msm_dp_ctrl_config_ctrl_streams(struct msm_= dp_ctrl_private *ctrl, =20 drm_dbg_dp(ctrl->drm_dev, "stream DP_CONFIGURATION_CTRL=3D0x%x\n", config= ); =20 - msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL, config); + if (msm_dp_panel->stream_id =3D=3D DP_STREAM_1) + reg_offset =3D REG_DP1_CONFIGURATION_CTRL - REG_DP_CONFIGURATION_CTRL; } =20 static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl) @@ -451,12 +453,16 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm= _dp_ctrl_private *ctrl, struct msm_dp_panel *msm_dp_panel) { u32 colorimetry_cfg, test_bits_depth, misc_val; + u32 reg_offset =3D 0; =20 test_bits_depth =3D msm_dp_link_get_test_bits_depth(ctrl->link, msm_dp_panel->msm_dp_mode.bpp); colorimetry_cfg =3D msm_dp_link_get_colorimetry_config(ctrl->link); =20 - misc_val =3D msm_dp_read_link(ctrl, REG_DP_MISC1_MISC0); + if (msm_dp_panel->stream_id =3D=3D DP_STREAM_1) + reg_offset =3D REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0; + + misc_val =3D msm_dp_read_link(ctrl, REG_DP_MISC1_MISC0 + reg_offset); =20 /* clear bpp bits */ misc_val &=3D ~(0x07 << DP_MISC0_TEST_BITS_DEPTH_SHIFT); @@ -466,7 +472,7 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_d= p_ctrl_private *ctrl, misc_val |=3D DP_MISC0_SYNCHRONOUS_CLK; =20 drm_dbg_dp(ctrl->drm_dev, "misc settings =3D 0x%x\n", misc_val); - msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0, misc_val); + msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0 + reg_offset, misc_val); } =20 static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private= *ctrl, @@ -2431,6 +2437,7 @@ static int msm_dp_ctrl_link_retrain(struct msm_dp_ctr= l_private *ctrl) } =20 static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *msm_dp_panel, u32 rate, u32 stream_rate_khz, bool is_ycbcr_420) { @@ -2440,6 +2447,12 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ctr= l_private *ctrl, u32 const link_rate_hbr2 =3D 540000; u32 const link_rate_hbr3 =3D 810000; unsigned long den, num; + u32 mvid_reg_off =3D 0, nvid_reg_off =3D 0; + + if (msm_dp_panel->stream_id =3D=3D DP_STREAM_1) { + mvid_reg_off =3D REG_DP1_SOFTWARE_MVID - REG_DP_SOFTWARE_MVID; + nvid_reg_off =3D REG_DP1_SOFTWARE_NVID - REG_DP_SOFTWARE_NVID; + } =20 if (rate =3D=3D link_rate_hbr3) pixel_div =3D 6; @@ -2482,8 +2495,8 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ctrl= _private *ctrl, nvid *=3D 3; =20 drm_dbg_dp(ctrl->drm_dev, "mvid=3D0x%x, nvid=3D0x%x\n", mvid, nvid); - msm_dp_write_link(ctrl, REG_DP_SOFTWARE_MVID, mvid); - msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID, nvid); + msm_dp_write_link(ctrl, REG_DP_SOFTWARE_MVID + mvid_reg_off, mvid); + msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID + nvid_reg_off, nvid); } =20 int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train) @@ -2559,6 +2572,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, struct msm_dp_panel * msm_dp_ctrl_configure_source_params(ctrl, msm_dp_panel); =20 msm_dp_ctrl_config_msa(ctrl, + msm_dp_panel, ctrl->link->link_params.rate, pixel_rate_orig, msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420); diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index e8c1cf0c7dab7217b8bfe7ecd586af33d7547ca9..d1af389dffcfee2d21a616de6ee= 027374997aaee 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -377,27 +377,35 @@ static void msm_dp_panel_send_vsc_sdp(struct msm_dp_p= anel_private *panel, struct u32 header[2]; u32 val; int i; + u32 offset =3D 0; + + if (panel->msm_dp_panel.stream_id =3D=3D DP_STREAM_1) + offset =3D MMSS_DP1_GENERIC0_0 - MMSS_DP_GENERIC0_0; =20 msm_dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header); =20 - msm_dp_write_link(panel, MMSS_DP_GENERIC0_0, header[0]); - msm_dp_write_link(panel, MMSS_DP_GENERIC0_1, header[1]); + msm_dp_write_link(panel, MMSS_DP_GENERIC0_0 + offset, header[0]); + msm_dp_write_link(panel, MMSS_DP_GENERIC0_1 + offset, header[1]); =20 for (i =3D 0; i < sizeof(vsc_sdp->db); i +=3D 4) { val =3D ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i += 2] << 16) | (vsc_sdp->db[i + 3] << 24)); - msm_dp_write_link(panel, MMSS_DP_GENERIC0_2 + i, val); + msm_dp_write_link(panel, MMSS_DP_GENERIC0_2 + i + offset, val); } } =20 static void msm_dp_panel_update_sdp(struct msm_dp_panel_private *panel) { u32 hw_revision =3D panel->msm_dp_panel.hw_revision; + u32 offset =3D 0; + + if (panel->msm_dp_panel.stream_id =3D=3D DP_STREAM_1) + offset =3D MMSS_DP1_SDP_CFG3 - MMSS_DP_SDP_CFG3; =20 if (hw_revision >=3D DP_HW_VERSION_1_0 && hw_revision < DP_HW_VERSION_1_2) { - msm_dp_write_link(panel, MMSS_DP_SDP_CFG3, UPDATE_SDP); - msm_dp_write_link(panel, MMSS_DP_SDP_CFG3, 0x0); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG3 + offset, UPDATE_SDP); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG3 + offset, 0x0); } } =20 @@ -406,16 +414,25 @@ void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel = *msm_dp_panel, struct dp_sd struct msm_dp_panel_private *panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); u32 cfg, cfg2, misc; + u32 misc_reg_offset =3D 0; + u32 sdp_cfg_offset =3D 0; + u32 sdp_cfg2_offset =3D 0; + + if (msm_dp_panel->stream_id =3D=3D DP_STREAM_1) { + misc_reg_offset =3D REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0; + sdp_cfg_offset =3D MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG; + sdp_cfg2_offset =3D MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2; + } =20 - cfg =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG); - cfg2 =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG2); - misc =3D msm_dp_read_link(panel, REG_DP_MISC1_MISC0); + cfg =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset); + cfg2 =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset); + misc =3D msm_dp_read_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset); =20 cfg |=3D GEN0_SDP_EN; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG, cfg); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset, cfg); =20 cfg2 |=3D GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG2, cfg2); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, cfg2); =20 msm_dp_panel_send_vsc_sdp(panel, vsc_sdp); =20 @@ -425,7 +442,7 @@ void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *m= sm_dp_panel, struct dp_sd drm_dbg_dp(panel->drm_dev, "vsc sdp enable=3D1\n"); =20 pr_debug("misc settings =3D 0x%x\n", misc); - msm_dp_write_link(panel, REG_DP_MISC1_MISC0, misc); + msm_dp_write_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset, misc); =20 msm_dp_panel_update_sdp(panel); } @@ -435,16 +452,25 @@ void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel= *msm_dp_panel) struct msm_dp_panel_private *panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_panel); u32 cfg, cfg2, misc; + u32 misc_reg_offset =3D 0; + u32 sdp_cfg_offset =3D 0; + u32 sdp_cfg2_offset =3D 0; + + if (msm_dp_panel->stream_id =3D=3D DP_STREAM_1) { + misc_reg_offset =3D REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0; + sdp_cfg_offset =3D MMSS_DP1_SDP_CFG - MMSS_DP_SDP_CFG; + sdp_cfg2_offset =3D MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2; + } =20 - cfg =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG); - cfg2 =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG2); - misc =3D msm_dp_read_link(panel, REG_DP_MISC1_MISC0); + cfg =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset); + cfg2 =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset); + misc =3D msm_dp_read_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset); =20 cfg &=3D ~GEN0_SDP_EN; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG, cfg); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset, cfg); =20 cfg2 &=3D ~GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG2, cfg2); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, cfg2); =20 /* switch back to MSA */ misc &=3D ~DP_MISC1_VSC_SDP; @@ -452,7 +478,7 @@ void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *= msm_dp_panel) drm_dbg_dp(panel->drm_dev, "vsc sdp enable=3D0\n"); =20 pr_debug("misc settings =3D 0x%x\n", misc); - msm_dp_write_link(panel, REG_DP_MISC1_MISC0, misc); + msm_dp_write_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset, misc); =20 msm_dp_panel_update_sdp(panel); } @@ -510,6 +536,7 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp= _panel, bool wide_bus_en) u32 msm_dp_active; u32 total; u32 reg; + u32 offset =3D 0; =20 panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); drm_mode =3D &panel->msm_dp_panel.msm_dp_mode.drm_mode; @@ -524,6 +551,9 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_dp= _panel, bool wide_bus_en) drm_mode->vsync_start - drm_mode->vdisplay, drm_mode->vsync_end - drm_mode->vsync_start); =20 + if (msm_dp_panel->stream_id =3D=3D DP_STREAM_1) + offset =3D REG_DP1_TOTAL_HOR_VER - REG_DP_TOTAL_HOR_VER; + total_hor =3D drm_mode->htotal; =20 total_ver =3D drm_mode->vtotal; @@ -554,10 +584,10 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_= dp_panel, bool wide_bus_en) =20 msm_dp_active =3D data; =20 - msm_dp_write_link(panel, REG_DP_TOTAL_HOR_VER, total); - msm_dp_write_link(panel, REG_DP_START_HOR_VER_FROM_SYNC, sync_start); - msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY, width_blankin= g); - msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER, msm_dp_active); + msm_dp_write_link(panel, REG_DP_TOTAL_HOR_VER + offset, total); + msm_dp_write_link(panel, REG_DP_START_HOR_VER_FROM_SYNC + offset, sync_s= tart); + msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY + offset, widt= h_blanking); + msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER + offset, msm_dp_active); =20 reg =3D msm_dp_read_pn(panel, MMSS_DP_INTF_CONFIG); if (wide_bus_en) diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_re= g.h index b851efc132ea03884ce2563990fbc24c9577e724..43a9ce0539906e1f185abf250fd= f161e462d9645 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -141,6 +141,7 @@ #define DP_STATE_CTRL_PUSH_IDLE (0x00000100) =20 #define REG_DP_CONFIGURATION_CTRL (0x00000008) +#define REG_DP1_CONFIGURATION_CTRL (0x00000400) #define DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK (0x00000001) #define DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN (0x00000002) #define DP_CONFIGURATION_CTRL_P_INTERLACED (0x00000004) @@ -159,11 +160,15 @@ #define REG_DP_SOFTWARE_MVID (0x00000010) #define REG_DP_SOFTWARE_NVID (0x00000018) #define REG_DP_TOTAL_HOR_VER (0x0000001C) +#define REG_DP1_SOFTWARE_MVID (0x00000414) +#define REG_DP1_SOFTWARE_NVID (0x00000418) +#define REG_DP1_TOTAL_HOR_VER (0x0000041C) #define REG_DP_START_HOR_VER_FROM_SYNC (0x00000020) #define REG_DP_HSYNC_VSYNC_WIDTH_POLARITY (0x00000024) #define REG_DP_ACTIVE_HOR_VER (0x00000028) =20 #define REG_DP_MISC1_MISC0 (0x0000002C) +#define REG_DP1_MISC1_MISC0 (0x0000042C) #define DP_MISC0_SYNCHRONOUS_CLK (0x00000001) #define DP_MISC0_COLORIMETRY_CFG_SHIFT (0x00000001) #define DP_MISC0_TEST_BITS_DEPTH_SHIFT (0x00000005) @@ -230,8 +235,10 @@ #define MMSS_DP_AUDIO_CTRL_RESET (0x00000214) =20 #define MMSS_DP_SDP_CFG (0x00000228) +#define MMSS_DP1_SDP_CFG (0x000004E0) #define GEN0_SDP_EN (0x00020000) #define MMSS_DP_SDP_CFG2 (0x0000022C) +#define MMSS_DP1_SDP_CFG2 (0x000004E4) #define MMSS_DP_AUDIO_TIMESTAMP_0 (0x00000230) #define MMSS_DP_AUDIO_TIMESTAMP_1 (0x00000234) #define GENERIC0_SDPSIZE_VALID (0x00010000) @@ -240,6 +247,7 @@ #define MMSS_DP_AUDIO_STREAM_1 (0x00000244) =20 #define MMSS_DP_SDP_CFG3 (0x0000024c) +#define MMSS_DP1_SDP_CFG3 (0x000004E8) #define UPDATE_SDP (0x00000001) =20 #define MMSS_DP_EXTENSION_0 (0x00000250) @@ -288,6 +296,7 @@ #define MMSS_DP_GENERIC1_7 (0x00000344) #define MMSS_DP_GENERIC1_8 (0x00000348) #define MMSS_DP_GENERIC1_9 (0x0000034C) +#define MMSS_DP1_GENERIC0_0 (0x00000490) =20 #define MMSS_DP_VSCEXT_0 (0x000002D0) #define MMSS_DP_VSCEXT_1 (0x000002D4) --=20 2.34.1 From nobody Fri Oct 3 20:22:40 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E31E2FF65C for ; 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These clocks share the same register definitions but use different base addresses. This patch adds catalog support to enable programming of these blocks. Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 82 ++++++++++++++++++--- drivers/gpu/drm/msm/dp/dp_ctrl.h | 4 +- drivers/gpu/drm/msm/dp/dp_display.c | 24 ++++++- drivers/gpu/drm/msm/dp/dp_panel.c | 138 ++++++++++++++++++++++++++++++--= ---- drivers/gpu/drm/msm/dp/dp_panel.h | 4 +- drivers/gpu/drm/msm/dp/dp_reg.h | 14 ++++ 6 files changed, 230 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index b8b6a09966aed96f705bdd54cb16ea63e5f0141f..608a1a077301b2ef3c77c271d87= 3bb4364abe779 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -118,6 +118,8 @@ struct msm_dp_ctrl_private { struct msm_dp_link *link; void __iomem *ahb_base; void __iomem *link_base; + void __iomem *mst2link_base; + void __iomem *mst3link_base; =20 struct phy *phy; =20 @@ -172,6 +174,40 @@ static inline void msm_dp_write_link(struct msm_dp_ctr= l_private *ctrl, writel(data, ctrl->link_base + offset); } =20 +static inline u32 msm_dp_read_mstlink(struct msm_dp_ctrl_private *ctrl, + enum msm_dp_stream_id stream_id, u32 offset) +{ + switch (stream_id) { + case DP_STREAM_2: + return readl_relaxed(ctrl->mst2link_base + offset); + case DP_STREAM_3: + return readl_relaxed(ctrl->mst3link_base + offset); + default: + DRM_ERROR("error stream_id\n"); + return 0; + } +} + +static inline void msm_dp_write_mstlink(struct msm_dp_ctrl_private *ctrl, + enum msm_dp_stream_id stream_id, u32 offset, u32 data) +{ + /* + * To make sure link reg writes happens before any other operation, + * this function uses writel() instread of writel_relaxed() + */ + switch (stream_id) { + case DP_STREAM_2: + writel(data, ctrl->mst2link_base + offset); + break; + case DP_STREAM_3: + writel(data, ctrl->mst3link_base + offset); + break; + default: + DRM_ERROR("error stream_id\n"); + break; + } +} + static int msm_dp_aux_link_configure(struct drm_dp_aux *aux, struct msm_dp_link_info *link) { @@ -386,7 +422,11 @@ static void msm_dp_ctrl_config_ctrl_streams(struct msm= _dp_ctrl_private *ctrl, u32 config =3D 0, tbd; u32 reg_offset =3D 0; =20 - config =3D msm_dp_read_link(ctrl, REG_DP_CONFIGURATION_CTRL); + if (msm_dp_panel->stream_id < DP_STREAM_2) + config =3D msm_dp_read_link(ctrl, REG_DP_CONFIGURATION_CTRL); + + if (msm_dp_panel->stream_id =3D=3D DP_STREAM_1) + reg_offset =3D REG_DP1_CONFIGURATION_CTRL - REG_DP_CONFIGURATION_CTRL; =20 if (msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420) config |=3D DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */ @@ -401,8 +441,11 @@ static void msm_dp_ctrl_config_ctrl_streams(struct msm= _dp_ctrl_private *ctrl, =20 drm_dbg_dp(ctrl->drm_dev, "stream DP_CONFIGURATION_CTRL=3D0x%x\n", config= ); =20 - if (msm_dp_panel->stream_id =3D=3D DP_STREAM_1) - reg_offset =3D REG_DP1_CONFIGURATION_CTRL - REG_DP_CONFIGURATION_CTRL; + if (msm_dp_panel->stream_id > DP_STREAM_1) + msm_dp_write_mstlink(ctrl, msm_dp_panel->stream_id, + REG_DP_MSTLINK_CONFIGURATION_CTRL, config); + else + msm_dp_write_link(ctrl, REG_DP_CONFIGURATION_CTRL + reg_offset, config); } =20 static void msm_dp_ctrl_config_ctrl_link(struct msm_dp_ctrl_private *ctrl) @@ -462,7 +505,11 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_= dp_ctrl_private *ctrl, if (msm_dp_panel->stream_id =3D=3D DP_STREAM_1) reg_offset =3D REG_DP1_MISC1_MISC0 - REG_DP_MISC1_MISC0; =20 - misc_val =3D msm_dp_read_link(ctrl, REG_DP_MISC1_MISC0 + reg_offset); + if (msm_dp_panel->stream_id > DP_STREAM_1) + misc_val =3D msm_dp_read_mstlink(ctrl, msm_dp_panel->stream_id, + REG_DP_MSTLINK_MISC1_MISC0); + else + misc_val =3D msm_dp_read_link(ctrl, REG_DP_MISC1_MISC0 + reg_offset); =20 /* clear bpp bits */ misc_val &=3D ~(0x07 << DP_MISC0_TEST_BITS_DEPTH_SHIFT); @@ -472,7 +519,11 @@ static void msm_dp_ctrl_config_misc1_misc0(struct msm_= dp_ctrl_private *ctrl, misc_val |=3D DP_MISC0_SYNCHRONOUS_CLK; =20 drm_dbg_dp(ctrl->drm_dev, "misc settings =3D 0x%x\n", misc_val); - msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0 + reg_offset, misc_val); + if (msm_dp_panel->stream_id > DP_STREAM_1) + msm_dp_write_mstlink(ctrl, msm_dp_panel->stream_id, + REG_DP_MSTLINK_MISC1_MISC0, misc_val); + else + msm_dp_write_link(ctrl, REG_DP_MISC1_MISC0 + reg_offset, misc_val); } =20 static void msm_dp_ctrl_configure_source_params(struct msm_dp_ctrl_private= *ctrl, @@ -2495,8 +2546,15 @@ static void msm_dp_ctrl_config_msa(struct msm_dp_ctr= l_private *ctrl, nvid *=3D 3; =20 drm_dbg_dp(ctrl->drm_dev, "mvid=3D0x%x, nvid=3D0x%x\n", mvid, nvid); - msm_dp_write_link(ctrl, REG_DP_SOFTWARE_MVID + mvid_reg_off, mvid); - msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID + nvid_reg_off, nvid); + if (msm_dp_panel->stream_id > DP_STREAM_1) { + msm_dp_write_mstlink(ctrl, msm_dp_panel->stream_id, + REG_MSTLINK_SOFTWARE_MVID, mvid); + msm_dp_write_mstlink(ctrl, msm_dp_panel->stream_id, + REG_MSTLINK_SOFTWARE_NVID, nvid); + } else { + msm_dp_write_link(ctrl, REG_DP_SOFTWARE_MVID + mvid_reg_off, mvid); + msm_dp_write_link(ctrl, REG_DP_SOFTWARE_NVID + nvid_reg_off, nvid); + } } =20 int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train) @@ -2567,7 +2625,9 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, struct msm_dp_panel * =20 msm_dp_ctrl_lane_mapping(ctrl); msm_dp_setup_peripheral_flush(ctrl); - msm_dp_ctrl_config_ctrl_link(ctrl); + + if (msm_dp_panel->stream_id =3D=3D DP_STREAM_0) + msm_dp_ctrl_config_ctrl_link(ctrl); =20 msm_dp_ctrl_configure_source_params(ctrl, msm_dp_panel); =20 @@ -2745,7 +2805,9 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *de= v, struct msm_dp_link *link struct phy *phy, int max_stream, void __iomem *ahb_base, - void __iomem *link_base) + void __iomem *link_base, + void __iomem *mst2link_base, + void __iomem *mst3link_base) { struct msm_dp_ctrl_private *ctrl; int ret; @@ -2785,6 +2847,8 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *de= v, struct msm_dp_link *link ctrl->phy =3D phy; ctrl->ahb_base =3D ahb_base; ctrl->link_base =3D link_base; + ctrl->mst2link_base =3D mst2link_base; + ctrl->mst3link_base =3D mst3link_base; =20 ret =3D msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl, max_stream); if (ret) { diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index 32ff1455caf0e7fcb1bd74b1f3192c6c3c03ee74..2baf7a1ff44dd7139d2da863901= 21d5e7a063e9a 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -31,7 +31,9 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, struct phy *phy, int max_stream, void __iomem *ahb_base, - void __iomem *link_base); + void __iomem *link_base, + void __iomem *mst2link_base, + void __iomem *mst3link_base); =20 void msm_dp_ctrl_reset(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_phy_init(struct msm_dp_ctrl *msm_dp_ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 935a0c57a928b15a1e9a6f1fab2576b7b09acb8e..562a5eccf3f08c5669cc7c2ad12= 68897e975d0c4 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -84,6 +84,12 @@ struct msm_dp_display_private { void __iomem *link_base; size_t link_len; =20 + void __iomem *mst2link_base; + size_t mst2link_len; + + void __iomem *mst3link_base; + size_t mst3link_len; + void __iomem *pixel_base[DP_STREAM_MAX]; size_t pixel_len; =20 @@ -619,7 +625,8 @@ static int msm_dp_init_sub_modules(struct msm_dp_displa= y_private *dp) goto error_link; } =20 - dp->panel =3D msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, dp-= >pixel_base); + dp->panel =3D msm_dp_panel_get(dev, dp->aux, dp->link, dp->link_base, + dp->mst2link_base, dp->mst3link_base, dp->pixel_base); if (IS_ERR(dp->panel)) { rc =3D PTR_ERR(dp->panel); DRM_ERROR("failed to initialize panel, rc =3D %d\n", rc); @@ -628,7 +635,8 @@ static int msm_dp_init_sub_modules(struct msm_dp_displa= y_private *dp) } =20 dp->ctrl =3D msm_dp_ctrl_get(dev, dp->link, dp->panel, dp->aux, - phy, dp->max_stream, dp->ahb_base, dp->link_base); + phy, dp->max_stream, dp->ahb_base, + dp->link_base, dp->mst2link_base, dp->mst3link_base); if (IS_ERR(dp->ctrl)) { rc =3D PTR_ERR(dp->ctrl); DRM_ERROR("failed to initialize ctrl, rc =3D %d\n", rc); @@ -937,6 +945,10 @@ void msm_dp_snapshot(struct msm_disp_state *disp_state= , struct msm_dp *dp) msm_dp_display->aux_base, "dp_aux"); msm_disp_snapshot_add_block(disp_state, msm_dp_display->link_len, msm_dp_display->link_base, "dp_link"); + msm_disp_snapshot_add_block(disp_state, msm_dp_display->mst2link_len, + msm_dp_display->mst2link_base, "dp_mst2link"); + msm_disp_snapshot_add_block(disp_state, msm_dp_display->mst3link_len, + msm_dp_display->mst3link_base, "dp_mst3link"); msm_disp_snapshot_add_block(disp_state, msm_dp_display->pixel_len, msm_dp_display->pixel_base[0], "dp_p0"); } @@ -1245,6 +1257,14 @@ static int msm_dp_display_get_io(struct msm_dp_displ= ay_private *display) display->pixel_base[i]); } =20 + display->mst2link_base =3D msm_dp_ioremap(pdev, 7, &display->mst2link_len= ); + if (IS_ERR(display->mst2link_base)) + DRM_DEBUG_DP("unable to remap link region: %pe\n", display->mst2link_bas= e); + + display->mst3link_base =3D msm_dp_ioremap(pdev, 8, &display->mst3link_len= ); + if (IS_ERR(display->mst3link_base)) + DRM_DEBUG_DP("unable to remap link region: %pe\n", display->mst3link_bas= e); + return 0; } =20 diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index d1af389dffcfee2d21a616de6ee027374997aaee..f792687c315a2c8203305a20b72= 90a93b0d791f4 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -26,6 +26,8 @@ struct msm_dp_panel_private { struct drm_dp_aux *aux; struct msm_dp_link *link; void __iomem *link_base; + void __iomem *mst2link_base; + void __iomem *mst3link_base; void __iomem *pixel_base[DP_STREAM_MAX]; bool panel_on; }; @@ -45,6 +47,39 @@ static inline void msm_dp_write_link(struct msm_dp_panel= _private *panel, writel(data, panel->link_base + offset); } =20 +static inline u32 msm_dp_read_mstlink(struct msm_dp_panel_private *panel, = u32 offset) +{ + switch (panel->msm_dp_panel.stream_id) { + case DP_STREAM_2: + return readl_relaxed(panel->mst2link_base + offset); + case DP_STREAM_3: + return readl_relaxed(panel->mst3link_base + offset); + default: + DRM_ERROR("error stream_id\n"); + return 0; + } +} + +static inline void msm_dp_write_mstlink(struct msm_dp_panel_private *panel, + u32 offset, u32 data) +{ + /* + * To make sure link reg writes happens before any other operation, + * this function uses writel() instread of writel_relaxed() + */ + switch (panel->msm_dp_panel.stream_id) { + case DP_STREAM_2: + writel(data, panel->mst2link_base + offset); + break; + case DP_STREAM_3: + writel(data, panel->mst3link_base + offset); + break; + default: + DRM_ERROR("error stream_id\n"); + break; + } +} + static inline void msm_dp_write_pn(struct msm_dp_panel_private *panel, u32 offset, u32 data) { @@ -384,13 +419,22 @@ static void msm_dp_panel_send_vsc_sdp(struct msm_dp_p= anel_private *panel, struct =20 msm_dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header); =20 - msm_dp_write_link(panel, MMSS_DP_GENERIC0_0 + offset, header[0]); - msm_dp_write_link(panel, MMSS_DP_GENERIC0_1 + offset, header[1]); + if (panel->msm_dp_panel.stream_id > DP_STREAM_1) { + msm_dp_write_mstlink(panel, MMSS_DP_MSTLINK_GENERIC0_0, header[0]); + msm_dp_write_mstlink(panel, MMSS_DP_MSTLINK_GENERIC0_1, header[1]); + } else { + msm_dp_write_link(panel, MMSS_DP_GENERIC0_0 + offset, header[0]); + msm_dp_write_link(panel, MMSS_DP_GENERIC0_1 + offset, header[1]); + } =20 for (i =3D 0; i < sizeof(vsc_sdp->db); i +=3D 4) { val =3D ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i += 2] << 16) | (vsc_sdp->db[i + 3] << 24)); - msm_dp_write_link(panel, MMSS_DP_GENERIC0_2 + i + offset, val); + + if (panel->msm_dp_panel.stream_id > DP_STREAM_1) + msm_dp_write_mstlink(panel, MMSS_DP_MSTLINK_GENERIC0_2 + i, val); + else + msm_dp_write_link(panel, MMSS_DP_GENERIC0_2 + i + offset, val); } } =20 @@ -404,8 +448,13 @@ static void msm_dp_panel_update_sdp(struct msm_dp_pane= l_private *panel) =20 if (hw_revision >=3D DP_HW_VERSION_1_0 && hw_revision < DP_HW_VERSION_1_2) { - msm_dp_write_link(panel, MMSS_DP_SDP_CFG3 + offset, UPDATE_SDP); - msm_dp_write_link(panel, MMSS_DP_SDP_CFG3 + offset, 0x0); + if (panel->msm_dp_panel.stream_id > DP_STREAM_1) { + msm_dp_write_mstlink(panel, MMSS_DP_MSTLINK_SDP_CFG3, UPDATE_SDP); + msm_dp_write_mstlink(panel, MMSS_DP_MSTLINK_SDP_CFG3, 0x00); + } else { + msm_dp_write_link(panel, MMSS_DP_SDP_CFG3 + offset, UPDATE_SDP); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG3 + offset, 0x0); + } } } =20 @@ -424,15 +473,26 @@ void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel = *msm_dp_panel, struct dp_sd sdp_cfg2_offset =3D MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2; } =20 - cfg =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset); - cfg2 =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset); - misc =3D msm_dp_read_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset); + if (msm_dp_panel->stream_id > DP_STREAM_1) { + cfg =3D msm_dp_read_mstlink(panel, MMSS_DP_MSTLINK_SDP_CFG); + cfg2 =3D msm_dp_read_mstlink(panel, MMSS_DP_MSTLINK_SDP_CFG2); + misc =3D msm_dp_read_mstlink(panel, REG_DP_MSTLINK_MISC1_MISC0); + } else { + cfg =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset); + cfg2 =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset); + misc =3D msm_dp_read_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset); + } =20 cfg |=3D GEN0_SDP_EN; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset, cfg); - cfg2 |=3D GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, cfg2); + + if (msm_dp_panel->stream_id > DP_STREAM_1) { + msm_dp_write_mstlink(panel, MMSS_DP_MSTLINK_SDP_CFG, cfg); + msm_dp_write_mstlink(panel, MMSS_DP_MSTLINK_SDP_CFG2, cfg2); + } else { + msm_dp_write_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset, cfg); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, cfg2); + } =20 msm_dp_panel_send_vsc_sdp(panel, vsc_sdp); =20 @@ -442,7 +502,10 @@ void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *= msm_dp_panel, struct dp_sd drm_dbg_dp(panel->drm_dev, "vsc sdp enable=3D1\n"); =20 pr_debug("misc settings =3D 0x%x\n", misc); - msm_dp_write_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset, misc); + if (msm_dp_panel->stream_id > DP_STREAM_1) + msm_dp_write_mstlink(panel, REG_DP_MSTLINK_MISC1_MISC0, misc); + else + msm_dp_write_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset, misc); =20 msm_dp_panel_update_sdp(panel); } @@ -462,15 +525,26 @@ void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel= *msm_dp_panel) sdp_cfg2_offset =3D MMSS_DP1_SDP_CFG2 - MMSS_DP_SDP_CFG2; } =20 - cfg =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset); - cfg2 =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset); - misc =3D msm_dp_read_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset); + if (msm_dp_panel->stream_id > DP_STREAM_1) { + cfg =3D msm_dp_read_mstlink(panel, MMSS_DP_MSTLINK_SDP_CFG); + cfg2 =3D msm_dp_read_mstlink(panel, MMSS_DP_MSTLINK_SDP_CFG2); + misc =3D msm_dp_read_mstlink(panel, REG_DP_MSTLINK_MISC1_MISC0); + } else { + cfg =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset); + cfg2 =3D msm_dp_read_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset); + misc =3D msm_dp_read_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset); + } =20 cfg &=3D ~GEN0_SDP_EN; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset, cfg); - cfg2 &=3D ~GENERIC0_SDPSIZE_VALID; - msm_dp_write_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, cfg2); + + if (msm_dp_panel->stream_id > DP_STREAM_1) { + msm_dp_write_mstlink(panel, MMSS_DP_MSTLINK_SDP_CFG, cfg); + msm_dp_write_mstlink(panel, MMSS_DP_MSTLINK_SDP_CFG2, cfg2); + } else { + msm_dp_write_link(panel, MMSS_DP_SDP_CFG + sdp_cfg_offset, cfg); + msm_dp_write_link(panel, MMSS_DP_SDP_CFG2 + sdp_cfg2_offset, cfg2); + } =20 /* switch back to MSA */ misc &=3D ~DP_MISC1_VSC_SDP; @@ -478,7 +552,10 @@ void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel = *msm_dp_panel) drm_dbg_dp(panel->drm_dev, "vsc sdp enable=3D0\n"); =20 pr_debug("misc settings =3D 0x%x\n", misc); - msm_dp_write_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset, misc); + if (msm_dp_panel->stream_id > DP_STREAM_1) + msm_dp_write_mstlink(panel, REG_DP_MSTLINK_MISC1_MISC0, misc); + else + msm_dp_write_link(panel, REG_DP_MISC1_MISC0 + misc_reg_offset, misc); =20 msm_dp_panel_update_sdp(panel); } @@ -584,10 +661,20 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_= dp_panel, bool wide_bus_en) =20 msm_dp_active =3D data; =20 - msm_dp_write_link(panel, REG_DP_TOTAL_HOR_VER + offset, total); - msm_dp_write_link(panel, REG_DP_START_HOR_VER_FROM_SYNC + offset, sync_s= tart); - msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY + offset, widt= h_blanking); - msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER + offset, msm_dp_active); + if (msm_dp_panel->stream_id > DP_STREAM_1) { + msm_dp_write_mstlink(panel, REG_DP_MSTLINK_TOTAL_HOR_VER, total); + msm_dp_write_mstlink(panel, REG_DP_MSTLINK_START_HOR_VER_FROM_SYNC, + sync_start); + msm_dp_write_mstlink(panel, REG_DP_MSTLINK_HSYNC_VSYNC_WIDTH_POLARITY, + width_blanking); + msm_dp_write_mstlink(panel, REG_DP_MSTLINK_ACTIVE_HOR_VER, msm_dp_active= ); + } else { + msm_dp_write_link(panel, REG_DP_TOTAL_HOR_VER + offset, total); + msm_dp_write_link(panel, REG_DP_START_HOR_VER_FROM_SYNC + offset, sync_= start); + msm_dp_write_link(panel, REG_DP_HSYNC_VSYNC_WIDTH_POLARITY + offset, + width_blanking); + msm_dp_write_link(panel, REG_DP_ACTIVE_HOR_VER + offset, msm_dp_active); + } =20 reg =3D msm_dp_read_pn(panel, MMSS_DP_INTF_CONFIG); if (wide_bus_en) @@ -703,6 +790,8 @@ static int msm_dp_panel_parse_dt(struct msm_dp_panel *m= sm_dp_panel) struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_au= x *aux, struct msm_dp_link *link, void __iomem *link_base, + void __iomem *mst2link_base, + void __iomem *mst3link_base, void __iomem *pixel_base[]) { struct msm_dp_panel_private *panel; @@ -722,6 +811,9 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *de= v, struct drm_dp_aux *aux panel->aux =3D aux; panel->link =3D link; panel->link_base =3D link_base; + panel->mst2link_base =3D mst2link_base; + panel->mst3link_base =3D mst3link_base; + memcpy(panel->pixel_base, pixel_base, sizeof(panel->pixel_base)); =20 msm_dp_panel =3D &panel->msm_dp_panel; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index 23b3e78e40479d133893a8afe1a69cfe8c16abdf..2bfe3695994235d04e209a27859= 15107c6a8e413 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -103,5 +103,7 @@ static inline bool is_lane_count_valid(u32 lane_count) struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_au= x *aux, struct msm_dp_link *link, void __iomem *link_base, - void __iomem *p0_base); + void __iomem *mst2link_base, + void __iomem *mst3link_base, + void __iomem *pixel_base[]); #endif /* _DP_PANEL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_re= g.h index 43a9ce0539906e1f185abf250fdf161e462d9645..a806d397ff9d9ad3830b1f53961= 4bffcc955a786 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -142,6 +142,7 @@ =20 #define REG_DP_CONFIGURATION_CTRL (0x00000008) #define REG_DP1_CONFIGURATION_CTRL (0x00000400) +#define REG_DP_MSTLINK_CONFIGURATION_CTRL (0x00000034) #define DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK (0x00000001) #define DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN (0x00000002) #define DP_CONFIGURATION_CTRL_P_INTERLACED (0x00000004) @@ -163,12 +164,19 @@ #define REG_DP1_SOFTWARE_MVID (0x00000414) #define REG_DP1_SOFTWARE_NVID (0x00000418) #define REG_DP1_TOTAL_HOR_VER (0x0000041C) +#define REG_MSTLINK_SOFTWARE_MVID (0x00000040) +#define REG_MSTLINK_SOFTWARE_NVID (0x00000044) +#define REG_DP_MSTLINK_TOTAL_HOR_VER (0x00000048) #define REG_DP_START_HOR_VER_FROM_SYNC (0x00000020) +#define REG_DP_MSTLINK_START_HOR_VER_FROM_SYNC (0x0000004C) #define REG_DP_HSYNC_VSYNC_WIDTH_POLARITY (0x00000024) +#define REG_DP_MSTLINK_HSYNC_VSYNC_WIDTH_POLARITY (0x00000050) #define REG_DP_ACTIVE_HOR_VER (0x00000028) +#define REG_DP_MSTLINK_ACTIVE_HOR_VER (0x00000054) =20 #define REG_DP_MISC1_MISC0 (0x0000002C) #define REG_DP1_MISC1_MISC0 (0x0000042C) +#define REG_DP_MSTLINK_MISC1_MISC0 (0x00000058) #define DP_MISC0_SYNCHRONOUS_CLK (0x00000001) #define DP_MISC0_COLORIMETRY_CFG_SHIFT (0x00000001) #define DP_MISC0_TEST_BITS_DEPTH_SHIFT (0x00000005) @@ -236,9 +244,11 @@ =20 #define MMSS_DP_SDP_CFG (0x00000228) #define MMSS_DP1_SDP_CFG (0x000004E0) +#define MMSS_DP_MSTLINK_SDP_CFG (0x0000010c) #define GEN0_SDP_EN (0x00020000) #define MMSS_DP_SDP_CFG2 (0x0000022C) #define MMSS_DP1_SDP_CFG2 (0x000004E4) +#define MMSS_DP_MSTLINK_SDP_CFG2 (0x0000011c) #define MMSS_DP_AUDIO_TIMESTAMP_0 (0x00000230) #define MMSS_DP_AUDIO_TIMESTAMP_1 (0x00000234) #define GENERIC0_SDPSIZE_VALID (0x00010000) @@ -248,6 +258,7 @@ =20 #define MMSS_DP_SDP_CFG3 (0x0000024c) #define MMSS_DP1_SDP_CFG3 (0x000004E8) +#define MMSS_DP_MSTLINK_SDP_CFG3 (0x00000114) #define UPDATE_SDP (0x00000001) =20 #define MMSS_DP_EXTENSION_0 (0x00000250) @@ -297,6 +308,9 @@ #define MMSS_DP_GENERIC1_8 (0x00000348) #define MMSS_DP_GENERIC1_9 (0x0000034C) #define MMSS_DP1_GENERIC0_0 (0x00000490) +#define MMSS_DP_MSTLINK_GENERIC0_0 (0x000000BC) +#define MMSS_DP_MSTLINK_GENERIC0_1 (0x000000C0) +#define MMSS_DP_MSTLINK_GENERIC0_2 (0x000000C4) =20 #define MMSS_DP_VSCEXT_0 (0x000002D0) #define MMSS_DP_VSCEXT_1 (0x000002D4) --=20 2.34.1 From nobody Fri Oct 3 20:22:40 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 696772FF675 for ; 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This would be applicable during the start and stop of the pixel stream. Add the infrastructure to be able to send ACT packets for the DP controller when operating in MST mode. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 39 +++++++++++++++++++++++++++++++++= ++-- drivers/gpu/drm/msm/dp/dp_ctrl.h | 4 ++-- drivers/gpu/drm/msm/dp/dp_display.c | 3 ++- drivers/gpu/drm/msm/dp/dp_display.h | 1 + drivers/gpu/drm/msm/dp/dp_reg.h | 2 ++ 5 files changed, 44 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 608a1a077301b2ef3c77c271d873bb4364abe779..16e5ed58e791971d5dca3077cbb= 77bfcc186505a 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -142,6 +142,7 @@ struct msm_dp_ctrl_private { bool core_clks_on; bool link_clks_on; bool stream_clks_on[DP_STREAM_MAX]; + bool mst_active; }; =20 static inline u32 msm_dp_read_ahb(const struct msm_dp_ctrl_private *ctrl, = u32 offset) @@ -227,6 +228,32 @@ static int msm_dp_aux_link_configure(struct drm_dp_aux= *aux, return 0; } =20 +void msm_dp_ctrl_mst_send_act(struct msm_dp_ctrl *msm_dp_ctrl) +{ + struct msm_dp_ctrl_private *ctrl; + bool act_complete; + + ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); + + if (!ctrl->mst_active) + return; + + msm_dp_write_link(ctrl, REG_DP_MST_ACT, 0x1); + /* make sure ACT signal is performed */ + wmb(); + + msleep(20); /* needs 1 frame time */ + + act_complete =3D msm_dp_read_link(ctrl, REG_DP_MST_ACT); + + if (!act_complete) + drm_dbg_dp(ctrl->drm_dev, "mst ACT trigger complete SUCCESS\n"); + else + drm_dbg_dp(ctrl->drm_dev, "mst ACT trigger complete failed\n"); + + return; +} + /* * NOTE: resetting DP controller will also clear any pending HPD related i= nterrupts */ @@ -2079,6 +2106,8 @@ static int msm_dp_ctrl_link_maintenance(struct msm_dp= _ctrl_private *ctrl) =20 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); =20 + msm_dp_ctrl_mst_send_act(&ctrl->msm_dp_ctrl); + ret =3D msm_dp_ctrl_wait4video_ready(ctrl); end: return ret; @@ -2275,7 +2304,7 @@ static int msm_dp_ctrl_process_phy_test_request(struc= t msm_dp_ctrl_private *ctrl msm_dp_ctrl_off_pixel_clk(&ctrl->msm_dp_ctrl, ctrl->panel->stream_id); msm_dp_ctrl_off_link(&ctrl->msm_dp_ctrl); =20 - ret =3D msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl); + ret =3D msm_dp_ctrl_on_link(&ctrl->msm_dp_ctrl, false); if (ret) { DRM_ERROR("failed to enable DP link controller\n"); return ret; @@ -2355,7 +2384,7 @@ static bool msm_dp_ctrl_channel_eq_ok(struct msm_dp_c= trl_private *ctrl) return drm_dp_channel_eq_ok(link_status, num_lanes); } =20 -int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl) +int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl, bool mst_active) { int rc =3D 0; struct msm_dp_ctrl_private *ctrl; @@ -2373,6 +2402,7 @@ int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ct= rl) =20 rate =3D ctrl->panel->link_info.rate; pixel_rate =3D ctrl->panel->msm_dp_mode.drm_mode.clock; + ctrl->mst_active =3D mst_active; =20 msm_dp_ctrl_core_clk_enable(&ctrl->msm_dp_ctrl); =20 @@ -2643,6 +2673,8 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, struct msm_dp_panel * =20 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); =20 + msm_dp_ctrl_mst_send_act(msm_dp_ctrl); + ret =3D msm_dp_ctrl_wait4video_ready(ctrl); if (ret) return ret; @@ -2682,6 +2714,8 @@ void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_= ctrl) =20 msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); =20 + ctrl->mst_active =3D false; + dev_pm_opp_set_rate(ctrl->dev, 0); msm_dp_ctrl_link_clk_disable(&ctrl->msm_dp_ctrl); =20 @@ -2849,6 +2883,7 @@ struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *de= v, struct msm_dp_link *link ctrl->link_base =3D link_base; ctrl->mst2link_base =3D mst2link_base; ctrl->mst3link_base =3D mst3link_base; + ctrl->mst_active =3D false; =20 ret =3D msm_dp_ctrl_clk_init(&ctrl->msm_dp_ctrl, max_stream); if (ret) { diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index 2baf7a1ff44dd7139d2da86390121d5e7a063e9a..abf84ddf463638900684f251154= 9a593783d2247 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -16,7 +16,7 @@ struct msm_dp_ctrl { =20 struct phy; =20 -int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl); +int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl, bool mst_active); int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_p= anel *msm_dp_panel); int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train); void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl); @@ -50,5 +50,5 @@ void msm_dp_ctrl_enable_irq(struct msm_dp_ctrl *msm_dp_ct= rl); void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_ctrl); =20 void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_dp_ctrl); - +void msm_dp_ctrl_mst_send_act(struct msm_dp_ctrl *msm_dp_ctrl); #endif /* _DP_CTRL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 562a5eccf3f08c5669cc7c2ad1268897e975d0c4..eeba73f81c5ce7929dac88f4b47= ac3741659864b 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -709,7 +709,7 @@ static int msm_dp_display_prepare(struct msm_dp_display= _private *dp) force_link_train =3D true; } =20 - rc =3D msm_dp_ctrl_on_link(dp->ctrl); + rc =3D msm_dp_ctrl_on_link(dp->ctrl, msm_dp_display->mst_active); if (rc) { DRM_ERROR("Failed link training (rc=3D%d)\n", rc); msm_dp_display->connector->state->link_status =3D DRM_LINK_STATUS_BAD; @@ -1557,6 +1557,7 @@ void msm_dp_display_atomic_disable(struct msm_dp *dp) msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); =20 msm_dp_ctrl_push_idle(msm_dp_display->ctrl); + msm_dp_ctrl_mst_send_act(msm_dp_display->ctrl); } =20 static void msm_dp_display_unprepare(struct msm_dp_display_private *dp) diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index a839d0a3941eac3e277185e42fddea15ca05a17f..9442157bca9d63467b4c43fa644= 651ad2cbcbef5 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -21,6 +21,7 @@ struct msm_dp { bool audio_enabled; bool power_on; bool prepared; + bool mst_active; unsigned int connector_type; bool is_edp; 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Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 17 +++++++++++++++++ drivers/gpu/drm/msm/dp/dp_reg.h | 1 + 2 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 16e5ed58e791971d5dca3077cbb77bfcc186505a..d562377a8d2846099bf0f875712= 8978a162745c3 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -254,6 +254,19 @@ void msm_dp_ctrl_mst_send_act(struct msm_dp_ctrl *msm_= dp_ctrl) return; } =20 +static void msm_dp_ctrl_mst_config(struct msm_dp_ctrl_private *ctrl, bool = enable) +{ + u32 mainlink_ctrl; + + mainlink_ctrl =3D msm_dp_read_link(ctrl, REG_DP_MAINLINK_CTRL); + if (enable) + mainlink_ctrl |=3D DP_MAINLINK_CTRL_MST_EN; + else + mainlink_ctrl &=3D ~DP_MAINLINK_CTRL_MST_EN; + + msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); +} + /* * NOTE: resetting DP controller will also clear any pending HPD related i= nterrupts */ @@ -2656,6 +2669,9 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, struct msm_dp_panel * msm_dp_ctrl_lane_mapping(ctrl); msm_dp_setup_peripheral_flush(ctrl); =20 + if (ctrl->mst_active) + msm_dp_ctrl_mst_config(ctrl, true); + if (msm_dp_panel->stream_id =3D=3D DP_STREAM_0) msm_dp_ctrl_config_ctrl_link(ctrl); =20 @@ -2711,6 +2727,7 @@ void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_= ctrl) phy =3D ctrl->phy; =20 msm_dp_ctrl_mainlink_disable(ctrl); + msm_dp_ctrl_mst_config(ctrl, false); =20 msm_dp_ctrl_reset(&ctrl->msm_dp_ctrl); =20 diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_re= g.h index de3d0b8b52c269fd7575edf3f4096a4284ad0b8d..fda847b33f8d0d6ec4d2589586b= 5a3d6c9b1ccf3 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -128,6 +128,7 @@ #define DP_MAINLINK_FLUSH_MODE_UPDATE_SDP FIELD_PREP(DP_MAINLINK_CTRL_FLUS= H_MODE_MASK, 1) #define DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE FIELD_PREP(DP_MAINLINK_CT= RL_FLUSH_MODE_MASK, 3) #define DP_MAINLINK_FB_BOUNDARY_SEL (0x02000000) +#define DP_MAINLINK_CTRL_MST_EN (0x04000100) =20 #define REG_DP_STATE_CTRL (0x00000004) #define DP_STATE_CTRL_LINK_TRAINING_PATTERN1 (0x00000001) --=20 2.34.1 From nobody Fri Oct 3 20:22:40 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E49A3002C0 for ; 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Skip the TU programming for MST cases. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index d562377a8d2846099bf0f8757128978a162745c3..c313a3b4853a1571c43a9f3c9e9= 81fbc22d51d55 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -2685,7 +2685,8 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, struct msm_dp_panel * =20 msm_dp_panel_clear_dsc_dto(msm_dp_panel); =20 - msm_dp_ctrl_setup_tr_unit(ctrl); + if (!ctrl->mst_active) + msm_dp_ctrl_setup_tr_unit(ctrl); =20 msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); =20 --=20 2.34.1 From nobody Fri Oct 3 20:22:40 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6424D2FCBEA for ; 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This patch adds support for calculating the rate governor, slot allocation, and slot reservation in the DP controller. Each MST stream can reserve its slots by calling dp_display_set_stream_info() from its bridge callbacks. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 213 ++++++++++++++++++++++++++++++++= +++- drivers/gpu/drm/msm/dp/dp_ctrl.h | 7 +- drivers/gpu/drm/msm/dp/dp_display.c | 40 ++++--- drivers/gpu/drm/msm/dp/dp_display.h | 5 +- drivers/gpu/drm/msm/dp/dp_panel.h | 1 + drivers/gpu/drm/msm/dp/dp_reg.h | 14 ++- 6 files changed, 262 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index c313a3b4853a1571c43a9f3c9e981fbc22d51d55..9d58d9480fc4ab33c58218ef9be= b54c64805c34c 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -109,6 +109,11 @@ struct msm_dp_vc_tu_mapping_table { u8 tu_size_minus1; }; =20 +struct msm_dp_mst_ch_slot_info { + u32 start_slot; + u32 tot_slots; +}; + struct msm_dp_ctrl_private { struct msm_dp_ctrl msm_dp_ctrl; struct drm_device *drm_dev; @@ -143,6 +148,8 @@ struct msm_dp_ctrl_private { bool link_clks_on; bool stream_clks_on[DP_STREAM_MAX]; bool mst_active; + + struct msm_dp_mst_ch_slot_info mst_ch_info[DP_STREAM_MAX]; }; =20 static inline u32 msm_dp_read_ahb(const struct msm_dp_ctrl_private *ctrl, = u32 offset) @@ -267,6 +274,77 @@ static void msm_dp_ctrl_mst_config(struct msm_dp_ctrl_= private *ctrl, bool enable msm_dp_write_link(ctrl, REG_DP_MAINLINK_CTRL, mainlink_ctrl); } =20 +static void msm_dp_ctrl_mst_channel_alloc(struct msm_dp_ctrl_private *ctrl, + enum msm_dp_stream_id stream_id, u32 ch_start_slot, + u32 tot_slot_cnt) +{ + u32 i, slot_reg_1, slot_reg_2, slot; + u32 reg_off =3D 0; + int const num_slots_per_reg =3D 32; + + if (ch_start_slot > DP_MAX_TIME_SLOTS || + (ch_start_slot + tot_slot_cnt > DP_MAX_TIME_SLOTS)) { + DRM_ERROR("invalid slots start %d, tot %d\n", + ch_start_slot, tot_slot_cnt); + return; + } + + drm_dbg_dp(ctrl->drm_dev, "stream_id %d, start_slot %d, tot_slot %d\n", + stream_id, ch_start_slot, tot_slot_cnt); + + if (stream_id =3D=3D DP_STREAM_1) + reg_off =3D REG_DP_DP1_TIMESLOT_1_32 - REG_DP_DP0_TIMESLOT_1_32; + + slot_reg_1 =3D 0; + slot_reg_2 =3D 0; + + if (ch_start_slot && tot_slot_cnt) { + ch_start_slot--; + for (i =3D 0; i < tot_slot_cnt; i++) { + if (ch_start_slot < num_slots_per_reg) { + slot_reg_1 |=3D BIT(ch_start_slot); + } else { + slot =3D ch_start_slot - num_slots_per_reg; + slot_reg_2 |=3D BIT(slot); + } + ch_start_slot++; + } + } + + drm_dbg_dp(ctrl->drm_dev, "stream_id:%d slot_reg_1:%d, slot_reg_2:%d\n", = stream_id, + slot_reg_1, slot_reg_2); + + if (stream_id > DP_STREAM_1) { + msm_dp_write_mstlink(ctrl, stream_id, REG_DP_MSTLINK_TIMESLOT_1_32, + slot_reg_1); + msm_dp_write_mstlink(ctrl, stream_id, REG_DP_MSTLINK_TIMESLOT_33_63, + slot_reg_2); + } else { + msm_dp_write_link(ctrl, REG_DP_DP0_TIMESLOT_1_32 + reg_off, slot_reg_1); + msm_dp_write_link(ctrl, REG_DP_DP0_TIMESLOT_33_63 + reg_off, slot_reg_2); + } +} + +static void msm_dp_ctrl_update_rg(struct msm_dp_ctrl_private *ctrl, + enum msm_dp_stream_id stream_id, u32 x_int, u32 y_frac_enum) +{ + u32 rg, reg_off =3D 0; + + rg =3D y_frac_enum; + rg |=3D (x_int << 16); + + drm_dbg_dp(ctrl->drm_dev, "stream_id: %d x_int:%d y_frac_enum:%d rg:%d\n", + stream_id, x_int, y_frac_enum, rg); + + if (stream_id =3D=3D DP_STREAM_1) + reg_off =3D REG_DP_DP1_RG - REG_DP_DP0_RG; + + if (stream_id > DP_STREAM_1) + msm_dp_write_mstlink(ctrl, stream_id, REG_DP_MSTLINK_DP_RG, rg); + else + msm_dp_write_link(ctrl, REG_DP_DP0_RG + reg_off, rg); +} + /* * NOTE: resetting DP controller will also clear any pending HPD related i= nterrupts */ @@ -2634,7 +2712,105 @@ int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctr= l *msm_dp_ctrl, bool force_li return ret; } =20 -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_p= anel *msm_dp_panel) +static void msm_dp_ctrl_mst_calculate_rg(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *panel, + u32 *p_x_int, u32 *p_y_frac_enum) +{ + u64 min_slot_cnt, max_slot_cnt; + u64 raw_target_sc, target_sc_fixp; + u64 ts_denom, ts_enum, ts_int; + u64 pclk =3D panel->msm_dp_mode.drm_mode.clock; + u64 lclk =3D 0; + u64 lanes =3D ctrl->link->link_params.num_lanes; + u64 bpp =3D panel->msm_dp_mode.bpp; + u64 pbn =3D panel->pbn; + u64 numerator, denominator, temp, temp1, temp2; + u32 x_int =3D 0, y_frac_enum =3D 0; + u64 target_strm_sym, ts_int_fixp, ts_frac_fixp, y_frac_enum_fixp; + + lclk =3D ctrl->link->link_params.rate; + + /* min_slot_cnt */ + numerator =3D pclk * bpp * 64 * 1000; + denominator =3D lclk * lanes * 8 * 1000; + min_slot_cnt =3D drm_fixp_from_fraction(numerator, denominator); + + /* max_slot_cnt */ + numerator =3D pbn * 54 * 1000; + denominator =3D lclk * lanes; + max_slot_cnt =3D drm_fixp_from_fraction(numerator, denominator); + + /* raw_target_sc */ + numerator =3D max_slot_cnt + min_slot_cnt; + denominator =3D drm_fixp_from_fraction(2, 1); + raw_target_sc =3D drm_fixp_div(numerator, denominator); + + /* target_sc */ + temp =3D drm_fixp_from_fraction(256 * lanes, 1); + numerator =3D drm_fixp_mul(raw_target_sc, temp); + denominator =3D drm_fixp_from_fraction(256 * lanes, 1); + target_sc_fixp =3D drm_fixp_div(numerator, denominator); + + ts_enum =3D 256 * lanes; + ts_denom =3D drm_fixp_from_fraction(256 * lanes, 1); + ts_int =3D drm_fixp2int(target_sc_fixp); + + temp =3D drm_fixp2int_ceil(raw_target_sc); + if (temp !=3D ts_int) { + temp =3D drm_fixp_from_fraction(ts_int, 1); + temp1 =3D raw_target_sc - temp; + temp2 =3D drm_fixp_mul(temp1, ts_denom); + ts_enum =3D drm_fixp2int(temp2); + } + + /* target_strm_sym */ + ts_int_fixp =3D drm_fixp_from_fraction(ts_int, 1); + ts_frac_fixp =3D drm_fixp_from_fraction(ts_enum, drm_fixp2int(ts_denom)); + temp =3D ts_int_fixp + ts_frac_fixp; + temp1 =3D drm_fixp_from_fraction(lanes, 1); + target_strm_sym =3D drm_fixp_mul(temp, temp1); + + /* x_int */ + x_int =3D drm_fixp2int(target_strm_sym); + + /* y_enum_frac */ + temp =3D drm_fixp_from_fraction(x_int, 1); + temp1 =3D target_strm_sym - temp; + temp2 =3D drm_fixp_from_fraction(256, 1); + y_frac_enum_fixp =3D drm_fixp_mul(temp1, temp2); + + temp1 =3D drm_fixp2int(y_frac_enum_fixp); + temp2 =3D drm_fixp2int_ceil(y_frac_enum_fixp); + + y_frac_enum =3D (u32)((temp1 =3D=3D temp2) ? temp1 : temp1 + 1); + + *p_x_int =3D x_int; + *p_y_frac_enum =3D y_frac_enum; + + drm_dbg_dp(ctrl->drm_dev, "mst lane_cnt:%llu, rate:%llu x_int:%d, y_frac:= %d\n", + lanes, lclk, x_int, y_frac_enum); +} + +static void msm_dp_ctrl_mst_stream_setup(struct msm_dp_ctrl_private *ctrl, + struct msm_dp_panel *panel, + u32 max_streams) +{ + u32 x_int, y_frac_enum; + + if (!ctrl->mst_active) + return; + + drm_dbg_dp(ctrl->drm_dev, "mst stream channel allocation\n"); + + msm_dp_ctrl_mst_stream_channel_slot_setup(&ctrl->msm_dp_ctrl, max_streams= ); + + msm_dp_ctrl_mst_calculate_rg(ctrl, panel, &x_int, &y_frac_enum); + + msm_dp_ctrl_update_rg(ctrl, panel->stream_id, x_int, y_frac_enum); +} + +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *msm_dp_panel, u32 max_streams) { int ret =3D 0; bool mainlink_ready =3D false; @@ -2688,6 +2864,8 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_= ctrl, struct msm_dp_panel * if (!ctrl->mst_active) msm_dp_ctrl_setup_tr_unit(ctrl); =20 + msm_dp_ctrl_mst_stream_setup(ctrl, msm_dp_panel, max_streams); + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_SEND_VIDEO); =20 msm_dp_ctrl_mst_send_act(msm_dp_ctrl); @@ -2742,6 +2920,39 @@ void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp= _ctrl) phy, phy->init_count, phy->power_count); } =20 +void msm_dp_ctrl_set_mst_channel_info(struct msm_dp_ctrl *msm_dp_ctrl, + enum msm_dp_stream_id stream_id, + u32 start_slot, u32 tot_slots) +{ + struct msm_dp_ctrl_private *ctrl; + + if (!msm_dp_ctrl || stream_id >=3D DP_STREAM_MAX) { + DRM_ERROR("invalid input\n"); + return; + } + + ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); + + ctrl->mst_ch_info[stream_id].start_slot =3D start_slot; + ctrl->mst_ch_info[stream_id].tot_slots =3D tot_slots; +} + +void msm_dp_ctrl_mst_stream_channel_slot_setup(struct msm_dp_ctrl *msm_dp_= ctrl, u32 max_streams) +{ + struct msm_dp_ctrl_private *ctrl; + int i; + + ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); + + if (!ctrl->mst_active) + return; + + for (i =3D DP_STREAM_0; i < max_streams; i++) { + msm_dp_ctrl_mst_channel_alloc(ctrl, i, ctrl->mst_ch_info[i].start_slot, + ctrl->mst_ch_info[i].tot_slots); + } +} + irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl) { struct msm_dp_ctrl_private *ctrl; diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index abf84ddf463638900684f2511549a593783d2247..751f00c97b94dc3b9e8fae2a86e= 261f71f293425 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -17,7 +17,8 @@ struct msm_dp_ctrl { struct phy; =20 int msm_dp_ctrl_on_link(struct msm_dp_ctrl *msm_dp_ctrl, bool mst_active); -int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_p= anel *msm_dp_panel); +int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, + struct msm_dp_panel *msm_dp_panel, u32 max_streams); int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train); void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl, enum msm_d= p_stream_id stream_id); @@ -51,4 +52,8 @@ void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_c= trl); =20 void msm_dp_ctrl_reinit_phy(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_mst_send_act(struct msm_dp_ctrl *msm_dp_ctrl); +void msm_dp_ctrl_mst_stream_channel_slot_setup(struct msm_dp_ctrl *msm_dp_= ctrl, u32 max_streams); +void msm_dp_ctrl_set_mst_channel_info(struct msm_dp_ctrl *msm_dp_ctrl, + enum msm_dp_stream_id stream_id, + u32 start_slot, u32 tot_slots); #endif /* _DP_CTRL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index eeba73f81c5ce7929dac88f4b47ac3741659864b..17633ba79aa7642856051b69227= e8f5b23d76730 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -733,7 +733,7 @@ static int msm_dp_display_enable(struct msm_dp_display_= private *dp) return 0; } =20 - rc =3D msm_dp_ctrl_on_stream(dp->ctrl, dp->panel); + rc =3D msm_dp_ctrl_on_stream(dp->ctrl, dp->panel, dp->max_stream); if (!rc) msm_dp_display->power_on =3D true; =20 @@ -817,21 +817,33 @@ static int msm_dp_display_disable(struct msm_dp_displ= ay_private *dp) return 0; } =20 -int msm_dp_display_set_stream_id(struct msm_dp *dp, - struct msm_dp_panel *panel, enum msm_dp_stream_id stream_id) +int msm_dp_display_set_stream_info(struct msm_dp *msm_dp_display, struct m= sm_dp_panel *panel, + enum msm_dp_stream_id stream_id, u32 start_slot, + u32 num_slots, u32 pbn, int vcpi) { int rc =3D 0; - struct msm_dp_display_private *msm_dp_display; + struct msm_dp_display_private *dp; + const int max_slots =3D 64; =20 - msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - if (!msm_dp_display) { + if (!dp) { DRM_ERROR("invalid input\n"); return -EINVAL; } =20 - if (panel) + if (start_slot + num_slots > max_slots) { + DRM_ERROR("invalid channel info received. start:%d, slots:%d\n", + start_slot, num_slots); + return -EINVAL; + } + + msm_dp_ctrl_set_mst_channel_info(dp->ctrl, stream_id, start_slot, num_slo= ts); + + if (panel) { panel->stream_id =3D stream_id; + panel->pbn =3D pbn; + } =20 return rc; } @@ -1533,7 +1545,7 @@ void msm_dp_display_atomic_enable(struct msm_dp *msm_= dp_display) =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - msm_dp_display_set_stream_id(msm_dp_display, dp->panel, 0); + msm_dp_display_set_stream_info(msm_dp_display, dp->panel, 0, 0, 0, 0, 0); =20 if (msm_dp_display->prepared) { rc =3D msm_dp_display_enable(dp); @@ -1550,14 +1562,16 @@ void msm_dp_display_atomic_enable(struct msm_dp *ms= m_dp_display) drm_dbg_dp(msm_dp_display->drm_dev, "type=3D%d Done\n", msm_dp_display->c= onnector_type); } =20 -void msm_dp_display_atomic_disable(struct msm_dp *dp) +void msm_dp_display_atomic_disable(struct msm_dp *msm_dp_display) { - struct msm_dp_display_private *msm_dp_display; + struct msm_dp_display_private *dp; =20 - msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - msm_dp_ctrl_push_idle(msm_dp_display->ctrl); - msm_dp_ctrl_mst_send_act(msm_dp_display->ctrl); + msm_dp_ctrl_push_idle(dp->ctrl); + msm_dp_ctrl_mst_stream_channel_slot_setup(dp->ctrl, + dp->max_stream); + msm_dp_ctrl_mst_send_act(dp->ctrl); } =20 static void msm_dp_display_unprepare(struct msm_dp_display_private *dp) diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index 9442157bca9d63467b4c43fa644651ad2cbcbef5..fa92f763d2304f15af7c4e1e7e8= aab5a6ffd3459 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -48,7 +48,8 @@ void msm_dp_display_mode_set(struct msm_dp *dp, enum drm_mode_status msm_dp_display_mode_valid(struct msm_dp *dp, const struct drm_display_info *info, const struct drm_display_mode *mode); -int msm_dp_display_set_stream_id(struct msm_dp *dp, - struct msm_dp_panel *panel, enum msm_dp_stream_id stream_id); +int msm_dp_display_set_stream_info(struct msm_dp *dp_display, struct msm_d= p_panel *panel, + enum msm_dp_stream_id stream_id, + u32 start_slot, u32 num_slots, u32 pbn, int vcpi); =20 #endif /* _DP_DISPLAY_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index 2bfe3695994235d04e209a2785915107c6a8e413..cb5bf6c99a6f7a68995f0f0ac48= 382dc90beca31 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -50,6 +50,7 @@ struct msm_dp_panel { u32 hw_revision; =20 enum msm_dp_stream_id stream_id; + u32 pbn; =20 u32 max_dp_lanes; u32 max_dp_link_rate; diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_re= g.h index fda847b33f8d0d6ec4d2589586b5a3d6c9b1ccf3..ee4debf796910e00d370ab4c687= 009747bae5378 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -364,6 +364,19 @@ #define REG_DP_PHY_AUX_BIST_CFG (0x00000050) #define REG_DP_PHY_AUX_INTERRUPT_STATUS (0x000000BC) =20 +/* DP MST related registers */ +#define DP_MAX_TIME_SLOTS 64 + +#define REG_DP_MSTLINK_DP_RG (0X0000011C) +#define REG_DP_DP0_TIMESLOT_1_32 (0x00000404) +#define REG_DP_DP0_TIMESLOT_33_63 (0x00000408) +#define REG_DP_DP1_TIMESLOT_1_32 (0x0000040C) +#define REG_DP_DP1_TIMESLOT_33_63 (0x00000410) +#define REG_DP_MSTLINK_TIMESLOT_1_32 (0x00000038) +#define REG_DP_MSTLINK_TIMESLOT_33_63 (0x0000003C) +#define REG_DP_DP0_RG (0x000004F8) +#define REG_DP_DP1_RG (0x000004FC) + /* DP HDCP 1.3 registers */ #define DP_HDCP_CTRL (0x0A0) #define DP_HDCP_STATUS (0x0A4) @@ -388,5 +401,4 @@ #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA10 (0x018) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA11 (0x01C) #define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA12 (0x020) - #endif /* _DP_REG_H_ */ --=20 2.34.1 From nobody Fri Oct 3 20:22:40 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66341301013 for ; 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This patch adds support for triggering the VCPF sequence in the MSM DP controller. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 56 +++++++++++++++++++++++++++++++++= +--- drivers/gpu/drm/msm/dp/dp_ctrl.h | 2 +- drivers/gpu/drm/msm/dp/dp_display.c | 2 +- drivers/gpu/drm/msm/dp/dp_reg.h | 6 ++++ 4 files changed, 60 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 9d58d9480fc4ab33c58218ef9beb54c64805c34c..58e8c526253f77f306c669d474b= db2d1751b49a5 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -65,9 +65,18 @@ (PSR_UPDATE_MASK | PSR_CAPTURE_MASK | PSR_EXIT_MASK | \ PSR_UPDATE_ERROR_MASK | PSR_WAKE_ERROR_MASK) =20 +#define DP_INTERRUPT_STATUS5 \ + (DP_INTR_DP0_VCPF_SENT | DP_INTR_DP1_VCPF_SENT) +#define DP_INTERRUPT_STATUS5_MASK \ + (DP_INTERRUPT_STATUS5 << DP_INTERRUPT_STATUS_MASK_SHIFT) + #define DP_CTRL_INTR_READY_FOR_VIDEO BIT(0) #define DP_CTRL_INTR_IDLE_PATTERN_SENT BIT(3) =20 +#define DP_DP0_PUSH_VCPF BIT(12) +#define DP_DP1_PUSH_VCPF BIT(14) +#define DP_MSTLINK_PUSH_VCPF BIT(12) + #define MR_LINK_TRAINING1 0x8 #define MR_LINK_SYMBOL_ERM 0x80 #define MR_LINK_PRBS7 0x100 @@ -407,6 +416,8 @@ void msm_dp_ctrl_enable_irq(struct msm_dp_ctrl *msm_dp_= ctrl) DP_INTERRUPT_STATUS1_MASK); msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS2, DP_INTERRUPT_STATUS2_MASK); + msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS5, + DP_INTERRUPT_STATUS5_MASK); } =20 void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp_ctrl) @@ -416,6 +427,7 @@ void msm_dp_ctrl_disable_irq(struct msm_dp_ctrl *msm_dp= _ctrl) =20 msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS, 0x00); msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS2, 0x00); + msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS5, 0x00); } =20 static u32 msm_dp_ctrl_get_psr_interrupt(struct msm_dp_ctrl_private *ctrl) @@ -435,6 +447,20 @@ static void msm_dp_ctrl_config_psr_interrupt(struct ms= m_dp_ctrl_private *ctrl) msm_dp_write_ahb(ctrl, REG_DP_INTR_MASK4, DP_INTERRUPT_MASK4); } =20 +static u32 msm_dp_ctrl_get_mst_interrupt(struct msm_dp_ctrl_private *ctrl) +{ + u32 intr, intr_ack; + + intr =3D msm_dp_read_ahb(ctrl, REG_DP_INTR_STATUS5); + intr &=3D ~DP_INTERRUPT_STATUS5_MASK; + intr_ack =3D (intr & DP_INTERRUPT_STATUS5) + << DP_INTERRUPT_STATUS_ACK_SHIFT; + msm_dp_write_ahb(ctrl, REG_DP_INTR_STATUS5, + intr_ack | DP_INTERRUPT_STATUS5_MASK); + + return intr; +} + static void msm_dp_ctrl_psr_mainlink_enable(struct msm_dp_ctrl_private *ct= rl) { u32 val; @@ -518,14 +544,29 @@ static bool msm_dp_ctrl_mainlink_ready(struct msm_dp_= ctrl_private *ctrl) return true; } =20 -void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl) +void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_= panel *msm_dp_panel) { struct msm_dp_ctrl_private *ctrl; + u32 state =3D 0x0; =20 ctrl =3D container_of(msm_dp_ctrl, struct msm_dp_ctrl_private, msm_dp_ctr= l); =20 + if (!ctrl->mst_active) + state |=3D DP_STATE_CTRL_PUSH_IDLE; + else if (msm_dp_panel->stream_id =3D=3D DP_STREAM_0) + state |=3D DP_DP0_PUSH_VCPF; + else if (msm_dp_panel->stream_id =3D=3D DP_STREAM_1) + state |=3D DP_DP1_PUSH_VCPF; + else + state |=3D DP_MSTLINK_PUSH_VCPF; + reinit_completion(&ctrl->idle_comp); - msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, DP_STATE_CTRL_PUSH_IDLE); + + if (msm_dp_panel->stream_id > DP_STREAM_1) + msm_dp_write_mstlink(ctrl, msm_dp_panel->stream_id, + REG_DP_MSTLINK_STATE_CTRL, state); + else + msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, state); =20 if (!wait_for_completion_timeout(&ctrl->idle_comp, IDLE_PATTERN_COMPLETION_TIMEOUT_JIFFIES)) @@ -2074,7 +2115,7 @@ void msm_dp_ctrl_set_psr(struct msm_dp_ctrl *msm_dp_c= trl, bool enter) return; } =20 - msm_dp_ctrl_push_idle(msm_dp_ctrl); + msm_dp_ctrl_push_idle(msm_dp_ctrl, ctrl->panel); msm_dp_write_link(ctrl, REG_DP_STATE_CTRL, 0); =20 msm_dp_ctrl_psr_mainlink_disable(ctrl); @@ -2184,7 +2225,7 @@ static int msm_dp_ctrl_link_maintenance(struct msm_dp= _ctrl_private *ctrl) int ret =3D 0; int training_step =3D DP_TRAINING_NONE; =20 - msm_dp_ctrl_push_idle(&ctrl->msm_dp_ctrl); + msm_dp_ctrl_push_idle(&ctrl->msm_dp_ctrl, ctrl->panel); =20 ctrl->link->phy_params.p_level =3D 0; ctrl->link->phy_params.v_level =3D 0; @@ -2994,6 +3035,13 @@ irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_= dp_ctrl) ret =3D IRQ_HANDLED; } =20 + isr =3D msm_dp_ctrl_get_mst_interrupt(ctrl); + if (isr & (DP_INTR_DP0_VCPF_SENT | DP_INTR_DP1_VCPF_SENT)) { + drm_dbg_dp(ctrl->drm_dev, "vcpf sent\n"); + complete(&ctrl->idle_comp); + ret =3D IRQ_HANDLED; + } + /* DP aux isr */ isr =3D msm_dp_ctrl_get_aux_interrupt(ctrl); if (isr) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_c= trl.h index 751f00c97b94dc3b9e8fae2a86e261f71f293425..356030fda9a749f0caa4438ffad= 88c3f34ce8960 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -22,7 +22,7 @@ int msm_dp_ctrl_on_stream(struct msm_dp_ctrl *msm_dp_ctrl, int msm_dp_ctrl_prepare_stream_on(struct msm_dp_ctrl *msm_dp_ctrl, bool fo= rce_link_train); void msm_dp_ctrl_off_link(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_off_pixel_clk(struct msm_dp_ctrl *msm_dp_ctrl, enum msm_d= p_stream_id stream_id); -void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl); +void msm_dp_ctrl_push_idle(struct msm_dp_ctrl *msm_dp_ctrl, struct msm_dp_= panel *msm_dp_panel); irqreturn_t msm_dp_ctrl_isr(struct msm_dp_ctrl *msm_dp_ctrl); void msm_dp_ctrl_handle_sink_request(struct msm_dp_ctrl *msm_dp_ctrl); struct msm_dp_ctrl *msm_dp_ctrl_get(struct device *dev, diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 17633ba79aa7642856051b69227e8f5b23d76730..e02ada7a3dc3b89618aeadd998e= 9a41236ee6bbf 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -1568,7 +1568,7 @@ void msm_dp_display_atomic_disable(struct msm_dp *msm= _dp_display) =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - msm_dp_ctrl_push_idle(dp->ctrl); + msm_dp_ctrl_push_idle(dp->ctrl, dp->panel); msm_dp_ctrl_mst_stream_channel_slot_setup(dp->ctrl, dp->max_stream); msm_dp_ctrl_mst_send_act(dp->ctrl); diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_re= g.h index ee4debf796910e00d370ab4c687009747bae5378..70fb647a25c05dc89f6aaf21456= ddf2918cecbc3 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -42,9 +42,13 @@ #define DP_INTR_FRAME_END BIT(6) #define DP_INTR_CRC_UPDATED BIT(9) =20 +#define DP_INTR_DP0_VCPF_SENT BIT(0) +#define DP_INTR_DP1_VCPF_SENT BIT(3) + #define REG_DP_INTR_STATUS3 (0x00000028) =20 #define REG_DP_INTR_STATUS4 (0x0000002C) +#define REG_DP_INTR_STATUS5 (0x00000034) #define PSR_UPDATE_INT (0x00000001) #define PSR_CAPTURE_INT (0x00000004) #define PSR_EXIT_INT (0x00000010) @@ -377,6 +381,8 @@ #define REG_DP_DP0_RG (0x000004F8) #define REG_DP_DP1_RG (0x000004FC) =20 +#define REG_DP_MSTLINK_STATE_CTRL (0x00000000) + /* DP HDCP 1.3 registers */ #define DP_HDCP_CTRL (0x0A0) #define DP_HDCP_STATUS (0x0A4) --=20 2.34.1 From nobody Fri Oct 3 20:22:40 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 532752FCBEB for ; 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This patch ensures the register is configured accordingly. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 2 ++ drivers/gpu/drm/msm/dp/dp_panel.c | 12 ++++++++++++ drivers/gpu/drm/msm/dp/dp_panel.h | 2 ++ 3 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index 58e8c526253f77f306c669d474bdb2d1751b49a5..9f8733da78cea20593b4fd4d4a0= 7583fd17d316b 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -693,6 +693,8 @@ static void msm_dp_ctrl_configure_source_params(struct = msm_dp_ctrl_private *ctrl msm_dp_ctrl_config_misc1_misc0(ctrl, msm_dp_panel); =20 msm_dp_panel_timing_cfg(msm_dp_panel, ctrl->msm_dp_ctrl.wide_bus_en); + + msm_dp_panel_mst_async_fifo(msm_dp_panel, ctrl->mst_active); } =20 /* diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index f792687c315a2c8203305a20b7290a93b0d791f4..f58cf38a47a119790f86b40ee86= d45a3ffbd951f 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -694,6 +694,18 @@ int msm_dp_panel_timing_cfg(struct msm_dp_panel *msm_d= p_panel, bool wide_bus_en) return 0; } =20 +void msm_dp_panel_mst_async_fifo(struct msm_dp_panel *msm_dp_panel, bool m= st_en) +{ + struct msm_dp_panel_private *panel; + + panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); + + if (mst_en) + msm_dp_write_pn(panel, MMSS_DP_ASYNC_FIFO_CONFIG, 0x01); + else + msm_dp_write_pn(panel, MMSS_DP_ASYNC_FIFO_CONFIG, 0x00); +} + int msm_dp_panel_init_panel_info(struct msm_dp_panel *msm_dp_panel) { struct drm_display_mode *drm_mode; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index cb5bf6c99a6f7a68995f0f0ac48382dc90beca31..715ffc739ac4bec4d41bf4176a0= 4d6651e81bbd4 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -74,6 +74,8 @@ void msm_dp_panel_clear_dsc_dto(struct msm_dp_panel *msm_= dp_panel); void msm_dp_panel_enable_vsc_sdp(struct msm_dp_panel *msm_dp_panel, struct= dp_sdp *vsc_sdp); void msm_dp_panel_disable_vsc_sdp(struct msm_dp_panel *msm_dp_panel); =20 +void msm_dp_panel_mst_async_fifo(struct msm_dp_panel *msm_dp_panel, bool m= st_en); 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To be able to re-use these helpers for MST use-case abstract the helpers to use the panel which is passed in to them. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 138 +++++++++++++++++++++++---------= ---- drivers/gpu/drm/msm/dp/dp_display.h | 12 ++++ 2 files changed, 102 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index e02ada7a3dc3b89618aeadd998e9a41236ee6bbf..0815973e6597492e09f33359d97= 77c0e8ce31e0d 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -695,6 +695,11 @@ static int msm_dp_display_prepare(struct msm_dp_displa= y_private *dp) =20 drm_dbg_dp(dp->drm_dev, "sink_count=3D%d\n", dp->link->sink_count); =20 + if (msm_dp_display->prepared) { + drm_dbg_dp(dp->drm_dev, "Link already setup, return\n"); + return 0; + } + rc =3D pm_runtime_resume_and_get(&msm_dp_display->pdev->dev); if (rc) { DRM_ERROR("failed to pm_runtime_resume\n"); @@ -722,7 +727,8 @@ static int msm_dp_display_prepare(struct msm_dp_display= _private *dp) return rc; } =20 -static int msm_dp_display_enable(struct msm_dp_display_private *dp) +static int msm_dp_display_enable(struct msm_dp_display_private *dp, + struct msm_dp_panel *msm_dp_panel) { int rc =3D 0; struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; @@ -733,7 +739,7 @@ static int msm_dp_display_enable(struct msm_dp_display_= private *dp) return 0; } =20 - rc =3D msm_dp_ctrl_on_stream(dp->ctrl, dp->panel, dp->max_stream); + rc =3D msm_dp_ctrl_on_stream(dp->ctrl, msm_dp_panel, dp->max_stream); if (!rc) msm_dp_display->power_on =3D true; =20 @@ -779,37 +785,17 @@ static void msm_dp_display_audio_notify_disable(struc= t msm_dp_display_private *d msm_dp_display->audio_enabled =3D false; } =20 -static int msm_dp_display_disable(struct msm_dp_display_private *dp) +static int msm_dp_display_disable(struct msm_dp_display_private *dp, + struct msm_dp_panel *msm_dp_panel) { struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; =20 if (!msm_dp_display->power_on) return 0; =20 - msm_dp_panel_disable_vsc_sdp(dp->panel); + msm_dp_panel_disable_vsc_sdp(msm_dp_panel); =20 - /* dongle is still connected but sinks are disconnected */ - if (dp->link->sink_count =3D=3D 0) { - /* - * irq_hpd with sink_count =3D 0 - * hdmi unplugged out of dongle - */ - - /* set dongle to D3 (power off) mode */ - msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); - msm_dp_ctrl_off_pixel_clk(dp->ctrl, dp->panel->stream_id); - msm_dp_ctrl_off_link(dp->ctrl); - /* re-init the PHY so that we can listen to Dongle disconnect */ - msm_dp_ctrl_reinit_phy(dp->ctrl); - } else { - /* - * unplugged interrupt - * dongle unplugged out of DUT - */ - msm_dp_ctrl_off_pixel_clk(dp->ctrl, dp->panel->stream_id); - msm_dp_ctrl_off_link(dp->ctrl); - msm_dp_display_host_phy_exit(dp); - } + msm_dp_ctrl_off_pixel_clk(dp->ctrl, msm_dp_panel->stream_id); =20 msm_dp_display->power_on =3D false; =20 @@ -1538,52 +1524,90 @@ void msm_dp_display_atomic_prepare(struct msm_dp *m= sm_dp_display) return; } =20 -void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display) +void msm_dp_display_enable_helper(struct msm_dp *msm_dp_display, struct ms= m_dp_panel *msm_dp_panel) { struct msm_dp_display_private *dp; int rc =3D 0; =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - msm_dp_display_set_stream_info(msm_dp_display, dp->panel, 0, 0, 0, 0, 0); - if (msm_dp_display->prepared) { - rc =3D msm_dp_display_enable(dp); + rc =3D msm_dp_display_enable(dp, msm_dp_panel); if (rc) DRM_ERROR("DP display enable failed, rc=3D%d\n", rc); =20 rc =3D msm_dp_display_post_enable(msm_dp_display); if (rc) { DRM_ERROR("DP display post enable failed, rc=3D%d\n", rc); - msm_dp_display_disable(dp); + msm_dp_display_disable(dp, msm_dp_panel); } } =20 drm_dbg_dp(msm_dp_display->drm_dev, "type=3D%d Done\n", msm_dp_display->c= onnector_type); } =20 -void msm_dp_display_atomic_disable(struct msm_dp *msm_dp_display) +void msm_dp_display_atomic_enable(struct msm_dp *msm_dp_display) { struct msm_dp_display_private *dp; =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 - msm_dp_ctrl_push_idle(dp->ctrl, dp->panel); + msm_dp_display_set_stream_info(msm_dp_display, dp->panel, 0, 0, 0, 0, 0); + + msm_dp_display_enable_helper(msm_dp_display, dp->panel); +} + +void msm_dp_display_disable_helper(struct msm_dp *msm_dp_display, + struct msm_dp_panel *msm_dp_panel) +{ + struct msm_dp_display_private *dp; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); + + msm_dp_ctrl_push_idle(dp->ctrl, msm_dp_panel); msm_dp_ctrl_mst_stream_channel_slot_setup(dp->ctrl, dp->max_stream); msm_dp_ctrl_mst_send_act(dp->ctrl); } =20 -static void msm_dp_display_unprepare(struct msm_dp_display_private *dp) +void msm_dp_display_atomic_disable(struct msm_dp *msm_dp_display) { - struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; + struct msm_dp_display_private *dp; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); + + msm_dp_display_disable_helper(msm_dp_display, dp->panel); +} + +void msm_dp_display_unprepare(struct msm_dp *msm_dp_display) +{ + struct msm_dp_display_private *dp; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); + + if (!msm_dp_display->prepared) { + drm_dbg_dp(dp->drm_dev, "Link already setup, return\n"); + return; + } + + /* dongle is still connected but sinks are disconnected */ + if (dp->link->sink_count =3D=3D 0) + msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); + + msm_dp_ctrl_off_link(dp->ctrl); + + /* re-init the PHY so that we can listen to Dongle disconnect */ + if (dp->link->sink_count =3D=3D 0) + msm_dp_ctrl_reinit_phy(dp->ctrl); + else + msm_dp_display_host_phy_exit(dp); =20 pm_runtime_put_sync(&msm_dp_display->pdev->dev); =20 msm_dp_display->prepared =3D false; } =20 -void msm_dp_display_atomic_post_disable(struct msm_dp *dp) +void msm_dp_display_atomic_post_disable_helper(struct msm_dp *dp, struct m= sm_dp_panel *msm_dp_panel) { struct msm_dp_display_private *msm_dp_display; =20 @@ -1597,28 +1621,46 @@ void msm_dp_display_atomic_post_disable(struct msm_= dp *dp) =20 msm_dp_display_audio_notify_disable(msm_dp_display); =20 - msm_dp_display_disable(msm_dp_display); + msm_dp_display_disable(msm_dp_display, msm_dp_panel); + + drm_dbg_dp(dp->drm_dev, "type=3D%d Done\n", dp->connector_type); +} + +void msm_dp_display_atomic_post_disable(struct msm_dp *msm_dp_display) +{ + struct msm_dp_display_private *dp; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); + + msm_dp_display_atomic_post_disable_helper(msm_dp_display, dp->panel); =20 msm_dp_display_unprepare(msm_dp_display); +} =20 - drm_dbg_dp(dp->drm_dev, "type=3D%d Done\n", dp->connector_type); +void msm_dp_display_mode_set_helper(struct msm_dp *msm_dp, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode, + struct msm_dp_panel *msm_dp_panel) +{ + struct msm_dp_display_private *dp; + + dp =3D container_of(msm_dp, struct msm_dp_display_private, msm_dp_display= ); + + msm_dp_display_set_mode(msm_dp, adjusted_mode, msm_dp_panel); + /* populate wide_bus_support to different layers */ + dp->ctrl->wide_bus_en =3D msm_dp_panel->msm_dp_mode.out_fmt_is_yuv_420 ? + false : dp->wide_bus_supported; } =20 -void msm_dp_display_mode_set(struct msm_dp *dp, +void msm_dp_display_mode_set(struct msm_dp *msm_dp, const struct drm_display_mode *mode, const struct drm_display_mode *adjusted_mode) { - struct msm_dp_display_private *msm_dp_display; - struct msm_dp_panel *msm_dp_panel; - - msm_dp_display =3D container_of(dp, struct msm_dp_display_private, msm_dp= _display); - msm_dp_panel =3D msm_dp_display->panel; + struct msm_dp_display_private *dp; =20 - msm_dp_display_set_mode(dp, adjusted_mode, msm_dp_panel); + dp =3D container_of(msm_dp, struct msm_dp_display_private, msm_dp_display= ); =20 - /* populate wide_bus_support to different layers */ - msm_dp_display->ctrl->wide_bus_en =3D msm_dp_panel->msm_dp_mode.out_fmt_i= s_yuv_420 ? - false : msm_dp_display->wide_bus_supported; + msm_dp_display_mode_set_helper(msm_dp, mode, adjusted_mode, dp->panel); } =20 void msm_dp_bridge_hpd_enable(struct drm_bridge *bridge) diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index fa92f763d2304f15af7c4e1e7e8aab5a6ffd3459..20b7ed735b3f428e894b82ae275= 6d0efcfa47624 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -51,5 +51,17 @@ enum drm_mode_status msm_dp_display_mode_valid(struct ms= m_dp *dp, int msm_dp_display_set_stream_info(struct msm_dp *dp_display, struct msm_d= p_panel *panel, enum msm_dp_stream_id stream_id, u32 start_slot, u32 num_slots, u32 pbn, int vcpi); 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Introduce an active_stream_cnt to track the number of active streams and necessary state handling. Replace the power_on variable with active_stream_cnt as power_on boolean works only for a single stream. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_audio.c | 2 +- drivers/gpu/drm/msm/dp/dp_display.c | 50 ++++++++++++++++++++++++---------= ---- drivers/gpu/drm/msm/dp/dp_display.h | 3 ++- 3 files changed, 36 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_audio.c b/drivers/gpu/drm/msm/dp/dp_= audio.c index 41018e82efa10ec863eb4b60d8df66c23c432fa5..e84c8b8e83d9ec689c0d29e8ac6= 9860a745a4877 100644 --- a/drivers/gpu/drm/msm/dp/dp_audio.c +++ b/drivers/gpu/drm/msm/dp/dp_audio.c @@ -284,7 +284,7 @@ int msm_dp_audio_prepare(struct drm_bridge *bridge, * such cases check for connection status and bail out if not * connected. */ - if (!msm_dp_display->power_on) { + if (!msm_dp_display_get_active_stream_cnt(msm_dp_display)) { rc =3D -EINVAL; goto end; } diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 0815973e6597492e09f33359d9777c0e8ce31e0d..e2e6b0ea2f9dbfe49a599ca19b1= d205669365c4c 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -73,6 +73,8 @@ struct msm_dp_display_private { =20 bool wide_bus_supported; =20 + u32 active_stream_cnt; + struct msm_dp_audio *audio; =20 void __iomem *ahb_base; @@ -175,6 +177,15 @@ static const struct of_device_id msm_dp_dt_match[] =3D= { {} }; =20 +int msm_dp_display_get_active_stream_cnt(struct msm_dp *msm_dp_display) +{ + struct msm_dp_display_private *dp; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); + + return dp->active_stream_cnt; +} + static struct msm_dp_display_private *dev_get_dp_display_private(struct de= vice *dev) { struct msm_dp *dp =3D dev_get_drvdata(dev); @@ -709,15 +720,17 @@ static int msm_dp_display_prepare(struct msm_dp_displ= ay_private *dp) if (dp->link->sink_count =3D=3D 0) return rc; =20 - if (msm_dp_display->link_ready && !msm_dp_display->power_on) { + if (msm_dp_display->link_ready && !dp->active_stream_cnt) { msm_dp_display_host_phy_init(dp); force_link_train =3D true; } =20 - rc =3D msm_dp_ctrl_on_link(dp->ctrl, msm_dp_display->mst_active); - if (rc) { - DRM_ERROR("Failed link training (rc=3D%d)\n", rc); - msm_dp_display->connector->state->link_status =3D DRM_LINK_STATUS_BAD; + if (!dp->active_stream_cnt) { + rc =3D msm_dp_ctrl_on_link(dp->ctrl, msm_dp_display->mst_active); + if (rc) { + DRM_ERROR("Failed link training (rc=3D%d)\n", rc); + msm_dp_display->connector->state->link_status =3D DRM_LINK_STATUS_BAD; + } } =20 rc =3D msm_dp_ctrl_prepare_stream_on(dp->ctrl, force_link_train); @@ -731,17 +744,10 @@ static int msm_dp_display_enable(struct msm_dp_displa= y_private *dp, struct msm_dp_panel *msm_dp_panel) { int rc =3D 0; - struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; =20 drm_dbg_dp(dp->drm_dev, "sink_count=3D%d\n", dp->link->sink_count); - if (msm_dp_display->power_on) { - drm_dbg_dp(dp->drm_dev, "Link already setup, return\n"); - return 0; - } =20 rc =3D msm_dp_ctrl_on_stream(dp->ctrl, msm_dp_panel, dp->max_stream); - if (!rc) - msm_dp_display->power_on =3D true; =20 return rc; } @@ -788,16 +794,14 @@ static void msm_dp_display_audio_notify_disable(struc= t msm_dp_display_private *d static int msm_dp_display_disable(struct msm_dp_display_private *dp, struct msm_dp_panel *msm_dp_panel) { - struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; - - if (!msm_dp_display->power_on) + if (!dp->active_stream_cnt) return 0; =20 msm_dp_panel_disable_vsc_sdp(msm_dp_panel); =20 msm_dp_ctrl_off_pixel_clk(dp->ctrl, msm_dp_panel->stream_id); =20 - msm_dp_display->power_on =3D false; + dp->active_stream_cnt--; =20 drm_dbg_dp(dp->drm_dev, "sink count: %d\n", dp->link->sink_count); return 0; @@ -934,7 +938,7 @@ void msm_dp_snapshot(struct msm_disp_state *disp_state,= struct msm_dp *dp) * power_on status before dumping DP registers to avoid crash due * to unclocked access */ - if (!dp->power_on) + if (!msm_dp_display->active_stream_cnt) return; =20 msm_disp_snapshot_add_block(disp_state, msm_dp_display->ahb_len, @@ -1543,6 +1547,8 @@ void msm_dp_display_enable_helper(struct msm_dp *msm_= dp_display, struct msm_dp_p } } =20 + dp->active_stream_cnt++; + drm_dbg_dp(msm_dp_display->drm_dev, "type=3D%d Done\n", msm_dp_display->c= onnector_type); } =20 @@ -1564,6 +1570,11 @@ void msm_dp_display_disable_helper(struct msm_dp *ms= m_dp_display, =20 dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); =20 + if (!dp->active_stream_cnt) { + drm_dbg_dp(dp->drm_dev, "no active streams\n"); + return; + } + msm_dp_ctrl_push_idle(dp->ctrl, msm_dp_panel); msm_dp_ctrl_mst_stream_channel_slot_setup(dp->ctrl, dp->max_stream); @@ -1590,6 +1601,11 @@ void msm_dp_display_unprepare(struct msm_dp *msm_dp_= display) return; } =20 + if (dp->active_stream_cnt) { + drm_dbg_dp(dp->drm_dev, "stream still active, return\n"); + return; + } + /* dongle is still connected but sinks are disconnected */ if (dp->link->sink_count =3D=3D 0) msm_dp_link_psm_config(dp->link, &dp->panel->link_info, true); diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index 20b7ed735b3f428e894b82ae2756d0efcfa47624..b1ea027438d952c94f3ae80725c= 92e46c631bdb2 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -19,7 +19,6 @@ struct msm_dp { struct drm_bridge *bridge; bool link_ready; bool audio_enabled; - bool power_on; bool prepared; bool mst_active; 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In MST mode, connector detection is handled by MST bridges. This patch skips detection for the SST bridge when MST is active. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dp/dp_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index e2e6b0ea2f9dbfe49a599ca19b1d205669365c4c..cb433103d439ac6b8089bdecf0e= e6be35c914db1 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -986,7 +986,7 @@ enum drm_connector_status msm_dp_bridge_detect(struct d= rm_bridge *bridge, struct =20 priv =3D container_of(dp, struct msm_dp_display_private, msm_dp_display); =20 - if (!dp->link_ready) + if (!dp->link_ready || dp->mst_active) return status; =20 msm_dp_aux_enable_xfers(priv->aux, true); --=20 2.34.1 From nobody Fri Oct 3 20:22:40 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A53883019DF for ; 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Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 55 ++++++++++++++++++++++++++++++---= ---- 1 file changed, 45 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index cb433103d439ac6b8089bdecf0ee6be35c914db1..84df34306fb557341bea288ea8c= 13b0c81b11919 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -14,6 +14,7 @@ #include #include #include +#include #include =20 #include "msm_drv.h" @@ -297,6 +298,35 @@ static int msm_dp_display_lttpr_init(struct msm_dp_dis= play_private *dp, u8 *dpcd return lttpr_count; } =20 +static void msm_dp_display_mst_init(struct msm_dp_display_private *dp) +{ + const unsigned long clear_mstm_ctrl_timeout_us =3D 100000; + u8 old_mstm_ctrl; + struct msm_dp *msm_dp =3D &dp->msm_dp_display; + int ret; + + /* clear sink mst state */ + drm_dp_dpcd_readb(dp->aux, DP_MSTM_CTRL, &old_mstm_ctrl); + drm_dp_dpcd_writeb(dp->aux, DP_MSTM_CTRL, 0); + + /* add extra delay if MST old state is on*/ + if (old_mstm_ctrl) { + drm_dbg_dp(dp->drm_dev, "wait %luus to set DP_MSTM_CTRL set 0\n", + clear_mstm_ctrl_timeout_us); + usleep_range(clear_mstm_ctrl_timeout_us, + clear_mstm_ctrl_timeout_us + 1000); + } + + ret =3D drm_dp_dpcd_writeb(dp->aux, DP_MSTM_CTRL, + DP_MST_EN | DP_UP_REQ_EN | DP_UPSTREAM_IS_SRC); + if (ret < 0) { + DRM_ERROR("sink mst enablement failed\n"); + return; + } + + msm_dp->mst_active =3D true; +} + static int msm_dp_display_process_hpd_high(struct msm_dp_display_private *= dp) { struct drm_connector *connector =3D dp->msm_dp_display.connector; @@ -315,18 +345,20 @@ static int msm_dp_display_process_hpd_high(struct msm= _dp_display_private *dp) if (rc) goto end; =20 - drm_edid =3D drm_edid_read_ddc(connector, &dp->aux->ddc); - drm_edid_connector_update(connector, drm_edid); + if (!dp->mst_supported || !drm_dp_read_mst_cap(dp->aux, dp->panel->dpcd))= { + drm_edid =3D drm_edid_read_ddc(connector, &dp->aux->ddc); + drm_edid_connector_update(connector, drm_edid); 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Since some of the fields of DP panel are private, dp_display module needs to initialize these parts and return the panel back. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 23 +++++++++++++++++++++++ drivers/gpu/drm/msm/dp/dp_display.h | 2 ++ 2 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 84df34306fb557341bea288ea8c13b0c81b11919..abcab3ed43b6da5ef898355cf9b= 7561cd9fe0404 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -632,6 +632,29 @@ static int msm_dp_irq_hpd_handle(struct msm_dp_display= _private *dp, u32 data) return 0; } =20 +struct msm_dp_panel *msm_dp_display_get_panel(struct msm_dp *msm_dp_displa= y) +{ + struct msm_dp_display_private *dp; + struct msm_dp_panel *dp_panel; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); + + dp_panel =3D msm_dp_panel_get(&dp->msm_dp_display.pdev->dev, dp->aux, dp-= >link, + dp->link_base, dp->mst2link_base, dp->mst3link_base, + dp->pixel_base); + + if (IS_ERR(dp->panel)) { + DRM_ERROR("failed to initialize panel\n"); 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Each MST encoder creates one bridge and each bridge is bound to its own dp_panel abstraction to manage the operations of its pipeline. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/Makefile | 3 +- drivers/gpu/drm/msm/dp/dp_display.h | 3 + drivers/gpu/drm/msm/dp/dp_mst_drm.c | 556 ++++++++++++++++++++++++++++++++= ++++ drivers/gpu/drm/msm/dp/dp_mst_drm.h | 86 ++++++ 4 files changed, 647 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 0c0dfb25f01b193b10946fae20138caf32cf0ed2..a61fa2637ff317ed4dee715de5d= 12a7befa987f5 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -142,7 +142,8 @@ msm-display-$(CONFIG_DRM_MSM_DP)+=3D dp/dp_aux.o \ dp/dp_link.o \ dp/dp_panel.o \ dp/dp_audio.o \ - dp/dp_utils.o + dp/dp_utils.o \ + dp/dp_mst_drm.o =20 msm-display-$(CONFIG_DRM_MSM_HDMI_HDCP) +=3D hdmi/hdmi_hdcp.o =20 diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/d= p_display.h index d5889b801d190b6f33b180ead898c1e4ebcbf8f3..f958de6244b556df5452a5dbec6= 899fb79a57193 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -7,6 +7,7 @@ #define _DP_DISPLAY_H_ =20 #include "dp_panel.h" +#include "dp_mst_drm.h" #include "disp/msm_disp_snapshot.h" =20 #define DP_MAX_PIXEL_CLK_KHZ 675000 @@ -25,6 +26,8 @@ struct msm_dp { bool is_edp; bool internal_hpd; =20 + struct msm_dp_mst *msm_dp_mst; + struct msm_dp_audio *msm_dp_audio; bool psr_supported; }; diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.c b/drivers/gpu/drm/msm/dp/d= p_mst_drm.c new file mode 100644 index 0000000000000000000000000000000000000000..73de29136801ef5f45e0b2d0928= 0fe113021b68c --- /dev/null +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.c @@ -0,0 +1,556 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/* + * Copyright =C2=A9 2014 Red Hat. + * + * Permission to use, copy, modify, distribute, and sell this software and= its + * documentation for any purpose is hereby granted without fee, provided t= hat + * the above copyright notice appear in all copies and that both that copy= right + * notice and this permission notice appear in supporting documentation, a= nd + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided= "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTW= ARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF = USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFOR= MANCE + * OF THIS SOFTWARE. + */ + +#include "dp_mst_drm.h" + +#define to_msm_dp_mst_bridge(x) container_of((x), struct msm_dp_mst_br= idge, base) +#define to_msm_dp_mst_bridge_priv(x) \ + container_of((x), struct msm_dp_mst_bridge, obj) +#define to_msm_dp_mst_bridge_state_priv(x) \ + container_of((x), struct msm_dp_mst_bridge_state, base) +#define to_msm_dp_mst_bridge_state(x) \ + to_msm_dp_mst_bridge_state_priv((x)->obj.state) +#define to_msm_dp_mst_connector(x) \ + container_of((x), struct msm_dp_mst_connector, connector) + +#define DP_MST_CONN_ID(bridge) ((bridge)->connector ? \ + (bridge)->connector->base.id : 0) + +#define MAX_DPCD_TRANSACTION_BYTES 16 + +static struct drm_private_state *msm_dp_mst_duplicate_bridge_state(struct = drm_private_obj *obj) +{ + struct msm_dp_mst_bridge_state *mst_bridge_state; + + mst_bridge_state =3D kmemdup(obj->state, sizeof(*mst_bridge_state), GFP_K= ERNEL); + if (!mst_bridge_state) + return NULL; + + __drm_atomic_helper_private_obj_duplicate_state(obj, &mst_bridge_state->b= ase); + + return &mst_bridge_state->base; +} + +static void msm_dp_mst_destroy_bridge_state(struct drm_private_obj *obj, + struct drm_private_state *state) +{ + struct msm_dp_mst_bridge_state *mst_bridge_state =3D + to_msm_dp_mst_bridge_state_priv(state); + + kfree(mst_bridge_state); +} + +static const struct drm_private_state_funcs msm_dp_mst_bridge_state_funcs = =3D { + .atomic_duplicate_state =3D msm_dp_mst_duplicate_bridge_state, + .atomic_destroy_state =3D msm_dp_mst_destroy_bridge_state, +}; + +/** + * dp_mst_find_vcpi_slots() - Find VCPI slots for this PBN value + * @mgr: manager to use + * @pbn: payload bandwidth to convert into slots. + * + * Calculate the number of VCPI slots that will be required for the given = PBN + * value. + * + * RETURNS: + * The total slots required for this port, or error. + */ +static int msm_dp_mst_find_vcpi_slots(struct drm_dp_mst_topology_mgr *mgr,= int pbn) +{ + int num_slots; + struct drm_dp_mst_topology_state *state; + + state =3D to_drm_dp_mst_topology_state(mgr->base.state); + num_slots =3D DIV_ROUND_UP(pbn, dfixed_trunc(state->pbn_div)); + + /* max. time slots - one slot for MTP header */ + if (num_slots > 63) + return -ENOSPC; + return num_slots; +} + +static void msm_dp_mst_update_timeslots(struct msm_dp_mst *mst, + struct msm_dp_mst_bridge *mst_bridge, + struct drm_atomic_state *state, + struct drm_dp_mst_port *port) +{ + int i; + struct msm_dp_mst_bridge *msm_dp_bridge; + struct drm_dp_mst_topology_state *mst_state; + struct drm_dp_mst_atomic_payload *payload; + struct msm_dp_mst_bridge_state *mst_bridge_state; + int prev_start =3D 0; + int prev_slots =3D 0; + + mst_state =3D to_drm_dp_mst_topology_state(mst->mst_mgr.base.state); + payload =3D drm_atomic_get_mst_payload_state(mst_state, port); + + if (!payload) { + DRM_ERROR("mst bridge [%d] update_timeslots failed, null payload\n", + mst_bridge->id); + return; + } + + for (i =3D 0; i < mst->max_streams; i++) { + msm_dp_bridge =3D mst->mst_bridge[i]; + if (mst_bridge =3D=3D msm_dp_bridge) { + mst_bridge_state =3D to_msm_dp_mst_bridge_state(msm_dp_bridge); + /* + * When a payload was removed make sure to move any payloads after it + * to the left so all payloads are aligned to the left. + */ + if (payload->vc_start_slot < 0) { + // cache the payload + prev_start =3D mst_bridge_state->start_slot; + prev_slots =3D mst_bridge_state->num_slots; + mst_bridge_state->pbn =3D 0; + mst_bridge_state->start_slot =3D 1; + mst_bridge_state->num_slots =3D 0; + mst_bridge_state->vcpi =3D 0; + } else { //add payload + mst_bridge_state->pbn =3D payload->pbn; + mst_bridge_state->start_slot =3D payload->vc_start_slot; + mst_bridge_state->num_slots =3D payload->time_slots; + mst_bridge_state->vcpi =3D payload->vcpi; + } + } + } + + // Now commit all the updated payloads + for (i =3D 0; i < mst->max_streams; i++) { + msm_dp_bridge =3D mst->mst_bridge[i]; + + mst_bridge_state =3D to_msm_dp_mst_bridge_state(msm_dp_bridge); + //Shift payloads to the left if there was a removed payload. + if (payload->vc_start_slot < 0 && mst_bridge_state->start_slot > prev_st= art) + mst_bridge_state->start_slot -=3D prev_slots; + + msm_dp_display_set_stream_info(mst->msm_dp, msm_dp_bridge->msm_dp_panel, + msm_dp_bridge->id, mst_bridge_state->start_slot, + mst_bridge_state->num_slots, + mst_bridge_state->pbn, mst_bridge_state->vcpi); + drm_dbg_dp(mst->msm_dp->drm_dev, + "conn:%d vcpi:%d start_slot:%d num_slots:%d, pbn:%d\n", + DP_MST_CONN_ID(msm_dp_bridge), mst_bridge_state->vcpi, + mst_bridge_state->start_slot, + mst_bridge_state->num_slots, mst_bridge_state->pbn); + } +} + +static int msm_dp_mst_bridge_pre_enable_part1(struct msm_dp_mst_bridge *dp= _bridge, + struct drm_atomic_state *state) +{ + struct msm_dp *dp_display =3D dp_bridge->display; + struct msm_dp_mst *mst =3D dp_display->msm_dp_mst; + struct msm_dp_mst_connector *mst_conn =3D to_msm_dp_mst_connector(dp_brid= ge->connector); + struct drm_dp_mst_port *port =3D mst_conn->mst_port; + struct drm_dp_mst_topology_state *mst_state; + struct drm_dp_mst_atomic_payload *payload; + struct msm_dp_panel *dp_panel =3D mst_conn->dp_panel; + int pbn, slots; + int rc =3D 0; + + mst_state =3D drm_atomic_get_new_mst_topology_state(state, &mst->mst_mgr); + + pbn =3D drm_dp_calc_pbn_mode(dp_panel->msm_dp_mode.drm_mode.clock, + (mst_conn->connector.display_info.bpc * 3) << 4); + + slots =3D msm_dp_mst_find_vcpi_slots(&mst->mst_mgr, pbn); + + drm_dbg_dp(dp_display->drm_dev, "conn:%d pbn:%d, slots:%d\n", DP_MST_CONN= _ID(dp_bridge), + pbn, slots); + + payload =3D drm_atomic_get_mst_payload_state(mst_state, port); + if (!payload || payload->time_slots <=3D 0) { + DRM_ERROR("time slots not allocated for conn:%d\n", DP_MST_CONN_ID(dp_br= idge)); + rc =3D -EINVAL; + return rc; + } + + drm_dp_mst_update_slots(mst_state, DP_CAP_ANSI_8B10B); + + rc =3D drm_dp_add_payload_part1(&mst->mst_mgr, mst_state, payload); + if (rc) { + DRM_ERROR("payload allocation failure for conn:%d\n", DP_MST_CONN_ID(dp_= bridge)); + return rc; + } + + msm_dp_mst_update_timeslots(mst, dp_bridge, state, port); + + return rc; +} + +static void _msm_dp_mst_bridge_pre_enable_part2(struct msm_dp_mst_bridge *= dp_bridge, + struct drm_atomic_state *state) +{ + struct msm_dp *dp_display =3D dp_bridge->display; + struct msm_dp_mst *mst =3D dp_display->msm_dp_mst; + struct msm_dp_mst_connector *mst_conn =3D to_msm_dp_mst_connector(dp_brid= ge->connector); + struct drm_dp_mst_port *port =3D mst_conn->mst_port; + struct drm_dp_mst_topology_state *mst_state; + struct drm_dp_mst_atomic_payload *payload; + + drm_dp_check_act_status(&mst->mst_mgr); + + mst_state =3D to_drm_dp_mst_topology_state(mst->mst_mgr.base.state); + payload =3D drm_atomic_get_mst_payload_state(mst_state, port); + + if (!payload) { + DRM_ERROR("mst bridge [%d] null payload\n", dp_bridge->id); + return; + } + + if (!payload->port) { + DRM_ERROR("mst bridge [%d] null port\n", dp_bridge->id); + return; + } + + if (!payload->port->connector) { + DRM_ERROR("mst bridge [%d] part-2 failed, null connector\n", + dp_bridge->id); + return; + } + + if (payload->vc_start_slot =3D=3D -1) { + DRM_ERROR("mst bridge [%d] part-2 failed, payload alloc part 1 failed\n", + dp_bridge->id); + return; + } + + drm_dp_add_payload_part2(&mst->mst_mgr, payload); + + drm_dbg_dp(dp_display->drm_dev, "mst bridge [%d] _pre enable part-2 compl= ete\n", + dp_bridge->id); +} + +static void msm_dp_mst_bridge_pre_disable_part1(struct msm_dp_mst_bridge *= dp_bridge, + struct drm_atomic_state *state) +{ + struct msm_dp *dp_display =3D dp_bridge->display; + struct msm_dp_mst *mst =3D dp_display->msm_dp_mst; + struct msm_dp_mst_connector *mst_conn =3D to_msm_dp_mst_connector(dp_brid= ge->connector); + struct drm_dp_mst_port *port =3D mst_conn->mst_port; + struct drm_dp_mst_topology_state *old_mst_state; + struct drm_dp_mst_topology_state *new_mst_state; + const struct drm_dp_mst_atomic_payload *old_payload; + struct drm_dp_mst_atomic_payload *new_payload; + + old_mst_state =3D drm_atomic_get_old_mst_topology_state(state, &mst->mst_= mgr); + + new_mst_state =3D drm_atomic_get_new_mst_topology_state(state, &mst->mst_= mgr); + + old_payload =3D drm_atomic_get_mst_payload_state(old_mst_state, port); + new_payload =3D drm_atomic_get_mst_payload_state(new_mst_state, port); + + if (!old_payload || !new_payload) { + DRM_ERROR("mst bridge [%d] _pre disable part-1 failed, null payload\n", + dp_bridge->id); + return; + } + + drm_dp_remove_payload_part1(&mst->mst_mgr, new_mst_state, new_payload); + drm_dp_remove_payload_part2(&mst->mst_mgr, new_mst_state, old_payload, ne= w_payload); + + msm_dp_mst_update_timeslots(mst, dp_bridge, state, port); + + drm_dbg_dp(dp_display->drm_dev, "mst bridge [%d] _pre disable part-1 comp= lete\n", + dp_bridge->id); +} + +static void msm_dp_mst_bridge_atomic_pre_enable(struct drm_bridge *drm_bri= dge, + struct drm_atomic_state *state) +{ + int rc =3D 0; + struct msm_dp_mst_bridge *bridge; + struct msm_dp *dp_display; + struct msm_dp_mst_bridge_state *mst_bridge_state; + struct msm_dp_mst *dp_mst; + + if (!drm_bridge) { + DRM_ERROR("Invalid params\n"); + return; + } + + bridge =3D to_msm_dp_mst_bridge(drm_bridge); + mst_bridge_state =3D to_msm_dp_mst_bridge_state(bridge); + dp_display =3D bridge->display; + dp_mst =3D dp_display->msm_dp_mst; + + /* to cover cases of bridge_disable/bridge_enable without modeset */ + bridge->connector =3D mst_bridge_state->connector; + bridge->msm_dp_panel =3D mst_bridge_state->msm_dp_panel; + + if (!bridge->connector) { + DRM_ERROR("Invalid connector\n"); + return; + } + + mutex_lock(&dp_mst->mst_lock); + msm_dp_display_atomic_prepare(dp_display); + + rc =3D msm_dp_mst_bridge_pre_enable_part1(bridge, state); + if (rc) { + DRM_ERROR("[%d] DP display pre-enable failed, rc=3D%d\n", bridge->id, rc= ); + msm_dp_display_unprepare(dp_display); + mutex_unlock(&dp_mst->mst_lock); + return; + } + + msm_dp_display_enable_helper(dp_display, bridge->msm_dp_panel); + + _msm_dp_mst_bridge_pre_enable_part2(bridge, state); + + mutex_unlock(&dp_mst->mst_lock); + + drm_dbg_dp(dp_display->drm_dev, "conn:%d mode:%s fps:%d vcpi:%d slots:%d = to %d\n", + DP_MST_CONN_ID(bridge), bridge->msm_dp_panel->msm_dp_mode.drm_mode.na= me, + drm_mode_vrefresh(&bridge->msm_dp_panel->msm_dp_mode.drm_mode), + mst_bridge_state->vcpi, mst_bridge_state->start_slot, + mst_bridge_state->start_slot + mst_bridge_state->num_slots); +} + +static void msm_dp_mst_bridge_atomic_disable(struct drm_bridge *drm_bridge, + struct drm_atomic_state *state) +{ + struct msm_dp_mst_bridge *bridge; + struct msm_dp *dp_display; + struct msm_dp_mst *mst; + + if (!drm_bridge) { + DRM_ERROR("Invalid params\n"); + return; + } + + bridge =3D to_msm_dp_mst_bridge(drm_bridge); + if (!bridge->connector) { + DRM_ERROR("Invalid connector\n"); + return; + } + + dp_display =3D bridge->display; + mst =3D dp_display->msm_dp_mst; + + mutex_lock(&mst->mst_lock); + + msm_dp_mst_bridge_pre_disable_part1(bridge, state); + + msm_dp_display_disable_helper(dp_display, bridge->msm_dp_panel); + + drm_dp_check_act_status(&mst->mst_mgr); + + mutex_unlock(&mst->mst_lock); + + drm_dbg_dp(dp_display->drm_dev, "mst bridge:%d conn:%d disable complete\n= ", bridge->id, + DP_MST_CONN_ID(bridge)); +} + +static void msm_dp_mst_bridge_atomic_post_disable(struct drm_bridge *drm_b= ridge, + struct drm_atomic_state *state) +{ + int conn =3D 0; + struct msm_dp_mst_bridge *bridge; + struct msm_dp *dp_display; + struct msm_dp_mst *mst; + + if (!drm_bridge) { + DRM_ERROR("Invalid params\n"); + return; + } + + bridge =3D to_msm_dp_mst_bridge(drm_bridge); + if (!bridge->connector) { + DRM_ERROR("Invalid connector\n"); + return; + } + + conn =3D DP_MST_CONN_ID(bridge); + + dp_display =3D bridge->display; + mst =3D dp_display->msm_dp_mst; + + mutex_lock(&mst->mst_lock); + + msm_dp_display_atomic_post_disable_helper(dp_display, bridge->msm_dp_pane= l); + + if (!dp_display->mst_active) + msm_dp_display_unprepare(dp_display); + + bridge->connector =3D NULL; + bridge->msm_dp_panel =3D NULL; + + mutex_unlock(&mst->mst_lock); + + drm_dbg_dp(dp_display->drm_dev, "mst bridge:%d conn:%d post disable compl= ete\n", + bridge->id, conn); +} + +static int msm_dp_mst_bridge_atomic_check(struct drm_bridge *drm_bridge, + struct drm_bridge_state *bridge_state, + struct drm_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct drm_atomic_state *state =3D crtc_state->state; + struct drm_connector *connector =3D conn_state->connector; + struct drm_dp_mst_topology_state *mst_state; + struct msm_dp_mst_connector *mst_conn; + struct msm_dp *dp_display; + struct msm_dp_mst *mst; + int rc =3D 0, pbn, slots; + u32 bpp; + + if (!drm_atomic_crtc_needs_modeset(crtc_state) || !crtc_state->enable) { + return 0; + } + + mst_conn =3D to_msm_dp_mst_connector(connector); + dp_display =3D mst_conn->msm_dp; + mst =3D dp_display->msm_dp_mst; + + bpp =3D connector->display_info.bpc * 3; + + if (!bpp) + bpp =3D 24; + + pbn =3D drm_dp_calc_pbn_mode(crtc_state->mode.clock, bpp << 4); + + mst_state =3D to_drm_dp_mst_topology_state(mst->mst_mgr.base.state); + if (IS_ERR(mst_state)) + return PTR_ERR(mst_state); + + if (!dfixed_trunc(mst_state->pbn_div)) { + mst_state->pbn_div =3D + drm_dp_get_vc_payload_bw(mst_conn->dp_panel->link_info.rate, + mst_conn->dp_panel->link_info.num_lanes); + } + + slots =3D drm_dp_atomic_find_time_slots(state, &mst->mst_mgr, mst_conn->m= st_port, pbn); + + drm_dbg_dp(dp_display->drm_dev, "add slots, conn:%d pbn:%d slots:%d rc:%d= \n", + connector->base.id, pbn, slots, rc); + + return 0; +} + +static void msm_dp_mst_bridge_mode_set(struct drm_bridge *drm_bridge, + const struct drm_display_mode *mode, + const struct drm_display_mode *adjusted_mode) +{ + struct msm_dp_mst_bridge *bridge; + struct msm_dp_mst_bridge_state *mst_bridge_state; + struct msm_dp *dp_display; + struct msm_dp_panel *msm_dp_panel; + + if (!drm_bridge || !mode || !adjusted_mode) { + DRM_ERROR("Invalid params\n"); + return; + } + + bridge =3D to_msm_dp_mst_bridge(drm_bridge); + + mst_bridge_state =3D to_msm_dp_mst_bridge_state(bridge); + bridge->connector =3D mst_bridge_state->connector; + bridge->msm_dp_panel =3D mst_bridge_state->msm_dp_panel; + + msm_dp_panel =3D bridge->msm_dp_panel; + dp_display =3D bridge->display; + + msm_dp_display_mode_set_helper(dp_display, mode, adjusted_mode, bridge->m= sm_dp_panel); + msm_dp_panel->pbn =3D drm_dp_calc_pbn_mode(msm_dp_panel->msm_dp_mode.drm_= mode.clock, + (msm_dp_panel->msm_dp_mode.bpp << 4)); + drm_dbg_dp(dp_display->drm_dev, "mst bridge:%d conn:%d mode set complete = %s\n", bridge->id, + DP_MST_CONN_ID(bridge), mode->name); +} + +/* DP MST Bridge APIs */ +static const struct drm_bridge_funcs msm_dp_mst_bridge_ops =3D { + .atomic_duplicate_state =3D drm_atomic_helper_bridge_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_bridge_destroy_state, + .atomic_reset =3D drm_atomic_helper_bridge_reset, + .atomic_pre_enable =3D msm_dp_mst_bridge_atomic_pre_enable, + .atomic_disable =3D msm_dp_mst_bridge_atomic_disable, + .atomic_post_disable =3D msm_dp_mst_bridge_atomic_post_disable, + .atomic_check =3D msm_dp_mst_bridge_atomic_check, + .mode_set =3D msm_dp_mst_bridge_mode_set, +}; + +int msm_dp_mst_drm_bridge_init(struct msm_dp *dp_display, struct drm_encod= er *encoder) +{ + int rc =3D 0; + struct msm_dp_mst_bridge *bridge =3D NULL; + struct msm_dp_mst_bridge_state *mst_bridge_state; + struct drm_device *dev; + struct msm_dp_mst *mst =3D dp_display->msm_dp_mst; + int i; + + for (i =3D 0; i < mst->max_streams; i++) { + if (!mst->mst_bridge[i]->in_use) { + bridge =3D mst->mst_bridge[i]; + bridge->encoder =3D encoder; + bridge->in_use =3D true; + bridge->id =3D i; + break; + } + } + + if (i =3D=3D mst->max_streams) { + DRM_ERROR("mst supports only %d bridges\n", i); + rc =3D -EACCES; + goto end; + } + + dev =3D dp_display->drm_dev; + bridge->display =3D dp_display; + bridge->base.funcs =3D &msm_dp_mst_bridge_ops; + bridge->base.encoder =3D encoder; + bridge->base.type =3D dp_display->connector_type; + bridge->base.ops =3D DRM_BRIDGE_OP_MODES; + drm_bridge_add(&bridge->base); + + rc =3D drm_bridge_attach(encoder, &bridge->base, NULL, 0); + if (rc) { + DRM_ERROR("failed to attach bridge, rc=3D%d\n", rc); + goto end; + } + + mst_bridge_state =3D kzalloc(sizeof(*mst_bridge_state), GFP_KERNEL); + if (!mst_bridge_state) { + rc =3D -ENOMEM; + goto end; + } + + drm_atomic_private_obj_init(dev, &bridge->obj, + &mst_bridge_state->base, + &msm_dp_mst_bridge_state_funcs); + + drm_dbg_dp(dp_display->drm_dev, "mst drm bridge init. bridge id:%d\n", i); + + return 0; + +end: + return rc; +} diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.h b/drivers/gpu/drm/msm/dp/d= p_mst_drm.h new file mode 100644 index 0000000000000000000000000000000000000000..d75731ca2e5870377026e8ad105= 7bdcc5f0d4c78 --- /dev/null +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + * + * Permission to use, copy, modify, distribute, and sell this software and= its + * documentation for any purpose is hereby granted without fee, provided t= hat + * the above copyright notice appear in all copies and that both that copy= right + * notice and this permission notice appear in supporting documentation, a= nd + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided= "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTW= ARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF = USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFOR= MANCE + * OF THIS SOFTWARE. + */ + +#ifndef _DP_MST_DRM_H_ +#define _DP_MST_DRM_H_ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dp_panel.h" +#include "dp_display.h" + +struct msm_dp_mst_bridge { + struct drm_bridge base; + struct drm_private_obj obj; + u32 id; + + bool in_use; + + struct msm_dp *display; + struct drm_encoder *encoder; + + struct drm_connector *connector; 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This complements the existing drm_atomic_helper_check() and allows the MST framework to perform its own consistency checks during atomic updates, such as validating connector states and topology changes. Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_atomic.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_ato= mic.c index 87a91148a731dc911f30695add4c8f5002770220..3aa0020dec3a90b693ad3d4171c= fcffc091aad4c 100644 --- a/drivers/gpu/drm/msm/msm_atomic.c +++ b/drivers/gpu/drm/msm/msm_atomic.c @@ -6,6 +6,7 @@ =20 #include #include +#include =20 #include "msm_atomic_trace.h" #include "msm_drv.h" @@ -207,7 +208,11 @@ int msm_atomic_check(struct drm_device *dev, struct dr= m_atomic_state *state) if (ret) return ret; =20 - return drm_atomic_helper_check(dev, state); + ret =3D drm_atomic_helper_check(dev, state); + if (ret) + return ret; + + return drm_dp_mst_atomic_check(state); } =20 void msm_atomic_commit_tail(struct drm_atomic_state *state) --=20 2.34.1 From nobody Fri Oct 3 20:22:40 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E30F7303CAF for ; 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Each MST encoder is connected through a DRM bridge to a MST connector and each MST connector has a DP panel abstraction attached to it. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_mst_drm.c | 391 ++++++++++++++++++++++++++++++++= +++- drivers/gpu/drm/msm/dp/dp_mst_drm.h | 3 + 2 files changed, 393 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.c b/drivers/gpu/drm/msm/dp/d= p_mst_drm.c index 73de29136801ef5f45e0b2d09280fe113021b68c..b4f640134af544c77ab262d2cbe= 0b67e1e2e1b3a 100644 --- a/drivers/gpu/drm/msm/dp/dp_mst_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.c @@ -25,6 +25,8 @@ * OF THIS SOFTWARE. */ =20 +#include +#include #include "dp_mst_drm.h" =20 #define to_msm_dp_mst_bridge(x) container_of((x), struct msm_dp_mst_br= idge, base) @@ -525,7 +527,6 @@ int msm_dp_mst_drm_bridge_init(struct msm_dp *dp_displa= y, struct drm_encoder *en =20 dev =3D dp_display->drm_dev; bridge->display =3D dp_display; - bridge->base.funcs =3D &msm_dp_mst_bridge_ops; bridge->base.encoder =3D encoder; bridge->base.type =3D dp_display->connector_type; bridge->base.ops =3D DRM_BRIDGE_OP_MODES; @@ -554,3 +555,391 @@ int msm_dp_mst_drm_bridge_init(struct msm_dp *dp_disp= lay, struct drm_encoder *en end: return rc; } + +static struct msm_dp_mst_bridge_state *msm_dp_mst_br_priv_state(struct drm= _atomic_state *st, + struct msm_dp_mst_bridge *bridge) +{ + struct drm_device *dev =3D bridge->base.dev; + struct drm_private_state *obj_state =3D drm_atomic_get_private_obj_state(= st, &bridge->obj); + + WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); + + return to_msm_dp_mst_bridge_state_priv(obj_state); +} + +/* DP MST Connector OPs */ +static int +msm_dp_mst_connector_detect(struct drm_connector *connector, + struct drm_modeset_acquire_ctx *ctx, + bool force) +{ + struct msm_dp_mst_connector *mst_conn =3D to_msm_dp_mst_connector(connect= or); + struct msm_dp *dp_display =3D mst_conn->msm_dp; + struct msm_dp_mst *mst =3D dp_display->msm_dp_mst; + enum drm_connector_status status =3D connector_status_disconnected; + + if (drm_connector_is_unregistered(&mst_conn->connector)) + return status; + + if (dp_display->link_ready && dp_display->mst_active) + status =3D drm_dp_mst_detect_port(connector, + ctx, &mst->mst_mgr, mst_conn->mst_port); + + drm_dbg_dp(dp_display->drm_dev, "conn:%d status:%d\n", connector->base.id= , status); + + return status; +} + +static int msm_dp_mst_connector_get_modes(struct drm_connector *connector) +{ + struct msm_dp_mst_connector *mst_conn =3D to_msm_dp_mst_connector(connect= or); + struct msm_dp *dp_display =3D mst_conn->msm_dp; + struct msm_dp_mst *mst =3D dp_display->msm_dp_mst; + const struct drm_edid *drm_edid; + + if (drm_connector_is_unregistered(&mst_conn->connector)) + return drm_edid_connector_update(connector, NULL); + + drm_edid =3D drm_dp_mst_edid_read(connector, &mst->mst_mgr, mst_conn->mst= _port); + drm_edid_connector_update(connector, drm_edid); + + return drm_edid_connector_add_modes(connector); +} + +static enum drm_mode_status msm_dp_mst_connector_mode_valid(struct drm_con= nector *connector, + const struct drm_display_mode *mode) +{ + struct msm_dp_mst_connector *mst_conn; + struct msm_dp *dp_display; + struct drm_dp_mst_port *mst_port; + struct msm_dp_panel *dp_panel; + struct msm_dp_mst *mst; + struct msm_dp_mst_bridge_state *mst_bridge_state; + u16 full_pbn, required_pbn; + int i, active_enc_cnt =3D 0; + + if (drm_connector_is_unregistered(connector)) + return 0; + + mst_conn =3D to_msm_dp_mst_connector(connector); + dp_display =3D mst_conn->msm_dp; + mst =3D dp_display->msm_dp_mst; + mst_port =3D mst_conn->mst_port; + dp_panel =3D mst_conn->dp_panel; + + if (!dp_panel || !mst_port) + return MODE_ERROR; + + for (i =3D 0; i < mst->max_streams; i++) { + mst_bridge_state =3D to_msm_dp_mst_bridge_state(mst->mst_bridge[i]); + if (mst_bridge_state->connector && + mst_bridge_state->connector !=3D connector) + active_enc_cnt++; + } + + if (active_enc_cnt < DP_STREAM_MAX) + full_pbn =3D mst_port->full_pbn; + else { + DRM_ERROR("all MST streams are active\n"); + return MODE_BAD; + } + + required_pbn =3D drm_dp_calc_pbn_mode(mode->clock, (connector->display_in= fo.bpc * 3) << 4); + + if (required_pbn > full_pbn) { + drm_dbg_dp(dp_display->drm_dev, "mode:%s not supported. pbn %d vs %d\n", + mode->name, required_pbn, full_pbn); + return MODE_BAD; + } + + return msm_dp_display_mode_valid(dp_display, &dp_panel->connector->displa= y_info, mode); +} + +static struct drm_encoder * +msm_dp_mst_atomic_best_encoder(struct drm_connector *connector, struct drm= _atomic_state *state) +{ + struct msm_dp_mst_connector *mst_conn =3D to_msm_dp_mst_connector(connect= or); + struct msm_dp *dp_display =3D mst_conn->msm_dp; + struct msm_dp_mst *mst =3D dp_display->msm_dp_mst; + struct drm_encoder *enc =3D NULL; + struct msm_dp_mst_bridge_state *mst_bridge_state; + u32 i; + struct drm_connector_state *conn_state =3D drm_atomic_get_new_connector_s= tate(state, + connector); + + if (conn_state && conn_state->best_encoder) + return conn_state->best_encoder; + + for (i =3D 0; i < mst->max_streams; i++) { + mst_bridge_state =3D msm_dp_mst_br_priv_state(state, mst->mst_bridge[i]); + if (IS_ERR(mst_bridge_state)) + goto end; + + if (mst_bridge_state->connector =3D=3D connector) { + enc =3D mst->mst_bridge[i]->encoder; + goto end; + } + } + + for (i =3D 0; i < mst->max_streams; i++) { + mst_bridge_state =3D msm_dp_mst_br_priv_state(state, mst->mst_bridge[i]); + + if (!mst_bridge_state->connector) { + mst_bridge_state->connector =3D connector; + mst_bridge_state->msm_dp_panel =3D mst_conn->dp_panel; + enc =3D mst->mst_bridge[i]->encoder; + break; + } + } + +end: + if (enc) + drm_dbg_dp(dp_display->drm_dev, "mst connector:%d atomic best encoder:%d= \n", + connector->base.id, i); + else + drm_dbg_dp(dp_display->drm_dev, "mst connector:%d atomic best encoder fa= iled\n", + connector->base.id); + + return enc; +} + +static int msm_dp_mst_connector_atomic_check(struct drm_connector *connect= or, + struct drm_atomic_state *state) +{ + int rc =3D 0, slots; + struct drm_connector_state *old_conn_state; + struct drm_connector_state *new_conn_state; + struct drm_crtc *old_crtc; + struct drm_crtc_state *crtc_state; + struct msm_dp_mst_bridge *bridge; + struct msm_dp_mst_bridge_state *mst_bridge_state; + struct drm_bridge *drm_bridge; + struct msm_dp_mst_connector *mst_conn =3D to_msm_dp_mst_connector(connect= or); + struct msm_dp *dp_display =3D mst_conn->msm_dp; + struct msm_dp_mst *mst =3D dp_display->msm_dp_mst; + struct drm_dp_mst_atomic_payload *payload; + struct drm_dp_mst_topology_state *mst_state; + + if (!state) + return rc; + + new_conn_state =3D drm_atomic_get_new_connector_state(state, connector); + if (!new_conn_state) + return rc; + + old_conn_state =3D drm_atomic_get_old_connector_state(state, connector); + if (!old_conn_state) + goto end; + + old_crtc =3D old_conn_state->crtc; + if (!old_crtc) + goto end; + + crtc_state =3D drm_atomic_get_new_crtc_state(state, old_crtc); + + /* attempt to release vcpi slots on a modeset change for crtc state */ + if (drm_atomic_crtc_needs_modeset(crtc_state)) { + if (WARN_ON(!old_conn_state->best_encoder)) { + rc =3D -EINVAL; + goto end; + } + + drm_bridge =3D drm_bridge_chain_get_first_bridge(old_conn_state->best_en= coder); + if (WARN_ON(!drm_bridge)) { + rc =3D -EINVAL; + goto end; + } + bridge =3D to_msm_dp_mst_bridge(drm_bridge); + + mst_bridge_state =3D msm_dp_mst_br_priv_state(state, bridge); + + mst_state =3D to_drm_dp_mst_topology_state(mst->mst_mgr.base.state); +=09 + payload =3D drm_atomic_get_mst_payload_state(mst_state, mst_conn->mst_po= rt); + + slots =3D payload->time_slots; + if (slots > 0) { + rc =3D drm_dp_atomic_release_time_slots(state, + &mst->mst_mgr, + mst_conn->mst_port); + if (rc) { + DRM_ERROR("failed releasing %d vcpi slots %d\n", slots, rc); + goto end; + } + } + + if (!new_conn_state->crtc) { + /* for cases where crtc is not disabled the slots are not + * freed by drm_dp_atomic_release_time_slots. this results + * in subsequent atomic_check failing since internal slots + * were freed but not the DP MST mgr's + */ + mst_bridge_state->num_slots =3D 0; + mst_bridge_state->connector =3D NULL; + mst_bridge_state->msm_dp_panel =3D NULL; + + drm_dbg_dp(dp_display->drm_dev, "clear best encoder: %d\n", bridge->id); + } + } + +end: + drm_dbg_dp(dp_display->drm_dev, "mst connector:%d atomic check ret %d\n", + connector->base.id, rc); + return rc; +} + +static void dp_mst_connector_destroy(struct drm_connector *connector) +{ + struct msm_dp_mst_connector *mst_conn =3D to_msm_dp_mst_connector(connect= or); + + drm_connector_cleanup(connector); + drm_dp_mst_put_port_malloc(mst_conn->mst_port); + kfree(mst_conn); +} + +/* DRM MST callbacks */ +static const struct drm_connector_helper_funcs msm_dp_drm_mst_connector_he= lper_funcs =3D { + .get_modes =3D msm_dp_mst_connector_get_modes, + .detect_ctx =3D msm_dp_mst_connector_detect, + .mode_valid =3D msm_dp_mst_connector_mode_valid, + .atomic_best_encoder =3D msm_dp_mst_atomic_best_encoder, + .atomic_check =3D msm_dp_mst_connector_atomic_check, +}; + +static const struct drm_connector_funcs msm_dp_drm_mst_connector_funcs =3D= { + .reset =3D drm_atomic_helper_connector_reset, + .destroy =3D dp_mst_connector_destroy, + .fill_modes =3D drm_helper_probe_single_connector_modes, + .atomic_duplicate_state =3D drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state =3D drm_atomic_helper_connector_destroy_state, +}; + +static struct drm_connector * +msm_dp_mst_add_connector(struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port, const char *pathprop) +{ + struct msm_dp_mst *dp_mst; + struct drm_device *dev; + struct msm_dp *dp_display; + struct msm_dp_mst_connector *mst_conn; + struct drm_connector *connector; + int rc, i; + + dp_mst =3D container_of(mgr, struct msm_dp_mst, mst_mgr); + + dp_display =3D dp_mst->msm_dp; + dev =3D dp_display->drm_dev; + + mst_conn =3D kzalloc(sizeof(*mst_conn), GFP_KERNEL); + + if (!mst_conn) + return NULL; + + drm_modeset_lock_all(dev); + + connector =3D &mst_conn->connector; + rc =3D drm_connector_dynamic_init(dev, connector, + &msm_dp_drm_mst_connector_funcs, + DRM_MODE_CONNECTOR_DisplayPort, NULL); + if (rc) { + kfree(mst_conn); + drm_modeset_unlock_all(dev); + return NULL; + } + + mst_conn->dp_panel =3D msm_dp_display_get_panel(dp_display); + if (!mst_conn->dp_panel) { + DRM_ERROR("failed to get dp_panel for connector\n"); + kfree(mst_conn); + drm_modeset_unlock_all(dev); + return NULL; + } + + mst_conn->dp_panel->connector =3D connector; + mst_conn->msm_dp =3D dp_display; + + drm_connector_helper_add(connector, &msm_dp_drm_mst_connector_helper_func= s); + + if (connector->funcs->reset) + connector->funcs->reset(connector); + + /* add all encoders as possible encoders */ + for (i =3D 0; i < dp_mst->max_streams; i++) { + rc =3D drm_connector_attach_encoder(connector, dp_mst->mst_bridge[i]->en= coder); + + if (rc) { + DRM_ERROR("failed to attach encoder to connector, %d\n", rc); + kfree(mst_conn); + drm_modeset_unlock_all(dev); + return NULL; + } + } + + mst_conn->mst_port =3D port; + drm_dp_mst_get_port_malloc(mst_conn->mst_port); + + drm_object_attach_property(&connector->base, + dev->mode_config.path_property, 0); + drm_object_attach_property(&connector->base, + dev->mode_config.tile_property, 0); + + drm_modeset_unlock_all(dev); + + drm_dbg_dp(dp_display->drm_dev, "add MST connector id:%d\n", connector->b= ase.id); + + return connector; +} + +static const struct drm_dp_mst_topology_cbs msm_dp_mst_drm_cbs =3D { + .add_connector =3D msm_dp_mst_add_connector, +}; + +int msm_dp_mst_init(struct msm_dp *dp_display, u32 max_streams, struct drm= _dp_aux *drm_aux) +{ + struct drm_device *dev; + int conn_base_id =3D 0; + int ret; + struct msm_dp_mst *msm_dp_mst; + + if (!dp_display) { + DRM_ERROR("invalid params\n"); + return 0; + } + + dev =3D dp_display->drm_dev; + + msm_dp_mst =3D devm_kzalloc(dev->dev, sizeof(*msm_dp_mst), GFP_KERNEL); + if (!msm_dp_mst) + return -ENOMEM; + + memset(&msm_dp_mst->mst_mgr, 0, sizeof(msm_dp_mst->mst_mgr)); + msm_dp_mst->mst_mgr.cbs =3D &msm_dp_mst_drm_cbs; + conn_base_id =3D dp_display->connector->base.id; + msm_dp_mst->msm_dp =3D dp_display; + msm_dp_mst->max_streams =3D max_streams; + + for (int i =3D 0; i < DP_STREAM_MAX; i++) { + msm_dp_mst->mst_bridge[i] =3D devm_drm_bridge_alloc(dev->dev, + struct msm_dp_mst_bridge, base, + &msm_dp_mst_bridge_ops); + } + + msm_dp_mst->dp_aux =3D drm_aux; + + ret =3D drm_dp_mst_topology_mgr_init(&msm_dp_mst->mst_mgr, dev, + drm_aux, + MAX_DPCD_TRANSACTION_BYTES, + max_streams, + conn_base_id); + if (ret) { + DRM_ERROR("DP DRM MST topology manager init failed\n"); + return ret; + } + + dp_display->msm_dp_mst =3D msm_dp_mst; + + mutex_init(&msm_dp_mst->mst_lock); + + drm_dbg_dp(dp_display->drm_dev, "DP DRM MST topology manager init complet= ed\n"); + return ret; +} diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.h b/drivers/gpu/drm/msm/dp/d= p_mst_drm.h index d75731ca2e5870377026e8ad1057bdcc5f0d4c78..1484fabd92ad0075eac5369aac8= ca462acbd3eda 100644 --- a/drivers/gpu/drm/msm/dp/dp_mst_drm.h +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.h @@ -70,6 +70,7 @@ struct msm_dp_mst { struct drm_dp_mst_topology_mgr mst_mgr; struct msm_dp_mst_bridge *mst_bridge[DP_STREAM_MAX]; struct msm_dp *msm_dp; + struct drm_dp_aux *dp_aux; u32 max_streams; struct mutex mst_lock; }; @@ -83,4 +84,6 @@ struct msm_dp_mst_connector { =20 int msm_dp_mst_drm_bridge_init(struct msm_dp *dp, struct drm_encoder *enco= der); =20 +int msm_dp_mst_init(struct msm_dp *dp_display, u32 max_streams, struct drm= _dp_aux *drm_aux); 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In MST case, route the HPD messages to MST module. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 15 ++++++++++++--- drivers/gpu/drm/msm/dp/dp_mst_drm.c | 34 ++++++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/dp/dp_mst_drm.h | 2 ++ 3 files changed, 48 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index abcab3ed43b6da5ef898355cf9b7561cd9fe0404..59720e1ad4b1193e33a4fc6aad0= c401eaf9cbec8 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -500,9 +500,16 @@ static int msm_dp_display_handle_irq_hpd(struct msm_dp= _display_private *dp) =20 static int msm_dp_display_usbpd_attention_cb(struct device *dev) { - int rc =3D 0; - u32 sink_request; struct msm_dp_display_private *dp =3D dev_get_dp_display_private(dev); + struct msm_dp *msm_dp_display =3D &dp->msm_dp_display; + u32 sink_request; + int rc =3D 0; + + if (msm_dp_display->mst_active) { + if (msm_dp_aux_is_link_connected(dp->aux) !=3D ISR_DISCONNECTED) + msm_dp_mst_display_hpd_irq(&dp->msm_dp_display); + return 0; + } =20 /* check for any test request issued by sink */ rc =3D msm_dp_link_process_request(dp->link); @@ -1129,8 +1136,10 @@ static irqreturn_t msm_dp_display_irq_thread(int irq= , void *dev_id) if (hpd_isr_status & DP_DP_HPD_UNPLUG_INT_MASK) msm_dp_display_send_hpd_notification(dp, false); =20 - if (hpd_isr_status & DP_DP_IRQ_HPD_INT_MASK) + if (hpd_isr_status & DP_DP_IRQ_HPD_INT_MASK) { msm_dp_display_send_hpd_notification(dp, true); + msm_dp_irq_hpd_handle(dp, 0); + } =20 ret =3D IRQ_HANDLED; =20 diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.c b/drivers/gpu/drm/msm/dp/d= p_mst_drm.c index b4f640134af544c77ab262d2cbe0b67e1e2e1b3a..331d08854049d9c74d49aa231f3= 507539986099e 100644 --- a/drivers/gpu/drm/msm/dp/dp_mst_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.c @@ -567,6 +567,40 @@ static struct msm_dp_mst_bridge_state *msm_dp_mst_br_p= riv_state(struct drm_atomi return to_msm_dp_mst_bridge_state_priv(obj_state); } =20 +/* DP MST HPD IRQ callback */ +void msm_dp_mst_display_hpd_irq(struct msm_dp *dp_display) +{ + int rc; + struct msm_dp_mst *mst =3D dp_display->msm_dp_mst; + u8 ack[8] =3D {}; + u8 esi[4]; + unsigned int esi_res =3D DP_SINK_COUNT_ESI + 1; + bool handled; + + rc =3D drm_dp_dpcd_read(mst->dp_aux, DP_SINK_COUNT_ESI, + esi, 4); + if (rc !=3D 4) { + DRM_ERROR("dpcd sink status read failed, rlen=3D%d\n", rc); + return; + } + + drm_dbg_dp(dp_display->drm_dev, "mst irq: esi1[0x%x] esi2[0x%x] esi3[%x]\= n", + esi[1], esi[2], esi[3]); + + rc =3D drm_dp_mst_hpd_irq_handle_event(&mst->mst_mgr, esi, ack, &handled); + + /* ack the request */ + if (handled) { + rc =3D drm_dp_dpcd_writeb(mst->dp_aux, esi_res, ack[1]); + + if (rc !=3D 1) + DRM_ERROR("dpcd esi_res failed. rc=3D%d\n", rc); + + drm_dp_mst_hpd_irq_send_new_request(&mst->mst_mgr); + } + drm_dbg_dp(dp_display->drm_dev, "mst display hpd_irq handled:%d rc:%d\n",= handled, rc); +} + /* DP MST Connector OPs */ static int msm_dp_mst_connector_detect(struct drm_connector *connector, diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.h b/drivers/gpu/drm/msm/dp/d= p_mst_drm.h index 1484fabd92ad0075eac5369aac8ca462acbd3eda..5e1b4db8aea4506b0e1cc1cc689= 80dd617d3f72a 100644 --- a/drivers/gpu/drm/msm/dp/dp_mst_drm.h +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.h @@ -86,4 +86,6 @@ int msm_dp_mst_drm_bridge_init(struct msm_dp *dp, struct = drm_encoder *encoder); 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Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 10 +++++++++- drivers/gpu/drm/msm/dp/dp_mst_drm.c | 15 +++++++++++++++ drivers/gpu/drm/msm/dp/dp_mst_drm.h | 1 + 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 59720e1ad4b1193e33a4fc6aad0c401eaf9cbec8..909c84a5c97f56138d0d62c5d85= 6d2fd18d36b8c 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -28,6 +28,7 @@ #include "dp_drm.h" #include "dp_audio.h" #include "dp_debug.h" +#include "dp_mst_drm.h" =20 static bool psr_enabled =3D false; module_param(psr_enabled, bool, 0); @@ -269,7 +270,6 @@ static int msm_dp_display_send_hpd_notification(struct = msm_dp_display_private *d dp->panel->video_test =3D false; } =20 - drm_dbg_dp(dp->drm_dev, "type=3D%d hpd=3D%d\n", dp->msm_dp_display.connector_type, hpd); =20 @@ -386,6 +386,9 @@ static int msm_dp_display_process_hpd_high(struct msm_d= p_display_private *dp) =20 msm_dp_link_reset_phy_params_vx_px(dp->link); =20 + if (dp->msm_dp_display.mst_active) + msm_dp_mst_display_set_mgr_state(&dp->msm_dp_display, true); + if (!dp->msm_dp_display.internal_hpd) msm_dp_display_send_hpd_notification(dp, true); =20 @@ -608,6 +611,11 @@ static int msm_dp_hpd_unplug_handle(struct msm_dp_disp= lay_private *dp, u32 data) if (!dp->msm_dp_display.internal_hpd) msm_dp_display_send_hpd_notification(dp, false); =20 + if (dp->msm_dp_display.mst_active) { + msm_dp_mst_display_set_mgr_state(&dp->msm_dp_display, false); + dp->msm_dp_display.mst_active =3D false; + } + /* signal the disconnect event early to ensure proper teardown */ msm_dp_display_handle_plugged_change(&dp->msm_dp_display, false); =20 diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.c b/drivers/gpu/drm/msm/dp/d= p_mst_drm.c index 331d08854049d9c74d49aa231f3507539986099e..ca654b1963467c8220dd7ee073f= 25216455d0490 100644 --- a/drivers/gpu/drm/msm/dp/dp_mst_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.c @@ -924,6 +924,21 @@ msm_dp_mst_add_connector(struct drm_dp_mst_topology_mg= r *mgr, return connector; } =20 +int msm_dp_mst_display_set_mgr_state(struct msm_dp *dp_display, bool state) +{ + int rc; + struct msm_dp_mst *mst =3D dp_display->msm_dp_mst; + + rc =3D drm_dp_mst_topology_mgr_set_mst(&mst->mst_mgr, state); + if (rc < 0) { + DRM_ERROR("failed to set topology mgr state to %d. rc %d\n", + state, rc); + } + + drm_dbg_dp(dp_display->drm_dev, "dp_mst_display_set_mgr_state state:%d\n"= , state); + return rc; +} + static const struct drm_dp_mst_topology_cbs msm_dp_mst_drm_cbs =3D { .add_connector =3D msm_dp_mst_add_connector, }; diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.h b/drivers/gpu/drm/msm/dp/d= p_mst_drm.h index 5e1b4db8aea4506b0e1cc1cc68980dd617d3f72a..8fe6cbbe741da4abb232256b3a1= 5ba6b16ca4f3e 100644 --- a/drivers/gpu/drm/msm/dp/dp_mst_drm.h +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.h @@ -87,5 +87,6 @@ int msm_dp_mst_drm_bridge_init(struct msm_dp *dp, struct = drm_encoder *encoder); int msm_dp_mst_init(struct msm_dp *dp_display, u32 max_streams, struct drm= _dp_aux *drm_aux); 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This patch only applies to MST. For SST, non-blocking commits are already handled via commit_tail(), which internally calls drm_atomic_helper_wait_for_dependencies() in the DRM core. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/msm_atomic.c | 3 +++ drivers/gpu/drm/msm/msm_kms.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_ato= mic.c index 3aa0020dec3a90b693ad3d4171cfcffc091aad4c..b1656fb456d54af11ba8a30d497= 1fface114c7a1 100644 --- a/drivers/gpu/drm/msm/msm_atomic.c +++ b/drivers/gpu/drm/msm/msm_atomic.c @@ -4,6 +4,7 @@ * Author: Rob Clark */ =20 +#include #include #include #include @@ -226,6 +227,8 @@ void msm_atomic_commit_tail(struct drm_atomic_state *st= ate) =20 trace_msm_atomic_commit_tail_start(async, crtc_mask); =20 + drm_dp_mst_atomic_wait_for_dependencies(state); + kms->funcs->enable_commit(kms); =20 /* diff --git a/drivers/gpu/drm/msm/msm_kms.c b/drivers/gpu/drm/msm/msm_kms.c index 6889f1c1e72121dcc735fa460ea04cdab11c6705..09776be1d3d854f4c77d7df3afa= 8d56f53639411 100644 --- a/drivers/gpu/drm/msm/msm_kms.c +++ b/drivers/gpu/drm/msm/msm_kms.c @@ -10,6 +10,7 @@ #include #include =20 +#include #include #include #include @@ -29,6 +30,7 @@ static const struct drm_mode_config_funcs mode_config_fun= cs =3D { =20 static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = =3D { .atomic_commit_tail =3D msm_atomic_commit_tail, + .atomic_commit_setup =3D drm_dp_mst_atomic_setup_commit, }; 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Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 2 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 23 ++++++++++++++++++++++- drivers/gpu/drm/msm/dp/dp_mst_drm.h | 2 -- drivers/gpu/drm/msm/msm_drv.h | 13 +++++++++++++ 4 files changed, 37 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.h index ca1ca2e51d7ead0eb34b27f3168e6bb06a71a11a..2eb4c39b111c1d8622e09e78ffa= fef017e28bbf6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -28,6 +28,7 @@ * @h_tile_instance: Controller instance used per tile. Number of eleme= nts is * based on num_of_h_tiles * @is_cmd_mode Boolean to indicate if the CMD mode is requested + * @stream_id stream id for which the interface needs to be acquired * @vsync_source: Source of the TE signal for DSI CMD devices */ struct msm_display_info { @@ -35,6 +36,7 @@ struct msm_display_info { uint32_t num_of_h_tiles; uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY]; bool is_cmd_mode; + int stream_id; enum dpu_vsync_source vsync_source; }; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 12dcb32b472497f9e59619db4e810abfbf610c7c..0b9d9207f4f69e0d0725ff265c6= 24828b5816a8b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -653,7 +653,8 @@ static int _dpu_kms_initialize_displayport(struct drm_d= evice *dev, struct msm_display_info info; bool yuv_supported; int rc; - int i; + int i, stream_id; + int stream_cnt; =20 for (i =3D 0; i < ARRAY_SIZE(priv->kms->dp); i++) { if (!priv->kms->dp[i]) @@ -676,6 +677,26 @@ static int _dpu_kms_initialize_displayport(struct drm_= device *dev, DPU_ERROR("modeset_init failed for DP, rc =3D %d\n", rc); return rc; } + + stream_cnt =3D msm_dp_get_mst_max_stream(priv->kms->dp[i]); + + if (stream_cnt > 1) { + for (stream_id =3D 0; stream_id < stream_cnt; stream_id++) { + info.stream_id =3D stream_id; + encoder =3D dpu_encoder_init(dev, DRM_MODE_ENCODER_DPMST, &info); + if (IS_ERR(encoder)) { + DPU_ERROR("encoder init failed for dp mst display\n"); + return PTR_ERR(encoder); + } + + rc =3D msm_dp_mst_drm_bridge_init(priv->kms->dp[i], encoder); + if (rc) { + DPU_ERROR("dp mst bridge %d init failed, %d\n", + stream_id, rc); + continue; + } + } + } } =20 return 0; diff --git a/drivers/gpu/drm/msm/dp/dp_mst_drm.h b/drivers/gpu/drm/msm/dp/d= p_mst_drm.h index 8fe6cbbe741da4abb232256b3a15ba6b16ca4f3e..d73e3f908439094532e88945ed4= d41ed092051c9 100644 --- a/drivers/gpu/drm/msm/dp/dp_mst_drm.h +++ b/drivers/gpu/drm/msm/dp/dp_mst_drm.h @@ -82,8 +82,6 @@ struct msm_dp_mst_connector { struct msm_dp_panel *dp_panel; }; =20 -int msm_dp_mst_drm_bridge_init(struct msm_dp *dp, struct drm_encoder *enco= der); - int msm_dp_mst_init(struct msm_dp *dp_display, u32 max_streams, struct drm= _dp_aux *drm_aux); =20 void msm_dp_mst_display_hpd_irq(struct msm_dp *dp_display); diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 985db9febd98e35dfed51d39dac1a522abe5a351..3e64ec7b7dbe1d1107e85def9aa= 80277131f40bf 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -363,6 +363,9 @@ bool msm_dp_needs_periph_flush(const struct msm_dp *dp_= display, const struct drm_display_mode *mode); bool msm_dp_wide_bus_available(const struct msm_dp *dp_display); =20 +int msm_dp_get_mst_max_stream(struct msm_dp *dp_display); +int msm_dp_mst_drm_bridge_init(struct msm_dp *dp_display, struct drm_encod= er *encoder); + #else static inline int __init msm_dp_register(void) { @@ -379,6 +382,16 @@ static inline int msm_dp_modeset_init(struct msm_dp *d= p_display, return -EINVAL; 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The DP MST module for each controller is the central entity to manage its topology related operations as well as interfacing with the rest of the DP driver. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 6 ++++++ drivers/gpu/drm/msm/dp/dp_display.c | 9 +++++++++ drivers/gpu/drm/msm/msm_drv.h | 6 ++++++ 3 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index 0b9d9207f4f69e0d0725ff265c624828b5816a8b..4036d3445946930e635401109ac= 4720ed2282c2f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -681,6 +681,12 @@ static int _dpu_kms_initialize_displayport(struct drm_= device *dev, stream_cnt =3D msm_dp_get_mst_max_stream(priv->kms->dp[i]); =20 if (stream_cnt > 1) { + rc =3D msm_dp_mst_register(priv->kms->dp[i]); + if (rc) { + DPU_ERROR("dp_mst_init failed for DP, rc =3D %d\n", rc); + return rc; + } + for (stream_id =3D 0; stream_id < stream_cnt; stream_id++) { info.stream_id =3D stream_id; encoder =3D dpu_encoder_init(dev, DRM_MODE_ENCODER_DPMST, &info); diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 909c84a5c97f56138d0d62c5d856d2fd18d36b8c..897ef653b3cea08904bb3595e8a= c10fd7fcf811f 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -1586,6 +1586,15 @@ int msm_dp_modeset_init(struct msm_dp *msm_dp_displa= y, struct drm_device *dev, return 0; } =20 +inline int msm_dp_mst_register(struct msm_dp *msm_dp_display) +{ + struct msm_dp_display_private *dp; + + dp =3D container_of(msm_dp_display, struct msm_dp_display_private, msm_dp= _display); + + return msm_dp_mst_init(msm_dp_display, dp->max_stream, dp->aux); +} + void msm_dp_display_atomic_prepare(struct msm_dp *msm_dp_display) { int rc =3D 0; diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 3e64ec7b7dbe1d1107e85def9aa80277131f40bf..c46c88cf06598df996a17c23631= 570fda078b371 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -365,6 +365,7 @@ bool msm_dp_wide_bus_available(const struct msm_dp *dp_= display); =20 int msm_dp_get_mst_max_stream(struct msm_dp *dp_display); int msm_dp_mst_drm_bridge_init(struct msm_dp *dp_display, struct drm_encod= er *encoder); +int msm_dp_mst_register(struct msm_dp *dp_display); =20 #else static inline int __init msm_dp_register(void) @@ -392,6 +393,11 @@ static inline int msm_dp_mst_drm_bridge_init(struct ms= m_dp *dp_display, struct d return -EINVAL; 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Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 51 +++++++++++++++++++++++++= ---- 1 file changed, 44 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index 05e5f3463e30c9a6bd5b740580720ae2bf6b3246..2eb5397d15732b224372c68d0b2= b7167da9f2896 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1429,17 +1429,52 @@ static void dpu_encoder_virt_atomic_disable(struct = drm_encoder *drm_enc, =20 static struct dpu_hw_intf *dpu_encoder_get_intf(const struct dpu_mdss_cfg = *catalog, struct dpu_rm *dpu_rm, - enum dpu_intf_type type, u32 controller_id) + enum dpu_intf_type type, int enc_type, u32 id) { - int i =3D 0; + int i =3D 0, cnt =3D 0; + int controller_id =3D id >> 16; + int stream_id =3D id & 0x0F; =20 if (type =3D=3D INTF_WB) return NULL; =20 - for (i =3D 0; i < catalog->intf_count; i++) { - if (catalog->intf[i].type =3D=3D type - && catalog->intf[i].controller_id =3D=3D controller_id) { - return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id); + if (enc_type =3D=3D DRM_MODE_ENCODER_DPMST) { + /* The intf order in dpu_intf_cfg matches the mapping in the DP HPG. + * example: + * DPU_8_4_0 - DP Controller intf to stream Mapping + * + * +-------------+----------+----------+----------+----------+ + * | stream_id |=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0= =C2=A0=C2=A0 1=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0=C2=A0=C2=A0 2=C2=A0=C2=A0=C2= =A0=C2=A0 |=C2=A0=C2=A0=C2=A0 3=C2=A0=C2=A0=C2=A0=C2=A0 | + * +-------------+----------+----------+----------+----------+ + * | DP0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | INTF_0=C2=A0= =C2=A0 | INTF_3=C2=A0=C2=A0 | INTF_6=C2=A0=C2=A0 | INTF_7=C2=A0=C2=A0 | + * | DP1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | INTF_4=C2=A0= =C2=A0 | INTF_8=C2=A0=C2=A0 |=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0 |=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | + * +-------------+----------+----------+----------+----------+ + * + * DPU_9_2_0 - DP Controller intf to stream Mapping + * + * +-------------+----------+----------+ + * | Controller=C2=A0 |=C2=A0=C2=A0=C2=A0 0=C2=A0=C2=A0=C2=A0=C2=A0 |=C2= =A0=C2=A0=C2=A0 1=C2=A0=C2=A0=C2=A0=C2=A0 | + * +-------------+----------+----------+ + * | DP0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | INTF_0=C2=A0= =C2=A0 | INTF_3=C2=A0=C2=A0 | + * | DP1=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | INTF_4=C2=A0= =C2=A0 | INTF_8=C2=A0=C2=A0 | + * | DP2=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | INTF_6=C2=A0= =C2=A0 | INTF_7=C2=A0=C2=A0 | + * +-------------+----------+----------+ + */ + DPU_DEBUG("controller_id %d for stream_id =3D %d\n", controller_id, stre= am_id); + for (i =3D 0; i < catalog->intf_count; i++) { + if (catalog->intf[i].type =3D=3D INTF_DP + && controller_id =3D=3D catalog->intf[i].controller_id) { + if (cnt =3D=3D stream_id) + return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id); + cnt++; + } + } + } else { + for (i =3D 0; i < catalog->intf_count; i++) { + if (catalog->intf[i].type =3D=3D type + && catalog->intf[i].controller_id =3D=3D controller_id) { + return dpu_rm_get_intf(dpu_rm, catalog->intf[i].id); + } } } =20 @@ -2670,7 +2705,9 @@ static int dpu_encoder_setup_display(struct dpu_encod= er_virt *dpu_enc, =20 phys_params.hw_intf =3D dpu_encoder_get_intf(dpu_kms->catalog, &dpu_kms-= >rm, disp_info->intf_type, - controller_id); + dpu_enc->base.encoder_type, + controller_id << 16 + | disp_info->stream_id); =20 if (disp_info->intf_type =3D=3D INTF_WB && controller_id < WB_MAX) phys_params.hw_wb =3D dpu_rm_get_wb(&dpu_kms->rm, controller_id); --=20 2.34.1 From nobody Fri Oct 3 20:22:40 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EBD68308F33 for ; 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Update this to INTF_DP. And correct the intf_6 intr_underrun/intr_vsync index for dpu_8_4_sa8775p. Signed-off-by: Abhinav Kumar Signed-off-by: Yongxing Mou Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 6 +++--- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h index 303d33dc7783ac91a496fa0a19860564ad0b6d5d..ea2329f0b5e977bb0ee3035ec1b= 3a3e23bbe5b1e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h @@ -319,7 +319,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x37000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), @@ -351,7 +351,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] =3D { }, { .name =3D "intf_7", .id =3D INTF_7, .base =3D 0x3b000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_2, .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18), @@ -359,7 +359,7 @@ static const struct dpu_intf_cfg sc8280xp_intf[] =3D { }, { .name =3D "intf_8", .id =3D INTF_8, .base =3D 0x3c000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h index 0f7b4a224e4c971f482c3778c92e8c170b44223f..00fd0c8cc115a4a108363f6185e= df93e771b2bf5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h @@ -347,7 +347,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x37000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), @@ -363,15 +363,15 @@ static const struct dpu_intf_cfg sa8775p_intf[] =3D { }, { .name =3D "intf_6", .id =3D INTF_6, .base =3D 0x3A000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case =3D 24, - .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17), - .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16), + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17), }, { .name =3D "intf_7", .id =3D INTF_7, .base =3D 0x3b000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18), @@ -379,7 +379,7 @@ static const struct dpu_intf_cfg sa8775p_intf[] =3D { }, { .name =3D "intf_8", .id =3D INTF_8, .base =3D 0x3c000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */ .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/dri= vers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index 7243eebb85f36f2a8ae848f2c95d21b0bc3bebef..826f65adb18b118cf8b70208837= aa7979c5701b6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -335,7 +335,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] =3D { }, { .name =3D "intf_3", .id =3D INTF_3, .base =3D 0x37000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), @@ -367,7 +367,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] =3D { }, { .name =3D "intf_7", .id =3D INTF_7, .base =3D 0x3b000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */ .prog_fetch_lines_worst_case =3D 24, .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18), @@ -375,7 +375,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] =3D { }, { .name =3D "intf_8", .id =3D INTF_8, .base =3D 0x3c000, .len =3D 0x280, - .type =3D INTF_NONE, + .type =3D INTF_DP, .controller_id =3D MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */ .prog_fetch_lines_worst_case =3D 24, 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d2e1a72fcca58-770401eb20dsm7672339b3a.79.2025.08.25.07.19.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Aug 2025 07:19:47 -0700 (PDT) From: Yongxing Mou Date: Mon, 25 Aug 2025 22:16:24 +0800 Subject: [PATCH v3 38/38] drm/msm/dp: Add MST stream support for SA8775P DP controller 0 and 1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-msm-dp-mst-v3-38-01faacfcdedd@oss.qualcomm.com> References: <20250825-msm-dp-mst-v3-0-01faacfcdedd@oss.qualcomm.com> In-Reply-To: <20250825-msm-dp-mst-v3-0-01faacfcdedd@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Yongxing Mou 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DisplayPort streams. As all necessary code for MST support was already implemented in the previous series of patches. Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index 897ef653b3cea08904bb3595e8ac10fd7fcf811f..4a94f37513c21f9a273080b572a= 1e50a186a45ce 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -108,8 +108,10 @@ struct msm_dp_desc { }; =20 static const struct msm_dp_desc msm_dp_desc_sa8775p[] =3D { - { .io_start =3D 0x0af54000, .id =3D MSM_DP_CONTROLLER_0, .wide_bus_suppor= ted =3D true }, - { .io_start =3D 0x0af5c000, .id =3D MSM_DP_CONTROLLER_1, .wide_bus_suppor= ted =3D true }, + { .io_start =3D 0x0af54000, .id =3D MSM_DP_CONTROLLER_0, .wide_bus_suppor= ted =3D true, + .mst_streams =3D 4}, + { .io_start =3D 0x0af5c000, .id =3D MSM_DP_CONTROLLER_1, .wide_bus_suppor= ted =3D true, + .mst_streams =3D 2}, { .io_start =3D 0x22154000, .id =3D MSM_DP_CONTROLLER_2, .wide_bus_suppor= ted =3D true }, { .io_start =3D 0x2215c000, .id =3D MSM_DP_CONTROLLER_3, .wide_bus_suppor= ted =3D true }, {} --=20 2.34.1