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Mon, 25 Aug 2025 07:27:14 -0700 (PDT) From: Jerome Brunet Date: Mon, 25 Aug 2025 16:26:37 +0200 Subject: [PATCH v2 12/12] clk: amlogic: c3-peripherals: use helper for basic composite clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-meson-clk-cleanup-24-v2-12-0f402f01e117@baylibre.com> References: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> In-Reply-To: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet , Chuan Liu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=32323; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=ps9sLzPPWk2M8ivkTmXUaslXwG8/bmatTRMHNFG1fME=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBorHK4qpXm7JmpvPobuRaQvfv+8Nfs2wLyI4+RD dk9RSaqFQCJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaKxyuAAKCRDm/A8cN/La hRGoEACDZa/T4n3cZ+Et6j5Ca+v57X1x5SyuJ2iXWhlDxHe0rIZIRSBjD5FqDgNP8mePJIPqeOy 2YaS4wC25muwGthDedfsI6xl7XNhwxlCgKZ5h4CPT04FFyzHM3lXJtGqD4dkg07zLCTTfCz8Wdm WA7eRVBgKHlhd1ZBzjvkTyy1z1dwcHEegWC2tydllMeTYuLRViF+Tn+VHr8+7h8GwjuqOUNpMz6 ePO23AlWSuH7g6YssXUqKMLjhuijjzDlY1uZSvr9pxgWRR7YVz7O5FFV6qtSFCRJlEMywEl6DER mxWzs/7yug9/r40V4AAOgJm+jdwWkeshUssX6XcEUkYbtLlhB7+CpTUzgY/4jHVh/lZ9dI42aOZ Tu1ytx2J34WeRVMO3QcL8QmkXWzJA/AyAB6bRWXYohgCKprY4byIfuQnaWTpaJm2tuiGLLrItRz sOj2AS73uipN0gd2VJMelZ81x30d6g2MS8cJF2p883WZ6kCTbrXcAww3rU+ZKlSEg37WtE6Bj7J 92osANTpGYvFn49R1taeZOGT++1gKomnKByigaVhRiATOY+7AHatcRtAZb9IUzwt61UKAMEG8Bp z72ZPSjjHi28E4/zIJJnCIXF8XwZxn8+rbm5cT9k8XSNSk/8MPlJBhsdazQ6s33okylcFquTCHB NnnmDwwLOOG3xWA== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Use the composite clock helpers to define simple composite clocks of the c3-peripherals clock controller. This reduces the verbosity of the controller code on these very simple parts, making maintenance simpler. Reviewed-by: Chuan Liu Signed-off-by: Jerome Brunet --- drivers/clk/meson/c3-peripherals.c | 1029 +++-----------------------------= ---- 1 file changed, 63 insertions(+), 966 deletions(-) diff --git a/drivers/clk/meson/c3-peripherals.c b/drivers/clk/meson/c3-peri= pherals.c index fd35f9b7994720d069c5f72142d6064790d40b60..b158756cfee4dd4bad5c0c9576d= a02d2cb8ee515 100644 --- a/drivers/clk/meson/c3-peripherals.c +++ b/drivers/clk/meson/c3-peripherals.c @@ -467,52 +467,9 @@ static const struct clk_parent_data c3_saradc_parents[= ] =3D { { .fw_name =3D "sysclk" } }; =20 -static struct clk_regmap c3_saradc_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D SAR_CLK_CTRL0, - .mask =3D 0x1, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "saradc_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_saradc_parents, - .num_parents =3D ARRAY_SIZE(c3_saradc_parents), - }, -}; - -static struct clk_regmap c3_saradc_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D SAR_CLK_CTRL0, - .shift =3D 0, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "saradc_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_saradc_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_saradc =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D SAR_CLK_CTRL0, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "saradc", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_saradc_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(saradc, SAR_CLK_CTRL0, 9, 0x1, c3_saradc_parents); +static C3_COMP_DIV(saradc, SAR_CLK_CTRL0, 0, 8); +static C3_COMP_GATE(saradc, SAR_CLK_CTRL0, 8); =20 static const struct clk_parent_data c3_pwm_parents[] =3D { { .fw_name =3D "oscin" }, @@ -588,99 +545,13 @@ static const struct clk_parent_data c3_spicc_parents[= ] =3D { { .fw_name =3D "gp1" } }; =20 -static struct clk_regmap c3_spicc_a_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D SPICC_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "spicc_a_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_spicc_parents, - .num_parents =3D ARRAY_SIZE(c3_spicc_parents), - }, -}; - -static struct clk_regmap c3_spicc_a_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D SPICC_CLK_CTRL, - .shift =3D 0, - .width =3D 6, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "spicc_a_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_spicc_a_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_spicc_a =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D SPICC_CLK_CTRL, - .bit_idx =3D 6, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "spicc_a", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_spicc_a_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_spicc_b_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D SPICC_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 23, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "spicc_b_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_spicc_parents, - .num_parents =3D ARRAY_SIZE(c3_spicc_parents), - }, -}; - -static struct clk_regmap c3_spicc_b_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D SPICC_CLK_CTRL, - .shift =3D 16, - .width =3D 6, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "spicc_b_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_spicc_b_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(spicc_a, SPICC_CLK_CTRL, 7, 0x7, c3_spicc_parents); +static C3_COMP_DIV(spicc_a, SPICC_CLK_CTRL, 0, 6); +static C3_COMP_GATE(spicc_a, SPICC_CLK_CTRL, 6); =20 -static struct clk_regmap c3_spicc_b =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D SPICC_CLK_CTRL, - .bit_idx =3D 22, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "spicc_b", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_spicc_b_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(spicc_b, SPICC_CLK_CTRL, 23, 0x7, c3_spicc_parents); +static C3_COMP_DIV(spicc_b, SPICC_CLK_CTRL, 16, 6); +static C3_COMP_GATE(spicc_b, SPICC_CLK_CTRL, 22); =20 static const struct clk_parent_data c3_spifc_parents[] =3D { { .fw_name =3D "gp0" }, @@ -693,52 +564,9 @@ static const struct clk_parent_data c3_spifc_parents[]= =3D { { .fw_name =3D "fdiv7" } }; =20 -static struct clk_regmap c3_spifc_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D SPIFC_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "spifc_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_spifc_parents, - .num_parents =3D ARRAY_SIZE(c3_spifc_parents), - }, -}; - -static struct clk_regmap c3_spifc_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D SPIFC_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "spifc_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_spifc_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_spifc =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D SPIFC_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "spifc", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_spifc_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(spifc, SPIFC_CLK_CTRL, 9, 0x7, c3_spifc_parents); +static C3_COMP_DIV(spifc, SPIFC_CLK_CTRL, 0, 7); +static C3_COMP_GATE(spifc, SPIFC_CLK_CTRL, 8); =20 static const struct clk_parent_data c3_sd_emmc_parents[] =3D { { .fw_name =3D "oscin" }, @@ -751,146 +579,17 @@ static const struct clk_parent_data c3_sd_emmc_paren= ts[] =3D { { .fw_name =3D "gp0" } }; =20 -static struct clk_regmap c3_sd_emmc_a_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D SD_EMMC_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "sd_emmc_a_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_sd_emmc_parents, - .num_parents =3D ARRAY_SIZE(c3_sd_emmc_parents), - }, -}; - -static struct clk_regmap c3_sd_emmc_a_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D SD_EMMC_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "sd_emmc_a_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_sd_emmc_a_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_sd_emmc_a =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D SD_EMMC_CLK_CTRL, - .bit_idx =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "sd_emmc_a", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_sd_emmc_a_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_sd_emmc_b_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D SD_EMMC_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "sd_emmc_b_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_sd_emmc_parents, - .num_parents =3D ARRAY_SIZE(c3_sd_emmc_parents), - }, -}; - -static struct clk_regmap c3_sd_emmc_b_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D SD_EMMC_CLK_CTRL, - .shift =3D 16, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "sd_emmc_b_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_sd_emmc_b_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_sd_emmc_b =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D SD_EMMC_CLK_CTRL, - .bit_idx =3D 23, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "sd_emmc_b", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_sd_emmc_b_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_sd_emmc_c_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D NAND_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "sd_emmc_c_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_sd_emmc_parents, - .num_parents =3D ARRAY_SIZE(c3_sd_emmc_parents), - }, -}; +static C3_COMP_SEL(sd_emmc_a, SD_EMMC_CLK_CTRL, 9, 0x7, c3_sd_emmc_parents= ); +static C3_COMP_DIV(sd_emmc_a, SD_EMMC_CLK_CTRL, 0, 7); +static C3_COMP_GATE(sd_emmc_a, SD_EMMC_CLK_CTRL, 7); =20 -static struct clk_regmap c3_sd_emmc_c_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D NAND_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "sd_emmc_c_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_sd_emmc_c_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(sd_emmc_b, SD_EMMC_CLK_CTRL, 25, 0x7, c3_sd_emmc_parent= s); +static C3_COMP_DIV(sd_emmc_b, SD_EMMC_CLK_CTRL, 16, 7); +static C3_COMP_GATE(sd_emmc_b, SD_EMMC_CLK_CTRL, 23); =20 -static struct clk_regmap c3_sd_emmc_c =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D NAND_CLK_CTRL, - .bit_idx =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "sd_emmc_c", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_sd_emmc_c_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(sd_emmc_c, NAND_CLK_CTRL, 9, 0x7, c3_sd_emmc_parents); +static C3_COMP_DIV(sd_emmc_c, NAND_CLK_CTRL, 0, 7); +static C3_COMP_GATE(sd_emmc_c, NAND_CLK_CTRL, 7); =20 static struct clk_regmap c3_ts_div =3D { .data =3D &(struct clk_regmap_div_data) { @@ -996,52 +695,9 @@ static const struct clk_parent_data c3_mipi_dsi_meas_p= arents[] =3D { { .fw_name =3D "fdiv7" } }; =20 -static struct clk_regmap c3_mipi_dsi_meas_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D VDIN_MEAS_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 21, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "mipi_dsi_meas_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_mipi_dsi_meas_parents, - .num_parents =3D ARRAY_SIZE(c3_mipi_dsi_meas_parents), - }, -}; - -static struct clk_regmap c3_mipi_dsi_meas_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D VDIN_MEAS_CLK_CTRL, - .shift =3D 12, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "mipi_dsi_meas_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_mipi_dsi_meas_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_mipi_dsi_meas =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D VDIN_MEAS_CLK_CTRL, - .bit_idx =3D 20, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "mipi_dsi_meas", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_mipi_dsi_meas_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(mipi_dsi_meas, VDIN_MEAS_CLK_CTRL, 21, 0x7, c3_mipi_dsi= _meas_parents); +static C3_COMP_DIV(mipi_dsi_meas, VDIN_MEAS_CLK_CTRL, 12, 7); +static C3_COMP_GATE(mipi_dsi_meas, VDIN_MEAS_CLK_CTRL, 20); =20 static const struct clk_parent_data c3_dsi_phy_parents[] =3D { { .fw_name =3D "gp1" }, @@ -1054,52 +710,9 @@ static const struct clk_parent_data c3_dsi_phy_parent= s[] =3D { { .fw_name =3D "fdiv7" } }; =20 -static struct clk_regmap c3_dsi_phy_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D MIPIDSI_PHY_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 12, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "dsi_phy_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_dsi_phy_parents, - .num_parents =3D ARRAY_SIZE(c3_dsi_phy_parents), - }, -}; - -static struct clk_regmap c3_dsi_phy_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D MIPIDSI_PHY_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "dsi_phy_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_dsi_phy_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_dsi_phy =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D MIPIDSI_PHY_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "dsi_phy", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_dsi_phy_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(dsi_phy, MIPIDSI_PHY_CLK_CTRL, 12, 0x7, c3_dsi_phy_pare= nts); +static C3_COMP_DIV(dsi_phy, MIPIDSI_PHY_CLK_CTRL, 0, 7); +static C3_COMP_GATE(dsi_phy, MIPIDSI_PHY_CLK_CTRL, 8); =20 static const struct clk_parent_data c3_vout_mclk_parents[] =3D { { .fw_name =3D "fdiv2p5" }, @@ -1112,52 +725,9 @@ static const struct clk_parent_data c3_vout_mclk_pare= nts[] =3D { { .fw_name =3D "fdiv7" } }; =20 -static struct clk_regmap c3_vout_mclk_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D VOUTENC_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vout_mclk_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_vout_mclk_parents, - .num_parents =3D ARRAY_SIZE(c3_vout_mclk_parents), - }, -}; - -static struct clk_regmap c3_vout_mclk_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D VOUTENC_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vout_mclk_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vout_mclk_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_vout_mclk =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D VOUTENC_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vout_mclk", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vout_mclk_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(vout_mclk, VOUTENC_CLK_CTRL, 9, 0x7, c3_vout_mclk_paren= ts); +static C3_COMP_DIV(vout_mclk, VOUTENC_CLK_CTRL, 0, 7); +static C3_COMP_GATE(vout_mclk, VOUTENC_CLK_CTRL, 8); =20 static const struct clk_parent_data c3_vout_enc_parents[] =3D { { .fw_name =3D "gp1" }, @@ -1170,52 +740,9 @@ static const struct clk_parent_data c3_vout_enc_paren= ts[] =3D { { .fw_name =3D "fdiv7" } }; =20 -static struct clk_regmap c3_vout_enc_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D VOUTENC_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vout_enc_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_vout_enc_parents, - .num_parents =3D ARRAY_SIZE(c3_vout_enc_parents), - }, -}; - -static struct clk_regmap c3_vout_enc_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D VOUTENC_CLK_CTRL, - .shift =3D 16, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vout_enc_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vout_enc_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_vout_enc =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D VOUTENC_CLK_CTRL, - .bit_idx =3D 24, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vout_enc", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vout_enc_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(vout_enc, VOUTENC_CLK_CTRL, 25, 0x7, c3_vout_enc_parent= s); +static C3_COMP_DIV(vout_enc, VOUTENC_CLK_CTRL, 16, 7); +static C3_COMP_GATE(vout_enc, VOUTENC_CLK_CTRL, 24); =20 static const struct clk_parent_data c3_hcodec_pre_parents[] =3D { { .fw_name =3D "fdiv2p5" }, @@ -1228,99 +755,13 @@ static const struct clk_parent_data c3_hcodec_pre_pa= rents[] =3D { { .fw_name =3D "oscin" } }; =20 -static struct clk_regmap c3_hcodec_0_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D VDEC_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "hcodec_0_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_hcodec_pre_parents, - .num_parents =3D ARRAY_SIZE(c3_hcodec_pre_parents), - }, -}; +static C3_COMP_SEL(hcodec_0, VDEC_CLK_CTRL, 9, 0x7, c3_hcodec_pre_parents= ); +static C3_COMP_DIV(hcodec_0, VDEC_CLK_CTRL, 0, 7); +static C3_COMP_GATE(hcodec_0, VDEC_CLK_CTRL, 8); =20 -static struct clk_regmap c3_hcodec_0_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D VDEC_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "hcodec_0_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_hcodec_0_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_hcodec_0 =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D VDEC_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "hcodec_0", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_hcodec_0_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_hcodec_1_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D VDEC3_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "hcodec_1_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_hcodec_pre_parents, - .num_parents =3D ARRAY_SIZE(c3_hcodec_pre_parents), - }, -}; - -static struct clk_regmap c3_hcodec_1_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D VDEC3_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "hcodec_1_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_hcodec_1_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_hcodec_1 =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D VDEC3_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "hcodec_1", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_hcodec_1_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(hcodec_1, VDEC3_CLK_CTRL, 9, 0x7, c3_hcodec_pre_parents= ); +static C3_COMP_DIV(hcodec_1, VDEC3_CLK_CTRL, 0, 7); +static C3_COMP_GATE(hcodec_1, VDEC3_CLK_CTRL, 8); =20 static const struct clk_parent_data c3_hcodec_parents[] =3D { { .hw =3D &c3_hcodec_0.hw }, @@ -1353,99 +794,13 @@ static const struct clk_parent_data c3_vc9000e_paren= ts[] =3D { { .fw_name =3D "gp0" } }; =20 -static struct clk_regmap c3_vc9000e_aclk_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D VC9000E_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vc9000e_aclk_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_vc9000e_parents, - .num_parents =3D ARRAY_SIZE(c3_vc9000e_parents), - }, -}; - -static struct clk_regmap c3_vc9000e_aclk_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D VC9000E_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vc9000e_aclk_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vc9000e_aclk_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_vc9000e_aclk =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D VC9000E_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vc9000e_aclk", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vc9000e_aclk_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_vc9000e_core_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D VC9000E_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vc9000e_core_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_vc9000e_parents, - .num_parents =3D ARRAY_SIZE(c3_vc9000e_parents), - }, -}; - -static struct clk_regmap c3_vc9000e_core_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D VC9000E_CLK_CTRL, - .shift =3D 16, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vc9000e_core_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vc9000e_core_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(vc9000e_aclk, VC9000E_CLK_CTRL, 9, 0x7, c3_vc9000e_pare= nts); +static C3_COMP_DIV(vc9000e_aclk, VC9000E_CLK_CTRL, 0, 7); +static C3_COMP_GATE(vc9000e_aclk, VC9000E_CLK_CTRL, 8); =20 -static struct clk_regmap c3_vc9000e_core =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D VC9000E_CLK_CTRL, - .bit_idx =3D 24, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vc9000e_core", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vc9000e_core_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(vc9000e_core, VC9000E_CLK_CTRL, 25, 0x7, c3_vc9000e_par= ents); +static C3_COMP_DIV(vc9000e_core, VC9000E_CLK_CTRL, 16, 7); +static C3_COMP_GATE(vc9000e_core, VC9000E_CLK_CTRL, 24); =20 static const struct clk_parent_data c3_csi_phy_parents[] =3D { { .fw_name =3D "fdiv2p5" }, @@ -1458,52 +813,9 @@ static const struct clk_parent_data c3_csi_phy_parent= s[] =3D { { .fw_name =3D "oscin" } }; =20 -static struct clk_regmap c3_csi_phy0_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D ISP0_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "csi_phy0_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_csi_phy_parents, - .num_parents =3D ARRAY_SIZE(c3_csi_phy_parents), - }, -}; - -static struct clk_regmap c3_csi_phy0_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D ISP0_CLK_CTRL, - .shift =3D 16, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "csi_phy0_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_csi_phy0_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_csi_phy0 =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D ISP0_CLK_CTRL, - .bit_idx =3D 24, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "csi_phy0", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_csi_phy0_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(csi_phy0, ISP0_CLK_CTRL, 25, 0x7, c3_csi_phy_parents); +static C3_COMP_DIV(csi_phy0, ISP0_CLK_CTRL, 16, 7); +static C3_COMP_GATE(csi_phy0, ISP0_CLK_CTRL, 24); =20 static const struct clk_parent_data c3_dewarpa_parents[] =3D { { .fw_name =3D "fdiv2p5" }, @@ -1516,52 +828,9 @@ static const struct clk_parent_data c3_dewarpa_parent= s[] =3D { { .fw_name =3D "fdiv7" } }; =20 -static struct clk_regmap c3_dewarpa_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D DEWARPA_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "dewarpa_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_dewarpa_parents, - .num_parents =3D ARRAY_SIZE(c3_dewarpa_parents), - }, -}; - -static struct clk_regmap c3_dewarpa_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D DEWARPA_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "dewarpa_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_dewarpa_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_dewarpa =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D DEWARPA_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "dewarpa", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_dewarpa_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(dewarpa, DEWARPA_CLK_CTRL, 9, 0x7, c3_dewarpa_parents); +static C3_COMP_DIV(dewarpa, DEWARPA_CLK_CTRL, 0, 7); +static C3_COMP_GATE(dewarpa, DEWARPA_CLK_CTRL, 8); =20 static const struct clk_parent_data c3_isp_parents[] =3D { { .fw_name =3D "fdiv2p5" }, @@ -1574,52 +843,9 @@ static const struct clk_parent_data c3_isp_parents[] = =3D { { .fw_name =3D "oscin" } }; =20 -static struct clk_regmap c3_isp0_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D ISP0_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "isp0_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_isp_parents, - .num_parents =3D ARRAY_SIZE(c3_isp_parents), - }, -}; - -static struct clk_regmap c3_isp0_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D ISP0_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "isp0_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_isp0_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_isp0 =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D ISP0_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "isp0", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_isp0_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(isp0, ISP0_CLK_CTRL, 9, 0x7, c3_isp_parents); +static C3_COMP_DIV(isp0, ISP0_CLK_CTRL, 0, 7); +static C3_COMP_GATE(isp0, ISP0_CLK_CTRL, 8); =20 static const struct clk_parent_data c3_nna_core_parents[] =3D { { .fw_name =3D "oscin" }, @@ -1632,52 +858,9 @@ static const struct clk_parent_data c3_nna_core_paren= ts[] =3D { { .fw_name =3D "hifi" } }; =20 -static struct clk_regmap c3_nna_core_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D NNA_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "nna_core_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_nna_core_parents, - .num_parents =3D ARRAY_SIZE(c3_nna_core_parents), - }, -}; - -static struct clk_regmap c3_nna_core_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D NNA_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "nna_core_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_nna_core_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_nna_core =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D NNA_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "nna_core", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_nna_core_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(nna_core, NNA_CLK_CTRL, 9, 0x7, c3_nna_core_parents); +static C3_COMP_DIV(nna_core, NNA_CLK_CTRL, 0, 7); +static C3_COMP_GATE(nna_core, NNA_CLK_CTRL, 8); =20 static const struct clk_parent_data c3_ge2d_parents[] =3D { { .fw_name =3D "oscin" }, @@ -1690,52 +873,9 @@ static const struct clk_parent_data c3_ge2d_parents[]= =3D { { .hw =3D &c3_rtc_clk.hw } }; =20 -static struct clk_regmap c3_ge2d_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D GE2D_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "ge2d_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_ge2d_parents, - .num_parents =3D ARRAY_SIZE(c3_ge2d_parents), - }, -}; - -static struct clk_regmap c3_ge2d_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D GE2D_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "ge2d_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_ge2d_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_ge2d =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D GE2D_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "ge2d", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_ge2d_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(ge2d, GE2D_CLK_CTRL, 9, 0x7, c3_ge2d_parents); +static C3_COMP_DIV(ge2d, GE2D_CLK_CTRL, 0, 7); +static C3_COMP_GATE(ge2d, GE2D_CLK_CTRL, 8); =20 static const struct clk_parent_data c3_vapb_parents[] =3D { { .fw_name =3D "fdiv2p5" }, @@ -1748,52 +888,9 @@ static const struct clk_parent_data c3_vapb_parents[]= =3D { { .fw_name =3D "oscin" }, }; =20 -static struct clk_regmap c3_vapb_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D VAPB_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vapb_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_vapb_parents, - .num_parents =3D ARRAY_SIZE(c3_vapb_parents), - }, -}; - -static struct clk_regmap c3_vapb_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D VAPB_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vapb_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vapb_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_vapb =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D VAPB_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vapb", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vapb_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(vapb, VAPB_CLK_CTRL, 9, 0x7, c3_vapb_parents); +static C3_COMP_DIV(vapb, VAPB_CLK_CTRL, 0, 7); +static C3_COMP_GATE(vapb, VAPB_CLK_CTRL, 8); =20 static struct clk_hw *c3_peripherals_hw_clks[] =3D { [CLKID_RTC_XTAL_CLKIN] =3D &c3_rtc_xtal_clkin.hw, --=20 2.47.2