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Mon, 25 Aug 2025 07:27:13 -0700 (PDT) From: Jerome Brunet Date: Mon, 25 Aug 2025 16:26:35 +0200 Subject: [PATCH v2 10/12] clk: amlogic: add composite clock helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-meson-clk-cleanup-24-v2-10-0f402f01e117@baylibre.com> References: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> In-Reply-To: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2898; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=suncESI2oSW1jGwgW8HALT/gxYfqW5NYgFG0TK2ZRwc=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBorHK2LR9cAulu/Dg7wzveWSkLYkNJ9hi4wbYHo pFJxTH5+cWJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaKxytgAKCRDm/A8cN/La hSDrD/9Qb0PyVOZn3hszgeqgrG8upaAQ55iBmu/kHai53eku7dMNLCgo/GSxS12i1nnj8NSriLW ErB6hHemrtB7p9fYVUslxB/hZ9MISdi7tRa1yZjB6FuxI8XE+mZUICX5tmrea/cNAxFLAGcnQlN 63CIJ7+aYY6X0vM9nQIrY4D0gluWYwi85q2rxa4VaD0z7DzmhXUjKIF6XaztRJxp4rl4Zz54u+g P0Px1NL0pQdh3m1V4ADCp0hlht2Mnzvxneei7m4Mu8jAdo8K1TjrabWY8mAWheTSZ0JCSyg6KJi WvlFlQcKiK6nsgepnfrp+MXo2+/dpljD8J+K3zwkmA65txvZMac3NcBacKTG2ToB0oNKzFqOiRO TijnFU8ByjWNQOhGlD/H3vfpxvxIV5Rglm8Ds6CBqTLTFPEPc1iFTE9E41mrWxLok/nvH8ov6vQ hPfIhHKuIgFGlxtEZsqxcY9WiPpqIMqaQyzueRkUhy+j7LTEhT8+kSduPZUUsKYRwFnZFxcTMYk XyKrwLv4GAN4/x6tEqqXKSPmolH2SND4jkjse858xq0S+3Y05806RQL0270Q4/6IOLKcstu4hZE 5VHDw8Ltk2K0/Psd8SrPWGv2XkA703A+IqUiQuQ0kc7LPsCvpD3crNQrMt3bDU+csrYlXJ1V78w eaM64tYtmmBuiWw== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Device composite clocks tend to reproduce the usual sel/div/gate arrangement. Add macros to help define simple composite clocks in the system. The idea is _not_ to replace all instances of mux, div or gate with those macros. It is rather to use it for recurring and/or simple composite clocks, reducing controller verbosity where it makes sense. This should help reviews focus on the tricky parts. Signed-off-by: Jerome Brunet --- drivers/clk/meson/meson-clkc-utils.h | 57 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 57 insertions(+) diff --git a/drivers/clk/meson/meson-clkc-utils.h b/drivers/clk/meson/meson= -clkc-utils.h index 95d9f85f7ca22f63a16f8665d6f7a250b21bfdb8..ddadf14b4923781d8807546f35a= 1ba2e6a8a894a 100644 --- a/drivers/clk/meson/meson-clkc-utils.h +++ b/drivers/clk/meson/meson-clkc-utils.h @@ -48,4 +48,61 @@ struct clk_regmap _name =3D { \ #define MESON_PCLK_RO(_name, _reg, _bit, _pdata, _flags) \ __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pdata, _flags) =20 +/* Helpers for the usual sel/div/gate composite clocks */ +#define MESON_COMP_SEL(_prefix, _name, _reg, _shift, _mask, _pdata, \ + _table, _dflags, _iflags) \ +struct clk_regmap _prefix##_name##_sel =3D { \ + .data =3D &(struct clk_regmap_mux_data) { \ + .offset =3D (_reg), \ + .mask =3D (_mask), \ + .shift =3D (_shift), \ + .flags =3D (_dflags), \ + .table =3D (_table), \ + }, \ + .hw.init =3D &(struct clk_init_data){ \ + .name =3D #_name "_sel", \ + .ops =3D &clk_regmap_mux_ops, \ + .parent_data =3D _pdata, \ + .num_parents =3D ARRAY_SIZE(_pdata), \ + .flags =3D (_iflags), \ + }, \ +} + +#define MESON_COMP_DIV(_prefix, _name, _reg, _shift, _width, \ + _dflags, _iflags) \ +struct clk_regmap _prefix##_name##_div =3D { \ + .data =3D &(struct clk_regmap_div_data) { \ + .offset =3D (_reg), \ + .shift =3D (_shift), \ + .width =3D (_width), \ + .flags =3D (_dflags), \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D #_name "_div", \ + .ops =3D &clk_regmap_divider_ops, \ + .parent_hws =3D (const struct clk_hw *[]) { \ + &_prefix##_name##_sel.hw \ + }, \ + .num_parents =3D 1, \ + .flags =3D (_iflags), \ + }, \ +} + +#define MESON_COMP_GATE(_prefix, _name, _reg, _bit, _iflags) \ +struct clk_regmap _prefix##_name =3D { \ + .data =3D &(struct clk_regmap_gate_data) { \ + .offset =3D (_reg), \ + .bit_idx =3D (_bit), \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D #_name, \ + .ops =3D &clk_regmap_gate_ops, \ + .parent_hws =3D (const struct clk_hw *[]) { \ + &_prefix##_name##_div.hw \ + }, \ + .num_parents =3D 1, \ + .flags =3D (_iflags), \ + }, \ +} + #endif --=20 2.47.2