From nobody Fri Oct 3 20:30:33 2025 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C82EE2FB98F for ; Mon, 25 Aug 2025 14:27:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132033; cv=none; b=aLWdXQf8tGuYwV2x7/sejhHqF5ZPgqgSxid5ETrKUCiw7If7w46Overve85mqvKLKubQSarlfXljYmbypZ2ymZMo6+YPxpcwm2PVVyRzDarai+KRo6oMmNUGc8rkRExDBf+aSEehy9qRN9POl+Md/E/KWZvGD75PmSAjQ3RooQc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132033; c=relaxed/simple; bh=wIEIXo0GxVU4ywzJB/g6XZYic4UF9s5rP6rG75651IM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=I5zRotc+AlMh9xVRZUifVr2mrNl3yU4c9cgxuN4UhH6XsI4KW1OQMbDaT++/AozlqshRJu32T1i4PVlSMJ/BAGdv8/epdIME/26EtUCoe224RWXlHNTCJiiyoazrvcwDNsfFGiZW+IcJ8Ym324ugAnnpZyVz4OOvINJbuwmMdaw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=kCvU29sP; arc=none smtp.client-ip=209.85.221.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="kCvU29sP" Received: by mail-wr1-f41.google.com with SMTP id ffacd0b85a97d-3c380aa1ad0so2194249f8f.3 for ; Mon, 25 Aug 2025 07:27:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1756132027; x=1756736827; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=kzzrp9eAHi9yGAEdwpG/XTAQ7mJqh8kLZKSZyAhHltg=; b=kCvU29sPAN5TDjJMN1Hu4LwPJrwRLcEKYkNVH9z5h1sscfdyU2Qxpts7lFkk4xU+zl l+HG8oyZvrZfsidGHUJBeZIywbEid7e2soNJL12CAky3KHlm6sn4kja9xpDwDKm3ejBS jGi7t3MlsaOdelshsNuRk+FeJzCPIJPXAcGslIK1GbjLUi8yg7UqZ06X87xsaIRg1YfL ZrhUokDP1nbj6zCxS1B4wy2PChqw6IQKC5ObWUsQfmSI4HjwGo8Cr34cb3v530T/L6no aIeGcQT2gFVTnv1pejslACOwl/jw3EC/psA5qN0ybN0f6GpZYxeBUxezYwHQkTEP3vmQ OT6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756132027; x=1756736827; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kzzrp9eAHi9yGAEdwpG/XTAQ7mJqh8kLZKSZyAhHltg=; b=KCPKRVJl0vkA4gto/Ym5CwLHOPuXQI/jpJskn/E4HxbQNUaMl7+Zo5mau8yeurzGmq Yowiv/a4/AW33d+7B4678YOo10cRU/bgQk6Bnx5YuZO5V+Beq8U2A96a10hvKL+tyk5z P/sF+W9BrPcE8wQ7Pj6RQDm8B2GUiQGxcWr04Gfs9p5Uj+O3jo9prtEcJis208fo0tkZ gkudWS12+8yrnGekFCm0Q5fEodllFdkf47LR8fjJdl5jdfHFdwQUmvrVaeDwAHdLG0kZ O3hkDDgclWWhxIPTnP2Wu/MrO28hWwqR143McgmxhOYDPbDmrZI2YYuK/NExLZYG3bnU GtZw== X-Forwarded-Encrypted: i=1; AJvYcCVnS4G2assZEFBWUp0s2VEt8+CUQlgdvjps3zwTtTrjl591TB/+BadWhfJwWZ0HKga8+KXEGQzjlQ+XogE=@vger.kernel.org X-Gm-Message-State: AOJu0YwpaMpqK81WHni0bbCly9FQ74dLTDbl3xnNY30Cmp/bRPc//rD5 FdqGYG5vMKWWhoysisHQDf56NKSIOrYnG6TE1J6ZFeTWhuSdO+xrUpu0W5ysmpyMfEQ3SzwjWoB +o5SV X-Gm-Gg: ASbGncuWXJCPKNsmvhBwSojZ+nfUFDMmJYm+J2C62MHtAbSJm2aGZEBDNPb0RY8mj2C oVtWt1HgtJckdH9hL1fRg2PX3M3wHj08Mjx0bq5qfLBQK6opJyBGp6nn1T3akPY/uHAyBHPD8TJ EEnimn0n6R7/nuQxYys9fdpGoYXo40jcG3TNhBsHxU+QhRj4ttT37C0QbyNKP75/w1dRIwm32o6 IYirZ7X2i7qveGrZfjVy7fkiuTHGf/3TYesyhv/XLlb9JD6gcxzYI9LuOo9tFt6QFm9CNm3FEeM SzO+Bct1tS8uyuW5CiWZmjQrVin9Qy+C/kBttXmjEOmJ+NMESnJzaCTNMS5UhDSZ6b0Rpb2/Z+7 KZloBwSUTh4pCbr1FoIFE2yCiwNNw3H5i8WWJ X-Google-Smtp-Source: AGHT+IEXVdyh48H8oH0/xUTvKXSChcH9i9wf/zeGtDmNyTYV1hOK38cVudoH4thFOwcevE2sV19FMA== X-Received: by 2002:a5d:5f81:0:b0:3b8:f2f2:e417 with SMTP id ffacd0b85a97d-3c5dcdfc643mr9512373f8f.51.1756132026883; Mon, 25 Aug 2025 07:27:06 -0700 (PDT) Received: from toaster.baylibre.com ([2a01:e0a:3c5:5fb1:b261:baab:ed3d:3cb6]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3c70e4b9e1fsm12634462f8f.14.2025.08.25.07.27.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Aug 2025 07:27:06 -0700 (PDT) From: Jerome Brunet Date: Mon, 25 Aug 2025 16:26:26 +0200 Subject: [PATCH v2 01/12] clk: amlogic: drop meson-clkcee Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-meson-clk-cleanup-24-v2-1-0f402f01e117@baylibre.com> References: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> In-Reply-To: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=14449; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=wIEIXo0GxVU4ywzJB/g6XZYic4UF9s5rP6rG75651IM=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBorHKuPU1yavCa12WCaKa7rXOwVuzm2LqDkuG9T AdoZYbNdvSJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaKxyrgAKCRDm/A8cN/La hQFfD/4/X5co3XCJrSHU/q3oQiOYDRDcRyCDwxFGgtqBezb/7/8BhAqnkJgpuu4F+d9buKMdOA2 7ZQQ4rMMp12y8/zchEsdh+ZKFUVD5DGEU3aRgsmaob45eeqGoZwqlBBu+2UmIAzujMuaTp/dHOZ mdLyjClhSeCly6hLlzh8jWcFMB3aP2QaEOsPHKjBMb+/6e7NDjjZ6453Mi87Qh9Ei0xmq8w9YM9 qy3Tk+H8FcnLLvjy9feu4D3E/Z7/Un4Kzx3I0hBrgIyReyVqCRZnJHShVVTDRavT/O1l6Tbk9CR 0mpYBAR+wyMW9v3kUplPkl0ZX8CX2cYOZCWLN7O4/TQ179fAXT9T9GxbFXlvy3jv1yC3QET+xkx bl5iv2cX4nNQDc4jF4S0pHW1j37Ssf5sua7ItVKDbzT01C7AxolCQzqDXHI5Pr6x6WEyguMOBXZ YTw7SZRD6ruLY6K8/sA5pUT98HhA5U2KolM9AMKzwaf4nRHu4keIGmkjkL0HzaaPxvBPbrK9fIs Gl7/TX8mqg8W9+60V/N+F9uP3uS4wbMzmTfBF/sE9ZZkEv9PkRzZK0QAcSbEeJgWbwpBpaaMrJ1 w1EwsgkznSEhQZ8uQvjNCldY/QBcfXHhJ11qAa2N2OQDjYP9wKcdaDfzinBMRkDyrKFylNw2Hmn HervvwEJ8PMD/Rg== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 What is being done by the Amlogic clock controller registration helper for EE controllers could benefit other controllers. As such, having a specific module for this makes little sense. Move the helper function to clkc-utils and rename it to describe what it does, registering syscon based controller, instead of what it serves. Signed-off-by: Jerome Brunet --- drivers/clk/meson/Kconfig | 13 +++----- drivers/clk/meson/Makefile | 1 - drivers/clk/meson/axg.c | 6 ++-- drivers/clk/meson/g12a.c | 28 ++++++++--------- drivers/clk/meson/gxbb.c | 8 ++--- drivers/clk/meson/meson-clkc-utils.c | 50 +++++++++++++++++++++++++++++- drivers/clk/meson/meson-clkc-utils.h | 10 ++++++ drivers/clk/meson/meson-eeclk.c | 60 --------------------------------= ---- drivers/clk/meson/meson-eeclk.h | 24 --------------- 9 files changed, 85 insertions(+), 115 deletions(-) diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig index 7197d23543b8bb8a9020cde316170b50bc359a6c..71481607a6d55d14898f9ecca68= f004ccc6f6231 100644 --- a/drivers/clk/meson/Kconfig +++ b/drivers/clk/meson/Kconfig @@ -36,6 +36,8 @@ config COMMON_CLK_MESON_VCLK select COMMON_CLK_MESON_REGMAP =20 config COMMON_CLK_MESON_CLKC_UTILS + select REGMAP + select MFD_SYSCON tristate =20 config COMMON_CLK_MESON_AO_CLKC @@ -44,11 +46,6 @@ config COMMON_CLK_MESON_AO_CLKC select COMMON_CLK_MESON_CLKC_UTILS select RESET_CONTROLLER =20 -config COMMON_CLK_MESON_EE_CLKC - tristate - select COMMON_CLK_MESON_REGMAP - select COMMON_CLK_MESON_CLKC_UTILS - config COMMON_CLK_MESON_CPU_DYNDIV tristate select COMMON_CLK_MESON_REGMAP @@ -73,12 +70,12 @@ config COMMON_CLK_GXBB depends on ARM64 default ARCH_MESON select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_CLKC_UTILS select COMMON_CLK_MESON_DUALDIV select COMMON_CLK_MESON_VID_PLL_DIV select COMMON_CLK_MESON_MPLL select COMMON_CLK_MESON_PLL select COMMON_CLK_MESON_AO_CLKC - select COMMON_CLK_MESON_EE_CLKC select MFD_SYSCON help Support for the clock controller on AmLogic S905 devices, aka gxbb. @@ -89,11 +86,11 @@ config COMMON_CLK_AXG depends on ARM64 default ARCH_MESON select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_CLKC_UTILS select COMMON_CLK_MESON_DUALDIV select COMMON_CLK_MESON_MPLL select COMMON_CLK_MESON_PLL select COMMON_CLK_MESON_AO_CLKC - select COMMON_CLK_MESON_EE_CLKC select MFD_SYSCON help Support for the clock controller on AmLogic A113D devices, aka axg. @@ -167,11 +164,11 @@ config COMMON_CLK_G12A depends on ARM64 default ARCH_MESON select COMMON_CLK_MESON_REGMAP + select COMMON_CLK_MESON_CLKC_UTILS select COMMON_CLK_MESON_DUALDIV select COMMON_CLK_MESON_MPLL select COMMON_CLK_MESON_PLL select COMMON_CLK_MESON_AO_CLKC - select COMMON_CLK_MESON_EE_CLKC select COMMON_CLK_MESON_CPU_DYNDIV select COMMON_CLK_MESON_VID_PLL_DIV select COMMON_CLK_MESON_VCLK diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile index bc56a47931c1d27db7dde72b73d9842c93e74f62..c6998e752c683ec9d1736a6811b= 1cfd71559b289 100644 --- a/drivers/clk/meson/Makefile +++ b/drivers/clk/meson/Makefile @@ -5,7 +5,6 @@ obj-$(CONFIG_COMMON_CLK_MESON_CLKC_UTILS) +=3D meson-clkc-u= tils.o obj-$(CONFIG_COMMON_CLK_MESON_AO_CLKC) +=3D meson-aoclk.o obj-$(CONFIG_COMMON_CLK_MESON_CPU_DYNDIV) +=3D clk-cpu-dyndiv.o obj-$(CONFIG_COMMON_CLK_MESON_DUALDIV) +=3D clk-dualdiv.o -obj-$(CONFIG_COMMON_CLK_MESON_EE_CLKC) +=3D meson-eeclk.o obj-$(CONFIG_COMMON_CLK_MESON_MPLL) +=3D clk-mpll.o obj-$(CONFIG_COMMON_CLK_MESON_PHASE) +=3D clk-phase.o obj-$(CONFIG_COMMON_CLK_MESON_PLL) +=3D clk-pll.o diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 7273178d33f788a989297d7c6fdb5b033630887c..021bc7658f7f49911835abd22ba= dac3eba64a10c 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -18,7 +18,7 @@ #include "clk-regmap.h" #include "clk-pll.h" #include "clk-mpll.h" -#include "meson-eeclk.h" +#include "meson-clkc-utils.h" =20 #include =20 @@ -2110,7 +2110,7 @@ static struct clk_hw *axg_hw_clks[] =3D { [CLKID_VDIN_MEAS] =3D &axg_vdin_meas.hw, }; =20 -static const struct meson_eeclkc_data axg_clkc_data =3D { +static const struct meson_clkc_data axg_clkc_data =3D { .hw_clks =3D { .hws =3D axg_hw_clks, .num =3D ARRAY_SIZE(axg_hw_clks), @@ -2124,7 +2124,7 @@ static const struct of_device_id axg_clkc_match_table= [] =3D { MODULE_DEVICE_TABLE(of, axg_clkc_match_table); =20 static struct platform_driver axg_clkc_driver =3D { - .probe =3D meson_eeclkc_probe, + .probe =3D meson_clkc_syscon_probe, .driver =3D { .name =3D "axg-clkc", .of_match_table =3D axg_clkc_match_table, diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index 7e2c0ce91964963ae5eb90a5125e5f04e40bc11f..c06a4b678b277e8789a33328e25= f0c615b3f1b9d 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -23,7 +23,7 @@ #include "clk-cpu-dyndiv.h" #include "vid-pll-div.h" #include "vclk.h" -#include "meson-eeclk.h" +#include "meson-clkc-utils.h" =20 #include =20 @@ -5360,26 +5360,26 @@ static int g12a_dvfs_setup(struct platform_device *= pdev) } =20 struct g12a_clkc_data { - const struct meson_eeclkc_data eeclkc_data; + const struct meson_clkc_data clkc_data; int (*dvfs_setup)(struct platform_device *pdev); }; =20 static int g12a_clkc_probe(struct platform_device *pdev) { - const struct meson_eeclkc_data *eeclkc_data; + const struct meson_clkc_data *clkc_data; const struct g12a_clkc_data *g12a_data; int ret; =20 - eeclkc_data =3D of_device_get_match_data(&pdev->dev); - if (!eeclkc_data) + clkc_data =3D of_device_get_match_data(&pdev->dev); + if (!clkc_data) return -EINVAL; =20 - ret =3D meson_eeclkc_probe(pdev); + ret =3D meson_clkc_syscon_probe(pdev); if (ret) return ret; =20 - g12a_data =3D container_of(eeclkc_data, struct g12a_clkc_data, - eeclkc_data); + g12a_data =3D container_of(clkc_data, struct g12a_clkc_data, + clkc_data); =20 if (g12a_data->dvfs_setup) return g12a_data->dvfs_setup(pdev); @@ -5388,7 +5388,7 @@ static int g12a_clkc_probe(struct platform_device *pd= ev) } =20 static const struct g12a_clkc_data g12a_clkc_data =3D { - .eeclkc_data =3D { + .clkc_data =3D { .hw_clks =3D { .hws =3D g12a_hw_clks, .num =3D ARRAY_SIZE(g12a_hw_clks), @@ -5400,7 +5400,7 @@ static const struct g12a_clkc_data g12a_clkc_data =3D= { }; =20 static const struct g12a_clkc_data g12b_clkc_data =3D { - .eeclkc_data =3D { + .clkc_data =3D { .hw_clks =3D { .hws =3D g12b_hw_clks, .num =3D ARRAY_SIZE(g12b_hw_clks), @@ -5410,7 +5410,7 @@ static const struct g12a_clkc_data g12b_clkc_data =3D= { }; =20 static const struct g12a_clkc_data sm1_clkc_data =3D { - .eeclkc_data =3D { + .clkc_data =3D { .hw_clks =3D { .hws =3D sm1_hw_clks, .num =3D ARRAY_SIZE(sm1_hw_clks), @@ -5422,15 +5422,15 @@ static const struct g12a_clkc_data sm1_clkc_data = =3D { static const struct of_device_id g12a_clkc_match_table[] =3D { { .compatible =3D "amlogic,g12a-clkc", - .data =3D &g12a_clkc_data.eeclkc_data + .data =3D &g12a_clkc_data.clkc_data }, { .compatible =3D "amlogic,g12b-clkc", - .data =3D &g12b_clkc_data.eeclkc_data + .data =3D &g12b_clkc_data.clkc_data }, { .compatible =3D "amlogic,sm1-clkc", - .data =3D &sm1_clkc_data.eeclkc_data + .data =3D &sm1_clkc_data.clkc_data }, {} }; diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 2ad29c7cd6cf04d3e65b25cd96f587d5156759e8..608c2cd34a455f48087dd65809d= bcda54f153a71 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -13,7 +13,7 @@ #include "clk-regmap.h" #include "clk-pll.h" #include "clk-mpll.h" -#include "meson-eeclk.h" +#include "meson-clkc-utils.h" #include "vid-pll-div.h" =20 #include @@ -3234,14 +3234,14 @@ static struct clk_hw *gxl_hw_clks[] =3D { [CLKID_ACODEC] =3D &gxl_acodec.hw, }; =20 -static const struct meson_eeclkc_data gxbb_clkc_data =3D { +static const struct meson_clkc_data gxbb_clkc_data =3D { .hw_clks =3D { .hws =3D gxbb_hw_clks, .num =3D ARRAY_SIZE(gxbb_hw_clks), }, }; =20 -static const struct meson_eeclkc_data gxl_clkc_data =3D { +static const struct meson_clkc_data gxl_clkc_data =3D { .hw_clks =3D { .hws =3D gxl_hw_clks, .num =3D ARRAY_SIZE(gxl_hw_clks), @@ -3256,7 +3256,7 @@ static const struct of_device_id gxbb_clkc_match_tabl= e[] =3D { MODULE_DEVICE_TABLE(of, gxbb_clkc_match_table); =20 static struct platform_driver gxbb_clkc_driver =3D { - .probe =3D meson_eeclkc_probe, + .probe =3D meson_clkc_syscon_probe, .driver =3D { .name =3D "gxbb-clkc", .of_match_table =3D gxbb_clkc_match_table, diff --git a/drivers/clk/meson/meson-clkc-utils.c b/drivers/clk/meson/meson= -clkc-utils.c index 6937d1482719bda00da127381025a165907e5db6..49f562d0f203b9a7d15b5119100= 216564c10cb21 100644 --- a/drivers/clk/meson/meson-clkc-utils.c +++ b/drivers/clk/meson/meson-clkc-utils.c @@ -3,9 +3,13 @@ * Copyright (c) 2023 Neil Armstrong */ =20 -#include #include +#include #include +#include +#include +#include + #include "meson-clkc-utils.h" =20 struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk= _hw_data) @@ -22,6 +26,50 @@ struct clk_hw *meson_clk_hw_get(struct of_phandle_args *= clkspec, void *clk_hw_da } EXPORT_SYMBOL_NS_GPL(meson_clk_hw_get, "CLK_MESON"); =20 +int meson_clkc_syscon_probe(struct platform_device *pdev) +{ + const struct meson_clkc_data *data; + struct device *dev =3D &pdev->dev; + struct device_node *np; + struct regmap *map; + struct clk_hw *hw; + int ret, i; + + data =3D of_device_get_match_data(dev); + if (!data) + return -EINVAL; + + np =3D of_get_parent(dev->of_node); + map =3D syscon_node_to_regmap(np); + of_node_put(np); + if (IS_ERR(map)) { + dev_err(dev, + "failed to get parent syscon regmap\n"); + return PTR_ERR(map); + } + + if (data->init_count) + regmap_multi_reg_write(map, data->init_regs, data->init_count); + + for (i =3D 0; i < data->hw_clks.num; i++) { + hw =3D data->hw_clks.hws[i]; + + /* array might be sparse */ + if (!hw) + continue; + + ret =3D devm_clk_hw_register(dev, hw); + if (ret) { + dev_err(dev, "registering %s clock failed\n", + hw->init->name); + return ret; + } + } + + return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->= hw_clks); +} +EXPORT_SYMBOL_NS_GPL(meson_clkc_syscon_probe, "CLK_MESON"); + MODULE_DESCRIPTION("Amlogic Clock Controller Utilities"); MODULE_LICENSE("GPL"); MODULE_IMPORT_NS("CLK_MESON"); diff --git a/drivers/clk/meson/meson-clkc-utils.h b/drivers/clk/meson/meson= -clkc-utils.h index fe6f407289496c5c4821b7c9e5a6b6e8a45068b2..26cd47544302b28ca1a342e1789= 56559a84b152a 100644 --- a/drivers/clk/meson/meson-clkc-utils.h +++ b/drivers/clk/meson/meson-clkc-utils.h @@ -9,6 +9,8 @@ #include #include =20 +struct platform_device; + struct meson_clk_hw_data { struct clk_hw **hws; unsigned int num; @@ -16,4 +18,12 @@ struct meson_clk_hw_data { =20 struct clk_hw *meson_clk_hw_get(struct of_phandle_args *clkspec, void *clk= _hw_data); =20 +struct meson_clkc_data { + const struct reg_sequence *init_regs; + unsigned int init_count; + struct meson_clk_hw_data hw_clks; +}; + +int meson_clkc_syscon_probe(struct platform_device *pdev); + #endif diff --git a/drivers/clk/meson/meson-eeclk.c b/drivers/clk/meson/meson-eecl= k.c deleted file mode 100644 index 6236bf970d79e85b1e739c713c03f35a00c291b9..000000000000000000000000000= 0000000000000 --- a/drivers/clk/meson/meson-eeclk.c +++ /dev/null @@ -1,60 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (c) 2019 BayLibre, SAS. - * Author: Jerome Brunet - */ - -#include -#include -#include -#include -#include -#include - -#include "clk-regmap.h" -#include "meson-eeclk.h" - -int meson_eeclkc_probe(struct platform_device *pdev) -{ - const struct meson_eeclkc_data *data; - struct device *dev =3D &pdev->dev; - struct device_node *np; - struct regmap *map; - int ret, i; - - data =3D of_device_get_match_data(dev); - if (!data) - return -EINVAL; - - /* Get the hhi system controller node */ - np =3D of_get_parent(dev->of_node); - map =3D syscon_node_to_regmap(np); - of_node_put(np); - if (IS_ERR(map)) { - dev_err(dev, - "failed to get HHI regmap\n"); - return PTR_ERR(map); - } - - if (data->init_count) - regmap_multi_reg_write(map, data->init_regs, data->init_count); - - for (i =3D 0; i < data->hw_clks.num; i++) { - /* array might be sparse */ - if (!data->hw_clks.hws[i]) - continue; - - ret =3D devm_clk_hw_register(dev, data->hw_clks.hws[i]); - if (ret) { - dev_err(dev, "Clock registration failed\n"); - return ret; - } - } - - return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->= hw_clks); -} -EXPORT_SYMBOL_NS_GPL(meson_eeclkc_probe, "CLK_MESON"); - -MODULE_DESCRIPTION("Amlogic Main Clock Controller Helpers"); -MODULE_LICENSE("GPL"); -MODULE_IMPORT_NS("CLK_MESON"); diff --git a/drivers/clk/meson/meson-eeclk.h b/drivers/clk/meson/meson-eecl= k.h deleted file mode 100644 index 6a81d67b46b2270315e24eb58042de8c09b37763..000000000000000000000000000= 0000000000000 --- a/drivers/clk/meson/meson-eeclk.h +++ /dev/null @@ -1,24 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) 2019 BayLibre, SAS. - * Author: Jerome Brunet - */ - -#ifndef __MESON_CLKC_H -#define __MESON_CLKC_H - -#include -#include "clk-regmap.h" -#include "meson-clkc-utils.h" - -struct platform_device; - -struct meson_eeclkc_data { - const struct reg_sequence *init_regs; - unsigned int init_count; - struct meson_clk_hw_data hw_clks; -}; - -int meson_eeclkc_probe(struct platform_device *pdev); - -#endif /* __MESON_CLKC_H */ --=20 2.47.2 From nobody Fri Oct 3 20:30:33 2025 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AAFFA302756 for ; Mon, 25 Aug 2025 14:27:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132033; cv=none; b=QKHKaqqi5F8iybR1xDcto5D74V8V22H1beVGmRgEqM7i/fKFpB905cEVzZQRaxlLBqXn+20/CNFOLbuSyv5M17UajlydPAxLkUnNtc26jBV88oTL43LO/RjwB5kKeizNfX4q6GUQY4FvRZxQ/dGGalv4p78kOBH9kEFMgGeTL9E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132033; c=relaxed/simple; bh=+HNEh7kwqO29/XBYa7Ua9Z9/DByHKmxsSbqdzoDcKd4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NC2x5BtMasuS2cGLKelqXtPCZDw6ZmxuC6CkXGwaMPI+8Z12eDf8cktzX07Y6LwPqrod59aYZfd1lDloCfwawGgA13nZANvg0s1Uq+6DhqOB/YRZS+mV80yCKeX+YRobszLnYXPUmU/8eBe2hflmdiZbwP5C3L8B/UkMeCOgFTs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=bKhikXIV; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="bKhikXIV" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-45a1b05a59fso35462015e9.1 for ; Mon, 25 Aug 2025 07:27:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1756132028; x=1756736828; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=3E0OX3l7hSZpbmIvG6p8r2X61gE3s0wO+uAxqyQVEXs=; b=bKhikXIVB329pJUWytfkQQXQfY3QvN5kQiBsB/5HfI65+b1hHr6gE/lLSBgh53GTiT Xy/q+7hjx4qrPcBVfTcpoLU68UvouWle6s1BWA99Jp310gjzCM/UQoqEUFzzKlRXmyLD pMdX8dOgEVNKImLEp3NlVzXyzLLKSobMdIfN3vJ43srkTbQhvLoatUCRtYpeYhAO8R2T 00Y5mp3LV/jZMJ9dVw4CWBIvT4Is1P36pIw/7u2jcyffsYvfGjoYiiOvCnW5cFf18pfl SgVOyLuuqxuJfMIX2MYVoK4z494QOlE6EHKr5eEdgJXiFLp86J3MhbyGvCmzlEv+hkC6 HosQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756132028; x=1756736828; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3E0OX3l7hSZpbmIvG6p8r2X61gE3s0wO+uAxqyQVEXs=; b=YnsPOfrkhkWnhqf+GdmkNIZseIyujFhcOu0M5zv1LbmRmKAqLYrmRoWxSMrQZ6scS+ V/BGjUAFMmdLQzJLccyp/0zLtpJFQmADWe3xvdJMl7el2dvXjMEGdmvVbwXevKXXAwmy vKmLuJZc/6H0sFIWtUw2WJp+BzvSuSgpLhqn9nvOuD/ZpXUP0muUg2W+DXEsywFd8slz iGkyh+qWOgqCMzGMK8vBZ+5UeXpwv5kp+XOg0lnSIYOHx/3fDpg75FZ7NISk1JbgPC2R Nw98sbxBaMZBJjGbdjC9fGZ1wswiggmA2dIszE/+EHCZQu6p12j/vyOR9Z4ZpEkuDg98 loaw== X-Forwarded-Encrypted: i=1; AJvYcCXk7fuAaDrhpwKfgrHdm4vLl1Ir5fd86zrhdGQxA1ZViUgz1nzwIwElQDvDokS5rgPPGIu4C7H3fnS+88w=@vger.kernel.org X-Gm-Message-State: AOJu0YxSIYQxSwGGg60LUD20E1SrbAEcTlSBQFTpehFvf1o6C/08iDuF M/ioQ36a395RrViRuFAuH9g7r1OkGtMQ/qGKDr77TSzJtbKSn9JMJp/cv4ysWSnQap0= X-Gm-Gg: ASbGncv5KLnYjR02UHCTUTyy92vSBQrrK79F41xCnkYCrqS5wr5M55daKCDr9y6sPLL RHpdmTiMFa3LQSUs5wiiqiC7tF+lf0FJN9uZTua6PPXQRpxpyp87G9OqD9JQkLadUYH88PV0K7J bA+O4qY2IyvVp/zz8ounEd0pBNk+cZfwUjobm3OB4j1abz8bnp5tHmghEBvpGKW08TFVCoRV/oZ zjG0MZU0cUPI+X7bCNerjDidf5E7jSsn5I/HLnPD15G3UsJDO4Ac8hHEAuninPyDBMFuOcMO6Ke DLEmAmYcG9dtOUh8809Xu8FbBlwcoXQdE8zc0fOBNaBkF8rr0wm+gAhurTOu6TF/K2iuEb65n+w dVmFKuaeoPu2gZNCLj1jd1md9AqdfVuC5gUAO X-Google-Smtp-Source: AGHT+IG97/qISA8MqcZl/mFg7nS0dUGfrxzbGW4TGxFceOnmVdStCa+f8SnHWO66tjzhKARbGRvgHg== X-Received: by 2002:a05:600c:3b2a:b0:453:2066:4a26 with SMTP id 5b1f17b1804b1-45b5179f3d1mr151618155e9.16.1756132027543; Mon, 25 Aug 2025 07:27:07 -0700 (PDT) Received: from toaster.baylibre.com ([2a01:e0a:3c5:5fb1:b261:baab:ed3d:3cb6]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3c70e4b9e1fsm12634462f8f.14.2025.08.25.07.27.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Aug 2025 07:27:07 -0700 (PDT) From: Jerome Brunet Date: Mon, 25 Aug 2025 16:26:27 +0200 Subject: [PATCH v2 02/12] clk: amlogic: add probe helper for mmio based controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-meson-clk-cleanup-24-v2-2-0f402f01e117@baylibre.com> References: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> In-Reply-To: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3563; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=+HNEh7kwqO29/XBYa7Ua9Z9/DByHKmxsSbqdzoDcKd4=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBorHKvxaowyPgU9EztKNOZEz2aQx91OrxuPgs8m 8sKoQw4BwGJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaKxyrwAKCRDm/A8cN/La hVQXD/0aAjUtx5KRzTTrPI2utKSOITXpjIpBAvWOFFJyhdNjV05yalKeYTT73MxL9ZEsqMnajIw 66jChhvqaYDcHddLUwTzMsX+EOJd/rhwUgqlIYEVXlGwmzg8dEQcp/qwJS1ECewk0Kta4JoYH+z OuD1oz4bbhp4xJLOSckzAKW43qHjy/5yjl7RjjVo5E29EmcE5mnRs9TKaN9K8f7/3SmDmyHMQfs 2DDziIS0L6j3BsURuw/oplHoooSN7de9FN5MgPQprrKdLvSxj6DKVMGYW5bUZOgXCAwXFkCRPyO 1qtBA5VYOXA6UfvPxHCu5t/r7rFYBj4Wr+GwEe5x7MODMm5ExB4daArLYtuD3d91rQPdyfk+IG3 yKIynnIKuC2W5CwvRJu/sfWruBp9yMhyV247opoYmx9vnqrmwBxB8ZyumqxcMarcmuEm5kdCXgI ORY2mdkUfYE2JgN1jDDzvzIg5rBrmITtlmAYpO6Jdsc2ixMYYsPKIjXTVHLhPxoXQdFm8kevemX 4foheR30XhsMspEdnJgRnoh82yVeVG+/fPUpFqqp4NTg+kTPGGvdY+QedZWsrzwfndqOE+EB2e/ IMlMcWjAKop3gFKJpRO4RIaKkm8sTCXYql/1QQ9DUB/im7pDrh3QPOWj3Y5zPeKZcFzYIIcH2rw 4zBO2MbxH7HjyhQ== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Add a 2nd probe function helper for mmio based controllers, which are getting the memory region from a resource instead of a syscon. Signed-off-by: Jerome Brunet --- drivers/clk/meson/meson-clkc-utils.c | 62 ++++++++++++++++++++++++++++----= ---- drivers/clk/meson/meson-clkc-utils.h | 1 + 2 files changed, 50 insertions(+), 13 deletions(-) diff --git a/drivers/clk/meson/meson-clkc-utils.c b/drivers/clk/meson/meson= -clkc-utils.c index 49f562d0f203b9a7d15b5119100216564c10cb21..870f50548e26841130dd4267f5a= 79c8bcd188c70 100644 --- a/drivers/clk/meson/meson-clkc-utils.c +++ b/drivers/clk/meson/meson-clkc-utils.c @@ -26,12 +26,9 @@ struct clk_hw *meson_clk_hw_get(struct of_phandle_args *= clkspec, void *clk_hw_da } EXPORT_SYMBOL_NS_GPL(meson_clk_hw_get, "CLK_MESON"); =20 -int meson_clkc_syscon_probe(struct platform_device *pdev) +static int meson_clkc_init(struct device *dev, struct regmap *map) { const struct meson_clkc_data *data; - struct device *dev =3D &pdev->dev; - struct device_node *np; - struct regmap *map; struct clk_hw *hw; int ret, i; =20 @@ -39,15 +36,6 @@ int meson_clkc_syscon_probe(struct platform_device *pdev) if (!data) return -EINVAL; =20 - np =3D of_get_parent(dev->of_node); - map =3D syscon_node_to_regmap(np); - of_node_put(np); - if (IS_ERR(map)) { - dev_err(dev, - "failed to get parent syscon regmap\n"); - return PTR_ERR(map); - } - if (data->init_count) regmap_multi_reg_write(map, data->init_regs, data->init_count); =20 @@ -68,8 +56,56 @@ int meson_clkc_syscon_probe(struct platform_device *pdev) =20 return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->= hw_clks); } + +int meson_clkc_syscon_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct device_node *np; + struct regmap *map; + + np =3D of_get_parent(dev->of_node); + map =3D syscon_node_to_regmap(np); + of_node_put(np); + if (IS_ERR(map)) { + dev_err(dev, "failed to get parent syscon regmap\n"); + return PTR_ERR(map); + } + + return meson_clkc_init(dev, map); +} EXPORT_SYMBOL_NS_GPL(meson_clkc_syscon_probe, "CLK_MESON"); =20 +int meson_clkc_mmio_probe(struct platform_device *pdev) +{ + const struct meson_clkc_data *data; + struct device *dev =3D &pdev->dev; + struct resource *res; + void __iomem *base; + struct regmap *map; + struct regmap_config regmap_cfg =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + }; + + data =3D of_device_get_match_data(dev); + if (!data) + return -EINVAL; + + base =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(base)) + return PTR_ERR(base); + + regmap_cfg.max_register =3D resource_size(res) - regmap_cfg.reg_stride; + + map =3D devm_regmap_init_mmio(dev, base, ®map_cfg); + if (IS_ERR(map)) + return PTR_ERR(map); + + return meson_clkc_init(dev, map); +} +EXPORT_SYMBOL_NS_GPL(meson_clkc_mmio_probe, "CLK_MESON"); + MODULE_DESCRIPTION("Amlogic Clock Controller Utilities"); MODULE_LICENSE("GPL"); MODULE_IMPORT_NS("CLK_MESON"); diff --git a/drivers/clk/meson/meson-clkc-utils.h b/drivers/clk/meson/meson= -clkc-utils.h index 26cd47544302b28ca1a342e178956559a84b152a..b45f85f630d7190fb6509b088f0= 5f17ca91fa1c8 100644 --- a/drivers/clk/meson/meson-clkc-utils.h +++ b/drivers/clk/meson/meson-clkc-utils.h @@ -25,5 +25,6 @@ struct meson_clkc_data { }; =20 int meson_clkc_syscon_probe(struct platform_device *pdev); +int meson_clkc_mmio_probe(struct platform_device *pdev); =20 #endif --=20 2.47.2 From nobody Fri Oct 3 20:30:33 2025 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2C632FC891 for ; Mon, 25 Aug 2025 14:27:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132034; cv=none; b=LLLJusDrgFdaV/QrS6tHgQWTHjaAWgJeZZY5aZLdPB5/eggR8BD+Do14OsSl1lk4SE8+LFfeSIB0oYIkiPliHbFLOmZ49Hx2TOqfGBjq1H6o0+TDZkKcAIuSsEyI70M8zLrYKJuoodMcKzm7S1Xkm6vyC/dYMbklebChUI8OGUE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132034; c=relaxed/simple; bh=mV4e9A5hAMuH50dPvN6Eogw/db6BsyrhlDBBLhpRuDk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=r05qH+478CfrA/unKcuXwunyb69OrUT88kQ/rKRb3KufJ0NHiKvZY2RhrqtPGoi/tQuI/uzNdETNrVWb18KIGPM5g3EoQb51F4wVKc7xJeTSFLJ/pTHIrERx9Us38mgbcRWedHNg84iT9s5i37vpC6YPaU04zstCdEsn8z9qLy4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=MI9Ro0pr; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="MI9Ro0pr" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-45b60fd5a1dso8308465e9.2 for ; Mon, 25 Aug 2025 07:27:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1756132028; x=1756736828; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=DIJEmsB/8rs8xNSH4XrNmepRzdvgwCQLygjTeJuMmaQ=; b=MI9Ro0prNH5juf+T6iLRAWBSWIFA6JPYMP//vYm0lf4cZxNly7zlD79xX+2tiZOTQL XFJ+wntdcCMtJeWQ7KCt8Gk8/ZiJHXyhzf4GIIR9NXRbPN0gZbuGkC1cC1Z0DoyM9UgC 9UsnkUov4IOqD1XaEUifh00ZIirz06UhvsRvOBPIXVTs0FCyUR7MFZjzo7Y6B5acaYuH thmWbGMJtxqpm3EJTnqqVLNfoviOQ7YK3VJc0au+xDr3hBQMw/ItORB9nTPIF+zGu9dH 7USBOd2Z1tCPWQOWhP8ndqkzkd8thdMqiSTGmKU+O1/Rj9wRf/TaytRQ8hVSVByd3GCV 1vRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756132028; x=1756736828; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DIJEmsB/8rs8xNSH4XrNmepRzdvgwCQLygjTeJuMmaQ=; b=VkivRIzE7U3c+cRrBiowoxA0kk5wovRpqM1gjG/WjDcmM5lq1zHasxSp5JldMwNLK2 SFvk00ocpzCO7d2S3nONOQos1wdJJYgD2fYlZlnsr4v5dATKeBslTWxvzFxZ/4Riuz+U 2oYJyVjCVOEDDsBYJF9Iqf8vjVtQzi7Hcw1vteDwsahBfDuGft7Y9Kp1Vc6yMjZPeP8X DpseLt8Tc6Mlrbmq+lioSH51S2apoOjzdoNZzUVxAlyMIQZEeYM0xKwp/5HQhbdzDrCg SakxRykyUyZ8/hFU0zaRZ7/pT7zx8iOOlRDplFeyjH8IuLjxVFIxX6OynOcZ43mI66km byWg== X-Forwarded-Encrypted: i=1; AJvYcCWecn6APcXS9g98iqbUrF9tSSvkl8XKtlI8bHQlM8x77j+vUpUYAHpWAS8ICE1LtvleBN9/52/l2d1BVFI=@vger.kernel.org X-Gm-Message-State: AOJu0YyqfYRClMqKiF862VLirIfoXKFs9/oq71xnqiOjdTqbZ4CvZ2nf c9S0aYqC18ob2Cr27ltfRir3Jq6SuCSPQEvOCixcw/zeJhJkrsK2znfAYl9nEzT5GpS8qBQY9hI Q31B7 X-Gm-Gg: ASbGnctFfajrmFcJaRN2zNwr1OOgR4CL8ipvabwz244Eol6OdqglnYrjo8f0cTSL0JQ hoyDHCFZhcpm/er8E09NhN1nS4XjpEE3ve6YQxICsYwM/EpxDyDJlwf38g5KAmthC1wGXF2Qqd+ /AuG3/jA1RGNSA4bgqEmHDC3qpkWxLJbpEJC17EpGm68QsrSGd+atVfQx5xmQluVwOOWrmthBhz wBFuxzFKPqOiYL/dzgI9to7L9NL8rnTYw/NRP92DlKRhE7LLoID848Jx0OutUtAlsS8CjvNlADg PkCRn1lNgA/6UUGEyYJG872VIDfOM924n85em3jh9UcYjENb07sLeAwqNCl1Qhce3jbeRV9Xwbp wSG743uKGo/35PCJnMJRoFvqVgwggiXKoZN0DopoR93xUA5Q= X-Google-Smtp-Source: AGHT+IEXfyq5m2bLUeQjUXFA2zrBYTIxS3J/1xQIovcTnCPbPWUNt6OGW4xg2+q3mV00zpwUEtqa3Q== X-Received: by 2002:a5d:4846:0:b0:3b7:6d95:56d2 with SMTP id ffacd0b85a97d-3c5da7402e3mr6635931f8f.7.1756132028370; Mon, 25 Aug 2025 07:27:08 -0700 (PDT) Received: from toaster.baylibre.com ([2a01:e0a:3c5:5fb1:b261:baab:ed3d:3cb6]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3c70e4b9e1fsm12634462f8f.14.2025.08.25.07.27.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Aug 2025 07:27:07 -0700 (PDT) From: Jerome Brunet Date: Mon, 25 Aug 2025 16:26:28 +0200 Subject: [PATCH v2 03/12] clk: amlogic: use probe helper in mmio based controllers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-meson-clk-cleanup-24-v2-3-0f402f01e117@baylibre.com> References: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> In-Reply-To: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet , Chuan Liu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=16590; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=mV4e9A5hAMuH50dPvN6Eogw/db6BsyrhlDBBLhpRuDk=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBorHKwFTVxum2O6ljQ+WO53Pz7AsJ09Q8raP7e+ 49CuC6SJT2JAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaKxysAAKCRDm/A8cN/La hU52D/47UTicmhVW7zkjB77rRCoL61Jnysns+K3Yf7zEjypTy4ajihwF3zobtWrskG0mj/i+/Yx U1qBg24vC0hV+hRO1OPaHCWLon7JJ0ej5tUBRXJ9kA37cg2ciBnBs0NpFxp95HcV6ETEJiB9kz3 M00zQ82Q4Iw2ltRXFmC6ykM0mXP0unSo613Dt6/MadcJqcBu3YaqgW5f2qiBE+z28E9Dlk6d49Q 9abfgkKCAz8SsOGf01an5M3pUAfNg2hqu1gNsauWbnSB4KTCJR8Uo0quMtcNPMYBpVbmRpABOYS huNi9kqwv69Fmg0objwMAs3JJ6GAbY6VitSNjsmbPREs7yGBbmELWfnPLOtRQ7QE5xZtOMT5Sdg 7z9Dj3f1ZZ34qKeIpTq8SUY4+Bm9/VQ0QM/Whif2vjxPrlNZVsGj59ILJjlijjxOn/ZnT33ljdK cL3JQfY2MUo13UFi01RpgDvHz8RkhxsoqhBa8JuFcB7XKzViLNvv/YfNN8bp0buApY59SjU0u4B QfUwG1r8w0+QVjW9H7ihFjmXcd5vLo2d6+rDzBI9tGQVWthBmdQDMStrrt+tm14dU/21OhvJR+8 SFyFr08Hs38pPayQbGaDsqr3rkL3qHHSl8jnJFE/vhHxfa8Ux8PbplrPpGzG4fvxDC0skdzROOB wDqtK4AQQ06KLwQ== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Factorize the probe function of the mmio based amlogic clock controllers using the newly introduced probe helper. This removes a fair amount of duplicated code. Reviewed-by: Chuan Liu Signed-off-by: Jerome Brunet --- drivers/clk/meson/a1-peripherals.c | 52 +++++++-------------------------- drivers/clk/meson/a1-pll.c | 52 +++++++-------------------------- drivers/clk/meson/c3-peripherals.c | 51 +++++--------------------------- drivers/clk/meson/c3-pll.c | 49 +++++-------------------------- drivers/clk/meson/meson8-ddr.c | 57 +++++++++-------------------------= -- drivers/clk/meson/s4-peripherals.c | 49 +++++-------------------------- drivers/clk/meson/s4-pll.c | 60 +++++++---------------------------= ---- 7 files changed, 66 insertions(+), 304 deletions(-) diff --git a/drivers/clk/meson/a1-peripherals.c b/drivers/clk/meson/a1-peri= pherals.c index 9e352dba54775c22126ee8bf7861ee1d981d6c88..b2feb8fe4775e38a17d8aa9ce9b= 992b3e1fb2bb8 100644 --- a/drivers/clk/meson/a1-peripherals.c +++ b/drivers/clk/meson/a1-peripherals.c @@ -2057,54 +2057,24 @@ static struct clk_hw *a1_peripherals_hw_clks[] =3D { [CLKID_DMC_SEL2] =3D &a1_dmc_sel2.hw, }; =20 -static const struct regmap_config a1_peripherals_regmap_cfg =3D { - .reg_bits =3D 32, - .val_bits =3D 32, - .reg_stride =3D 4, - .max_register =3D DMC_CLK_CTRL, -}; - -static struct meson_clk_hw_data a1_peripherals_clks =3D { - .hws =3D a1_peripherals_hw_clks, - .num =3D ARRAY_SIZE(a1_peripherals_hw_clks), -}; - -static int a1_peripherals_clkc_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - void __iomem *base; - struct regmap *map; - int clkid, err; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return dev_err_probe(dev, PTR_ERR(base), - "can't ioremap resource\n"); - - map =3D devm_regmap_init_mmio(dev, base, &a1_peripherals_regmap_cfg); - if (IS_ERR(map)) - return dev_err_probe(dev, PTR_ERR(map), - "can't init regmap mmio region\n"); - - for (clkid =3D 0; clkid < a1_peripherals_clks.num; clkid++) { - err =3D devm_clk_hw_register(dev, a1_peripherals_clks.hws[clkid]); - if (err) - return dev_err_probe(dev, err, - "clock[%d] registration failed\n", - clkid); - } - - return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &a1_peripherals= _clks); -} +static const struct meson_clkc_data a1_peripherals_clkc_data =3D { + .hw_clks =3D { + .hws =3D a1_peripherals_hw_clks, + .num =3D ARRAY_SIZE(a1_peripherals_hw_clks), + }, +}; =20 static const struct of_device_id a1_peripherals_clkc_match_table[] =3D { - { .compatible =3D "amlogic,a1-peripherals-clkc", }, + { + .compatible =3D "amlogic,a1-peripherals-clkc", + .data =3D &a1_peripherals_clkc_data, + }, {} }; MODULE_DEVICE_TABLE(of, a1_peripherals_clkc_match_table); =20 static struct platform_driver a1_peripherals_clkc_driver =3D { - .probe =3D a1_peripherals_clkc_probe, + .probe =3D meson_clkc_mmio_probe, .driver =3D { .name =3D "a1-peripherals-clkc", .of_match_table =3D a1_peripherals_clkc_match_table, diff --git a/drivers/clk/meson/a1-pll.c b/drivers/clk/meson/a1-pll.c index 79ef4cbe955326ecedceb68cda7f59bb8882b165..1f82e9c7c14ebeae5d43cf2623c= 3ab69427a8504 100644 --- a/drivers/clk/meson/a1-pll.c +++ b/drivers/clk/meson/a1-pll.c @@ -295,56 +295,24 @@ static struct clk_hw *a1_pll_hw_clks[] =3D { [CLKID_HIFI_PLL] =3D &a1_hifi_pll.hw, }; =20 -static const struct regmap_config a1_pll_regmap_cfg =3D { - .reg_bits =3D 32, - .val_bits =3D 32, - .reg_stride =3D 4, - .max_register =3D ANACTRL_HIFIPLL_STS, -}; - -static struct meson_clk_hw_data a1_pll_clks =3D { - .hws =3D a1_pll_hw_clks, - .num =3D ARRAY_SIZE(a1_pll_hw_clks), +static const struct meson_clkc_data a1_pll_clkc_data =3D { + .hw_clks =3D { + .hws =3D a1_pll_hw_clks, + .num =3D ARRAY_SIZE(a1_pll_hw_clks), + }, }; =20 -static int a1_pll_clkc_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - void __iomem *base; - struct regmap *map; - int clkid, err; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return dev_err_probe(dev, PTR_ERR(base), - "can't ioremap resource\n"); - - map =3D devm_regmap_init_mmio(dev, base, &a1_pll_regmap_cfg); - if (IS_ERR(map)) - return dev_err_probe(dev, PTR_ERR(map), - "can't init regmap mmio region\n"); - - /* Register clocks */ - for (clkid =3D 0; clkid < a1_pll_clks.num; clkid++) { - err =3D devm_clk_hw_register(dev, a1_pll_clks.hws[clkid]); - if (err) - return dev_err_probe(dev, err, - "clock[%d] registration failed\n", - clkid); - } - - return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, - &a1_pll_clks); -} - static const struct of_device_id a1_pll_clkc_match_table[] =3D { - { .compatible =3D "amlogic,a1-pll-clkc", }, + { + .compatible =3D "amlogic,a1-pll-clkc", + .data =3D &a1_pll_clkc_data, + }, {} }; MODULE_DEVICE_TABLE(of, a1_pll_clkc_match_table); =20 static struct platform_driver a1_pll_clkc_driver =3D { - .probe =3D a1_pll_clkc_probe, + .probe =3D meson_clkc_mmio_probe, .driver =3D { .name =3D "a1-pll-clkc", .of_match_table =3D a1_pll_clkc_match_table, diff --git a/drivers/clk/meson/c3-peripherals.c b/drivers/clk/meson/c3-peri= pherals.c index a09cb1435ab108b2dcc209c6557bcd1988c4ba1a..e9c1ef99be13d0542b8a972ceff= e69c8a9977118 100644 --- a/drivers/clk/meson/c3-peripherals.c +++ b/drivers/clk/meson/c3-peripherals.c @@ -2091,52 +2091,17 @@ static struct clk_hw *c3_peripherals_hw_clks[] =3D { [CLKID_VAPB] =3D &c3_vapb.hw, }; =20 -static const struct regmap_config c3_peripherals_regmap_cfg =3D { - .reg_bits =3D 32, - .val_bits =3D 32, - .reg_stride =3D 4, - .max_register =3D NNA_CLK_CTRL, -}; - -static struct meson_clk_hw_data c3_peripherals_clks =3D { - .hws =3D c3_peripherals_hw_clks, - .num =3D ARRAY_SIZE(c3_peripherals_hw_clks), -}; - -static int c3_peripherals_clkc_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct regmap *regmap; - void __iomem *base; - int clkid, ret; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - regmap =3D devm_regmap_init_mmio(dev, base, &c3_peripherals_regmap_cfg); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); - - for (clkid =3D 0; clkid < c3_peripherals_clks.num; clkid++) { - /* array might be sparse */ - if (!c3_peripherals_clks.hws[clkid]) - continue; - - ret =3D devm_clk_hw_register(dev, c3_peripherals_clks.hws[clkid]); - if (ret) { - dev_err(dev, "Clock registration failed\n"); - return ret; - } - } - - return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, - &c3_peripherals_clks); -} +static const struct meson_clkc_data c3_peripherals_clkc_data =3D { + .hw_clks =3D { + .hws =3D c3_peripherals_hw_clks, + .num =3D ARRAY_SIZE(c3_peripherals_hw_clks), + }, +}; =20 static const struct of_device_id c3_peripherals_clkc_match_table[] =3D { { .compatible =3D "amlogic,c3-peripherals-clkc", + .data =3D &c3_peripherals_clkc_data, }, { /* sentinel */ } }; @@ -2144,7 +2109,7 @@ static const struct of_device_id c3_peripherals_clkc_= match_table[] =3D { MODULE_DEVICE_TABLE(of, c3_peripherals_clkc_match_table); =20 static struct platform_driver c3_peripherals_clkc_driver =3D { - .probe =3D c3_peripherals_clkc_probe, + .probe =3D meson_clkc_mmio_probe, .driver =3D { .name =3D "c3-peripherals-clkc", .of_match_table =3D c3_peripherals_clkc_match_table, diff --git a/drivers/clk/meson/c3-pll.c b/drivers/clk/meson/c3-pll.c index ccfcd4b5be8996592c27df31fa62d4871c826926..dd047d17488c1309dcc4607dfb5= 5582ea978528d 100644 --- a/drivers/clk/meson/c3-pll.c +++ b/drivers/clk/meson/c3-pll.c @@ -653,59 +653,24 @@ static struct clk_hw *c3_pll_hw_clks[] =3D { [CLKID_MCLK1] =3D &c3_mclk1.hw }; =20 -static const struct regmap_config c3_pll_regmap_cfg =3D { - .reg_bits =3D 32, - .val_bits =3D 32, - .reg_stride =3D 4, - .max_register =3D ANACTRL_MPLL_CTRL4, -}; - -static struct meson_clk_hw_data c3_pll_clks =3D { - .hws =3D c3_pll_hw_clks, - .num =3D ARRAY_SIZE(c3_pll_hw_clks), +static const struct meson_clkc_data c3_pll_clkc_data =3D { + .hw_clks =3D { + .hws =3D c3_pll_hw_clks, + .num =3D ARRAY_SIZE(c3_pll_hw_clks), + }, }; =20 -static int c3_pll_clkc_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct regmap *regmap; - void __iomem *base; - int clkid, ret; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - regmap =3D devm_regmap_init_mmio(dev, base, &c3_pll_regmap_cfg); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); - - for (clkid =3D 0; clkid < c3_pll_clks.num; clkid++) { - /* array might be sparse */ - if (!c3_pll_clks.hws[clkid]) - continue; - - ret =3D devm_clk_hw_register(dev, c3_pll_clks.hws[clkid]); - if (ret) { - dev_err(dev, "Clock registration failed\n"); - return ret; - } - } - - return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, - &c3_pll_clks); -} - static const struct of_device_id c3_pll_clkc_match_table[] =3D { { .compatible =3D "amlogic,c3-pll-clkc", + .data =3D &c3_pll_clkc_data, }, {} }; MODULE_DEVICE_TABLE(of, c3_pll_clkc_match_table); =20 static struct platform_driver c3_pll_clkc_driver =3D { - .probe =3D c3_pll_clkc_probe, + .probe =3D meson_clkc_mmio_probe, .driver =3D { .name =3D "c3-pll-clkc", .of_match_table =3D c3_pll_clkc_match_table, diff --git a/drivers/clk/meson/meson8-ddr.c b/drivers/clk/meson/meson8-ddr.c index 6a9efde9b570d8a2609c118d7d38334a3b4a5dcc..0f93774f73718d29afca87b4c60= 1bd32b9745d30 100644 --- a/drivers/clk/meson/meson8-ddr.c +++ b/drivers/clk/meson/meson8-ddr.c @@ -83,57 +83,26 @@ static struct clk_hw *meson8_ddr_hw_clks[] =3D { [DDR_CLKID_DDR_PLL] =3D &meson8_ddr_pll.hw, }; =20 -static struct meson_clk_hw_data meson8_ddr_clks =3D { - .hws =3D meson8_ddr_hw_clks, - .num =3D ARRAY_SIZE(meson8_ddr_hw_clks), -}; - -static const struct regmap_config meson8_ddr_regmap_cfg =3D { - .reg_bits =3D 8, - .val_bits =3D 32, - .reg_stride =3D 4, - .max_register =3D DDR_CLK_STS, +static const struct meson_clkc_data meson8_ddr_clkc_data =3D { + .hw_clks =3D { + .hws =3D meson8_ddr_hw_clks, + .num =3D ARRAY_SIZE(meson8_ddr_hw_clks), + }, }; =20 -static int meson8_ddr_clkc_probe(struct platform_device *pdev) -{ - struct regmap *regmap; - void __iomem *base; - struct clk_hw *hw; - int ret, i; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - - regmap =3D devm_regmap_init_mmio(&pdev->dev, base, - &meson8_ddr_regmap_cfg); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); - - /* Register all clks */ - for (i =3D 0; i < meson8_ddr_clks.num; i++) { - hw =3D meson8_ddr_clks.hws[i]; - - ret =3D devm_clk_hw_register(&pdev->dev, hw); - if (ret) { - dev_err(&pdev->dev, "Clock registration failed\n"); - return ret; - } - } - - return devm_of_clk_add_hw_provider(&pdev->dev, meson_clk_hw_get, - &meson8_ddr_clks); -} - static const struct of_device_id meson8_ddr_clkc_match_table[] =3D { - { .compatible =3D "amlogic,meson8-ddr-clkc" }, - { .compatible =3D "amlogic,meson8b-ddr-clkc" }, + { + .compatible =3D "amlogic,meson8-ddr-clkc", + .data =3D &meson8_ddr_clkc_data, + }, { + .compatible =3D "amlogic,meson8b-ddr-clkc", + .data =3D &meson8_ddr_clkc_data, + }, { /* sentinel */ } }; =20 static struct platform_driver meson8_ddr_clkc_driver =3D { - .probe =3D meson8_ddr_clkc_probe, + .probe =3D meson_clkc_mmio_probe, .driver =3D { .name =3D "meson8-ddr-clkc", .of_match_table =3D meson8_ddr_clkc_match_table, diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peri= pherals.c index 9bcd35f12836de5e318fd1ad9c9ae15a2bfc3dd7..fc1500df926d056ce17252987dd= 91095a8399b55 100644 --- a/drivers/clk/meson/s4-peripherals.c +++ b/drivers/clk/meson/s4-peripherals.c @@ -3449,59 +3449,24 @@ static struct clk_hw *s4_peripherals_hw_clks[] =3D { [CLKID_HDCP22_SKPCLK] =3D &s4_hdcp22_skpclk.hw, }; =20 -static const struct regmap_config s4_peripherals_regmap_cfg =3D { - .reg_bits =3D 32, - .val_bits =3D 32, - .reg_stride =3D 4, - .max_register =3D CLKCTRL_DEMOD_CLK_CTRL, -}; - -static struct meson_clk_hw_data s4_peripherals_clks =3D { - .hws =3D s4_peripherals_hw_clks, - .num =3D ARRAY_SIZE(s4_peripherals_hw_clks), +static const struct meson_clkc_data s4_peripherals_clkc_data =3D { + .hw_clks =3D { + .hws =3D s4_peripherals_hw_clks, + .num =3D ARRAY_SIZE(s4_peripherals_hw_clks), + }, }; =20 -static int s4_peripherals_clkc_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct regmap *regmap; - void __iomem *base; - int ret, i; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return dev_err_probe(dev, PTR_ERR(base), - "can't ioremap resource\n"); - - regmap =3D devm_regmap_init_mmio(dev, base, &s4_peripherals_regmap_cfg); - if (IS_ERR(regmap)) - return dev_err_probe(dev, PTR_ERR(regmap), - "can't init regmap mmio region\n"); - - for (i =3D 0; i < s4_peripherals_clks.num; i++) { - /* array might be sparse */ - if (!s4_peripherals_clks.hws[i]) - continue; - - ret =3D devm_clk_hw_register(dev, s4_peripherals_clks.hws[i]); - if (ret) - return dev_err_probe(dev, ret, - "clock[%d] registration failed\n", i); - } - - return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, &s4_peripherals= _clks); -} - static const struct of_device_id s4_peripherals_clkc_match_table[] =3D { { .compatible =3D "amlogic,s4-peripherals-clkc", + .data =3D &s4_peripherals_clkc_data, }, {} }; MODULE_DEVICE_TABLE(of, s4_peripherals_clkc_match_table); =20 static struct platform_driver s4_peripherals_clkc_driver =3D { - .probe =3D s4_peripherals_clkc_probe, + .probe =3D meson_clkc_mmio_probe, .driver =3D { .name =3D "s4-peripherals-clkc", .of_match_table =3D s4_peripherals_clkc_match_table, diff --git a/drivers/clk/meson/s4-pll.c b/drivers/clk/meson/s4-pll.c index 6a266bcafd6257937c1de50cbc5606dcc6f8207b..56ce6f566e537a26e932db245ed= e17d900d9f093 100644 --- a/drivers/clk/meson/s4-pll.c +++ b/drivers/clk/meson/s4-pll.c @@ -798,66 +798,26 @@ static const struct reg_sequence s4_pll_init_regs[] = =3D { { .reg =3D ANACTRL_MPLL_CTRL0, .def =3D 0x00000543 }, }; =20 -static const struct regmap_config s4_pll_clkc_regmap_cfg =3D { - .reg_bits =3D 32, - .val_bits =3D 32, - .reg_stride =3D 4, - .max_register =3D ANACTRL_HDMIPLL_CTRL0, -}; - -static struct meson_clk_hw_data s4_pll_clks =3D { - .hws =3D s4_pll_hw_clks, - .num =3D ARRAY_SIZE(s4_pll_hw_clks), -}; - -static int s4_pll_clkc_probe(struct platform_device *pdev) -{ - struct device *dev =3D &pdev->dev; - struct regmap *regmap; - void __iomem *base; - int ret, i; - - base =3D devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return dev_err_probe(dev, PTR_ERR(base), - "can't ioremap resource\n"); - - regmap =3D devm_regmap_init_mmio(dev, base, &s4_pll_clkc_regmap_cfg); - if (IS_ERR(regmap)) - return dev_err_probe(dev, PTR_ERR(regmap), - "can't init regmap mmio region\n"); - - ret =3D regmap_multi_reg_write(regmap, s4_pll_init_regs, ARRAY_SIZE(s4_pl= l_init_regs)); - if (ret) - return dev_err_probe(dev, ret, - "Failed to init registers\n"); - - /* Register clocks */ - for (i =3D 0; i < s4_pll_clks.num; i++) { - /* array might be sparse */ - if (!s4_pll_clks.hws[i]) - continue; - - ret =3D devm_clk_hw_register(dev, s4_pll_clks.hws[i]); - if (ret) - return dev_err_probe(dev, ret, - "clock[%d] registration failed\n", i); - } - - return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, - &s4_pll_clks); -} +static const struct meson_clkc_data s4_pll_clkc_data =3D { + .hw_clks =3D { + .hws =3D s4_pll_hw_clks, + .num =3D ARRAY_SIZE(s4_pll_hw_clks), + }, + .init_regs =3D s4_pll_init_regs, + .init_count =3D ARRAY_SIZE(s4_pll_init_regs), +}; =20 static const struct of_device_id s4_pll_clkc_match_table[] =3D { { .compatible =3D "amlogic,s4-pll-clkc", + .data =3D &s4_pll_clkc_data, }, {} }; MODULE_DEVICE_TABLE(of, s4_pll_clkc_match_table); =20 static struct platform_driver s4_pll_clkc_driver =3D { - .probe =3D s4_pll_clkc_probe, + .probe =3D meson_clkc_mmio_probe, .driver =3D { .name =3D "s4-pll-clkc", .of_match_table =3D s4_pll_clkc_match_table, --=20 2.47.2 From nobody Fri Oct 3 20:30:33 2025 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6645F302772 for ; Mon, 25 Aug 2025 14:27:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132035; cv=none; b=PlhQowjfg4psUNwhV24+3ulWXKxOfPoeT4II4f6VWEQu90+SdbqOzeAiDRxmzMkAQ6QGme2/Ljeynb22JEqOFdkZlme+q7Be+sUkPF9C7Co2uorzioCVy4yXJBTlPdXL+ywoGmrA2iRtSm8BW4Azp4f5JVfYb7MxrdV7esTXlus= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132035; c=relaxed/simple; bh=ey5cZdSnxDBMQWblcJDibJDA5OZgFBnUd6WG9uhMGLo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JYLlrH+BmFiQ4JzP4SRQKVwNKDSvsOgDZNnmLn98vvUj5fWVuR+0sf2M+bL6hOpbR2mvQ2k6gFeKbFa/iYz/Dt64CgigUPCf/UGoe+Tfn+g57mHCx9YKVMdgK8/ZNsdHRvkZPtckwxtWNpNO5/E4qbqes2ML9YFhGwoImVrmPVg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=bHfKq4pP; arc=none smtp.client-ip=209.85.221.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="bHfKq4pP" Received: by mail-wr1-f46.google.com with SMTP id ffacd0b85a97d-3b9edf4cf6cso3756344f8f.3 for ; Mon, 25 Aug 2025 07:27:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1756132029; x=1756736829; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=bKeGjfnHALhz/AAzO7aZ77kwy1JfZMTwKgyrIVs7M5M=; b=bHfKq4pP1L8QXyHmrE3MH5F1giPmr7VN1c0rp2g3XX71LvD6vVill6AdNgOfY+sU9p XyjVtl9jA7R1vwZjqjbJNR2ZsIwG3/3/JIIGKwPQ5nNl88CBg+1lJUw4TlzihmGzwEvj XgYg2r6cAzh71SaMotH5QMCwrqYC44KmiRe62L0TA7Q+6LXmucpnVUmRSuDbryjACBFV st/ZG8ddhOewEKK7hYEHRXuBQT2IAk300lDxA22sZovN/UX6gvdUPhxbArFIbjw+CfEY i1wQFG4H7uP2Y2xJvqiSnQPS+l8JEc8XRDa5lDpoO5N4JEsDtRttQdTyId+cclSzb/rm jn/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756132029; x=1756736829; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bKeGjfnHALhz/AAzO7aZ77kwy1JfZMTwKgyrIVs7M5M=; b=pOpuHsAKa40MomOhWFj/HoYEQILLJsaTtLtvJINCfm9mby2wsyjII/7mrbrxt/k0lu RaDqO7ZwQNI9X/8Z8Riatmey0zpeTvve1EAEKm6LP97GzJBGcVgvsqjOeJB99KHNnH+c 31lwpTt6zDA/EjM/CbEFPedOGl59chkEUVNLArwrEGVtlpIul4l0u5XFVkxtqDVCIOWo IEadZAV2zapXN9KeClrvDod8lWE9atJqBMkj6o3iytBLy0dfb6AkiPNclgsAiGNNl6g/ VaS8tK/KVQF8GjnZUDDZ23nztW1g0SYYwj3PCrIGcFd6sqz6VVn8vknG/ZPjD0z/biQC ueUQ== X-Forwarded-Encrypted: i=1; AJvYcCXLpk6YnWiD4NBX5xfmqqarF6IkSfLuKx+t1mIRn/YzggujC4i+u6AupLPFqLWdbMRpvWM7PgeI1bKLtj8=@vger.kernel.org X-Gm-Message-State: AOJu0Yzwkx0OLUS8D7UTKyYeiac+SkNfaGMXT+iLJz4dP5BWmPHqA4r0 Qj9Beiy/FkRz8/EWA1IW/g2F4arrqDhQL3p/XdrOWcNdelDzKg7jwDO62VoN3erRwr0= X-Gm-Gg: ASbGncsb29ZvF4BCm/Vy6D2IoVmx8oCoXxxhUEopd/TdwZDDNuX8e4isd7jrZNEfHAx SCxNezFUtz/Xpf6uLCR22j+amFSOb9ANMGyksigWK5v68vpkvwKI3gUN23HlRLF7+wX75avzsqw WBBK+gGsk03s3A+qKfg3gei4eh/DuSLIU+qkemnhDhPwD5JQk+o8mKBFNvGHuuxc97biUOasEaI AoOP+0yVD5pMG/79o94ILKvHwozi4K13QKjQEE7bZYJRSWFqYrsluoruaIPgGQEWChNip/9r+VX DdJTlaVjsy1iGUmqR4SFz0Lz08yYwO0sruJR6ScqMt6ijBiPY1g+IbYWbyo/LP/VtCt3PJ52tzI /astVcpTM0wIbpmavlVWE5eD0xjcdoI2zjvsI X-Google-Smtp-Source: AGHT+IHt4lgpYTFRKVUdHW44E3mNT49oLGAxgQr8oV91u9YCleboiVtqxtigsGd/l4FjIi9FOMDqlA== X-Received: by 2002:a5d:64e4:0:b0:3ca:6a35:13f4 with SMTP id ffacd0b85a97d-3ca6a3516c3mr1642673f8f.46.1756132029030; Mon, 25 Aug 2025 07:27:09 -0700 (PDT) Received: from toaster.baylibre.com ([2a01:e0a:3c5:5fb1:b261:baab:ed3d:3cb6]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3c70e4b9e1fsm12634462f8f.14.2025.08.25.07.27.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Aug 2025 07:27:08 -0700 (PDT) From: Jerome Brunet Date: Mon, 25 Aug 2025 16:26:29 +0200 Subject: [PATCH v2 04/12] clk: amlogic: aoclk: use clkc-utils syscon probe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-meson-clk-cleanup-24-v2-4-0f402f01e117@baylibre.com> References: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> In-Reply-To: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5340; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=ey5cZdSnxDBMQWblcJDibJDA5OZgFBnUd6WG9uhMGLo=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBorHKxESzysED9LwfQG3fV63KVp0SL8l2UgmZXi 8CCokopy0WJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaKxysQAKCRDm/A8cN/La ha3yD/9FcCX7DiK/3I/l/3yH9yWepYrt+n+X3Gsl9mHQ0mS1p7l2/X+flH6m5LUNMEZDZj3203n +XvvAepAIKNwsGiqA00GHEmFIHZZmb1zgbjUx5zO80SjyPOMrXyxh5Ur0yM/9Jq6D1c0XqBbb7Y vpr+z7bmk2PphcrU+eA4R3aJo2EJFsHxSyQvtiNO/wAsQQMM35SM/goZyXvG5sUSND1FZuw9QMF lURAPl8N8+OmKOIrHbRndwoNnyRMM2MzZpoE+mh4i/x8ObxZisk5hn1its81dCEXuct3CxRdxPi K/IOo62RiY3lZGIhJ0lIubUW5fWLE+26rnwq7qfyqxmvZ68ifUzLMvJbYc5gU1sTSLRYdKiSVVG fdX4jgbLi8iWJbUd64Z3Qf5fJGlWlqWzcroWZIGciOM2+lI+Tp54TX2x+SiKcBbbh8Q714YoiTt pfkladXgNyTMzwJLYsPl3/8YDTDS8SOzrXtb/P3eq6Inb63FyTjl+FfwvXE3qg5pV0hpHoxT8Yb CAbnwrPNULHYs9jzbGFSZ88sl2Ds8KXNn9IcYA19LULt9Yji+Od+YwBJvM4cfbhT22/hLSK8XbG +agSjfpjdmbbzE3WHEIndXwlvrYZxYiVxeAAjEE6DOtZVQpl7eePNCi0vSTKHEJaeyQklyofR0p xu7N++N9VE+YEyA== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 The clock related part of aoclk probe function duplicates what the clkc-utils syscon helper does. Factorize this to have a single path to maintain. Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg-aoclk.c | 10 ++++++---- drivers/clk/meson/g12a-aoclk.c | 10 ++++++---- drivers/clk/meson/gxbb-aoclk.c | 10 ++++++---- drivers/clk/meson/meson-aoclk.c | 32 ++++++++++++++------------------ drivers/clk/meson/meson-aoclk.h | 2 +- 5 files changed, 33 insertions(+), 31 deletions(-) diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c index a0c58dc8e950a05c340c3427af4f6ff7661fa84e..efc33fd18c197df233d537e5f82= 44a376d4d0924 100644 --- a/drivers/clk/meson/axg-aoclk.c +++ b/drivers/clk/meson/axg-aoclk.c @@ -300,16 +300,18 @@ static const struct meson_aoclk_data axg_ao_clkc_data= =3D { .reset_reg =3D AO_RTI_GEN_CNTL_REG0, .num_reset =3D ARRAY_SIZE(axg_ao_reset), .reset =3D axg_ao_reset, - .hw_clks =3D { - .hws =3D axg_ao_hw_clks, - .num =3D ARRAY_SIZE(axg_ao_hw_clks), + .clkc_data =3D { + .hw_clks =3D { + .hws =3D axg_ao_hw_clks, + .num =3D ARRAY_SIZE(axg_ao_hw_clks), + }, }, }; =20 static const struct of_device_id axg_ao_clkc_match_table[] =3D { { .compatible =3D "amlogic,meson-axg-aoclkc", - .data =3D &axg_ao_clkc_data, + .data =3D &axg_ao_clkc_data.clkc_data, }, { } }; diff --git a/drivers/clk/meson/g12a-aoclk.c b/drivers/clk/meson/g12a-aoclk.c index 3eaf1db16f45a0adf0acd901ed7ae1f51a9c8dc1..872a7b800bb86bdf1ead56c3eec= 7e47f30637dbd 100644 --- a/drivers/clk/meson/g12a-aoclk.c +++ b/drivers/clk/meson/g12a-aoclk.c @@ -424,16 +424,18 @@ static const struct meson_aoclk_data g12a_ao_clkc_dat= a =3D { .reset_reg =3D AO_RTI_GEN_CNTL_REG0, .num_reset =3D ARRAY_SIZE(g12a_ao_reset), .reset =3D g12a_ao_reset, - .hw_clks =3D { - .hws =3D g12a_ao_hw_clks, - .num =3D ARRAY_SIZE(g12a_ao_hw_clks), + .clkc_data =3D { + .hw_clks =3D { + .hws =3D g12a_ao_hw_clks, + .num =3D ARRAY_SIZE(g12a_ao_hw_clks), + }, }, }; =20 static const struct of_device_id g12a_ao_clkc_match_table[] =3D { { .compatible =3D "amlogic,meson-g12a-aoclkc", - .data =3D &g12a_ao_clkc_data, + .data =3D &g12a_ao_clkc_data.clkc_data, }, { } }; diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c index 11b11fa7791eb1903938c0d3ee46121a23b94a46..ce8d2e9e071759ab8b8aa8619ad= 7400f1513c319 100644 --- a/drivers/clk/meson/gxbb-aoclk.c +++ b/drivers/clk/meson/gxbb-aoclk.c @@ -258,16 +258,18 @@ static const struct meson_aoclk_data gxbb_ao_clkc_dat= a =3D { .reset_reg =3D AO_RTI_GEN_CNTL_REG0, .num_reset =3D ARRAY_SIZE(gxbb_ao_reset), .reset =3D gxbb_ao_reset, - .hw_clks =3D { - .hws =3D gxbb_ao_hw_clks, - .num =3D ARRAY_SIZE(gxbb_ao_hw_clks), + .clkc_data =3D { + .hw_clks =3D { + .hws =3D gxbb_ao_hw_clks, + .num =3D ARRAY_SIZE(gxbb_ao_hw_clks), + }, }, }; =20 static const struct of_device_id gxbb_ao_clkc_match_table[] =3D { { .compatible =3D "amlogic,meson-gx-aoclkc", - .data =3D &gxbb_ao_clkc_data, + .data =3D &gxbb_ao_clkc_data.clkc_data, }, { } }; diff --git a/drivers/clk/meson/meson-aoclk.c b/drivers/clk/meson/meson-aocl= k.c index 894c02fda072ddd0733165d5f60efe1d0da2388d..8f6bdea181197cc647398bd607d= 8b004ac81f747 100644 --- a/drivers/clk/meson/meson-aoclk.c +++ b/drivers/clk/meson/meson-aoclk.c @@ -37,15 +37,23 @@ static const struct reset_control_ops meson_aoclk_reset= _ops =3D { int meson_aoclkc_probe(struct platform_device *pdev) { struct meson_aoclk_reset_controller *rstc; - struct meson_aoclk_data *data; + const struct meson_clkc_data *clkc_data; + const struct meson_aoclk_data *data; struct device *dev =3D &pdev->dev; struct device_node *np; struct regmap *regmap; - int ret, clkid; + int ret; =20 - data =3D (struct meson_aoclk_data *) of_device_get_match_data(dev); - if (!data) - return -ENODEV; + clkc_data =3D of_device_get_match_data(dev); + if (!clkc_data) + return -EINVAL; + + ret =3D meson_clkc_syscon_probe(pdev); + if (ret) + return ret; + + data =3D container_of(clkc_data, struct meson_aoclk_data, + clkc_data); =20 rstc =3D devm_kzalloc(dev, sizeof(*rstc), GFP_KERNEL); if (!rstc) @@ -71,19 +79,7 @@ int meson_aoclkc_probe(struct platform_device *pdev) return ret; } =20 - /* Register all clks */ - for (clkid =3D 0; clkid < data->hw_clks.num; clkid++) { - if (!data->hw_clks.hws[clkid]) - continue; - - ret =3D devm_clk_hw_register(dev, data->hw_clks.hws[clkid]); - if (ret) { - dev_err(dev, "Clock registration failed\n"); - return ret; - } - } - - return devm_of_clk_add_hw_provider(dev, meson_clk_hw_get, (void *)&data->= hw_clks); + return 0; } EXPORT_SYMBOL_NS_GPL(meson_aoclkc_probe, "CLK_MESON"); =20 diff --git a/drivers/clk/meson/meson-aoclk.h b/drivers/clk/meson/meson-aocl= k.h index ea5fc61308af14c63489b7c72410d9d981d8745b..2c83e73d3a7753c2094d2acc7c7= 5b524edb5bb9e 100644 --- a/drivers/clk/meson/meson-aoclk.h +++ b/drivers/clk/meson/meson-aoclk.h @@ -20,10 +20,10 @@ #include "meson-clkc-utils.h" =20 struct meson_aoclk_data { + const struct meson_clkc_data clkc_data; const unsigned int reset_reg; const int num_reset; const unsigned int *reset; - struct meson_clk_hw_data hw_clks; }; =20 struct meson_aoclk_reset_controller { --=20 2.47.2 From nobody Fri Oct 3 20:30:33 2025 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54DAA2FABE3 for ; Mon, 25 Aug 2025 14:27:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132035; cv=none; b=fou3WoHLsjV9t3f4pzSgLwwkBCcz6l6DXAroidAJVKui760L7RG6pqG/vyQD54wIKzdNNiG8vKIwTH+BkPl3gHjwrYCY83rFE9SNq5MD1lvVwQMCYShMSibHWIUE1xqvBhq9TTv3Ur+u5WONFRnQk1yXwLpi02EdTuQubreU3H8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132035; c=relaxed/simple; bh=5iKLGNRbAiiV7znNVkmV2nYu93DQzEVzWcxt59v2OQ4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CRlgTWawFSY/dfZRxKGey0VOQ72OICgkKklKksb8/a9KUs8lHxjyU+yWtDbH9klP8C8PWNNBGhiohyNwY1AuWCFBFUk8CF+0argwoBQpGdKIGqd7LN4nPofVimYVRsaKjHh65ro4upswQLhqNASO3qRfIYKFZ6xoKz+RAN/B4tc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=CGbbosqL; arc=none smtp.client-ip=209.85.128.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="CGbbosqL" Received: by mail-wm1-f44.google.com with SMTP id 5b1f17b1804b1-45a1b0c8867so36674015e9.3 for ; Mon, 25 Aug 2025 07:27:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1756132030; x=1756736830; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Q2GKlTQ+1w74j9oubIC+GWZcqnBFxLSwzSHXC6Ex1dU=; b=CGbbosqLriNzDvMfcmkgC8Kxg1Kmgh/PP6PXQ/k9+zGC6CKHChKVyiJWFmJ8XjegOx kljCnu1jLtlRrSNWjWtDJM97pTdTVRmpPaSE7PHZQv5xjmG4c7CBF9FQP3ERy7hn1KmM azcI8ZwzmtubGMdLZpFD0/hUsQ4PcR5AISGfzRNy8UWIKdqrSTOvNQVCan8jzBavq2FO BG+yC9K3ga39D/r+V6sS1bpudKcBeUF2LN8ktamkOst31U1yWETuWxgEDXVsB9RoJrI1 rgtnQlggheNbaAjWTz4+2zf6UITQ8Oua6xE3FbpsF7YFbAkfSfKmaBD5sTxJDLgTqNH/ xj1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756132030; x=1756736830; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q2GKlTQ+1w74j9oubIC+GWZcqnBFxLSwzSHXC6Ex1dU=; b=esVS/bESIP2pI39JX2EFQ9POYibRB8i2DmemvVUDS1+Re0ADAxOJ9A9Af/SfhSf4xu Mnv+k61+Jy/FYy0zAL0Ywn7T8/ObV65pAwf1amtAVzYSre1Wcof7g5sxzQxK9S5+LrF5 sy2Dz6uDBR1wo0OZgHXdlpEoHEmSSAqhBOibuaWkzHnpvbUPKxGqaTgKCJCyIbT2p9JZ slwjUwEhA5ZlU7xdv4P8drbPZfS7Wl6eUlQZuG/a1NKpa+vNQ1pXlDLmVR2QAQVjbvWC Ho7JPr2U1OI272rqWzVjFRJ6SNfbIWAnA41KmSbY63uz5II2h/SzwSW9LYvvlgIC2DL8 9gKQ== X-Forwarded-Encrypted: i=1; AJvYcCXCg0IfwMhfXUil8Af9R+Jq0diAIdxFODs8lEFrqZ/etwnKXSIPtXF2/E2h+7Y1lhMtjImLYktjFWhnAjY=@vger.kernel.org X-Gm-Message-State: AOJu0YycLPVvm8h63Y3+DT6caMwCuHVd3t32di1Subb0JC7dTdUspECG kZoe/bL/fNgaEieJAaq4HNBPbY6VKxuL3osqOhZ0uP+vOBP1Mm3LwS6nerljy/6uadk= X-Gm-Gg: ASbGncuR9nfiyVJ0G4JT0gJZ6ImIrBCAGnXGB9st6oLLWY8xV9tN7Z+Bq7UvI0lipYc Nnn1DwX0t3VURut4mgUNovRnZ/hei0SwWsva6cksMzi+VzEQE+nP2VZWxKth1miRHTGnFXkVAXZ k8ZDbAFbtVbXNLW6ZJ59uN21CjA4sspdod5s++PDld0x6qOrxPMz/zfs9AkGB8Kx6wcL9AUAEUo OwGTEpr4niWGERr0G2pdoXSbWhZm6bus91Ok9ci0dcSRCMsiLn1Z7D6hr/YmuflXJzHInrL59Nf wbryFKuNFPmdJToef/XX+Sn7xd6t+72lnHziCWM8kpHvivgVsMdAnDRzPMs8ycBP2zl8d6A4oGq gwaipcv53GcYZ/+eJecq8rydDsiM2QufsQOkv X-Google-Smtp-Source: AGHT+IEPylErx21mcn6dCJV2kIoCD0AjzLCCsQU2klZrox1l+K+hy+rzX244+vSFz6N2S3mmScUSPg== X-Received: by 2002:a05:600c:1c20:b0:458:c059:7d9c with SMTP id 5b1f17b1804b1-45b5d48ea24mr53620055e9.6.1756132029678; Mon, 25 Aug 2025 07:27:09 -0700 (PDT) Received: from toaster.baylibre.com ([2a01:e0a:3c5:5fb1:b261:baab:ed3d:3cb6]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3c70e4b9e1fsm12634462f8f.14.2025.08.25.07.27.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Aug 2025 07:27:09 -0700 (PDT) From: Jerome Brunet Date: Mon, 25 Aug 2025 16:26:30 +0200 Subject: [PATCH v2 05/12] clk: amlogic: move PCLK definition to clkc-utils Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-meson-clk-cleanup-24-v2-5-0f402f01e117@baylibre.com> References: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> In-Reply-To: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2901; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=5iKLGNRbAiiV7znNVkmV2nYu93DQzEVzWcxt59v2OQ4=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBorHKy/cxvrqriA5RdgyQ8kngzsTGP4zIGETSvr bPIwwN/D/KJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaKxysgAKCRDm/A8cN/La hU6YD/9847LKHLtfPFP+98FtM+A/KPHuOXabho5DnlqQ4CTQm7TeTEECumy3BR3ViDcUWqmul6J mOcnAQ4VD/PQx47DoisFdLoyRgVYGi41vm/px3GlkNoiAoMuIbOQ1S7mK7b6Yo3bd6TARrh1yxI b2bXFz9x0w3hWAGTTBsDXfCyBWlUdRvSRosLINDT4bw/hFcnRljMaFx0C+8oFUMrGeKc/tblNsW evuqJI1g7805n992YNyaRg5OxHvkNzgwese6m7LyB+o/q/DBxPLzJuXypikMS8Ua0zCnPMMP+eO n5tt6cqV5DhMhAVE0bLvTxxvCRmGJZFGpe4wXSUCxZWiY08A4hLI5PVUPlnvM6l+lUOmtXU8uL1 lVd2y0PMtirwjQ7nyoy+FY5p8EeTpFii3D3a5Mq/tgwGDGIxQUE2C0FY85NTUFd6VedNMh1I3UF TnAqB5i+e8vakFIzBsJU4UQXdaVIYqfYkNTOKwq8YKN8s1TMTtFoYnH42Z4WqzK6aQ+KvoG74ZT PwROguP/QnE9zU1S4moPZwFjiYu7Kizf0I+hI5n5/TluEiSwbiXyLsUBYSbqzbdDvCYEDjqX09N zB7S+wUEQ/EO+L1pciA2bfTKsUvEZWtLYGqUyQ7LUn774lybqO7VWYI9hiMuUBE6AHgYh/C/37T pqUsLmEEHRMIMPg== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 clk-regmap was always meant to stay generic, without any amlogic specifics. The hope was that it could move out of the amlogic directory one day. Even if this may actually not become true, it should remain generic. Move the amlogic peripheral clock definition out of clk-regmap header. Signed-off-by: Jerome Brunet --- drivers/clk/meson/clk-regmap.h | 20 -------------------- drivers/clk/meson/meson-clkc-utils.h | 21 +++++++++++++++++++++ 2 files changed, 21 insertions(+), 20 deletions(-) diff --git a/drivers/clk/meson/clk-regmap.h b/drivers/clk/meson/clk-regmap.h index f8cac2df5755b0f894570305604485f54c17ea49..8e5c39b023e1334e37d5a9e0594= 436727f16c4f2 100644 --- a/drivers/clk/meson/clk-regmap.h +++ b/drivers/clk/meson/clk-regmap.h @@ -118,24 +118,4 @@ clk_get_regmap_mux_data(struct clk_regmap *clk) extern const struct clk_ops clk_regmap_mux_ops; extern const struct clk_ops clk_regmap_mux_ro_ops; =20 -#define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ -struct clk_regmap _name =3D { \ - .data =3D &(struct clk_regmap_gate_data){ \ - .offset =3D (_reg), \ - .bit_idx =3D (_bit), \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D #_name, \ - .ops =3D _ops, \ - .parent_hws =3D (const struct clk_hw *[]) { _pname }, \ - .num_parents =3D 1, \ - .flags =3D (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ - }, \ -} - -#define MESON_PCLK(_name, _reg, _bit, _pname) \ - __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname) - -#define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ - __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname) #endif /* __CLK_REGMAP_H */ diff --git a/drivers/clk/meson/meson-clkc-utils.h b/drivers/clk/meson/meson= -clkc-utils.h index b45f85f630d7190fb6509b088f05f17ca91fa1c8..0c228a6723bb2bddc0b9a4f9251= 5f05850a5613a 100644 --- a/drivers/clk/meson/meson-clkc-utils.h +++ b/drivers/clk/meson/meson-clkc-utils.h @@ -27,4 +27,25 @@ struct meson_clkc_data { int meson_clkc_syscon_probe(struct platform_device *pdev); int meson_clkc_mmio_probe(struct platform_device *pdev); =20 +#define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ +struct clk_regmap _name =3D { \ + .data =3D &(struct clk_regmap_gate_data) { \ + .offset =3D (_reg), \ + .bit_idx =3D (_bit), \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D #_name, \ + .ops =3D _ops, \ + .parent_hws =3D (const struct clk_hw *[]) { _pname }, \ + .num_parents =3D 1, \ + .flags =3D (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ + }, \ +} + +#define MESON_PCLK(_name, _reg, _bit, _pname) \ + __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname) + +#define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ + __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname) + #endif --=20 2.47.2 From nobody Fri Oct 3 20:30:33 2025 Received: from mail-wm1-f49.google.com (mail-wm1-f49.google.com [209.85.128.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8660A2FCC17 for ; Mon, 25 Aug 2025 14:27:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132035; cv=none; b=Vf+HCGvJY8SV7ncTgBoavgbEOGLNs+1uTHVOiGVPY5orw7wXWXdHyLsj3fVyA5CcNOFDIAe+wGSCPutaF+BmIIhMdKZLUVNtF0DvB8TCQ3gq5q99VcZwegzREW358zf8hAn1tYBWAVyDhzc1xiYl4WsH7xRY6Gp/2gCgHmQ5pww= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132035; c=relaxed/simple; bh=72WOcl72YOlZwt+/CKTosZbQzCnfjCTjpwRm9zwOmLc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Fywmo4n5DWsWdYWTqSbC95zvMShqXxmMzweKpmmcYI9jaM1J1VF12Pe8qd0unlXNSYHz5kMCs6Hm2UYWizqPKp1PtliovYKhEcqf+vsQAZiGl7FZpvnrKTi5vwCRgPZQp9bVsK1O3OmcaJgjf+VJic5DLMdm3QS9FoKW3g4e8Vw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=ngO3Vd07; arc=none smtp.client-ip=209.85.128.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="ngO3Vd07" Received: by mail-wm1-f49.google.com with SMTP id 5b1f17b1804b1-45a1b0bde14so24075145e9.2 for ; Mon, 25 Aug 2025 07:27:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1756132030; x=1756736830; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=xRqhnX04LSAiYdBNDlTGLugmcAxHcjqdN/6E4HSJk+A=; b=ngO3Vd07p8YnksEQNB5GsYMzc6Zee0Pf8MKA34nWuum+2k0KpX+HzIqstkJI5bXSiQ lDhDwPxhKa0sn7Jkmd4i5ZRAxZm7Pot5bmSMdpH/3c5aczmXjyne7l7EdOTRCiO9acwC Wjn+PnsjeNs1y46GF1qV/vwsdplUFPT4aVoL3T+O1sHTTCPtWVZQbfFgsNumbcIqXMR3 xPUCF04ZWIbs1gInBniC6ivGskZYb/qoviiGUf/j9rh/RNFRPZVFNPgOibu2+Qcce+nu yyJ7Cc7nJ2bsAT46+eHA/nuFu6gnocqfff0jF5+nkzFv3xeLwLLQMKZFDLAtKwkgzP2W J6QQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756132030; x=1756736830; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xRqhnX04LSAiYdBNDlTGLugmcAxHcjqdN/6E4HSJk+A=; b=FlXqzGClvY9JvKVHyCJ7/8lHjtWcanY6MwLFAHkqUR6eYkwFswLc2FV49+4vckwiJx WnbjFqyddOc0haU2VVuYQmzct/9otTlJtlTiOj5e8jVoVFGjkq2rxXtFANYaRk+O16u5 fFPJAYKKUZCUVDJDc36BFpgdhV53PGJuNnGimvSe8bDY4c3fdn075npcCiHSxcyiCCyx hnBquiQGv8gCnP38mtdTLTD91KlJdNdcetkvsognE1K66YCsuEYwRNItXgkiFKEu7BTL Q/Aeq1WE7Pmc6ZcdDuwEEJPiRchLz2cmZcssfCMRGnVRD3Q7s+JjhRSt92zzGMkH/l1S UC3Q== X-Forwarded-Encrypted: i=1; AJvYcCWoaNtmK7f5+VXGBeKApnNqeCgSI2S6LN0osfHey4EWeTMm6cY/XTHt62wmSKiXBVGQITk17qM3KbxxZfA=@vger.kernel.org X-Gm-Message-State: AOJu0YyXITMfzpNsHf0CIumRJeSGRhlB5MnB67pkJOukji6G54zvnnJN HF0tpS98nywDQCmY3W9pJWO0QloGDcH8eeAVK0jNT/39lMKtx8ah6ZoSG4H3KOZ9OMM= X-Gm-Gg: ASbGncvNXGfsQr7DONSOXyMBClFyXbCWxTxYshS/JUXwH+KjUrmSClSWM1et5QlZ2JX MZGphNQf590ddPJaZNMpd6usJ9MVy9JJvr7W9uExuwx4slHqnFlourHBllyiWPYMqz16RfAHpsy vXVPyCrjXM4qjunnLMEYDu5qg//gNkYJPNMAxs3GbwcqgDQjbSQ6Qdrmjf4hzUXFq5JHjzenkHS tkZPzDrJ9O6yHvIB03NADcLEqfthmMVGdu8M9CsjqDyCOQI3gZmX1fe3pefwRw2z+txsykdHPZn LpmVE/K/Oip99GTGuOaBbKTKD6KtIPSC8MsWhKvTaaddUsb1U61Kbl1262L31867GfEqTS86mF5 ZVYD0gjESko9dazy8TiCbRJwl57gumpZXgxlgmjnrDdOunU0= X-Google-Smtp-Source: AGHT+IFiPKoRqUt+ns9QGMzAHG5ADHsWD9oCSqbjBX7AALemd/YQHEFsuSaB7N7pDSlpI8XFCAMjJA== X-Received: by 2002:a05:6000:288a:b0:3c3:f134:28ba with SMTP id ffacd0b85a97d-3c5db2dcc73mr10078522f8f.28.1756132030376; Mon, 25 Aug 2025 07:27:10 -0700 (PDT) Received: from toaster.baylibre.com ([2a01:e0a:3c5:5fb1:b261:baab:ed3d:3cb6]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3c70e4b9e1fsm12634462f8f.14.2025.08.25.07.27.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Aug 2025 07:27:10 -0700 (PDT) From: Jerome Brunet Date: Mon, 25 Aug 2025 16:26:31 +0200 Subject: [PATCH v2 06/12] clk: amlogic: drop CLK_SET_RATE_PARENT from peripheral clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-meson-clk-cleanup-24-v2-6-0f402f01e117@baylibre.com> References: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> In-Reply-To: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1121; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=72WOcl72YOlZwt+/CKTosZbQzCnfjCTjpwRm9zwOmLc=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBorHKzmtWoqm6bakWO4aKPSmFt40T0qw2eFXNA3 VSI6WqYcXuJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaKxyswAKCRDm/A8cN/La hdhKD/kBP+rn+onWFFONaftlxYdK3A/70krVdI9E8Ed4u2qVKwNTK8gYdu+FC++MQR3SyZUdB61 jq56+0ekWz28V2fZ8FVwaH74fz4eoXQ3Zgme4vQUXSMw25zClzqCEdekFweiMZAkJjXhsrfC0so 5SrtlSz7jU/EIIW9TTll7tly7/cVkiWdoPF0tBj6y2Y3GOy9+sYhx/CWCQUYvcNvbqIMKQ+oUn0 NajUZsntJ4TkzY0REthSO/alUHbltx9JzK9mC7O/H9d4fdMm7RDm6YKq+qywCwU5N0uDwmUUmz9 /dERanMgbXxJF+H/DFcgYrxYpl6oXoXVmb+mbHbXswsikTfoFRjpbj3InOl356uuRYqhhm4nDUo I9yJfXxWJkKpUNlYi72srABYcdjCC7RCouxjKNBDnZkDeEABMrx+n8V18+qAgStQlbGEc5HNVxf 7EjAm+DfazEypaXlfLNuTFr5bXJOBgBDcRxFMXNn3CY709MnOhv+sQF2YECpppMZ5s8rBDu7oQC uN499gfY9WIKPtzkgmoIYCjaEVgizqzKNXpAgY4bFv9Plyo1rx8yS01hbj8tO7V6VpCF0SOKZWA uGG661IS0XryE9SfHYJJo2nwiOOP8qoNRti+7sL9KCjjkpfqr8GD57B7fvW4nQJAhcy1p9ZMT4F nmTT04JV8y9D3dw== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 On Amlogic SoCs, the rate of a peripheral clock should not be changed, let alone the rate of the parent PLL. These clocks are meant to be used as provided by the parent PLL. Changing the rate would be dangerous and would likely break a lot of devices running from the same PLL. Don't propagate any rate change request that may come from these clocks and drop the corresponding flag. Signed-off-by: Jerome Brunet --- drivers/clk/meson/meson-clkc-utils.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/meson-clkc-utils.h b/drivers/clk/meson/meson= -clkc-utils.h index 0c228a6723bb2bddc0b9a4f92515f05850a5613a..3e1fb7efe6da1f5d8e55993541d= 12d40464a47f5 100644 --- a/drivers/clk/meson/meson-clkc-utils.h +++ b/drivers/clk/meson/meson-clkc-utils.h @@ -38,7 +38,7 @@ struct clk_regmap _name =3D { \ .ops =3D _ops, \ .parent_hws =3D (const struct clk_hw *[]) { _pname }, \ .num_parents =3D 1, \ - .flags =3D (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ + .flags =3D CLK_IGNORE_UNUSED, \ }, \ } =20 --=20 2.47.2 From nobody Fri Oct 3 20:30:33 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76E33302749 for ; Mon, 25 Aug 2025 14:27:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132041; cv=none; b=IdcnEfrNkCsmFe3QOQqr6mQJWeiRgQQRA6YFOJ+NkgwNtxVhQA3I0a1aL7AQMENcKY0rTVdg+oxyPJbSFs7tbD+onTwAZ2SjGqoo4hnUX+55wTIawhCpj7GP+K7idxis07AOs62Ey3Ahy2mNR0PQrvun5GbqKsq9CBja7YSeEm8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132041; c=relaxed/simple; bh=X5//jNi74IpHsHYBbOdRVuP6Q8Mvlr1eAL2dNlSaP1Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lD+CWyrikbXxB/rYAkNHw1x1KVTSJIEBcniialDa4DNhvtoMk1h0unDh5YOcQnbCM+fBqV8zaT75erhX7x1GT/LuiKM7v6emfskTBu2L4RulwjwztNKu8h8vfQX0tenqQEDhMjJuPOYDXplUJu/0KwrjaMjtM6VZFY4CqZ9GGPk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=QZR18ve4; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="QZR18ve4" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-45a286135c8so27676445e9.0 for ; Mon, 25 Aug 2025 07:27:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1756132032; x=1756736832; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=obtHB0H0zF8/AUNa0Qw+GTMgbmBek7VKVmSq18IqlTc=; b=QZR18ve4RKYv0uifKtrh22Z8eozwOTM7q+8KFGrKXlc1FYjimdETd4/MMBUEYxefjv rEVKt/ZaVToIqpjl67Fckl/HT84N+4tEu5fJMndhdErV5CqYYqVqSGUnNpxVENmmm2sf pafTnsV8W5P5A/Xx0XE1IZ/Xr7pcRdu/WvGjAeqUi6Nao+UfSXciqSToPv2RtTGtY8ss c1RDauiG0/J2g+CLh+rCQE4jmNCGbfY6ZpYmu27hJVxhVcOQCvnaFwzvO1uCO1UjTX5e rR/qai0S2p7S0cauxDmFTapRrwgSs2XpdXyoVTmMIKOsulXou+y0+skVJLjW6BHkQ6GQ eHVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756132032; x=1756736832; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=obtHB0H0zF8/AUNa0Qw+GTMgbmBek7VKVmSq18IqlTc=; b=t1s9bz/OKFafVaQR3S0bT01Vu0ey0+lZBhvxj7fcyWaj7a8A1e4mlmuM6hFLSR2AtO bUd56N1ZK5GoPHuWAqDcDoqE0wVRljIytkwQDlUzCgv5D7xgQhSf+EVHmyDtQZiLye8s f9C/YXp42fZaLyAynOrHWliGkZNExGmNbnqtH+l6V+FiQRqJuFnNqDRACNq5EPkyyUIj kK5/xnYyyxXMZPKZOmUa+ghATPX+//3pSI1VoMT/1048B49OUL8YAWZgcc378z8nIRCz 3JvSEF6xazxVMwW6PLiX+zhbSMHCmK8IOjQ7yXXVXqVVKP3aDQNMs2Cc5Ln9NP+DbHtS 3Mdg== X-Forwarded-Encrypted: i=1; AJvYcCVqgyMNOTMptUTAirpjVGo2svbq5ljZt2RmgvG+LVQggoLt2zRxfaEbMuXKB4UpO58jPJvr+u1ZeEsCM/s=@vger.kernel.org X-Gm-Message-State: AOJu0YxpPZfIw71QeE7c0xcfnIpuuRUdVdHXDR4kSDsGKzDm+BULINbP efhtUIKKDr7q4fyFIo8Az+6rp1UPJ6oNfw9XOCkxCZ/YuW+Hew0J4D7btaNnUvG9hE4= X-Gm-Gg: ASbGncsB35r0rD2QJAJTR4Ms2NDw1hZjxbmXZjEd3XRTYSJ4MGi7N/oR0Z7GmgvIh2V ntpAwDYhD2k8X+sHLz/1FBnVWCL7bAsAEwcMwLKMZ799KGw8RQw4wnKKT8CWYnxVDNFg0zzFu6P oTxsoNrgGz1wr0op2aVGbICgf9j0BwKYmwOM2MDp2Mxpd6HJPntWiRD4JMhO0tCh+2UvImFiTMN LC2iA8U/rHJxT0njc2Nq1oWP6qinSN+kF96a5ZYR3m/+iQxCB+iFro5gkKwTKfq5aV9jBV5u/kG PpQsjLMa7ghRO6yWdOqUfEK1eRpXITC9rwyLlyqqsb9BEANe/mDRLOun1DHz57p5rOLSnAY4ulL 3FQo6ReEkscDlto4KoVGKmsMzKpqTMWQDUMii X-Google-Smtp-Source: AGHT+IFcq3ZXI3i0LHZWpsp/q+i24wDf6XY6QuEKult4QnrTYt+AlspnV3rhphQd1qYlTs82qh5j+Q== X-Received: by 2002:adf:f7d2:0:b0:3c5:921a:f440 with SMTP id ffacd0b85a97d-3c5922a3763mr9495467f8f.12.1756132031283; Mon, 25 Aug 2025 07:27:11 -0700 (PDT) Received: from toaster.baylibre.com ([2a01:e0a:3c5:5fb1:b261:baab:ed3d:3cb6]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3c70e4b9e1fsm12634462f8f.14.2025.08.25.07.27.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Aug 2025 07:27:10 -0700 (PDT) From: Jerome Brunet Date: Mon, 25 Aug 2025 16:26:32 +0200 Subject: [PATCH v2 07/12] clk: amlogic: pclk explicitly use CLK_IGNORE_UNUSED Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-meson-clk-cleanup-24-v2-7-0f402f01e117@baylibre.com> References: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> In-Reply-To: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet , Chuan Liu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=65122; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=X5//jNi74IpHsHYBbOdRVuP6Q8Mvlr1eAL2dNlSaP1Y=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBorHK0qxQE/1xHz8WUZ7io62TpsxvDFsBuEMZju mPz1+/hAh2JAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaKxytAAKCRDm/A8cN/La hcaSEACQNlTYtAvySYcw/eLaxmExXPR4vf97oYZwdL38KdU0P2oaV/NbrdLb3AGSClt3g6dwf/X jCqe9PmpPf+GsF7ifMO7RanyJ/0bwTKkJu8rphg1Jtb3KbGXcovm+x0U0jstR7NXN3Xyv6gMxu4 +RbfftkoP1LxQ3/XbRjX2Q40o15kHpqUdAy5R1kHWWDpW9W0tc/ofGGLEGEkf+kMtMY7JuaQX2i sywHhFG81fmWEyRTURdiI71Z8Y/OiACqDBCNdEXezNgnYQH/RNcc9VppbsMvYOx4x4y8m9m89VZ UvCnHvRGy1dWU8/MSFnDJ8s/mA01qBpgW4xV/nRzVVuARbZ2NlR1GaPx7YycgdmEb8Pr3w1FbFR 3cnh5CkUqWYb9fOZ6GuiEITTXdauXDakV3kA28pkHRhB5XUQDm0441psbJY7FnHat19unZ+Gr0z LRVj4e5x7ra74ObTpyLC3qzaVgNZOyTls7La6W7Fj5nt8v07WAFTaqeuClffCDtSdSB4ipMXnmZ qoUKTOxKSlisWJqev2kn+PI3dyQTsLnXqTh5/vOesA88Pfw/xB3a4lkXeA8ZcSV18gf49IRRwY7 C37EHrXxSPc2gBQilqCobeSFVapd3R9fgai3QCRCX86ACdlw4+E205rH9pOP8/hA0wkMjtRO4Xg Y1BfULMe9SFFOuw== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Every usage of CLK_IGNORE_UNUSED should be explicitly motivated and documented. However, the PCLK macros used by most Amlogic platforms are adding that flag systematically. Because of this, all pclks are marked with CLK_IGNORE_UNUSED, without any form of distinction or motivation. This may have been fine in the early days of CCF but it is not anymore. Just removing the flag is not an option at this stage since it could cause regression on existing platforms. Instead, drop the flag from the macro definition and add it to the each clock definition, for the existing clocks. This makes quite a nasty change but it will make it a lot easier for people to contribute to fixing the problem, clock by clock. It will also prevent new platform from being added with a silent use of the flag. Reviewed-by: Chuan Liu Signed-off-by: Jerome Brunet --- drivers/clk/meson/a1-peripherals.c | 125 ++++++++++++----------- drivers/clk/meson/axg-aoclk.c | 18 ++-- drivers/clk/meson/axg.c | 110 ++++++++++---------- drivers/clk/meson/g12a-aoclk.c | 49 ++++----- drivers/clk/meson/g12a.c | 176 ++++++++++++++++---------------- drivers/clk/meson/gxbb-aoclk.c | 16 +-- drivers/clk/meson/gxbb.c | 188 ++++++++++++++++++-------------= ---- drivers/clk/meson/meson-clkc-utils.h | 12 +-- drivers/clk/meson/meson8b.c | 183 ++++++++++++++++++-------------= --- drivers/clk/meson/s4-peripherals.c | 119 ++++++++++++---------- 10 files changed, 528 insertions(+), 468 deletions(-) diff --git a/drivers/clk/meson/a1-peripherals.c b/drivers/clk/meson/a1-peri= pherals.c index b2feb8fe4775e38a17d8aa9ce9b992b3e1fb2bb8..a7bd3822df18f5e043e58e2d7bb= caa24345ea404 100644 --- a/drivers/clk/meson/a1-peripherals.c +++ b/drivers/clk/meson/a1-peripherals.c @@ -1840,64 +1840,73 @@ static struct clk_regmap a1_cecb_32k_out =3D { }, }; =20 -#define A1_PCLK(_name, _reg, _bit) \ - MESON_PCLK(a1_##_name, _reg, _bit, &a1_sys.hw) - -static A1_PCLK(clktree, SYS_CLK_EN0, 0); -static A1_PCLK(reset_ctrl, SYS_CLK_EN0, 1); -static A1_PCLK(analog_ctrl, SYS_CLK_EN0, 2); -static A1_PCLK(pwr_ctrl, SYS_CLK_EN0, 3); -static A1_PCLK(pad_ctrl, SYS_CLK_EN0, 4); -static A1_PCLK(sys_ctrl, SYS_CLK_EN0, 5); -static A1_PCLK(temp_sensor, SYS_CLK_EN0, 6); -static A1_PCLK(am2axi_dev, SYS_CLK_EN0, 7); -static A1_PCLK(spicc_b, SYS_CLK_EN0, 8); -static A1_PCLK(spicc_a, SYS_CLK_EN0, 9); -static A1_PCLK(msr, SYS_CLK_EN0, 10); -static A1_PCLK(audio, SYS_CLK_EN0, 11); -static A1_PCLK(jtag_ctrl, SYS_CLK_EN0, 12); -static A1_PCLK(saradc_en, SYS_CLK_EN0, 13); -static A1_PCLK(pwm_ef, SYS_CLK_EN0, 14); -static A1_PCLK(pwm_cd, SYS_CLK_EN0, 15); -static A1_PCLK(pwm_ab, SYS_CLK_EN0, 16); -static A1_PCLK(cec, SYS_CLK_EN0, 17); -static A1_PCLK(i2c_s, SYS_CLK_EN0, 18); -static A1_PCLK(ir_ctrl, SYS_CLK_EN0, 19); -static A1_PCLK(i2c_m_d, SYS_CLK_EN0, 20); -static A1_PCLK(i2c_m_c, SYS_CLK_EN0, 21); -static A1_PCLK(i2c_m_b, SYS_CLK_EN0, 22); -static A1_PCLK(i2c_m_a, SYS_CLK_EN0, 23); -static A1_PCLK(acodec, SYS_CLK_EN0, 24); -static A1_PCLK(otp, SYS_CLK_EN0, 25); -static A1_PCLK(sd_emmc_a, SYS_CLK_EN0, 26); -static A1_PCLK(usb_phy, SYS_CLK_EN0, 27); -static A1_PCLK(usb_ctrl, SYS_CLK_EN0, 28); -static A1_PCLK(sys_dspb, SYS_CLK_EN0, 29); -static A1_PCLK(sys_dspa, SYS_CLK_EN0, 30); -static A1_PCLK(dma, SYS_CLK_EN0, 31); - -static A1_PCLK(irq_ctrl, SYS_CLK_EN1, 0); -static A1_PCLK(nic, SYS_CLK_EN1, 1); -static A1_PCLK(gic, SYS_CLK_EN1, 2); -static A1_PCLK(uart_c, SYS_CLK_EN1, 3); -static A1_PCLK(uart_b, SYS_CLK_EN1, 4); -static A1_PCLK(uart_a, SYS_CLK_EN1, 5); -static A1_PCLK(sys_psram, SYS_CLK_EN1, 6); -static A1_PCLK(rsa, SYS_CLK_EN1, 8); -static A1_PCLK(coresight, SYS_CLK_EN1, 9); - -static A1_PCLK(am2axi_vad, AXI_CLK_EN, 0); -static A1_PCLK(audio_vad, AXI_CLK_EN, 1); -static A1_PCLK(axi_dmc, AXI_CLK_EN, 3); -static A1_PCLK(axi_psram, AXI_CLK_EN, 4); -static A1_PCLK(ramb, AXI_CLK_EN, 5); -static A1_PCLK(rama, AXI_CLK_EN, 6); -static A1_PCLK(axi_spifc, AXI_CLK_EN, 7); -static A1_PCLK(axi_nic, AXI_CLK_EN, 8); -static A1_PCLK(axi_dma, AXI_CLK_EN, 9); -static A1_PCLK(cpu_ctrl, AXI_CLK_EN, 10); -static A1_PCLK(rom, AXI_CLK_EN, 11); -static A1_PCLK(prod_i2c, AXI_CLK_EN, 12); +#define A1_PCLK(_name, _reg, _bit, _flags) \ + MESON_PCLK(a1_##_name, _reg, _bit, &a1_sys.hw, _flags) + +/* + * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic re= asons + * Users are encouraged to test without it and submit changes to: + * - remove the flag if not necessary + * - replace the flag with something more adequate, such as CLK_IS_CRITIC= AL, + * if appropriate. + * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirab= le + * for a particular clock. + */ +static A1_PCLK(clktree, SYS_CLK_EN0, 0, CLK_IGNORE_UNUSED); +static A1_PCLK(reset_ctrl, SYS_CLK_EN0, 1, CLK_IGNORE_UNUSED); +static A1_PCLK(analog_ctrl, SYS_CLK_EN0, 2, CLK_IGNORE_UNUSED); +static A1_PCLK(pwr_ctrl, SYS_CLK_EN0, 3, CLK_IGNORE_UNUSED); +static A1_PCLK(pad_ctrl, SYS_CLK_EN0, 4, CLK_IGNORE_UNUSED); +static A1_PCLK(sys_ctrl, SYS_CLK_EN0, 5, CLK_IGNORE_UNUSED); +static A1_PCLK(temp_sensor, SYS_CLK_EN0, 6, CLK_IGNORE_UNUSED); +static A1_PCLK(am2axi_dev, SYS_CLK_EN0, 7, CLK_IGNORE_UNUSED); +static A1_PCLK(spicc_b, SYS_CLK_EN0, 8, CLK_IGNORE_UNUSED); +static A1_PCLK(spicc_a, SYS_CLK_EN0, 9, CLK_IGNORE_UNUSED); +static A1_PCLK(msr, SYS_CLK_EN0, 10, CLK_IGNORE_UNUSED); +static A1_PCLK(audio, SYS_CLK_EN0, 11, CLK_IGNORE_UNUSED); +static A1_PCLK(jtag_ctrl, SYS_CLK_EN0, 12, CLK_IGNORE_UNUSED); +static A1_PCLK(saradc_en, SYS_CLK_EN0, 13, CLK_IGNORE_UNUSED); +static A1_PCLK(pwm_ef, SYS_CLK_EN0, 14, CLK_IGNORE_UNUSED); +static A1_PCLK(pwm_cd, SYS_CLK_EN0, 15, CLK_IGNORE_UNUSED); +static A1_PCLK(pwm_ab, SYS_CLK_EN0, 16, CLK_IGNORE_UNUSED); +static A1_PCLK(cec, SYS_CLK_EN0, 17, CLK_IGNORE_UNUSED); +static A1_PCLK(i2c_s, SYS_CLK_EN0, 18, CLK_IGNORE_UNUSED); +static A1_PCLK(ir_ctrl, SYS_CLK_EN0, 19, CLK_IGNORE_UNUSED); +static A1_PCLK(i2c_m_d, SYS_CLK_EN0, 20, CLK_IGNORE_UNUSED); +static A1_PCLK(i2c_m_c, SYS_CLK_EN0, 21, CLK_IGNORE_UNUSED); +static A1_PCLK(i2c_m_b, SYS_CLK_EN0, 22, CLK_IGNORE_UNUSED); +static A1_PCLK(i2c_m_a, SYS_CLK_EN0, 23, CLK_IGNORE_UNUSED); +static A1_PCLK(acodec, SYS_CLK_EN0, 24, CLK_IGNORE_UNUSED); +static A1_PCLK(otp, SYS_CLK_EN0, 25, CLK_IGNORE_UNUSED); +static A1_PCLK(sd_emmc_a, SYS_CLK_EN0, 26, CLK_IGNORE_UNUSED); +static A1_PCLK(usb_phy, SYS_CLK_EN0, 27, CLK_IGNORE_UNUSED); +static A1_PCLK(usb_ctrl, SYS_CLK_EN0, 28, CLK_IGNORE_UNUSED); +static A1_PCLK(sys_dspb, SYS_CLK_EN0, 29, CLK_IGNORE_UNUSED); +static A1_PCLK(sys_dspa, SYS_CLK_EN0, 30, CLK_IGNORE_UNUSED); +static A1_PCLK(dma, SYS_CLK_EN0, 31, CLK_IGNORE_UNUSED); + +static A1_PCLK(irq_ctrl, SYS_CLK_EN1, 0, CLK_IGNORE_UNUSED); +static A1_PCLK(nic, SYS_CLK_EN1, 1, CLK_IGNORE_UNUSED); +static A1_PCLK(gic, SYS_CLK_EN1, 2, CLK_IGNORE_UNUSED); +static A1_PCLK(uart_c, SYS_CLK_EN1, 3, CLK_IGNORE_UNUSED); +static A1_PCLK(uart_b, SYS_CLK_EN1, 4, CLK_IGNORE_UNUSED); +static A1_PCLK(uart_a, SYS_CLK_EN1, 5, CLK_IGNORE_UNUSED); +static A1_PCLK(sys_psram, SYS_CLK_EN1, 6, CLK_IGNORE_UNUSED); +static A1_PCLK(rsa, SYS_CLK_EN1, 8, CLK_IGNORE_UNUSED); +static A1_PCLK(coresight, SYS_CLK_EN1, 9, CLK_IGNORE_UNUSED); + +static A1_PCLK(am2axi_vad, AXI_CLK_EN, 0, CLK_IGNORE_UNUSED); +static A1_PCLK(audio_vad, AXI_CLK_EN, 1, CLK_IGNORE_UNUSED); +static A1_PCLK(axi_dmc, AXI_CLK_EN, 3, CLK_IGNORE_UNUSED); +static A1_PCLK(axi_psram, AXI_CLK_EN, 4, CLK_IGNORE_UNUSED); +static A1_PCLK(ramb, AXI_CLK_EN, 5, CLK_IGNORE_UNUSED); +static A1_PCLK(rama, AXI_CLK_EN, 6, CLK_IGNORE_UNUSED); +static A1_PCLK(axi_spifc, AXI_CLK_EN, 7, CLK_IGNORE_UNUSED); +static A1_PCLK(axi_nic, AXI_CLK_EN, 8, CLK_IGNORE_UNUSED); +static A1_PCLK(axi_dma, AXI_CLK_EN, 9, CLK_IGNORE_UNUSED); +static A1_PCLK(cpu_ctrl, AXI_CLK_EN, 10, CLK_IGNORE_UNUSED); +static A1_PCLK(rom, AXI_CLK_EN, 11, CLK_IGNORE_UNUSED); +static A1_PCLK(prod_i2c, AXI_CLK_EN, 12, CLK_IGNORE_UNUSED); =20 /* Array of all clocks registered by this provider */ static struct clk_hw *a1_peripherals_hw_clks[] =3D { diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c index efc33fd18c197df233d537e5f8244a376d4d0924..74c2f51424f11cc04a80a3a4918= e4de0a5d11d08 100644 --- a/drivers/clk/meson/axg-aoclk.c +++ b/drivers/clk/meson/axg-aoclk.c @@ -34,7 +34,7 @@ #define AO_RTC_ALT_CLK_CNTL0 0x94 #define AO_RTC_ALT_CLK_CNTL1 0x98 =20 -#define AXG_AO_GATE(_name, _bit) \ +#define AXG_AO_GATE(_name, _bit, _flags) \ static struct clk_regmap axg_ao_##_name =3D { \ .data =3D &(struct clk_regmap_gate_data) { \ .offset =3D (AO_RTI_GEN_CNTL_REG0), \ @@ -47,17 +47,17 @@ static struct clk_regmap axg_ao_##_name =3D { \ .fw_name =3D "mpeg-clk", \ }, \ .num_parents =3D 1, \ - .flags =3D CLK_IGNORE_UNUSED, \ + .flags =3D (_flags), \ }, \ } =20 -AXG_AO_GATE(remote, 0); -AXG_AO_GATE(i2c_master, 1); -AXG_AO_GATE(i2c_slave, 2); -AXG_AO_GATE(uart1, 3); -AXG_AO_GATE(uart2, 5); -AXG_AO_GATE(ir_blaster, 6); -AXG_AO_GATE(saradc, 7); +AXG_AO_GATE(remote, 0, CLK_IGNORE_UNUSED); +AXG_AO_GATE(i2c_master, 1, CLK_IGNORE_UNUSED); +AXG_AO_GATE(i2c_slave, 2, CLK_IGNORE_UNUSED); +AXG_AO_GATE(uart1, 3, CLK_IGNORE_UNUSED); +AXG_AO_GATE(uart2, 5, CLK_IGNORE_UNUSED); +AXG_AO_GATE(ir_blaster, 6, CLK_IGNORE_UNUSED); +AXG_AO_GATE(saradc, 7, CLK_IGNORE_UNUSED); =20 static struct clk_regmap axg_ao_cts_oscin =3D { .data =3D &(struct clk_regmap_gate_data){ diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 021bc7658f7f49911835abd22badac3eba64a10c..fd9a7a362a1be1d8a584f855f45= 4daa354ae2ade 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -1915,59 +1915,69 @@ static struct clk_regmap axg_gen_clk =3D { }, }; =20 -#define AXG_PCLK(_name, _reg, _bit) \ - MESON_PCLK(axg_##_name, _reg, _bit, &axg_clk81.hw) - -/* Everything Else (EE) domain gates */ -static AXG_PCLK(ddr, HHI_GCLK_MPEG0, 0); -static AXG_PCLK(audio_locker, HHI_GCLK_MPEG0, 2); -static AXG_PCLK(mipi_dsi_host, HHI_GCLK_MPEG0, 3); -static AXG_PCLK(isa, HHI_GCLK_MPEG0, 5); -static AXG_PCLK(pl301, HHI_GCLK_MPEG0, 6); -static AXG_PCLK(periphs, HHI_GCLK_MPEG0, 7); -static AXG_PCLK(spicc_0, HHI_GCLK_MPEG0, 8); -static AXG_PCLK(i2c, HHI_GCLK_MPEG0, 9); -static AXG_PCLK(rng0, HHI_GCLK_MPEG0, 12); -static AXG_PCLK(uart0, HHI_GCLK_MPEG0, 13); -static AXG_PCLK(mipi_dsi_phy, HHI_GCLK_MPEG0, 14); -static AXG_PCLK(spicc_1, HHI_GCLK_MPEG0, 15); -static AXG_PCLK(pcie_a, HHI_GCLK_MPEG0, 16); -static AXG_PCLK(pcie_b, HHI_GCLK_MPEG0, 17); -static AXG_PCLK(hiu_reg, HHI_GCLK_MPEG0, 19); -static AXG_PCLK(assist_misc, HHI_GCLK_MPEG0, 23); -static AXG_PCLK(emmc_b, HHI_GCLK_MPEG0, 25); -static AXG_PCLK(emmc_c, HHI_GCLK_MPEG0, 26); -static AXG_PCLK(dma, HHI_GCLK_MPEG0, 27); -static AXG_PCLK(spi, HHI_GCLK_MPEG0, 30); - -static AXG_PCLK(audio, HHI_GCLK_MPEG1, 0); -static AXG_PCLK(eth_core, HHI_GCLK_MPEG1, 3); -static AXG_PCLK(uart1, HHI_GCLK_MPEG1, 16); -static AXG_PCLK(g2d, HHI_GCLK_MPEG1, 20); -static AXG_PCLK(usb0, HHI_GCLK_MPEG1, 21); -static AXG_PCLK(usb1, HHI_GCLK_MPEG1, 22); -static AXG_PCLK(reset, HHI_GCLK_MPEG1, 23); -static AXG_PCLK(usb_general, HHI_GCLK_MPEG1, 26); -static AXG_PCLK(ahb_arb0, HHI_GCLK_MPEG1, 29); -static AXG_PCLK(efuse, HHI_GCLK_MPEG1, 30); -static AXG_PCLK(boot_rom, HHI_GCLK_MPEG1, 31); - -static AXG_PCLK(ahb_data_bus, HHI_GCLK_MPEG2, 1); -static AXG_PCLK(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); -static AXG_PCLK(usb1_to_ddr, HHI_GCLK_MPEG2, 8); -static AXG_PCLK(usb0_to_ddr, HHI_GCLK_MPEG2, 9); -static AXG_PCLK(mmc_pclk, HHI_GCLK_MPEG2, 11); -static AXG_PCLK(vpu_intr, HHI_GCLK_MPEG2, 25); -static AXG_PCLK(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); -static AXG_PCLK(gic, HHI_GCLK_MPEG2, 30); +#define AXG_PCLK(_name, _reg, _bit, _flags) \ + MESON_PCLK(axg_##_name, _reg, _bit, &axg_clk81.hw, _flags) + +/* + * Everything Else (EE) domain gates + * + * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic re= asons + * Users are encouraged to test without it and submit changes to: + * - remove the flag if not necessary + * - replace the flag with something more adequate, such as CLK_IS_CRITIC= AL, + * if appropriate. + * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirab= le + * for a particular clock. + */ +static AXG_PCLK(ddr, HHI_GCLK_MPEG0, 0, CLK_IGNORE_UNUSED); +static AXG_PCLK(audio_locker, HHI_GCLK_MPEG0, 2, CLK_IGNORE_UNUSED); +static AXG_PCLK(mipi_dsi_host, HHI_GCLK_MPEG0, 3, CLK_IGNORE_UNUSED); +static AXG_PCLK(isa, HHI_GCLK_MPEG0, 5, CLK_IGNORE_UNUSED); +static AXG_PCLK(pl301, HHI_GCLK_MPEG0, 6, CLK_IGNORE_UNUSED); +static AXG_PCLK(periphs, HHI_GCLK_MPEG0, 7, CLK_IGNORE_UNUSED); +static AXG_PCLK(spicc_0, HHI_GCLK_MPEG0, 8, CLK_IGNORE_UNUSED); +static AXG_PCLK(i2c, HHI_GCLK_MPEG0, 9, CLK_IGNORE_UNUSED); +static AXG_PCLK(rng0, HHI_GCLK_MPEG0, 12, CLK_IGNORE_UNUSED); +static AXG_PCLK(uart0, HHI_GCLK_MPEG0, 13, CLK_IGNORE_UNUSED); +static AXG_PCLK(mipi_dsi_phy, HHI_GCLK_MPEG0, 14, CLK_IGNORE_UNUSED); +static AXG_PCLK(spicc_1, HHI_GCLK_MPEG0, 15, CLK_IGNORE_UNUSED); +static AXG_PCLK(pcie_a, HHI_GCLK_MPEG0, 16, CLK_IGNORE_UNUSED); +static AXG_PCLK(pcie_b, HHI_GCLK_MPEG0, 17, CLK_IGNORE_UNUSED); +static AXG_PCLK(hiu_reg, HHI_GCLK_MPEG0, 19, CLK_IGNORE_UNUSED); +static AXG_PCLK(assist_misc, HHI_GCLK_MPEG0, 23, CLK_IGNORE_UNUSED); +static AXG_PCLK(emmc_b, HHI_GCLK_MPEG0, 25, CLK_IGNORE_UNUSED); +static AXG_PCLK(emmc_c, HHI_GCLK_MPEG0, 26, CLK_IGNORE_UNUSED); +static AXG_PCLK(dma, HHI_GCLK_MPEG0, 27, CLK_IGNORE_UNUSED); +static AXG_PCLK(spi, HHI_GCLK_MPEG0, 30, CLK_IGNORE_UNUSED); + +static AXG_PCLK(audio, HHI_GCLK_MPEG1, 0, CLK_IGNORE_UNUSED); +static AXG_PCLK(eth_core, HHI_GCLK_MPEG1, 3, CLK_IGNORE_UNUSED); +static AXG_PCLK(uart1, HHI_GCLK_MPEG1, 16, CLK_IGNORE_UNUSED); +static AXG_PCLK(g2d, HHI_GCLK_MPEG1, 20, CLK_IGNORE_UNUSED); +static AXG_PCLK(usb0, HHI_GCLK_MPEG1, 21, CLK_IGNORE_UNUSED); +static AXG_PCLK(usb1, HHI_GCLK_MPEG1, 22, CLK_IGNORE_UNUSED); +static AXG_PCLK(reset, HHI_GCLK_MPEG1, 23, CLK_IGNORE_UNUSED); +static AXG_PCLK(usb_general, HHI_GCLK_MPEG1, 26, CLK_IGNORE_UNUSED); +static AXG_PCLK(ahb_arb0, HHI_GCLK_MPEG1, 29, CLK_IGNORE_UNUSED); +static AXG_PCLK(efuse, HHI_GCLK_MPEG1, 30, CLK_IGNORE_UNUSED); +static AXG_PCLK(boot_rom, HHI_GCLK_MPEG1, 31, CLK_IGNORE_UNUSED); + +static AXG_PCLK(ahb_data_bus, HHI_GCLK_MPEG2, 1, CLK_IGNORE_UNUSED); +static AXG_PCLK(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2, CLK_IGNORE_UNUSED); +static AXG_PCLK(usb1_to_ddr, HHI_GCLK_MPEG2, 8, CLK_IGNORE_UNUSED); +static AXG_PCLK(usb0_to_ddr, HHI_GCLK_MPEG2, 9, CLK_IGNORE_UNUSED); +static AXG_PCLK(mmc_pclk, HHI_GCLK_MPEG2, 11, CLK_IGNORE_UNUSED); +static AXG_PCLK(vpu_intr, HHI_GCLK_MPEG2, 25, CLK_IGNORE_UNUSED); +static AXG_PCLK(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26, CLK_IGNORE_UNUSED= ); +static AXG_PCLK(gic, HHI_GCLK_MPEG2, 30, CLK_IGNORE_UNUSED); =20 /* Always On (AO) domain gates */ =20 -static AXG_PCLK(ao_media_cpu, HHI_GCLK_AO, 0); -static AXG_PCLK(ao_ahb_sram, HHI_GCLK_AO, 1); -static AXG_PCLK(ao_ahb_bus, HHI_GCLK_AO, 2); -static AXG_PCLK(ao_iface, HHI_GCLK_AO, 3); -static AXG_PCLK(ao_i2c, HHI_GCLK_AO, 4); +static AXG_PCLK(ao_media_cpu, HHI_GCLK_AO, 0, CLK_IGNORE_UNUSED); +static AXG_PCLK(ao_ahb_sram, HHI_GCLK_AO, 1, CLK_IGNORE_UNUSED); +static AXG_PCLK(ao_ahb_bus, HHI_GCLK_AO, 2, CLK_IGNORE_UNUSED); +static AXG_PCLK(ao_iface, HHI_GCLK_AO, 3, CLK_IGNORE_UNUSED); +static AXG_PCLK(ao_i2c, HHI_GCLK_AO, 4, CLK_IGNORE_UNUSED); =20 /* Array of all clocks provided by this provider */ =20 diff --git a/drivers/clk/meson/g12a-aoclk.c b/drivers/clk/meson/g12a-aoclk.c index 872a7b800bb86bdf1ead56c3eec7e47f30637dbd..45e4df393feb6f916b6e035ad71= e379e6e30ee99 100644 --- a/drivers/clk/meson/g12a-aoclk.c +++ b/drivers/clk/meson/g12a-aoclk.c @@ -37,13 +37,7 @@ #define AO_RTC_ALT_CLK_CNTL0 0x94 #define AO_RTC_ALT_CLK_CNTL1 0x98 =20 -/* - * Like every other peripheral clock gate in Amlogic Clock drivers, - * we are using CLK_IGNORE_UNUSED here, so we keep the state of the - * bootloader. The goal is to remove this flag at some point. - * Actually removing it will require some extensive test to be done safely. - */ -#define G12A_AO_PCLK(_name, _reg, _bit) \ +#define G12A_AO_PCLK(_name, _reg, _bit, _flags) \ static struct clk_regmap g12a_ao_##_name =3D { \ .data =3D &(struct clk_regmap_gate_data) { \ .offset =3D (_reg), \ @@ -56,26 +50,35 @@ static struct clk_regmap g12a_ao_##_name =3D { \ .fw_name =3D "mpeg-clk", \ }, \ .num_parents =3D 1, \ - .flags =3D CLK_IGNORE_UNUSED, \ + .flags =3D (_flags), \ }, \ } =20 -G12A_AO_PCLK(ahb, AO_CLK_GATE0, 0); -G12A_AO_PCLK(ir_in, AO_CLK_GATE0, 1); -G12A_AO_PCLK(i2c_m0, AO_CLK_GATE0, 2); -G12A_AO_PCLK(i2c_s0, AO_CLK_GATE0, 3); -G12A_AO_PCLK(uart, AO_CLK_GATE0, 4); -G12A_AO_PCLK(prod_i2c, AO_CLK_GATE0, 5); -G12A_AO_PCLK(uart2, AO_CLK_GATE0, 6); -G12A_AO_PCLK(ir_out, AO_CLK_GATE0, 7); -G12A_AO_PCLK(saradc, AO_CLK_GATE0, 8); +/* + * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic re= asons + * Users are encouraged to test without it and submit changes to: + * - remove the flag if not necessary + * - replace the flag with something more adequate, such as CLK_IS_CRITIC= AL, + * if appropriate. + * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirab= le + * for a particular clock. + */ +G12A_AO_PCLK(ahb, AO_CLK_GATE0, 0, CLK_IGNORE_UNUSED); +G12A_AO_PCLK(ir_in, AO_CLK_GATE0, 1, CLK_IGNORE_UNUSED); +G12A_AO_PCLK(i2c_m0, AO_CLK_GATE0, 2, CLK_IGNORE_UNUSED); +G12A_AO_PCLK(i2c_s0, AO_CLK_GATE0, 3, CLK_IGNORE_UNUSED); +G12A_AO_PCLK(uart, AO_CLK_GATE0, 4, CLK_IGNORE_UNUSED); +G12A_AO_PCLK(prod_i2c, AO_CLK_GATE0, 5, CLK_IGNORE_UNUSED); +G12A_AO_PCLK(uart2, AO_CLK_GATE0, 6, CLK_IGNORE_UNUSED); +G12A_AO_PCLK(ir_out, AO_CLK_GATE0, 7, CLK_IGNORE_UNUSED); +G12A_AO_PCLK(saradc, AO_CLK_GATE0, 8, CLK_IGNORE_UNUSED); =20 -G12A_AO_PCLK(mailbox, AO_CLK_GATE0_SP, 0); -G12A_AO_PCLK(m3, AO_CLK_GATE0_SP, 1); -G12A_AO_PCLK(ahb_sram, AO_CLK_GATE0_SP, 2); -G12A_AO_PCLK(rti, AO_CLK_GATE0_SP, 3); -G12A_AO_PCLK(m4_fclk, AO_CLK_GATE0_SP, 4); -G12A_AO_PCLK(m4_hclk, AO_CLK_GATE0_SP, 5); +G12A_AO_PCLK(mailbox, AO_CLK_GATE0_SP, 0, CLK_IGNORE_UNUSED); +G12A_AO_PCLK(m3, AO_CLK_GATE0_SP, 1, CLK_IGNORE_UNUSED); +G12A_AO_PCLK(ahb_sram, AO_CLK_GATE0_SP, 2, CLK_IGNORE_UNUSED); +G12A_AO_PCLK(rti, AO_CLK_GATE0_SP, 3, CLK_IGNORE_UNUSED); +G12A_AO_PCLK(m4_fclk, AO_CLK_GATE0_SP, 4, CLK_IGNORE_UNUSED); +G12A_AO_PCLK(m4_hclk, AO_CLK_GATE0_SP, 5, CLK_IGNORE_UNUSED); =20 static struct clk_regmap g12a_ao_cts_oscin =3D { .data =3D &(struct clk_regmap_gate_data){ diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index c06a4b678b277e8789a33328e25f0c615b3f1b9d..bfa8815647aee9f8c0b373a36b8= b9ae5380c759e 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -4384,89 +4384,99 @@ static struct clk_regmap sm1_nna_core_clk =3D { }, }; =20 -#define G12A_PCLK(_name, _reg, _bit) \ - MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw) - -#define G12A_PCLK_RO(_name, _reg, _bit) \ - MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw) - -/* Everything Else (EE) domain gates */ -static G12A_PCLK(g12a_ddr, HHI_GCLK_MPEG0, 0); -static G12A_PCLK(g12a_dos, HHI_GCLK_MPEG0, 1); -static G12A_PCLK(g12a_audio_locker, HHI_GCLK_MPEG0, 2); -static G12A_PCLK(g12a_mipi_dsi_host, HHI_GCLK_MPEG0, 3); -static G12A_PCLK(g12a_eth_phy, HHI_GCLK_MPEG0, 4); -static G12A_PCLK(g12a_isa, HHI_GCLK_MPEG0, 5); -static G12A_PCLK(g12a_pl301, HHI_GCLK_MPEG0, 6); -static G12A_PCLK(g12a_periphs, HHI_GCLK_MPEG0, 7); -static G12A_PCLK(g12a_spicc_0, HHI_GCLK_MPEG0, 8); -static G12A_PCLK(g12a_i2c, HHI_GCLK_MPEG0, 9); -static G12A_PCLK(g12a_sana, HHI_GCLK_MPEG0, 10); -static G12A_PCLK(g12a_sd, HHI_GCLK_MPEG0, 11); -static G12A_PCLK(g12a_rng0, HHI_GCLK_MPEG0, 12); -static G12A_PCLK(g12a_uart0, HHI_GCLK_MPEG0, 13); -static G12A_PCLK(g12a_spicc_1, HHI_GCLK_MPEG0, 14); -static G12A_PCLK(g12a_hiu_reg, HHI_GCLK_MPEG0, 19); -static G12A_PCLK(g12a_mipi_dsi_phy, HHI_GCLK_MPEG0, 20); -static G12A_PCLK(g12a_assist_misc, HHI_GCLK_MPEG0, 23); -static G12A_PCLK(g12a_emmc_a, HHI_GCLK_MPEG0, 24); -static G12A_PCLK(g12a_emmc_b, HHI_GCLK_MPEG0, 25); -static G12A_PCLK(g12a_emmc_c, HHI_GCLK_MPEG0, 26); -static G12A_PCLK(g12a_audio_codec, HHI_GCLK_MPEG0, 28); - -static G12A_PCLK(g12a_audio, HHI_GCLK_MPEG1, 0); -static G12A_PCLK(g12a_eth_core, HHI_GCLK_MPEG1, 3); -static G12A_PCLK(g12a_demux, HHI_GCLK_MPEG1, 4); -static G12A_PCLK(g12a_audio_ififo, HHI_GCLK_MPEG1, 11); -static G12A_PCLK(g12a_adc, HHI_GCLK_MPEG1, 13); -static G12A_PCLK(g12a_uart1, HHI_GCLK_MPEG1, 16); -static G12A_PCLK(g12a_g2d, HHI_GCLK_MPEG1, 20); -static G12A_PCLK(g12a_reset, HHI_GCLK_MPEG1, 23); -static G12A_PCLK(g12a_pcie_comb, HHI_GCLK_MPEG1, 24); -static G12A_PCLK(g12a_parser, HHI_GCLK_MPEG1, 25); -static G12A_PCLK(g12a_usb_general, HHI_GCLK_MPEG1, 26); -static G12A_PCLK(g12a_pcie_phy, HHI_GCLK_MPEG1, 27); -static G12A_PCLK(g12a_ahb_arb0, HHI_GCLK_MPEG1, 29); - -static G12A_PCLK(g12a_ahb_data_bus, HHI_GCLK_MPEG2, 1); -static G12A_PCLK(g12a_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); -static G12A_PCLK(g12a_htx_hdcp22, HHI_GCLK_MPEG2, 3); -static G12A_PCLK(g12a_htx_pclk, HHI_GCLK_MPEG2, 4); -static G12A_PCLK(g12a_bt656, HHI_GCLK_MPEG2, 6); -static G12A_PCLK(g12a_usb1_to_ddr, HHI_GCLK_MPEG2, 8); -static G12A_PCLK(g12b_mipi_isp_gate, HHI_GCLK_MPEG2, 17); -static G12A_PCLK(g12a_mmc_pclk, HHI_GCLK_MPEG2, 11); -static G12A_PCLK(g12a_uart2, HHI_GCLK_MPEG2, 15); -static G12A_PCLK(g12a_vpu_intr, HHI_GCLK_MPEG2, 25); -static G12A_PCLK(g12b_csi_phy1, HHI_GCLK_MPEG2, 28); -static G12A_PCLK(g12b_csi_phy0, HHI_GCLK_MPEG2, 29); -static G12A_PCLK(g12a_gic, HHI_GCLK_MPEG2, 30); - -static G12A_PCLK(g12a_vclk2_venci0, HHI_GCLK_OTHER, 1); -static G12A_PCLK(g12a_vclk2_venci1, HHI_GCLK_OTHER, 2); -static G12A_PCLK(g12a_vclk2_vencp0, HHI_GCLK_OTHER, 3); -static G12A_PCLK(g12a_vclk2_vencp1, HHI_GCLK_OTHER, 4); -static G12A_PCLK(g12a_vclk2_venct0, HHI_GCLK_OTHER, 5); -static G12A_PCLK(g12a_vclk2_venct1, HHI_GCLK_OTHER, 6); -static G12A_PCLK(g12a_vclk2_other, HHI_GCLK_OTHER, 7); -static G12A_PCLK(g12a_vclk2_enci, HHI_GCLK_OTHER, 8); -static G12A_PCLK(g12a_vclk2_encp, HHI_GCLK_OTHER, 9); -static G12A_PCLK(g12a_dac_clk, HHI_GCLK_OTHER, 10); -static G12A_PCLK(g12a_aoclk_gate, HHI_GCLK_OTHER, 14); -static G12A_PCLK(g12a_iec958_gate, HHI_GCLK_OTHER, 16); -static G12A_PCLK(g12a_enc480p, HHI_GCLK_OTHER, 20); -static G12A_PCLK(g12a_rng1, HHI_GCLK_OTHER, 21); -static G12A_PCLK(g12a_vclk2_enct, HHI_GCLK_OTHER, 22); -static G12A_PCLK(g12a_vclk2_encl, HHI_GCLK_OTHER, 23); -static G12A_PCLK(g12a_vclk2_venclmmc, HHI_GCLK_OTHER, 24); -static G12A_PCLK(g12a_vclk2_vencl, HHI_GCLK_OTHER, 25); -static G12A_PCLK(g12a_vclk2_other1, HHI_GCLK_OTHER, 26); - -static G12A_PCLK_RO(g12a_dma, HHI_GCLK_OTHER2, 0); -static G12A_PCLK_RO(g12a_efuse, HHI_GCLK_OTHER2, 1); -static G12A_PCLK_RO(g12a_rom_boot, HHI_GCLK_OTHER2, 2); -static G12A_PCLK_RO(g12a_reset_sec, HHI_GCLK_OTHER2, 3); -static G12A_PCLK_RO(g12a_sec_ahb_apb3, HHI_GCLK_OTHER2, 4); +#define G12A_PCLK(_name, _reg, _bit, _flags) \ + MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw, _flags) + +#define G12A_PCLK_RO(_name, _reg, _bit, _flags) \ + MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw, _flags) + +/* + * Everything Else (EE) domain gates + * + * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic re= asons + * Users are encouraged to test without it and submit changes to: + * - remove the flag if not necessary + * - replace the flag with something more adequate, such as CLK_IS_CRITIC= AL, + * if appropriate. + * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirab= le + * for a particular clock. + */ +static G12A_PCLK(g12a_ddr, HHI_GCLK_MPEG0, 0, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_dos, HHI_GCLK_MPEG0, 1, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_audio_locker, HHI_GCLK_MPEG0, 2, CLK_IGNORE_UNUSED= ); +static G12A_PCLK(g12a_mipi_dsi_host, HHI_GCLK_MPEG0, 3, CLK_IGNORE_UNUSE= D); +static G12A_PCLK(g12a_eth_phy, HHI_GCLK_MPEG0, 4, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_isa, HHI_GCLK_MPEG0, 5, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_pl301, HHI_GCLK_MPEG0, 6, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_periphs, HHI_GCLK_MPEG0, 7, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_spicc_0, HHI_GCLK_MPEG0, 8, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_i2c, HHI_GCLK_MPEG0, 9, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_sana, HHI_GCLK_MPEG0, 10, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_sd, HHI_GCLK_MPEG0, 11, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_rng0, HHI_GCLK_MPEG0, 12, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_uart0, HHI_GCLK_MPEG0, 13, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_spicc_1, HHI_GCLK_MPEG0, 14, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_hiu_reg, HHI_GCLK_MPEG0, 19, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_mipi_dsi_phy, HHI_GCLK_MPEG0, 20, CLK_IGNORE_UNUSED= ); +static G12A_PCLK(g12a_assist_misc, HHI_GCLK_MPEG0, 23, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_emmc_a, HHI_GCLK_MPEG0, 24, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_emmc_b, HHI_GCLK_MPEG0, 25, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_emmc_c, HHI_GCLK_MPEG0, 26, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_audio_codec, HHI_GCLK_MPEG0, 28, CLK_IGNORE_UNUSED); + +static G12A_PCLK(g12a_audio, HHI_GCLK_MPEG1, 0, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_eth_core, HHI_GCLK_MPEG1, 3, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_demux, HHI_GCLK_MPEG1, 4, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_audio_ififo, HHI_GCLK_MPEG1, 11, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_adc, HHI_GCLK_MPEG1, 13, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_uart1, HHI_GCLK_MPEG1, 16, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_g2d, HHI_GCLK_MPEG1, 20, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_reset, HHI_GCLK_MPEG1, 23, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_pcie_comb, HHI_GCLK_MPEG1, 24, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_parser, HHI_GCLK_MPEG1, 25, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_usb_general, HHI_GCLK_MPEG1, 26, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_pcie_phy, HHI_GCLK_MPEG1, 27, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_ahb_arb0, HHI_GCLK_MPEG1, 29, CLK_IGNORE_UNUSED); + +static G12A_PCLK(g12a_ahb_data_bus, HHI_GCLK_MPEG2, 1, CLK_IGNORE_UNUSED= ); +static G12A_PCLK(g12a_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2, CLK_IGNORE_UNUSED= ); +static G12A_PCLK(g12a_htx_hdcp22, HHI_GCLK_MPEG2, 3, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_htx_pclk, HHI_GCLK_MPEG2, 4, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_bt656, HHI_GCLK_MPEG2, 6, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_usb1_to_ddr, HHI_GCLK_MPEG2, 8, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12b_mipi_isp_gate, HHI_GCLK_MPEG2, 17, CLK_IGNORE_UNUSE= D); +static G12A_PCLK(g12a_mmc_pclk, HHI_GCLK_MPEG2, 11, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_uart2, HHI_GCLK_MPEG2, 15, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_vpu_intr, HHI_GCLK_MPEG2, 25, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12b_csi_phy1, HHI_GCLK_MPEG2, 28, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12b_csi_phy0, HHI_GCLK_MPEG2, 29, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_gic, HHI_GCLK_MPEG2, 30, CLK_IGNORE_UNUSED); + +static G12A_PCLK(g12a_vclk2_venci0, HHI_GCLK_OTHER, 1, CLK_IGNORE_UNUSED= ); +static G12A_PCLK(g12a_vclk2_venci1, HHI_GCLK_OTHER, 2, CLK_IGNORE_UNUSED= ); +static G12A_PCLK(g12a_vclk2_vencp0, HHI_GCLK_OTHER, 3, CLK_IGNORE_UNUSED= ); +static G12A_PCLK(g12a_vclk2_vencp1, HHI_GCLK_OTHER, 4, CLK_IGNORE_UNUSED= ); +static G12A_PCLK(g12a_vclk2_venct0, HHI_GCLK_OTHER, 5, CLK_IGNORE_UNUSED= ); +static G12A_PCLK(g12a_vclk2_venct1, HHI_GCLK_OTHER, 6, CLK_IGNORE_UNUSED= ); +static G12A_PCLK(g12a_vclk2_other, HHI_GCLK_OTHER, 7, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_vclk2_enci, HHI_GCLK_OTHER, 8, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_vclk2_encp, HHI_GCLK_OTHER, 9, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_dac_clk, HHI_GCLK_OTHER, 10, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_aoclk_gate, HHI_GCLK_OTHER, 14, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_iec958_gate, HHI_GCLK_OTHER, 16, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_enc480p, HHI_GCLK_OTHER, 20, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_rng1, HHI_GCLK_OTHER, 21, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_vclk2_enct, HHI_GCLK_OTHER, 22, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_vclk2_encl, HHI_GCLK_OTHER, 23, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_vclk2_venclmmc, HHI_GCLK_OTHER, 24, CLK_IGNORE_UNUS= ED); +static G12A_PCLK(g12a_vclk2_vencl, HHI_GCLK_OTHER, 25, CLK_IGNORE_UNUSED); +static G12A_PCLK(g12a_vclk2_other1, HHI_GCLK_OTHER, 26, CLK_IGNORE_UNUSED= ); + +static G12A_PCLK_RO(g12a_dma, HHI_GCLK_OTHER2, 0, 0); +static G12A_PCLK_RO(g12a_efuse, HHI_GCLK_OTHER2, 1, 0); +static G12A_PCLK_RO(g12a_rom_boot, HHI_GCLK_OTHER2, 2, 0); +static G12A_PCLK_RO(g12a_reset_sec, HHI_GCLK_OTHER2, 3, 0); +static G12A_PCLK_RO(g12a_sec_ahb_apb3, HHI_GCLK_OTHER2, 4, 0); =20 /* Array of all clocks provided by this provider */ static struct clk_hw *g12a_hw_clks[] =3D { diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c index ce8d2e9e071759ab8b8aa8619ad7400f1513c319..2bf45fd7fe4ba0783e736fbbb12= 6209870985b22 100644 --- a/drivers/clk/meson/gxbb-aoclk.c +++ b/drivers/clk/meson/gxbb-aoclk.c @@ -23,7 +23,7 @@ #define AO_RTC_ALT_CLK_CNTL0 0x94 #define AO_RTC_ALT_CLK_CNTL1 0x98 =20 -#define GXBB_AO_PCLK(_name, _bit) \ +#define GXBB_AO_PCLK(_name, _bit, _flags) \ static struct clk_regmap gxbb_ao_##_name =3D { \ .data =3D &(struct clk_regmap_gate_data) { \ .offset =3D AO_RTI_GEN_CNTL_REG0, \ @@ -36,16 +36,16 @@ static struct clk_regmap gxbb_ao_##_name =3D { \ .fw_name =3D "mpeg-clk", \ }, \ .num_parents =3D 1, \ - .flags =3D CLK_IGNORE_UNUSED, \ + .flags =3D (_flags), \ }, \ } =20 -GXBB_AO_PCLK(remote, 0); -GXBB_AO_PCLK(i2c_master, 1); -GXBB_AO_PCLK(i2c_slave, 2); -GXBB_AO_PCLK(uart1, 3); -GXBB_AO_PCLK(uart2, 5); -GXBB_AO_PCLK(ir_blaster, 6); +GXBB_AO_PCLK(remote, 0, CLK_IGNORE_UNUSED); +GXBB_AO_PCLK(i2c_master, 1, CLK_IGNORE_UNUSED); +GXBB_AO_PCLK(i2c_slave, 2, CLK_IGNORE_UNUSED); +GXBB_AO_PCLK(uart1, 3, CLK_IGNORE_UNUSED); +GXBB_AO_PCLK(uart2, 5, CLK_IGNORE_UNUSED); +GXBB_AO_PCLK(ir_blaster, 6, CLK_IGNORE_UNUSED); =20 static struct clk_regmap gxbb_ao_cts_oscin =3D { .data =3D &(struct clk_regmap_gate_data){ diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index 608c2cd34a455f48087dd65809dbcda54f153a71..ccc1490a092814c242e719d4c37= c66c4b3e27f07 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -2721,100 +2721,110 @@ static struct clk_regmap gxbb_gen_clk =3D { }, }; =20 -#define GXBB_PCLK(_name, _reg, _bit) \ - MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw) - -/* Everything Else (EE) domain gates */ -static GXBB_PCLK(gxbb_ddr, HHI_GCLK_MPEG0, 0); -static GXBB_PCLK(gxbb_dos, HHI_GCLK_MPEG0, 1); -static GXBB_PCLK(gxbb_isa, HHI_GCLK_MPEG0, 5); -static GXBB_PCLK(gxbb_pl301, HHI_GCLK_MPEG0, 6); -static GXBB_PCLK(gxbb_periphs, HHI_GCLK_MPEG0, 7); -static GXBB_PCLK(gxbb_spicc, HHI_GCLK_MPEG0, 8); -static GXBB_PCLK(gxbb_i2c, HHI_GCLK_MPEG0, 9); -static GXBB_PCLK(gxbb_sana, HHI_GCLK_MPEG0, 10); -static GXBB_PCLK(gxbb_smart_card, HHI_GCLK_MPEG0, 11); -static GXBB_PCLK(gxbb_rng0, HHI_GCLK_MPEG0, 12); -static GXBB_PCLK(gxbb_uart0, HHI_GCLK_MPEG0, 13); -static GXBB_PCLK(gxbb_sdhc, HHI_GCLK_MPEG0, 14); -static GXBB_PCLK(gxbb_stream, HHI_GCLK_MPEG0, 15); -static GXBB_PCLK(gxbb_async_fifo, HHI_GCLK_MPEG0, 16); -static GXBB_PCLK(gxbb_sdio, HHI_GCLK_MPEG0, 17); -static GXBB_PCLK(gxbb_abuf, HHI_GCLK_MPEG0, 18); -static GXBB_PCLK(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19); -static GXBB_PCLK(gxbb_assist_misc, HHI_GCLK_MPEG0, 23); -static GXBB_PCLK(gxbb_emmc_a, HHI_GCLK_MPEG0, 24); -static GXBB_PCLK(gxbb_emmc_b, HHI_GCLK_MPEG0, 25); -static GXBB_PCLK(gxbb_emmc_c, HHI_GCLK_MPEG0, 26); -static GXBB_PCLK(gxl_acodec, HHI_GCLK_MPEG0, 28); -static GXBB_PCLK(gxbb_spi, HHI_GCLK_MPEG0, 30); - -static GXBB_PCLK(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2); -static GXBB_PCLK(gxbb_eth, HHI_GCLK_MPEG1, 3); -static GXBB_PCLK(gxbb_demux, HHI_GCLK_MPEG1, 4); -static GXBB_PCLK(gxbb_blkmv, HHI_GCLK_MPEG1, 14); -static GXBB_PCLK(gxbb_aiu, HHI_GCLK_MPEG1, 15); -static GXBB_PCLK(gxbb_uart1, HHI_GCLK_MPEG1, 16); -static GXBB_PCLK(gxbb_g2d, HHI_GCLK_MPEG1, 20); -static GXBB_PCLK(gxbb_usb0, HHI_GCLK_MPEG1, 21); -static GXBB_PCLK(gxbb_usb1, HHI_GCLK_MPEG1, 22); -static GXBB_PCLK(gxbb_reset, HHI_GCLK_MPEG1, 23); -static GXBB_PCLK(gxbb_nand, HHI_GCLK_MPEG1, 24); -static GXBB_PCLK(gxbb_dos_parser, HHI_GCLK_MPEG1, 25); -static GXBB_PCLK(gxbb_usb, HHI_GCLK_MPEG1, 26); -static GXBB_PCLK(gxbb_vdin1, HHI_GCLK_MPEG1, 28); -static GXBB_PCLK(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29); -static GXBB_PCLK(gxbb_efuse, HHI_GCLK_MPEG1, 30); -static GXBB_PCLK(gxbb_boot_rom, HHI_GCLK_MPEG1, 31); - -static GXBB_PCLK(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1); -static GXBB_PCLK(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); -static GXBB_PCLK(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3); -static GXBB_PCLK(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4); -static GXBB_PCLK(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); -static GXBB_PCLK(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); -static GXBB_PCLK(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11); -static GXBB_PCLK(gxbb_dvin, HHI_GCLK_MPEG2, 12); -static GXBB_PCLK(gxbb_uart2, HHI_GCLK_MPEG2, 15); -static GXBB_PCLK(gxbb_sar_adc, HHI_GCLK_MPEG2, 22); -static GXBB_PCLK(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25); -static GXBB_PCLK(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); -static GXBB_PCLK(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29); - -static GXBB_PCLK(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1); -static GXBB_PCLK(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2); -static GXBB_PCLK(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3); -static GXBB_PCLK(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4); -static GXBB_PCLK(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8); -static GXBB_PCLK(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9); -static GXBB_PCLK(gxbb_dac_clk, HHI_GCLK_OTHER, 10); -static GXBB_PCLK(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14); -static GXBB_PCLK(gxbb_iec958_gate, HHI_GCLK_OTHER, 16); -static GXBB_PCLK(gxbb_enc480p, HHI_GCLK_OTHER, 20); -static GXBB_PCLK(gxbb_rng1, HHI_GCLK_OTHER, 21); -static GXBB_PCLK(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22); -static GXBB_PCLK(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24); -static GXBB_PCLK(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25); -static GXBB_PCLK(gxbb_vclk_other, HHI_GCLK_OTHER, 26); -static GXBB_PCLK(gxbb_edp, HHI_GCLK_OTHER, 31); +#define GXBB_PCLK(_name, _reg, _bit, _flags) \ + MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw, _flags) + +/* + * Everything Else (EE) domain gates + * + * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic re= asons + * Users are encouraged to test without it and submit changes to: + * - remove the flag if not necessary + * - replace the flag with something more adequate, such as CLK_IS_CRITIC= AL, + * if appropriate. + * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirab= le + * for a particular clock. + */ +static GXBB_PCLK(gxbb_ddr, HHI_GCLK_MPEG0, 0, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_dos, HHI_GCLK_MPEG0, 1, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_isa, HHI_GCLK_MPEG0, 5, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_pl301, HHI_GCLK_MPEG0, 6, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_periphs, HHI_GCLK_MPEG0, 7, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_spicc, HHI_GCLK_MPEG0, 8, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_i2c, HHI_GCLK_MPEG0, 9, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_sana, HHI_GCLK_MPEG0, 10, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_smart_card, HHI_GCLK_MPEG0, 11, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_rng0, HHI_GCLK_MPEG0, 12, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_uart0, HHI_GCLK_MPEG0, 13, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_sdhc, HHI_GCLK_MPEG0, 14, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_stream, HHI_GCLK_MPEG0, 15, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_async_fifo, HHI_GCLK_MPEG0, 16, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_sdio, HHI_GCLK_MPEG0, 17, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_abuf, HHI_GCLK_MPEG0, 18, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_assist_misc, HHI_GCLK_MPEG0, 23, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_emmc_a, HHI_GCLK_MPEG0, 24, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_emmc_b, HHI_GCLK_MPEG0, 25, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_emmc_c, HHI_GCLK_MPEG0, 26, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxl_acodec, HHI_GCLK_MPEG0, 28, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_spi, HHI_GCLK_MPEG0, 30, CLK_IGNORE_UNUSED); + +static GXBB_PCLK(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_eth, HHI_GCLK_MPEG1, 3, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_demux, HHI_GCLK_MPEG1, 4, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_blkmv, HHI_GCLK_MPEG1, 14, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_aiu, HHI_GCLK_MPEG1, 15, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_uart1, HHI_GCLK_MPEG1, 16, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_g2d, HHI_GCLK_MPEG1, 20, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_usb0, HHI_GCLK_MPEG1, 21, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_usb1, HHI_GCLK_MPEG1, 22, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_reset, HHI_GCLK_MPEG1, 23, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_nand, HHI_GCLK_MPEG1, 24, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_dos_parser, HHI_GCLK_MPEG1, 25, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_usb, HHI_GCLK_MPEG1, 26, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_vdin1, HHI_GCLK_MPEG1, 28, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_efuse, HHI_GCLK_MPEG1, 30, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_boot_rom, HHI_GCLK_MPEG1, 31, CLK_IGNORE_UNUSED); + +static GXBB_PCLK(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3, CLK_IGNORE_UNUSE= D); +static GXBB_PCLK(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8, CLK_IGNORE_UNUS= ED); +static GXBB_PCLK(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9, CLK_IGNORE_UNUS= ED); +static GXBB_PCLK(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_dvin, HHI_GCLK_MPEG2, 12, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_uart2, HHI_GCLK_MPEG2, 15, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_sar_adc, HHI_GCLK_MPEG2, 22, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26, CLK_IGNORE_= UNUSED); +static GXBB_PCLK(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29, CLK_IGNORE_UNUSED); + +static GXBB_PCLK(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8, CLK_IGNORE_UNUS= ED); +static GXBB_PCLK(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9, CLK_IGNORE_UNUSE= D); +static GXBB_PCLK(gxbb_dac_clk, HHI_GCLK_OTHER, 10, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_iec958_gate, HHI_GCLK_OTHER, 16, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_enc480p, HHI_GCLK_OTHER, 20, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_rng1, HHI_GCLK_OTHER, 21, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22, CLK_IGNORE_UNUS= ED); +static GXBB_PCLK(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24, CLK_IGNORE_UNUSE= D); +static GXBB_PCLK(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_vclk_other, HHI_GCLK_OTHER, 26, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_edp, HHI_GCLK_OTHER, 31, CLK_IGNORE_UNUSED); =20 /* Always On (AO) domain gates */ =20 -static GXBB_PCLK(gxbb_ao_media_cpu, HHI_GCLK_AO, 0); -static GXBB_PCLK(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1); -static GXBB_PCLK(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2); -static GXBB_PCLK(gxbb_ao_iface, HHI_GCLK_AO, 3); -static GXBB_PCLK(gxbb_ao_i2c, HHI_GCLK_AO, 4); +static GXBB_PCLK(gxbb_ao_media_cpu, HHI_GCLK_AO, 0, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_ao_iface, HHI_GCLK_AO, 3, CLK_IGNORE_UNUSED); +static GXBB_PCLK(gxbb_ao_i2c, HHI_GCLK_AO, 4, CLK_IGNORE_UNUSED); =20 /* AIU gates */ -static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw); -static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw); -static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw); -static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw); -static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw); -static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw); -static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw); -static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw); +static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw, CLK_IGN= ORE_UNUSED); +static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw, CLK= _IGNORE_UNUSED); +static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw, CL= K_IGNORE_UNUSED); +static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw, CLK_= IGNORE_UNUSED); +static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw, CL= K_IGNORE_UNUSED); +static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw, CLK_= IGNORE_UNUSED); +static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw,= CLK_IGNORE_UNUSED); +static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw, CLK_IG= NORE_UNUSED); =20 /* Array of all clocks provided by this provider */ =20 diff --git a/drivers/clk/meson/meson-clkc-utils.h b/drivers/clk/meson/meson= -clkc-utils.h index 3e1fb7efe6da1f5d8e55993541d12d40464a47f5..03e38992c4c73ff4ee24f0fa99b= 7c34134376992 100644 --- a/drivers/clk/meson/meson-clkc-utils.h +++ b/drivers/clk/meson/meson-clkc-utils.h @@ -27,7 +27,7 @@ struct meson_clkc_data { int meson_clkc_syscon_probe(struct platform_device *pdev); int meson_clkc_mmio_probe(struct platform_device *pdev); =20 -#define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ +#define __MESON_PCLK(_name, _reg, _bit, _ops, _pname, _flags) \ struct clk_regmap _name =3D { \ .data =3D &(struct clk_regmap_gate_data) { \ .offset =3D (_reg), \ @@ -38,14 +38,14 @@ struct clk_regmap _name =3D { \ .ops =3D _ops, \ .parent_hws =3D (const struct clk_hw *[]) { _pname }, \ .num_parents =3D 1, \ - .flags =3D CLK_IGNORE_UNUSED, \ + .flags =3D (_flags), \ }, \ } =20 -#define MESON_PCLK(_name, _reg, _bit, _pname) \ - __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname) +#define MESON_PCLK(_name, _reg, _bit, _pname, _flags) \ + __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname, _flags) =20 -#define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ - __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname) +#define MESON_PCLK_RO(_name, _reg, _bit, _pname, _flags) \ + __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname, _flags) =20 #endif diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index 446e57d45d8deeab9516a923ddddcba7fa274203..a16ebbbf664cdd56b2c74db4f88= a8d0a22d2ddc3 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -2701,100 +2701,109 @@ static struct clk_regmap meson8b_cts_i958 =3D { }, }; =20 -#define MESON8B_PCLK(_name, _reg, _bit) \ - MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw) - -/* Everything Else (EE) domain gates */ - -static MESON8B_PCLK(meson8b_ddr, HHI_GCLK_MPEG0, 0); -static MESON8B_PCLK(meson8b_dos, HHI_GCLK_MPEG0, 1); -static MESON8B_PCLK(meson8b_isa, HHI_GCLK_MPEG0, 5); -static MESON8B_PCLK(meson8b_pl301, HHI_GCLK_MPEG0, 6); -static MESON8B_PCLK(meson8b_periphs, HHI_GCLK_MPEG0, 7); -static MESON8B_PCLK(meson8b_spicc, HHI_GCLK_MPEG0, 8); -static MESON8B_PCLK(meson8b_i2c, HHI_GCLK_MPEG0, 9); -static MESON8B_PCLK(meson8b_sar_adc, HHI_GCLK_MPEG0, 10); -static MESON8B_PCLK(meson8b_smart_card, HHI_GCLK_MPEG0, 11); -static MESON8B_PCLK(meson8b_rng0, HHI_GCLK_MPEG0, 12); -static MESON8B_PCLK(meson8b_uart0, HHI_GCLK_MPEG0, 13); -static MESON8B_PCLK(meson8b_sdhc, HHI_GCLK_MPEG0, 14); -static MESON8B_PCLK(meson8b_stream, HHI_GCLK_MPEG0, 15); -static MESON8B_PCLK(meson8b_async_fifo, HHI_GCLK_MPEG0, 16); -static MESON8B_PCLK(meson8b_sdio, HHI_GCLK_MPEG0, 17); -static MESON8B_PCLK(meson8b_abuf, HHI_GCLK_MPEG0, 18); -static MESON8B_PCLK(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19); -static MESON8B_PCLK(meson8b_assist_misc, HHI_GCLK_MPEG0, 23); -static MESON8B_PCLK(meson8b_spi, HHI_GCLK_MPEG0, 30); - -static MESON8B_PCLK(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2); -static MESON8B_PCLK(meson8b_eth, HHI_GCLK_MPEG1, 3); -static MESON8B_PCLK(meson8b_demux, HHI_GCLK_MPEG1, 4); -static MESON8B_PCLK(meson8b_blkmv, HHI_GCLK_MPEG1, 14); -static MESON8B_PCLK(meson8b_aiu, HHI_GCLK_MPEG1, 15); -static MESON8B_PCLK(meson8b_uart1, HHI_GCLK_MPEG1, 16); -static MESON8B_PCLK(meson8b_g2d, HHI_GCLK_MPEG1, 20); -static MESON8B_PCLK(meson8b_usb0, HHI_GCLK_MPEG1, 21); -static MESON8B_PCLK(meson8b_usb1, HHI_GCLK_MPEG1, 22); -static MESON8B_PCLK(meson8b_reset, HHI_GCLK_MPEG1, 23); -static MESON8B_PCLK(meson8b_nand, HHI_GCLK_MPEG1, 24); -static MESON8B_PCLK(meson8b_dos_parser, HHI_GCLK_MPEG1, 25); -static MESON8B_PCLK(meson8b_usb, HHI_GCLK_MPEG1, 26); -static MESON8B_PCLK(meson8b_vdin1, HHI_GCLK_MPEG1, 28); -static MESON8B_PCLK(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29); -static MESON8B_PCLK(meson8b_efuse, HHI_GCLK_MPEG1, 30); -static MESON8B_PCLK(meson8b_boot_rom, HHI_GCLK_MPEG1, 31); - -static MESON8B_PCLK(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1); -static MESON8B_PCLK(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2); -static MESON8B_PCLK(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3); -static MESON8B_PCLK(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4); -static MESON8B_PCLK(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8); -static MESON8B_PCLK(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9); -static MESON8B_PCLK(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11); -static MESON8B_PCLK(meson8b_dvin, HHI_GCLK_MPEG2, 12); -static MESON8B_PCLK(meson8b_uart2, HHI_GCLK_MPEG2, 15); -static MESON8B_PCLK(meson8b_sana, HHI_GCLK_MPEG2, 22); -static MESON8B_PCLK(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25); -static MESON8B_PCLK(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); -static MESON8B_PCLK(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29); - -static MESON8B_PCLK(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1); -static MESON8B_PCLK(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2); -static MESON8B_PCLK(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3); -static MESON8B_PCLK(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4); -static MESON8B_PCLK(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8); -static MESON8B_PCLK(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9); -static MESON8B_PCLK(meson8b_dac_clk, HHI_GCLK_OTHER, 10); -static MESON8B_PCLK(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14); -static MESON8B_PCLK(meson8b_iec958_gate, HHI_GCLK_OTHER, 16); -static MESON8B_PCLK(meson8b_enc480p, HHI_GCLK_OTHER, 20); -static MESON8B_PCLK(meson8b_rng1, HHI_GCLK_OTHER, 21); -static MESON8B_PCLK(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22); -static MESON8B_PCLK(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24); -static MESON8B_PCLK(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25); -static MESON8B_PCLK(meson8b_vclk2_other, HHI_GCLK_OTHER, 26); -static MESON8B_PCLK(meson8b_edp, HHI_GCLK_OTHER, 31); +#define MESON8B_PCLK(_name, _reg, _bit, _flags) \ + MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw, _flags) + +/* + * Everything Else (EE) domain gates + * + * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic re= asons + * Users are encouraged to test without it and submit changes to: + * - remove the flag if not necessary + * - replace the flag with something more adequate, such as CLK_IS_CRITIC= AL, + * if appropriate. + * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirab= le + * for a particular clock. + */ +static MESON8B_PCLK(meson8b_ddr, HHI_GCLK_MPEG0, 0, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_dos, HHI_GCLK_MPEG0, 1, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_isa, HHI_GCLK_MPEG0, 5, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_pl301, HHI_GCLK_MPEG0, 6, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_periphs, HHI_GCLK_MPEG0, 7, CLK_IGNORE_UNUSE= D); +static MESON8B_PCLK(meson8b_spicc, HHI_GCLK_MPEG0, 8, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_i2c, HHI_GCLK_MPEG0, 9, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_sar_adc, HHI_GCLK_MPEG0, 10, CLK_IGNORE_UNUSE= D); +static MESON8B_PCLK(meson8b_smart_card, HHI_GCLK_MPEG0, 11, CLK_IGNORE_UN= USED); +static MESON8B_PCLK(meson8b_rng0, HHI_GCLK_MPEG0, 12, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_uart0, HHI_GCLK_MPEG0, 13, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_sdhc, HHI_GCLK_MPEG0, 14, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_stream, HHI_GCLK_MPEG0, 15, CLK_IGNORE_UNUSED= ); +static MESON8B_PCLK(meson8b_async_fifo, HHI_GCLK_MPEG0, 16, CLK_IGNORE_UN= USED); +static MESON8B_PCLK(meson8b_sdio, HHI_GCLK_MPEG0, 17, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_abuf, HHI_GCLK_MPEG0, 18, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_hiu_iface, HHI_GCLK_MPEG0, 19, CLK_IGNORE_UNU= SED); +static MESON8B_PCLK(meson8b_assist_misc, HHI_GCLK_MPEG0, 23, CLK_IGNORE_UN= USED); +static MESON8B_PCLK(meson8b_spi, HHI_GCLK_MPEG0, 30, CLK_IGNORE_UNUSED); + +static MESON8B_PCLK(meson8b_i2s_spdif, HHI_GCLK_MPEG1, 2, CLK_IGNORE_UNU= SED); +static MESON8B_PCLK(meson8b_eth, HHI_GCLK_MPEG1, 3, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_demux, HHI_GCLK_MPEG1, 4, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_blkmv, HHI_GCLK_MPEG1, 14, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_aiu, HHI_GCLK_MPEG1, 15, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_uart1, HHI_GCLK_MPEG1, 16, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_g2d, HHI_GCLK_MPEG1, 20, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_usb0, HHI_GCLK_MPEG1, 21, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_usb1, HHI_GCLK_MPEG1, 22, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_reset, HHI_GCLK_MPEG1, 23, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_nand, HHI_GCLK_MPEG1, 24, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_dos_parser, HHI_GCLK_MPEG1, 25, CLK_IGNORE_UN= USED); +static MESON8B_PCLK(meson8b_usb, HHI_GCLK_MPEG1, 26, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_vdin1, HHI_GCLK_MPEG1, 28, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_ahb_arb0, HHI_GCLK_MPEG1, 29, CLK_IGNORE_UNUS= ED); +static MESON8B_PCLK(meson8b_efuse, HHI_GCLK_MPEG1, 30, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_boot_rom, HHI_GCLK_MPEG1, 31, CLK_IGNORE_UNUS= ED); + +static MESON8B_PCLK(meson8b_ahb_data_bus, HHI_GCLK_MPEG2, 1, CLK_IGNORE_U= NUSED); +static MESON8B_PCLK(meson8b_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2, CLK_IGNORE_U= NUSED); +static MESON8B_PCLK(meson8b_hdmi_intr_sync, HHI_GCLK_MPEG2, 3, CLK_IGNORE= _UNUSED); +static MESON8B_PCLK(meson8b_hdmi_pclk, HHI_GCLK_MPEG2, 4, CLK_IGNORE_UNU= SED); +static MESON8B_PCLK(meson8b_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8, CLK_IGNOR= E_UNUSED); +static MESON8B_PCLK(meson8b_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9, CLK_IGNOR= E_UNUSED); +static MESON8B_PCLK(meson8b_mmc_pclk, HHI_GCLK_MPEG2, 11, CLK_IGNORE_UNUS= ED); +static MESON8B_PCLK(meson8b_dvin, HHI_GCLK_MPEG2, 12, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_uart2, HHI_GCLK_MPEG2, 15, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_sana, HHI_GCLK_MPEG2, 22, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_vpu_intr, HHI_GCLK_MPEG2, 25, CLK_IGNORE_UNUS= ED); +static MESON8B_PCLK(meson8b_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26, CLK_I= GNORE_UNUSED); +static MESON8B_PCLK(meson8b_clk81_a9, HHI_GCLK_MPEG2, 29, CLK_IGNORE_UNUS= ED); + +static MESON8B_PCLK(meson8b_vclk2_venci0, HHI_GCLK_OTHER, 1, CLK_IGNORE_U= NUSED); +static MESON8B_PCLK(meson8b_vclk2_venci1, HHI_GCLK_OTHER, 2, CLK_IGNORE_U= NUSED); +static MESON8B_PCLK(meson8b_vclk2_vencp0, HHI_GCLK_OTHER, 3, CLK_IGNORE_U= NUSED); +static MESON8B_PCLK(meson8b_vclk2_vencp1, HHI_GCLK_OTHER, 4, CLK_IGNORE_U= NUSED); +static MESON8B_PCLK(meson8b_gclk_venci_int, HHI_GCLK_OTHER, 8, CLK_IGNORE= _UNUSED); +static MESON8B_PCLK(meson8b_gclk_vencp_int, HHI_GCLK_OTHER, 9, CLK_IGNORE= _UNUSED); +static MESON8B_PCLK(meson8b_dac_clk, HHI_GCLK_OTHER, 10, CLK_IGNORE_UNUSE= D); +static MESON8B_PCLK(meson8b_aoclk_gate, HHI_GCLK_OTHER, 14, CLK_IGNORE_UN= USED); +static MESON8B_PCLK(meson8b_iec958_gate, HHI_GCLK_OTHER, 16, CLK_IGNORE_UN= USED); +static MESON8B_PCLK(meson8b_enc480p, HHI_GCLK_OTHER, 20, CLK_IGNORE_UNUSE= D); +static MESON8B_PCLK(meson8b_rng1, HHI_GCLK_OTHER, 21, CLK_IGNORE_UNUSED); +static MESON8B_PCLK(meson8b_gclk_vencl_int, HHI_GCLK_OTHER, 22, CLK_IGNORE= _UNUSED); +static MESON8B_PCLK(meson8b_vclk2_venclmcc, HHI_GCLK_OTHER, 24, CLK_IGNORE= _UNUSED); +static MESON8B_PCLK(meson8b_vclk2_vencl, HHI_GCLK_OTHER, 25, CLK_IGNORE_UN= USED); +static MESON8B_PCLK(meson8b_vclk2_other, HHI_GCLK_OTHER, 26, CLK_IGNORE_UN= USED); +static MESON8B_PCLK(meson8b_edp, HHI_GCLK_OTHER, 31, CLK_IGNORE_UNUSED); =20 /* AIU gates */ -static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, &meson8b_aiu.hw); +static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, &meson8b_aiu.hw, CL= K_IGNORE_UNUSED); =20 -#define MESON_AIU_PCLK(_name, _reg, _bit) \ - MESON_PCLK(_name, _reg, _bit, &meson8b_aiu_glue.hw) +#define MESON_AIU_PCLK(_name, _reg, _bit, _flags) \ + MESON_PCLK(_name, _reg, _bit, &meson8b_aiu_glue.hw, _flags) =20 -static MESON_AIU_PCLK(meson8b_iec958, HHI_GCLK_MPEG1, 7); -static MESON_AIU_PCLK(meson8b_i2s_out, HHI_GCLK_MPEG1, 8); -static MESON_AIU_PCLK(meson8b_amclk, HHI_GCLK_MPEG1, 9); -static MESON_AIU_PCLK(meson8b_aififo2, HHI_GCLK_MPEG1, 10); -static MESON_AIU_PCLK(meson8b_mixer, HHI_GCLK_MPEG1, 11); -static MESON_AIU_PCLK(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12); -static MESON_AIU_PCLK(meson8b_adc, HHI_GCLK_MPEG1, 13); +static MESON_AIU_PCLK(meson8b_iec958, HHI_GCLK_MPEG1, 7, CLK_IGNORE_UNUS= ED); +static MESON_AIU_PCLK(meson8b_i2s_out, HHI_GCLK_MPEG1, 8, CLK_IGNORE_UNU= SED); +static MESON_AIU_PCLK(meson8b_amclk, HHI_GCLK_MPEG1, 9, CLK_IGNORE_UNUSE= D); +static MESON_AIU_PCLK(meson8b_aififo2, HHI_GCLK_MPEG1, 10, CLK_IGNORE_UNU= SED); +static MESON_AIU_PCLK(meson8b_mixer, HHI_GCLK_MPEG1, 11, CLK_IGNORE_UNUSE= D); +static MESON_AIU_PCLK(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12, CLK_IGNORE_= UNUSED); +static MESON_AIU_PCLK(meson8b_adc, HHI_GCLK_MPEG1, 13, CLK_IGNORE_UNUSED); =20 /* Always On (AO) domain gates */ =20 -static MESON8B_PCLK(meson8b_ao_media_cpu, HHI_GCLK_AO, 0); -static MESON8B_PCLK(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1); -static MESON8B_PCLK(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2); -static MESON8B_PCLK(meson8b_ao_iface, HHI_GCLK_AO, 3); +static MESON8B_PCLK(meson8b_ao_media_cpu, HHI_GCLK_AO, 0, CLK_IGNORE_UNUSE= D); +static MESON8B_PCLK(meson8b_ao_ahb_sram, HHI_GCLK_AO, 1, CLK_IGNORE_UNUSED= ); +static MESON8B_PCLK(meson8b_ao_ahb_bus, HHI_GCLK_AO, 2, CLK_IGNORE_UNUSED= ); +static MESON8B_PCLK(meson8b_ao_iface, HHI_GCLK_AO, 3, CLK_IGNORE_UNUSED); =20 static struct clk_hw *meson8_hw_clks[] =3D { [CLKID_PLL_FIXED] =3D &meson8b_fixed_pll.hw, diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peri= pherals.c index fc1500df926d056ce17252987dd91095a8399b55..23b51d84d8de40aa540dbc6dd5d= b9fb627e579de 100644 --- a/drivers/clk/meson/s4-peripherals.c +++ b/drivers/clk/meson/s4-peripherals.c @@ -3165,61 +3165,70 @@ static struct clk_regmap s4_gen_clk =3D { }, }; =20 -#define S4_PCLK(_name, _reg, _bit) \ - MESON_PCLK(_name, _reg, _bit, &s4_sys_clk.hw) - -static S4_PCLK(s4_ddr, CLKCTRL_SYS_CLK_EN0_REG0, 0); -static S4_PCLK(s4_dos, CLKCTRL_SYS_CLK_EN0_REG0, 1); -static S4_PCLK(s4_ethphy, CLKCTRL_SYS_CLK_EN0_REG0, 4); -static S4_PCLK(s4_mali, CLKCTRL_SYS_CLK_EN0_REG0, 6); -static S4_PCLK(s4_aocpu, CLKCTRL_SYS_CLK_EN0_REG0, 13); -static S4_PCLK(s4_aucpu, CLKCTRL_SYS_CLK_EN0_REG0, 14); -static S4_PCLK(s4_cec, CLKCTRL_SYS_CLK_EN0_REG0, 16); -static S4_PCLK(s4_sdemmca, CLKCTRL_SYS_CLK_EN0_REG0, 24); -static S4_PCLK(s4_sdemmcb, CLKCTRL_SYS_CLK_EN0_REG0, 25); -static S4_PCLK(s4_nand, CLKCTRL_SYS_CLK_EN0_REG0, 26); -static S4_PCLK(s4_smartcard, CLKCTRL_SYS_CLK_EN0_REG0, 27); -static S4_PCLK(s4_acodec, CLKCTRL_SYS_CLK_EN0_REG0, 28); -static S4_PCLK(s4_spifc, CLKCTRL_SYS_CLK_EN0_REG0, 29); -static S4_PCLK(s4_msr_clk, CLKCTRL_SYS_CLK_EN0_REG0, 30); -static S4_PCLK(s4_ir_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 31); - -static S4_PCLK(s4_audio, CLKCTRL_SYS_CLK_EN0_REG1, 0); -static S4_PCLK(s4_eth, CLKCTRL_SYS_CLK_EN0_REG1, 3); -static S4_PCLK(s4_uart_a, CLKCTRL_SYS_CLK_EN0_REG1, 5); -static S4_PCLK(s4_uart_b, CLKCTRL_SYS_CLK_EN0_REG1, 6); -static S4_PCLK(s4_uart_c, CLKCTRL_SYS_CLK_EN0_REG1, 7); -static S4_PCLK(s4_uart_d, CLKCTRL_SYS_CLK_EN0_REG1, 8); -static S4_PCLK(s4_uart_e, CLKCTRL_SYS_CLK_EN0_REG1, 9); -static S4_PCLK(s4_aififo, CLKCTRL_SYS_CLK_EN0_REG1, 11); -static S4_PCLK(s4_ts_ddr, CLKCTRL_SYS_CLK_EN0_REG1, 15); -static S4_PCLK(s4_ts_pll, CLKCTRL_SYS_CLK_EN0_REG1, 16); -static S4_PCLK(s4_g2d, CLKCTRL_SYS_CLK_EN0_REG1, 20); -static S4_PCLK(s4_spicc0, CLKCTRL_SYS_CLK_EN0_REG1, 21); -static S4_PCLK(s4_usb, CLKCTRL_SYS_CLK_EN0_REG1, 26); -static S4_PCLK(s4_i2c_m_a, CLKCTRL_SYS_CLK_EN0_REG1, 30); -static S4_PCLK(s4_i2c_m_b, CLKCTRL_SYS_CLK_EN0_REG1, 31); - -static S4_PCLK(s4_i2c_m_c, CLKCTRL_SYS_CLK_EN0_REG2, 0); -static S4_PCLK(s4_i2c_m_d, CLKCTRL_SYS_CLK_EN0_REG2, 1); -static S4_PCLK(s4_i2c_m_e, CLKCTRL_SYS_CLK_EN0_REG2, 2); -static S4_PCLK(s4_hdmitx_apb, CLKCTRL_SYS_CLK_EN0_REG2, 4); -static S4_PCLK(s4_i2c_s_a, CLKCTRL_SYS_CLK_EN0_REG2, 5); -static S4_PCLK(s4_usb1_to_ddr, CLKCTRL_SYS_CLK_EN0_REG2, 8); -static S4_PCLK(s4_hdcp22, CLKCTRL_SYS_CLK_EN0_REG2, 10); -static S4_PCLK(s4_mmc_apb, CLKCTRL_SYS_CLK_EN0_REG2, 11); -static S4_PCLK(s4_rsa, CLKCTRL_SYS_CLK_EN0_REG2, 18); -static S4_PCLK(s4_cpu_debug, CLKCTRL_SYS_CLK_EN0_REG2, 19); -static S4_PCLK(s4_vpu_intr, CLKCTRL_SYS_CLK_EN0_REG2, 25); -static S4_PCLK(s4_demod, CLKCTRL_SYS_CLK_EN0_REG2, 27); -static S4_PCLK(s4_sar_adc, CLKCTRL_SYS_CLK_EN0_REG2, 28); -static S4_PCLK(s4_gic, CLKCTRL_SYS_CLK_EN0_REG2, 30); - -static S4_PCLK(s4_pwm_ab, CLKCTRL_SYS_CLK_EN0_REG3, 7); -static S4_PCLK(s4_pwm_cd, CLKCTRL_SYS_CLK_EN0_REG3, 8); -static S4_PCLK(s4_pwm_ef, CLKCTRL_SYS_CLK_EN0_REG3, 9); -static S4_PCLK(s4_pwm_gh, CLKCTRL_SYS_CLK_EN0_REG3, 10); -static S4_PCLK(s4_pwm_ij, CLKCTRL_SYS_CLK_EN0_REG3, 11); +#define S4_PCLK(_name, _reg, _bit, _flags) \ + MESON_PCLK(_name, _reg, _bit, &s4_sys_clk.hw, _flags) + +/* + * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic re= asons + * Users are encouraged to test without it and submit changes to: + * - remove the flag if not necessary + * - replace the flag with something more adequate, such as CLK_IS_CRITIC= AL, + * if appropriate. + * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirab= le + * for a particular clock. + */ +static S4_PCLK(s4_ddr, CLKCTRL_SYS_CLK_EN0_REG0, 0, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_dos, CLKCTRL_SYS_CLK_EN0_REG0, 1, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_ethphy, CLKCTRL_SYS_CLK_EN0_REG0, 4, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_mali, CLKCTRL_SYS_CLK_EN0_REG0, 6, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_aocpu, CLKCTRL_SYS_CLK_EN0_REG0, 13, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_aucpu, CLKCTRL_SYS_CLK_EN0_REG0, 14, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_cec, CLKCTRL_SYS_CLK_EN0_REG0, 16, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_sdemmca, CLKCTRL_SYS_CLK_EN0_REG0, 24, CLK_IGNORE_UNUSED= ); +static S4_PCLK(s4_sdemmcb, CLKCTRL_SYS_CLK_EN0_REG0, 25, CLK_IGNORE_UNUSED= ); +static S4_PCLK(s4_nand, CLKCTRL_SYS_CLK_EN0_REG0, 26, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_smartcard, CLKCTRL_SYS_CLK_EN0_REG0, 27, CLK_IGNORE_UNUS= ED); +static S4_PCLK(s4_acodec, CLKCTRL_SYS_CLK_EN0_REG0, 28, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_spifc, CLKCTRL_SYS_CLK_EN0_REG0, 29, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_msr_clk, CLKCTRL_SYS_CLK_EN0_REG0, 30, CLK_IGNORE_UNUSED= ); +static S4_PCLK(s4_ir_ctrl, CLKCTRL_SYS_CLK_EN0_REG0, 31, CLK_IGNORE_UNUSED= ); + +static S4_PCLK(s4_audio, CLKCTRL_SYS_CLK_EN0_REG1, 0, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_eth, CLKCTRL_SYS_CLK_EN0_REG1, 3, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_uart_a, CLKCTRL_SYS_CLK_EN0_REG1, 5, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_uart_b, CLKCTRL_SYS_CLK_EN0_REG1, 6, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_uart_c, CLKCTRL_SYS_CLK_EN0_REG1, 7, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_uart_d, CLKCTRL_SYS_CLK_EN0_REG1, 8, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_uart_e, CLKCTRL_SYS_CLK_EN0_REG1, 9, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_aififo, CLKCTRL_SYS_CLK_EN0_REG1, 11, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_ts_ddr, CLKCTRL_SYS_CLK_EN0_REG1, 15, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_ts_pll, CLKCTRL_SYS_CLK_EN0_REG1, 16, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_g2d, CLKCTRL_SYS_CLK_EN0_REG1, 20, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_spicc0, CLKCTRL_SYS_CLK_EN0_REG1, 21, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_usb, CLKCTRL_SYS_CLK_EN0_REG1, 26, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_i2c_m_a, CLKCTRL_SYS_CLK_EN0_REG1, 30, CLK_IGNORE_UNUSED= ); +static S4_PCLK(s4_i2c_m_b, CLKCTRL_SYS_CLK_EN0_REG1, 31, CLK_IGNORE_UNUSED= ); + +static S4_PCLK(s4_i2c_m_c, CLKCTRL_SYS_CLK_EN0_REG2, 0, CLK_IGNORE_UNUSED= ); +static S4_PCLK(s4_i2c_m_d, CLKCTRL_SYS_CLK_EN0_REG2, 1, CLK_IGNORE_UNUSED= ); +static S4_PCLK(s4_i2c_m_e, CLKCTRL_SYS_CLK_EN0_REG2, 2, CLK_IGNORE_UNUSED= ); +static S4_PCLK(s4_hdmitx_apb, CLKCTRL_SYS_CLK_EN0_REG2, 4, CLK_IGNORE_UNU= SED); +static S4_PCLK(s4_i2c_s_a, CLKCTRL_SYS_CLK_EN0_REG2, 5, CLK_IGNORE_UNUSED= ); +static S4_PCLK(s4_usb1_to_ddr, CLKCTRL_SYS_CLK_EN0_REG2, 8, CLK_IGNORE_UN= USED); +static S4_PCLK(s4_hdcp22, CLKCTRL_SYS_CLK_EN0_REG2, 10, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_mmc_apb, CLKCTRL_SYS_CLK_EN0_REG2, 11, CLK_IGNORE_UNUSED= ); +static S4_PCLK(s4_rsa, CLKCTRL_SYS_CLK_EN0_REG2, 18, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_cpu_debug, CLKCTRL_SYS_CLK_EN0_REG2, 19, CLK_IGNORE_UNUS= ED); +static S4_PCLK(s4_vpu_intr, CLKCTRL_SYS_CLK_EN0_REG2, 25, CLK_IGNORE_UNUSE= D); +static S4_PCLK(s4_demod, CLKCTRL_SYS_CLK_EN0_REG2, 27, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_sar_adc, CLKCTRL_SYS_CLK_EN0_REG2, 28, CLK_IGNORE_UNUSED= ); +static S4_PCLK(s4_gic, CLKCTRL_SYS_CLK_EN0_REG2, 30, CLK_IGNORE_UNUSED); + +static S4_PCLK(s4_pwm_ab, CLKCTRL_SYS_CLK_EN0_REG3, 7, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_pwm_cd, CLKCTRL_SYS_CLK_EN0_REG3, 8, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_pwm_ef, CLKCTRL_SYS_CLK_EN0_REG3, 9, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_pwm_gh, CLKCTRL_SYS_CLK_EN0_REG3, 10, CLK_IGNORE_UNUSED); +static S4_PCLK(s4_pwm_ij, CLKCTRL_SYS_CLK_EN0_REG3, 11, CLK_IGNORE_UNUSED); =20 /* Array of all clocks provided by this provider */ static struct clk_hw *s4_peripherals_hw_clks[] =3D { --=20 2.47.2 From nobody Fri Oct 3 20:30:33 2025 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1442302CB3 for ; Mon, 25 Aug 2025 14:27:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132037; cv=none; b=QSEw15JIGBxqYZcgwY9Zu/Wc2DL4lCLJW8bQ50L8EkOb+DMNYq3kpSWu7mvdp8BrtuuaMWVgR7+TMLhVAIvo6GGG0frsbmFxSu1hLZ1KVPPRi19eYCH/lDVSkGCRYBbFEgskErq1oWi6PLII7iw8okONExZHMjRipYEJwF5Zw6U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132037; c=relaxed/simple; bh=Y56X7oQHuKA4lo20ZsgXO5l4gyfh+4L+P05X7w+y73Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=h0i7dChfBOFJaT0wk6f+yKG9oo1kHDunlPMuA5CG2eoqVSVfcugzpY+GC2Yo91ePkfoGmWe4KFrTPPEG/7l+uKyuRL4WeHipsps40jhIhKMaCKR/TaSJd83IT2luqtXwCBJknYpw0hcqkZ5zTB5h/PK/0V7FzvQG85LfhU0buoU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=Zo2r49nt; arc=none smtp.client-ip=209.85.221.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="Zo2r49nt" Received: by mail-wr1-f50.google.com with SMTP id ffacd0b85a97d-3c84aea9d32so649502f8f.2 for ; Mon, 25 Aug 2025 07:27:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1756132032; x=1756736832; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=euKCmjTtqFHDoU6LHakJngU3/m3WiWXa94SHMvLwXS4=; b=Zo2r49ntVGfSFLvlXBHgE/hLX4KkpF7bWJpNISHZWyPv6b6qyvs/qO0tsFOuZEt6dv qQDL6fj7pRh5kxpIP8n5aZWuCrntP1mxXWzcWyPJXxU3UBACBuXPuFZp1SFFJYC0MMn4 ntaIVAsbGOWTMKOQ7CYRRoSp/YWHeNO2aXbGN2rpDelP8JW+CoD8SFneP41Jnc8XXV+Y x7vTGDv4P+YBbBDEBhKG4FQJBMs18om0SQZKSs1EzWG/YmuDRFLJ21nxeJJomb5uDSnN bM364AT2r/NNE+hxjRvDGMx5u7kKOsQaaG5rPxK9luHaaRZ1X2iVexE0AsymfKEUlufL tmlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756132032; x=1756736832; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=euKCmjTtqFHDoU6LHakJngU3/m3WiWXa94SHMvLwXS4=; b=cGatHqvuvPj7t2eqjCNP/d0wm1rj/6XVu/EoUMr7BQGU8JN/QPtOrAi0Sfis+fYZ8+ JIVBvA3eCugv3Ki6P4CyQg8+R3v3+4neyrsTZrmiZXN7fl7jORPLLTz3v/Hu5QbZM7j8 SJLjnt9p2nTA3REKiZdmoHhzdvL8h7TkDuxiDUwhQKTLxa+4rxL+0Z1tvSbhdoEbZRlj 780pKesAU9SK03Jfz+C//A52dSYgD6rS1X+PLqm3b1BOgvvmYq+aTsbb+DkPwwlh5/IL vs/KN6fEPX0SXklnUthfN2zPCfPqSzP6RJJgjdbjWq7kEufkhV9k7O2EnhMXLsdbKB3M A3hw== X-Forwarded-Encrypted: i=1; AJvYcCUJAp/WtsBZ8taEIz4L6m1x+b34wwBt+VtK9E/Ui0UPCP4S+KyF1yVmeGUBjHmcZGmz9x1p7tsNIw8cdgw=@vger.kernel.org X-Gm-Message-State: AOJu0Yx44/jk50ywiHmN4TFn0xU9fjz+E11UC0zML6MBSQzCRSQJ55v6 mUtmkNr593VO82SycbORn4eMAY5VUrSxvqcyZNwaNJFUcf04Jx3oWv3YX0/m9f/iKhE= X-Gm-Gg: ASbGncvnCnf3WCRrB+iDwnxBx+Zhm8fC4drHawzaQj3t8EK6BkztFsU2e+hu9BEQWlR inDXI/zafqmD4WdMlBlMR1eVIOptG3yBf+rspF+QL3aKz5WdgGmEcSZqBMFKk1SROhizERdkC7f SB0nLhykIsxPwxH40m3MjxTyfuY3bvY0xDfkcltQiGpREpLjH+FX0Qcj6d99fLmduFtKd1XXqN6 m5h7BWDitn1njUmpsaX7T9RWkU8B9XS6XCvUcSB8lCnffGnUZ5pM98InXGW2MQthnLf3ZNuCS4+ FeSczRh7hnpT71gWq1P63N835Sc6LVtntpA3haOGJFDMGTlPTzZgMW6X6PcsdmLbYbTeort/0b9 9a8wwKDAlkSUdtXQ4A8uIcpBcO4Cis7eWpxb+ X-Google-Smtp-Source: AGHT+IHzf1zBMogo6qwNYmdim+KUSN44hRz+cqBwGOk4IKKU5b5IVPiFT1z370fUAp1wSCO64WjI8Q== X-Received: by 2002:a5d:5d0a:0:b0:3b7:792c:e8d9 with SMTP id ffacd0b85a97d-3c5daf023eamr10484620f8f.14.1756132032010; Mon, 25 Aug 2025 07:27:12 -0700 (PDT) Received: from toaster.baylibre.com ([2a01:e0a:3c5:5fb1:b261:baab:ed3d:3cb6]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3c70e4b9e1fsm12634462f8f.14.2025.08.25.07.27.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Aug 2025 07:27:11 -0700 (PDT) From: Jerome Brunet Date: Mon, 25 Aug 2025 16:26:33 +0200 Subject: [PATCH v2 08/12] clk: amlogic: introduce a common pclk definition Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-meson-clk-cleanup-24-v2-8-0f402f01e117@baylibre.com> References: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> In-Reply-To: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet , Chuan Liu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10129; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=Y56X7oQHuKA4lo20ZsgXO5l4gyfh+4L+P05X7w+y73Q=; b=kA0DAAoB5vwPHDfy2oUByyZiAGiscrSg+dyaK5A9W6G75hRGdsahgRm0IWxHdlVu6XUqS05L2 YkCMwQAAQoAHRYhBPThWa4Y8/VtXxu3G+b8Dxw38tqFBQJorHK0AAoJEOb8Dxw38tqFUfAP/00z URL2EFIIxTrVtSV8q0c1qew6G9U3/f7ug8TWr3aww8AIbXna9bL0bI3ZZsGE+NBNygyFS1cU5Ci /l8SouTRGvRqGiIFgdO2cxKyserGsTNsI37O4fzaS2oCrpWZAFu2HbKiDMO06n4PCJzNkG7Db5F W8TkUSV35yriuAdzITs4thtIPG9wgqxdox3PlEcEbuW+CCsDPztuesf1di8ZfXs2fYeWHr+JdRF eDcWEUisLEQ4zb/kYQyasnDLgKmcAKfGwTVQtsHZjDKl7SkN7twuC55IbT8Cv+OV932F8Vta1n6 XzO1BVkwXO/zx5axgByF3NjX+gQW9TmXCxLF8riPt8cCKwUaVvOQGST/16Q5839+vEkkrIugEL3 MSDpZJmC/mDYM1w/5yglgWwnpzyX2mvr+v/QO9q4SV8k6ElpwEmxIg2LKJO+3skK50mxRn9nmmj MV+nRJ8P1mZCNOqA3s3EXBcFKVeNE6TxTGb2a/nmUUHNCacmDq5Qq9IRYy88uElt7vuTVbC8ipL zo/+xSZ9mZHQRjoig1Hnz247XfteEnd52uryqPPkhTwtXcSXsexa2b6ZSTpFVzm9xHvHOg0bkWK R/ca5uwteWQ/ZGL/vzYyJ9q8xDe556e04lv4AidECCb4Nelr8zFmWawAnmVifVVgymwcPZ5xv3d gLksK X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 All Amlogic peripheral clocks are more or less the same. The only thing that differs is the parent data. Adapt the common pclk definition so it takes clk_parent_data and can be used by all controllers. Reviewed-by: Chuan Liu Signed-off-by: Jerome Brunet --- drivers/clk/meson/a1-peripherals.c | 4 +++- drivers/clk/meson/axg.c | 4 +++- drivers/clk/meson/g12a.c | 6 ++++-- drivers/clk/meson/gxbb.c | 26 +++++++++++++++++--------- drivers/clk/meson/meson-clkc-utils.h | 12 ++++++------ drivers/clk/meson/meson8b.c | 31 ++++++++++++++++++------------- drivers/clk/meson/s4-peripherals.c | 4 +++- 7 files changed, 54 insertions(+), 33 deletions(-) diff --git a/drivers/clk/meson/a1-peripherals.c b/drivers/clk/meson/a1-peri= pherals.c index a7bd3822df18f5e043e58e2d7bbcaa24345ea404..5e0d58c01405c1925a5c25ee6d0= a547fd2e69911 100644 --- a/drivers/clk/meson/a1-peripherals.c +++ b/drivers/clk/meson/a1-peripherals.c @@ -1840,8 +1840,10 @@ static struct clk_regmap a1_cecb_32k_out =3D { }, }; =20 +static const struct clk_parent_data a1_pclk_parents =3D { .hw =3D &a1_sys.= hw }; + #define A1_PCLK(_name, _reg, _bit, _flags) \ - MESON_PCLK(a1_##_name, _reg, _bit, &a1_sys.hw, _flags) + MESON_PCLK(a1_##_name, _reg, _bit, &a1_pclk_parents, _flags) =20 /* * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic re= asons diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index fd9a7a362a1be1d8a584f855f454daa354ae2ade..0a25c649ef1d4847fad1ebb7bc4= bd8c16c83d4d0 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -1915,8 +1915,10 @@ static struct clk_regmap axg_gen_clk =3D { }, }; =20 +static const struct clk_parent_data axg_pclk_parents =3D { .hw =3D &axg_cl= k81.hw }; + #define AXG_PCLK(_name, _reg, _bit, _flags) \ - MESON_PCLK(axg_##_name, _reg, _bit, &axg_clk81.hw, _flags) + MESON_PCLK(axg_##_name, _reg, _bit, &axg_pclk_parents, _flags) =20 /* * Everything Else (EE) domain gates diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c index bfa8815647aee9f8c0b373a36b8b9ae5380c759e..348aff4fae68bf3f856e70de5fa= 4f687e3d8144f 100644 --- a/drivers/clk/meson/g12a.c +++ b/drivers/clk/meson/g12a.c @@ -4384,11 +4384,13 @@ static struct clk_regmap sm1_nna_core_clk =3D { }, }; =20 +static const struct clk_parent_data g12a_pclk_parents =3D { .hw =3D &g12a_= clk81.hw }; + #define G12A_PCLK(_name, _reg, _bit, _flags) \ - MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw, _flags) + MESON_PCLK(_name, _reg, _bit, &g12a_pclk_parents, _flags) =20 #define G12A_PCLK_RO(_name, _reg, _bit, _flags) \ - MESON_PCLK_RO(_name, _reg, _bit, &g12a_clk81.hw, _flags) + MESON_PCLK_RO(_name, _reg, _bit, &g12a_pclk_parents, _flags) =20 /* * Everything Else (EE) domain gates diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index ccc1490a092814c242e719d4c37c66c4b3e27f07..5a229c4ffae105bc112824f79af= 5785ff6c5a710 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -2721,8 +2721,10 @@ static struct clk_regmap gxbb_gen_clk =3D { }, }; =20 +static const struct clk_parent_data gxbb_pclk_parents =3D { .hw =3D &gxbb_= clk81.hw }; + #define GXBB_PCLK(_name, _reg, _bit, _flags) \ - MESON_PCLK(_name, _reg, _bit, &gxbb_clk81.hw, _flags) + MESON_PCLK(_name, _reg, _bit, &gxbb_pclk_parents, _flags) =20 /* * Everything Else (EE) domain gates @@ -2817,14 +2819,20 @@ static GXBB_PCLK(gxbb_ao_iface, HHI_GCLK_AO, 3, CL= K_IGNORE_UNUSED); static GXBB_PCLK(gxbb_ao_i2c, HHI_GCLK_AO, 4, CLK_IGNORE_UNUSED); =20 /* AIU gates */ -static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu.hw, CLK_IGN= ORE_UNUSED); -static MESON_PCLK(gxbb_iec958, HHI_GCLK_MPEG1, 7, &gxbb_aiu_glue.hw, CLK= _IGNORE_UNUSED); -static MESON_PCLK(gxbb_i2s_out, HHI_GCLK_MPEG1, 8, &gxbb_aiu_glue.hw, CL= K_IGNORE_UNUSED); -static MESON_PCLK(gxbb_amclk, HHI_GCLK_MPEG1, 9, &gxbb_aiu_glue.hw, CLK_= IGNORE_UNUSED); -static MESON_PCLK(gxbb_aififo2, HHI_GCLK_MPEG1, 10, &gxbb_aiu_glue.hw, CL= K_IGNORE_UNUSED); -static MESON_PCLK(gxbb_mixer, HHI_GCLK_MPEG1, 11, &gxbb_aiu_glue.hw, CLK_= IGNORE_UNUSED); -static MESON_PCLK(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12, &gxbb_aiu_glue.hw,= CLK_IGNORE_UNUSED); -static MESON_PCLK(gxbb_adc, HHI_GCLK_MPEG1, 13, &gxbb_aiu_glue.hw, CLK_IG= NORE_UNUSED); +static const struct clk_parent_data gxbb_aiu_glue_parents =3D { .hw =3D &g= xbb_aiu.hw }; +static MESON_PCLK(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6, &gxbb_aiu_glue_parent= s, CLK_IGNORE_UNUSED); + +static const struct clk_parent_data gxbb_aiu_pclk_parents =3D { .hw =3D &g= xbb_aiu_glue.hw }; +#define GXBB_AIU_PCLK(_name, _bit, _flags) \ + MESON_PCLK(_name, HHI_GCLK_MPEG1, _bit, &gxbb_aiu_pclk_parents, _flags) + +static GXBB_AIU_PCLK(gxbb_iec958, 7, CLK_IGNORE_UNUSED); +static GXBB_AIU_PCLK(gxbb_i2s_out, 8, CLK_IGNORE_UNUSED); +static GXBB_AIU_PCLK(gxbb_amclk, 9, CLK_IGNORE_UNUSED); +static GXBB_AIU_PCLK(gxbb_aififo2, 10, CLK_IGNORE_UNUSED); +static GXBB_AIU_PCLK(gxbb_mixer, 11, CLK_IGNORE_UNUSED); +static GXBB_AIU_PCLK(gxbb_mixer_iface, 12, CLK_IGNORE_UNUSED); +static GXBB_AIU_PCLK(gxbb_adc, 13, CLK_IGNORE_UNUSED); =20 /* Array of all clocks provided by this provider */ =20 diff --git a/drivers/clk/meson/meson-clkc-utils.h b/drivers/clk/meson/meson= -clkc-utils.h index 03e38992c4c73ff4ee24f0fa99b7c34134376992..95d9f85f7ca22f63a16f8665d6f= 7a250b21bfdb8 100644 --- a/drivers/clk/meson/meson-clkc-utils.h +++ b/drivers/clk/meson/meson-clkc-utils.h @@ -27,7 +27,7 @@ struct meson_clkc_data { int meson_clkc_syscon_probe(struct platform_device *pdev); int meson_clkc_mmio_probe(struct platform_device *pdev); =20 -#define __MESON_PCLK(_name, _reg, _bit, _ops, _pname, _flags) \ +#define __MESON_PCLK(_name, _reg, _bit, _ops, _pdata, _flags) \ struct clk_regmap _name =3D { \ .data =3D &(struct clk_regmap_gate_data) { \ .offset =3D (_reg), \ @@ -36,16 +36,16 @@ struct clk_regmap _name =3D { \ .hw.init =3D &(struct clk_init_data) { \ .name =3D #_name, \ .ops =3D _ops, \ - .parent_hws =3D (const struct clk_hw *[]) { _pname }, \ + .parent_data =3D (_pdata), \ .num_parents =3D 1, \ .flags =3D (_flags), \ }, \ } =20 -#define MESON_PCLK(_name, _reg, _bit, _pname, _flags) \ - __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname, _flags) +#define MESON_PCLK(_name, _reg, _bit, _pdata, _flags) \ + __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pdata, _flags) =20 -#define MESON_PCLK_RO(_name, _reg, _bit, _pname, _flags) \ - __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname, _flags) +#define MESON_PCLK_RO(_name, _reg, _bit, _pdata, _flags) \ + __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pdata, _flags) =20 #endif diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c index a16ebbbf664cdd56b2c74db4f88a8d0a22d2ddc3..95d0b9cbd90404ee1c7ec551a27= 48665b4ef9ccd 100644 --- a/drivers/clk/meson/meson8b.c +++ b/drivers/clk/meson/meson8b.c @@ -2701,8 +2701,10 @@ static struct clk_regmap meson8b_cts_i958 =3D { }, }; =20 +static const struct clk_parent_data meson8b_pclk_parents =3D { .hw =3D &me= son8b_clk81.hw }; + #define MESON8B_PCLK(_name, _reg, _bit, _flags) \ - MESON_PCLK(_name, _reg, _bit, &meson8b_clk81.hw, _flags) + MESON_PCLK(_name, _reg, _bit, &meson8b_pclk_parents, _flags) =20 /* * Everything Else (EE) domain gates @@ -2785,18 +2787,21 @@ static MESON8B_PCLK(meson8b_vclk2_other, HHI_GCLK_O= THER, 26, CLK_IGNORE_UNUSED); static MESON8B_PCLK(meson8b_edp, HHI_GCLK_OTHER, 31, CLK_IGNORE_UNUSED); =20 /* AIU gates */ -static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, &meson8b_aiu.hw, CL= K_IGNORE_UNUSED); - -#define MESON_AIU_PCLK(_name, _reg, _bit, _flags) \ - MESON_PCLK(_name, _reg, _bit, &meson8b_aiu_glue.hw, _flags) - -static MESON_AIU_PCLK(meson8b_iec958, HHI_GCLK_MPEG1, 7, CLK_IGNORE_UNUS= ED); -static MESON_AIU_PCLK(meson8b_i2s_out, HHI_GCLK_MPEG1, 8, CLK_IGNORE_UNU= SED); -static MESON_AIU_PCLK(meson8b_amclk, HHI_GCLK_MPEG1, 9, CLK_IGNORE_UNUSE= D); -static MESON_AIU_PCLK(meson8b_aififo2, HHI_GCLK_MPEG1, 10, CLK_IGNORE_UNU= SED); -static MESON_AIU_PCLK(meson8b_mixer, HHI_GCLK_MPEG1, 11, CLK_IGNORE_UNUSE= D); -static MESON_AIU_PCLK(meson8b_mixer_iface, HHI_GCLK_MPEG1, 12, CLK_IGNORE_= UNUSED); -static MESON_AIU_PCLK(meson8b_adc, HHI_GCLK_MPEG1, 13, CLK_IGNORE_UNUSED); +static const struct clk_parent_data meson8b_aiu_glue_parents =3D { .hw =3D= &meson8b_aiu.hw }; +static MESON_PCLK(meson8b_aiu_glue, HHI_GCLK_MPEG1, 6, + &meson8b_aiu_glue_parents, CLK_IGNORE_UNUSED); + +static const struct clk_parent_data meson8b_aiu_pclk_parents =3D { .hw =3D= &meson8b_aiu_glue.hw }; +#define MESON8B_AIU_PCLK(_name, _bit, _flags) \ + MESON_PCLK(_name, HHI_GCLK_MPEG1, _bit, &meson8b_aiu_pclk_parents, _flags) + +static MESON8B_AIU_PCLK(meson8b_iec958, 7, CLK_IGNORE_UNUSED); +static MESON8B_AIU_PCLK(meson8b_i2s_out, 8, CLK_IGNORE_UNUSED); +static MESON8B_AIU_PCLK(meson8b_amclk, 9, CLK_IGNORE_UNUSED); +static MESON8B_AIU_PCLK(meson8b_aififo2, 10, CLK_IGNORE_UNUSED); +static MESON8B_AIU_PCLK(meson8b_mixer, 11, CLK_IGNORE_UNUSED); +static MESON8B_AIU_PCLK(meson8b_mixer_iface, 12, CLK_IGNORE_UNUSED); +static MESON8B_AIU_PCLK(meson8b_adc, 13, CLK_IGNORE_UNUSED); =20 /* Always On (AO) domain gates */ =20 diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peri= pherals.c index 23b51d84d8de40aa540dbc6dd5db9fb627e579de..3e048e645b080f9e5982ef908e3= f9c43578a0b5f 100644 --- a/drivers/clk/meson/s4-peripherals.c +++ b/drivers/clk/meson/s4-peripherals.c @@ -3165,8 +3165,10 @@ static struct clk_regmap s4_gen_clk =3D { }, }; =20 +static const struct clk_parent_data s4_pclk_parents =3D { .hw =3D &s4_sys_= clk.hw }; + #define S4_PCLK(_name, _reg, _bit, _flags) \ - MESON_PCLK(_name, _reg, _bit, &s4_sys_clk.hw, _flags) + MESON_PCLK(_name, _reg, _bit, &s4_pclk_parents, _flags) =20 /* * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic re= asons --=20 2.47.2 From nobody Fri Oct 3 20:30:33 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B639E303CBF for ; Mon, 25 Aug 2025 14:27:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132039; cv=none; b=ENdDYz8UGHBp5fld+FsDmpKM4dYRyAtAhH4CdYpcr6e0FRDAG7tNTDYxgQr+Pvi08tH8egGjg/rNtsISxjEh/yRDhEb3fgfxRz4eyfQGrQLwLUJdku3WlmCHm7i8IC2rI6MkFJutExZAEWC3okBxXUsU+42Gj7Q68saUqvIyXJk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132039; c=relaxed/simple; bh=ssDaR4wz9jG+IVUW3bzaW/s+xN9zK8sGhakg0LDPY+Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XzaCTuijL74ggK1fAIGhpg8HFcxDx4FQGUnWBDOdNu06qZH9vN7EccJSD0qoQ2TMCHl5SQzmTXIiqlYW+y4WmIrOVOvFH6YUowT/KEqlIY1+TOynvbmKaAIu7SwJvCK9He6AcfeaMXXAJSjVcDcGY2TbeS7Qge6zXGX8S9bxEII= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=Dn+wcVFP; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="Dn+wcVFP" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-45a1b0bde14so24075415e9.2 for ; Mon, 25 Aug 2025 07:27:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1756132033; x=1756736833; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=NZFizNzZeDwxlG4/SOUoWjAfRTsGu/AR5Ui24dmicOw=; b=Dn+wcVFP/ZbbSXQlU1lU/pI4gkH4miaemZqAvEvmvVb9JifUYvI4iVgqmvC75NPG+P ZIGUbVctD/Mc0+GTVfu9o0KkzrWMJw6rMvT+HYnRarjhvVjBtRTftgnGWLQR5gNjUmcK hIyPvxHah7UtKszZWKaW6HwfAply8IImpmwr7k+EiRv55sPvJ7m9zKjhCgimKTe5Am8A pANPggrynbQVWpWNNQ5Rb9FTRyHWXYSwG7y/rtQfb3sXU+kLIg2DXHGp+izSp0lo0LfE zV6Mb8fB94v7S6VQWY3PJIwZwmKusm9bZQyTqMSCCeJc6tZwjBbxFIqpx74EEyGjum9S LuYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756132033; x=1756736833; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NZFizNzZeDwxlG4/SOUoWjAfRTsGu/AR5Ui24dmicOw=; b=K5qCWVL63Sp8Ycn9fvjk71N3l9BovpeGUlcI1tGAhm7ZvRjp+BnS3dLYTIZrjjeKT7 BjPNvfj89fQeqzcLd/ADn7CjrFeq1bsm9pdz751ZIwEiaFLJSxgj94/C6OeW2totYtp5 JMEqJiS5JV5NS+TZObZt+9ZqaVNfIT13K1fRmyWAr5QwUdEecNyKJY4G0V6EeReSRHaS xtAlciJhGgiPP/yvlee1yF5btbOACb9plcyD1Nm5FWURJFy7o1iFYXRtoy7JqoJY1cCN v4OjOi3ZiBsY4NR7spgXz+bGbT7itF51g/vSSm5w2/VDmHCth0KYAPM5rSTM7GR2M/yJ JAww== X-Forwarded-Encrypted: i=1; AJvYcCXzAPqAKFHWeyOBejfw79mnyiaX19VcLXXpRVCzU80QVYF9AFPerNsYRwLVy3JqFtkZ+rXV5wdNCRFsh6I=@vger.kernel.org X-Gm-Message-State: AOJu0YyfhbABADI6vLkaVLUnYUhuz8kxX0p+9Cg1Gu+OjF/l6SoVMdDs FH+0XMImaAPOxe+8gWDpEgWbtw70l7Jy+fnxy6VRkd4g6znSAZFwlFh1+dvJ5VpFEbo= X-Gm-Gg: ASbGncvCyhu74fKBTp12g7EdMwJn60gTKBf93kja6WGRIGHEPRPy2fwOod+5ZUOpH3Z bcaFh72CNWa6HYcptUxlV4Xxn6olENveXtfihdis/u8MXzr50SGexz5GHuWaoDyvSOycA71eA3I 6Mj1hrfp6JxDU/7UwX6rD9CsBuf3utJwYh38gzfopRCzxA10srVGoAHSpZ8wLYKrYKDreoTm2dM kyepQGsKelwAhOvMdHAI8Q1+cFXab1Txinp6DjA7IYxoLnbgpuE/+05l3SQkJTJpvxmbOXjhGpZ ou7v0kvhM2lcqH/tvoTYTJP2lQbxvhmBEtDHkZyQa/ZtjAoTkwFvlfTSyQmLoUXSYtVVZPF0Lzx ZvP38TKsJNmm8rKy3OnSJ5S4binIK9o5NGIPE X-Google-Smtp-Source: AGHT+IEX7kxqjPNKgzRc5FzaaGAx++7bJd2BZ0Co0JpBuqwb92/9N/1Cu7pGDaS30PlQl+fwDeeX+g== X-Received: by 2002:adf:e912:0:b0:3c6:cb4:e05e with SMTP id ffacd0b85a97d-3c60cb4e578mr7827667f8f.56.1756132032709; Mon, 25 Aug 2025 07:27:12 -0700 (PDT) Received: from toaster.baylibre.com ([2a01:e0a:3c5:5fb1:b261:baab:ed3d:3cb6]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3c70e4b9e1fsm12634462f8f.14.2025.08.25.07.27.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Aug 2025 07:27:12 -0700 (PDT) From: Jerome Brunet Date: Mon, 25 Aug 2025 16:26:34 +0200 Subject: [PATCH v2 09/12] clk: amlogic: use the common pclk definition Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-meson-clk-cleanup-24-v2-9-0f402f01e117@baylibre.com> References: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> In-Reply-To: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=9875; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=ssDaR4wz9jG+IVUW3bzaW/s+xN9zK8sGhakg0LDPY+Q=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBorHK1XCoZgxVMFC8fEWvbXexWAF6ILhH1Z8QIs W7L+unfqrmJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaKxytQAKCRDm/A8cN/La hReZD/9IOkOqaQw7NpA3Ed83SvElIRCwDS93n8wA/pakL03R+G7MjmDwhrSnqIgeYkL9YyRRyZV dWWfJGtaHui0SDUokqEdnhDwxEajYUHwB1zAyxT7DVL+V0AcDL+/CmIfCZnBmQsGWDwlvHnOup8 0quDjTTETx1wWkO6STK+2dI/T/VE+zES5ZDQGss0WzmNxmSL276QwfAp77cTOLnMr/GzJT4wn50 kgFOjOLk3Adgs4eHzH7qD9VPUWbOKesg4xJr7wdHQwxDh0bhXmLbmvB7qiRzX4RJur5SWEGR75K jFQJrHx1zdVlybnWyCFWomOPxafXFMsMmA8O8G5RQywACwHbgvRhY2hahygzb4hYjNAk+G+GA1I Wy6YdUNksqln4vNZwDtMqwpGwPj9ABAdrMFvsiBWUg+ARapT1Pg6YVK9KXgBfuR1QWXLHrQ/oDd Hl9KLZ9M8YBjX+qbwgmIa4LYKKoF34GhCCClZxAH7j3RVLHKR7yjA54/tzEnghQ4Av4tkHNsa7/ mV1aZnpSpcSWEDDd8xLKQI2Vb7Jj+g+FTZP3FVVBhdsLYMEoRztyOz2m5ipwyYMJqWCEZqbeZcO K9VLWEWIhf8qGpiCS0GL7YX4l3J5YfIv7znrvmoMTK8m5buRBlxszxNJEeyPuQqCPPNs5qHkz+o xZYAaw1yRw2Du0w== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Replace marcros defining pclks with the common one, reducing code duplication. Signed-off-by: Jerome Brunet --- drivers/clk/meson/axg-aoclk.c | 35 +++++++++----------------- drivers/clk/meson/c3-peripherals.c | 34 +++++++------------------- drivers/clk/meson/g12a-aoclk.c | 50 +++++++++++++++-------------------= ---- drivers/clk/meson/gxbb-aoclk.c | 33 +++++++++---------------- 4 files changed, 51 insertions(+), 101 deletions(-) diff --git a/drivers/clk/meson/axg-aoclk.c b/drivers/clk/meson/axg-aoclk.c index 74c2f51424f11cc04a80a3a4918e4de0a5d11d08..902fbd34039cc06d512f1237a1e= 5d9050fd00b4b 100644 --- a/drivers/clk/meson/axg-aoclk.c +++ b/drivers/clk/meson/axg-aoclk.c @@ -34,30 +34,19 @@ #define AO_RTC_ALT_CLK_CNTL0 0x94 #define AO_RTC_ALT_CLK_CNTL1 0x98 =20 -#define AXG_AO_GATE(_name, _bit, _flags) \ -static struct clk_regmap axg_ao_##_name =3D { \ - .data =3D &(struct clk_regmap_gate_data) { \ - .offset =3D (AO_RTI_GEN_CNTL_REG0), \ - .bit_idx =3D (_bit), \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "axg_ao_" #_name, \ - .ops =3D &clk_regmap_gate_ops, \ - .parent_data =3D &(const struct clk_parent_data) { \ - .fw_name =3D "mpeg-clk", \ - }, \ - .num_parents =3D 1, \ - .flags =3D (_flags), \ - }, \ -} +static const struct clk_parent_data axg_ao_pclk_parents =3D { .fw_name =3D= "mpeg-clk" }; =20 -AXG_AO_GATE(remote, 0, CLK_IGNORE_UNUSED); -AXG_AO_GATE(i2c_master, 1, CLK_IGNORE_UNUSED); -AXG_AO_GATE(i2c_slave, 2, CLK_IGNORE_UNUSED); -AXG_AO_GATE(uart1, 3, CLK_IGNORE_UNUSED); -AXG_AO_GATE(uart2, 5, CLK_IGNORE_UNUSED); -AXG_AO_GATE(ir_blaster, 6, CLK_IGNORE_UNUSED); -AXG_AO_GATE(saradc, 7, CLK_IGNORE_UNUSED); +#define AXG_AO_GATE(_name, _bit, _flags) \ + MESON_PCLK(axg_ao_##_name, AO_RTI_GEN_CNTL_REG0, _bit, \ + &axg_ao_pclk_parents, _flags) + +static AXG_AO_GATE(remote, 0, CLK_IGNORE_UNUSED); +static AXG_AO_GATE(i2c_master, 1, CLK_IGNORE_UNUSED); +static AXG_AO_GATE(i2c_slave, 2, CLK_IGNORE_UNUSED); +static AXG_AO_GATE(uart1, 3, CLK_IGNORE_UNUSED); +static AXG_AO_GATE(uart2, 5, CLK_IGNORE_UNUSED); +static AXG_AO_GATE(ir_blaster, 6, CLK_IGNORE_UNUSED); +static AXG_AO_GATE(saradc, 7, CLK_IGNORE_UNUSED); =20 static struct clk_regmap axg_ao_cts_oscin =3D { .data =3D &(struct clk_regmap_gate_data){ diff --git a/drivers/clk/meson/c3-peripherals.c b/drivers/clk/meson/c3-peri= pherals.c index e9c1ef99be13d0542b8a972ceffe69c8a9977118..02c9820cd98655e57a290859b59= 5cf09d39e5fe3 100644 --- a/drivers/clk/meson/c3-peripherals.c +++ b/drivers/clk/meson/c3-peripherals.c @@ -164,30 +164,13 @@ static struct clk_regmap c3_rtc_clk =3D { }, }; =20 -#define C3_PCLK(_name, _reg, _bit, _fw_name, _ops, _flags) \ -struct clk_regmap c3_##_name =3D { \ - .data =3D &(struct clk_regmap_gate_data){ \ - .offset =3D (_reg), \ - .bit_idx =3D (_bit), \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "c3_" #_name, \ - .ops =3D _ops, \ - .parent_data =3D &(const struct clk_parent_data) { \ - .fw_name =3D (_fw_name), \ - }, \ - .num_parents =3D 1, \ - .flags =3D (_flags), \ - }, \ -} +static const struct clk_parent_data c3_sys_pclk_parents =3D { .fw_name =3D= "sysclk" }; =20 -#define C3_SYS_PCLK(_name, _reg, _bit, _flags) \ - C3_PCLK(_name, _reg, _bit, "sysclk", \ - &clk_regmap_gate_ops, _flags) +#define C3_SYS_PCLK(_name, _reg, _bit, _flags) \ + MESON_PCLK(c3_##_name, _reg, _bit, &c3_sys_pclk_parents, _flags) =20 -#define C3_SYS_PCLK_RO(_name, _reg, _bit) \ - C3_PCLK(_name, _reg, _bit, "sysclk", \ - &clk_regmap_gate_ro_ops, 0) +#define C3_SYS_PCLK_RO(_name, _reg, _bit) \ + MESON_PCLK_RO(c3_##_name, _reg, _bit, &c3_sys_pclk_parents, 0) =20 static C3_SYS_PCLK(sys_reset_ctrl, SYS_CLK_EN0_REG0, 1, 0); static C3_SYS_PCLK(sys_pwr_ctrl, SYS_CLK_EN0_REG0, 3, 0); @@ -290,9 +273,10 @@ static C3_SYS_PCLK(sys_vc9000e, SYS_CLK_EN0_REG2, 2, = 0); static C3_SYS_PCLK(sys_pwm_mn, SYS_CLK_EN0_REG2, 3, 0); static C3_SYS_PCLK(sys_sd_emmc_b, SYS_CLK_EN0_REG2, 4, 0); =20 -#define C3_AXI_PCLK(_name, _reg, _bit, _flags) \ - C3_PCLK(_name, _reg, _bit, "axiclk", \ - &clk_regmap_gate_ops, _flags) +static const struct clk_parent_data c3_axi_pclk_parents =3D { .fw_name =3D= "axiclk" }; + +#define C3_AXI_PCLK(_name, _reg, _bit, _flags) \ + MESON_PCLK(c3_##_name, _reg, _bit, &c3_axi_pclk_parents, _flags) =20 /* * NOTE: axi_sys_nic provides the clock to the AXI bus of the system NIC. = After diff --git a/drivers/clk/meson/g12a-aoclk.c b/drivers/clk/meson/g12a-aoclk.c index 45e4df393feb6f916b6e035ad71e379e6e30ee99..96981da271fa1453ebbe433e36c= ff4409661fa6a 100644 --- a/drivers/clk/meson/g12a-aoclk.c +++ b/drivers/clk/meson/g12a-aoclk.c @@ -37,22 +37,10 @@ #define AO_RTC_ALT_CLK_CNTL0 0x94 #define AO_RTC_ALT_CLK_CNTL1 0x98 =20 -#define G12A_AO_PCLK(_name, _reg, _bit, _flags) \ -static struct clk_regmap g12a_ao_##_name =3D { \ - .data =3D &(struct clk_regmap_gate_data) { \ - .offset =3D (_reg), \ - .bit_idx =3D (_bit), \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "g12a_ao_" #_name, \ - .ops =3D &clk_regmap_gate_ops, \ - .parent_data =3D &(const struct clk_parent_data) { \ - .fw_name =3D "mpeg-clk", \ - }, \ - .num_parents =3D 1, \ - .flags =3D (_flags), \ - }, \ -} +static const struct clk_parent_data g12a_ao_pclk_parents =3D { .fw_name = =3D "mpeg-clk" }; + +#define G12A_AO_PCLK(_name, _reg, _bit, _flags) \ + MESON_PCLK(g12a_ao_##_name, _reg, _bit, &g12a_ao_pclk_parents, _flags) =20 /* * NOTE: The gates below are marked with CLK_IGNORE_UNUSED for historic re= asons @@ -63,22 +51,22 @@ static struct clk_regmap g12a_ao_##_name =3D { \ * - add a comment explaining why the use of CLK_IGNORE_UNUSED is desirab= le * for a particular clock. */ -G12A_AO_PCLK(ahb, AO_CLK_GATE0, 0, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(ir_in, AO_CLK_GATE0, 1, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(i2c_m0, AO_CLK_GATE0, 2, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(i2c_s0, AO_CLK_GATE0, 3, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(uart, AO_CLK_GATE0, 4, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(prod_i2c, AO_CLK_GATE0, 5, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(uart2, AO_CLK_GATE0, 6, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(ir_out, AO_CLK_GATE0, 7, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(saradc, AO_CLK_GATE0, 8, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(ahb, AO_CLK_GATE0, 0, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(ir_in, AO_CLK_GATE0, 1, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(i2c_m0, AO_CLK_GATE0, 2, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(i2c_s0, AO_CLK_GATE0, 3, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(uart, AO_CLK_GATE0, 4, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(prod_i2c, AO_CLK_GATE0, 5, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(uart2, AO_CLK_GATE0, 6, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(ir_out, AO_CLK_GATE0, 7, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(saradc, AO_CLK_GATE0, 8, CLK_IGNORE_UNUSED); =20 -G12A_AO_PCLK(mailbox, AO_CLK_GATE0_SP, 0, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(m3, AO_CLK_GATE0_SP, 1, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(ahb_sram, AO_CLK_GATE0_SP, 2, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(rti, AO_CLK_GATE0_SP, 3, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(m4_fclk, AO_CLK_GATE0_SP, 4, CLK_IGNORE_UNUSED); -G12A_AO_PCLK(m4_hclk, AO_CLK_GATE0_SP, 5, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(mailbox, AO_CLK_GATE0_SP, 0, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(m3, AO_CLK_GATE0_SP, 1, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(ahb_sram, AO_CLK_GATE0_SP, 2, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(rti, AO_CLK_GATE0_SP, 3, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(m4_fclk, AO_CLK_GATE0_SP, 4, CLK_IGNORE_UNUSED); +static G12A_AO_PCLK(m4_hclk, AO_CLK_GATE0_SP, 5, CLK_IGNORE_UNUSED); =20 static struct clk_regmap g12a_ao_cts_oscin =3D { .data =3D &(struct clk_regmap_gate_data){ diff --git a/drivers/clk/meson/gxbb-aoclk.c b/drivers/clk/meson/gxbb-aoclk.c index 2bf45fd7fe4ba0783e736fbbb126209870985b22..c7dfb3a06cb5f70c98f65bb91b9= 37e1b870b34fe 100644 --- a/drivers/clk/meson/gxbb-aoclk.c +++ b/drivers/clk/meson/gxbb-aoclk.c @@ -23,29 +23,18 @@ #define AO_RTC_ALT_CLK_CNTL0 0x94 #define AO_RTC_ALT_CLK_CNTL1 0x98 =20 -#define GXBB_AO_PCLK(_name, _bit, _flags) \ -static struct clk_regmap gxbb_ao_##_name =3D { \ - .data =3D &(struct clk_regmap_gate_data) { \ - .offset =3D AO_RTI_GEN_CNTL_REG0, \ - .bit_idx =3D (_bit), \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D "gxbb_ao_" #_name, \ - .ops =3D &clk_regmap_gate_ops, \ - .parent_data =3D &(const struct clk_parent_data) { \ - .fw_name =3D "mpeg-clk", \ - }, \ - .num_parents =3D 1, \ - .flags =3D (_flags), \ - }, \ -} +static const struct clk_parent_data gxbb_ao_pclk_parents =3D { .fw_name = =3D "mpeg-clk" }; =20 -GXBB_AO_PCLK(remote, 0, CLK_IGNORE_UNUSED); -GXBB_AO_PCLK(i2c_master, 1, CLK_IGNORE_UNUSED); -GXBB_AO_PCLK(i2c_slave, 2, CLK_IGNORE_UNUSED); -GXBB_AO_PCLK(uart1, 3, CLK_IGNORE_UNUSED); -GXBB_AO_PCLK(uart2, 5, CLK_IGNORE_UNUSED); -GXBB_AO_PCLK(ir_blaster, 6, CLK_IGNORE_UNUSED); +#define GXBB_AO_PCLK(_name, _bit, _flags) \ + MESON_PCLK(gxbb_ao_##_name, AO_RTI_GEN_CNTL_REG0, _bit, \ + &gxbb_ao_pclk_parents, _flags) + +static GXBB_AO_PCLK(remote, 0, CLK_IGNORE_UNUSED); +static GXBB_AO_PCLK(i2c_master, 1, CLK_IGNORE_UNUSED); +static GXBB_AO_PCLK(i2c_slave, 2, CLK_IGNORE_UNUSED); +static GXBB_AO_PCLK(uart1, 3, CLK_IGNORE_UNUSED); +static GXBB_AO_PCLK(uart2, 5, CLK_IGNORE_UNUSED); +static GXBB_AO_PCLK(ir_blaster, 6, CLK_IGNORE_UNUSED); =20 static struct clk_regmap gxbb_ao_cts_oscin =3D { .data =3D &(struct clk_regmap_gate_data){ --=20 2.47.2 From nobody Fri Oct 3 20:30:33 2025 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59D29304BB4 for ; Mon, 25 Aug 2025 14:27:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132040; cv=none; b=NdECSWFjHd4hffkYbHgWu4+wOfDQIKvg4TMZuPFtbdqEnEYrZqVhsqebLwSuDieV+ptEnyELTNFTqGhO0h9aFQu3SDD4mOD6JRLkKyCRVf0QA58CjEYUrEyWuGKZzSa+pj+wsOKcst75/rwpbbm+C8T90AUKTDzyNa8hIH8PcSA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132040; c=relaxed/simple; bh=suncESI2oSW1jGwgW8HALT/gxYfqW5NYgFG0TK2ZRwc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tCI6cXwEPAZ5+zKxCmF3ZFv21DkejN7ku7mPsmO/FcW28OtD2FqC+chij6J825LYhqbtWZz+Wdbac8ZqLouPpplvT/ra/ufvCIiUQn3f0QmbgifWW0GZgaqDqcSikfDvEknQD21o6VTF1eNNswTgfHNpAtPTXR0o4iqyDSUlwRs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=vgfd8FLz; arc=none smtp.client-ip=209.85.221.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="vgfd8FLz" Received: by mail-wr1-f42.google.com with SMTP id ffacd0b85a97d-3c51f0158d8so3284838f8f.1 for ; Mon, 25 Aug 2025 07:27:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1756132033; x=1756736833; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=wmj4+KeJRz5xK/o1A5pSjOswraJHwrE5iHoxwCs+mmQ=; b=vgfd8FLzTLvULW5s1Ttkne+HaQReqPad1N3AXFPaioDQMKwXrRSNVhzFAbXcpBTybH wNyg5hngDROUVwD9a3izRNjbJnS5DA/ictcO82AH2IBOY/dc3+04lj70nzOO4YmTikT+ D7OlTkAO8cttwKvvTABoXkEHhtlOtNfwy7cy0u54DoEk2S/g+Si7mHifEX/elo1lRoHk 2WsOQiLJGO5qB+RBdEO/zLaOhzFhgmS7O4a0kFRH9npqVMdNs+ar2pbSwJoaEaXIfU3k pCzNrNNEyCRoD+e0Bq3xYoplS8Ib8KsaBGdx5585Xun3oNnUQNu79bt02dfXG98VS01o m3qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756132033; x=1756736833; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wmj4+KeJRz5xK/o1A5pSjOswraJHwrE5iHoxwCs+mmQ=; b=ikVtF2Np+ygK5O7rOro2R+t1TJUy4z+p40sMlRDU737V8oovh1sdjR0kX6cEJJVSag SGEX2mwcMVoGVG9zeY+Lbuld5qNokaunG1tMaJt2zetRiviMZVniGdtG589M82i+WPqG ubYQl0OzsgJdL6IA6wqeTN5bEMdEUoMfDIhXgZeO+sJygq4p3EilKwhY0lrsWI0hF1D9 eop/OGgdFz3a0QcFjz2Qn3/v5BChnXY0j1QCDRkJ/LyyRte/8+vZ5v9rfBSof7nXmO/8 VgBMr3isK6kjYwiC+2v4kso4rSljuE6NHHB+i/8kKfO6BzOPmYPxy4XVjE060O52wP7j KchQ== X-Forwarded-Encrypted: i=1; AJvYcCWTw98cLXGuRxZ+Ihq/ccm/YmSW3CEo0bSFGSztA1C1spFb1SUNVjO0V8FqkjF87QNBie8yue9e7/9QFq8=@vger.kernel.org X-Gm-Message-State: AOJu0YztGZ0zJg/FoXVyvBfRhJsqx5G6L6Me2A8D+EuIW66toqpF1YHO b/qUobPJeaR3rzmfHsPGBLMwcU74t2Dj2NM9iFgThJt6KCH9U+gtgcTlM2v2QnCSuh0= X-Gm-Gg: ASbGnctyqrdjOGce/HNW9WkJ8BhCU8+dQXnDm74I2ljAEa1yzHMuKoLcK2pqHm1G9sJ KyILj7o7RbTEXeCQTug+mkqkexTrRAomZcj80zxOlHqGLRst+rNGhmNEu/6JdY5JU2uh+VGZwYy qRMRnP8pA4B+UwFOkD3xJ/GcmIZwgzKEpmKKLKH0Ol+rH0JccLZnyCrfkWqCMufJf1dBDrgVXFw sLLKxWG9MXwStLEZKSh8P5M4SrPURlRB/71C3jxuXrH39YHc7iydfuHLXYQSGRsxkjvvYRxlC7u etun1Gp9G0JteZnTKoEK6e2DnruHlVnx+/4ejuERvhvswuHhcCUb0KzSYYUFsigr0bAk8TmC5ad tPXFRqntVt0p9YspxLvCcxNrTbboFGVHSZF/e X-Google-Smtp-Source: AGHT+IGnZNd0TF8B+2qH0v2ERRAcEJzB1LmVzNbD2rj+M2fJbkxWf2Ryny9Bv8Zv7wCD4HSuYBiLDw== X-Received: by 2002:a5d:6ac7:0:b0:3c6:cb4:e060 with SMTP id ffacd0b85a97d-3c60cb4e54amr5981665f8f.34.1756132033426; Mon, 25 Aug 2025 07:27:13 -0700 (PDT) Received: from toaster.baylibre.com ([2a01:e0a:3c5:5fb1:b261:baab:ed3d:3cb6]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3c70e4b9e1fsm12634462f8f.14.2025.08.25.07.27.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Aug 2025 07:27:13 -0700 (PDT) From: Jerome Brunet Date: Mon, 25 Aug 2025 16:26:35 +0200 Subject: [PATCH v2 10/12] clk: amlogic: add composite clock helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-meson-clk-cleanup-24-v2-10-0f402f01e117@baylibre.com> References: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> In-Reply-To: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2898; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=suncESI2oSW1jGwgW8HALT/gxYfqW5NYgFG0TK2ZRwc=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBorHK2LR9cAulu/Dg7wzveWSkLYkNJ9hi4wbYHo pFJxTH5+cWJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaKxytgAKCRDm/A8cN/La hSDrD/9Qb0PyVOZn3hszgeqgrG8upaAQ55iBmu/kHai53eku7dMNLCgo/GSxS12i1nnj8NSriLW ErB6hHemrtB7p9fYVUslxB/hZ9MISdi7tRa1yZjB6FuxI8XE+mZUICX5tmrea/cNAxFLAGcnQlN 63CIJ7+aYY6X0vM9nQIrY4D0gluWYwi85q2rxa4VaD0z7DzmhXUjKIF6XaztRJxp4rl4Zz54u+g P0Px1NL0pQdh3m1V4ADCp0hlht2Mnzvxneei7m4Mu8jAdo8K1TjrabWY8mAWheTSZ0JCSyg6KJi WvlFlQcKiK6nsgepnfrp+MXo2+/dpljD8J+K3zwkmA65txvZMac3NcBacKTG2ToB0oNKzFqOiRO TijnFU8ByjWNQOhGlD/H3vfpxvxIV5Rglm8Ds6CBqTLTFPEPc1iFTE9E41mrWxLok/nvH8ov6vQ hPfIhHKuIgFGlxtEZsqxcY9WiPpqIMqaQyzueRkUhy+j7LTEhT8+kSduPZUUsKYRwFnZFxcTMYk XyKrwLv4GAN4/x6tEqqXKSPmolH2SND4jkjse858xq0S+3Y05806RQL0270Q4/6IOLKcstu4hZE 5VHDw8Ltk2K0/Psd8SrPWGv2XkA703A+IqUiQuQ0kc7LPsCvpD3crNQrMt3bDU+csrYlXJ1V78w eaM64tYtmmBuiWw== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Device composite clocks tend to reproduce the usual sel/div/gate arrangement. Add macros to help define simple composite clocks in the system. The idea is _not_ to replace all instances of mux, div or gate with those macros. It is rather to use it for recurring and/or simple composite clocks, reducing controller verbosity where it makes sense. This should help reviews focus on the tricky parts. Signed-off-by: Jerome Brunet --- drivers/clk/meson/meson-clkc-utils.h | 57 ++++++++++++++++++++++++++++++++= ++++ 1 file changed, 57 insertions(+) diff --git a/drivers/clk/meson/meson-clkc-utils.h b/drivers/clk/meson/meson= -clkc-utils.h index 95d9f85f7ca22f63a16f8665d6f7a250b21bfdb8..ddadf14b4923781d8807546f35a= 1ba2e6a8a894a 100644 --- a/drivers/clk/meson/meson-clkc-utils.h +++ b/drivers/clk/meson/meson-clkc-utils.h @@ -48,4 +48,61 @@ struct clk_regmap _name =3D { \ #define MESON_PCLK_RO(_name, _reg, _bit, _pdata, _flags) \ __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pdata, _flags) =20 +/* Helpers for the usual sel/div/gate composite clocks */ +#define MESON_COMP_SEL(_prefix, _name, _reg, _shift, _mask, _pdata, \ + _table, _dflags, _iflags) \ +struct clk_regmap _prefix##_name##_sel =3D { \ + .data =3D &(struct clk_regmap_mux_data) { \ + .offset =3D (_reg), \ + .mask =3D (_mask), \ + .shift =3D (_shift), \ + .flags =3D (_dflags), \ + .table =3D (_table), \ + }, \ + .hw.init =3D &(struct clk_init_data){ \ + .name =3D #_name "_sel", \ + .ops =3D &clk_regmap_mux_ops, \ + .parent_data =3D _pdata, \ + .num_parents =3D ARRAY_SIZE(_pdata), \ + .flags =3D (_iflags), \ + }, \ +} + +#define MESON_COMP_DIV(_prefix, _name, _reg, _shift, _width, \ + _dflags, _iflags) \ +struct clk_regmap _prefix##_name##_div =3D { \ + .data =3D &(struct clk_regmap_div_data) { \ + .offset =3D (_reg), \ + .shift =3D (_shift), \ + .width =3D (_width), \ + .flags =3D (_dflags), \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D #_name "_div", \ + .ops =3D &clk_regmap_divider_ops, \ + .parent_hws =3D (const struct clk_hw *[]) { \ + &_prefix##_name##_sel.hw \ + }, \ + .num_parents =3D 1, \ + .flags =3D (_iflags), \ + }, \ +} + +#define MESON_COMP_GATE(_prefix, _name, _reg, _bit, _iflags) \ +struct clk_regmap _prefix##_name =3D { \ + .data =3D &(struct clk_regmap_gate_data) { \ + .offset =3D (_reg), \ + .bit_idx =3D (_bit), \ + }, \ + .hw.init =3D &(struct clk_init_data) { \ + .name =3D #_name, \ + .ops =3D &clk_regmap_gate_ops, \ + .parent_hws =3D (const struct clk_hw *[]) { \ + &_prefix##_name##_div.hw \ + }, \ + .num_parents =3D 1, \ + .flags =3D (_iflags), \ + }, \ +} + #endif --=20 2.47.2 From nobody Fri Oct 3 20:30:33 2025 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4144C304967 for ; Mon, 25 Aug 2025 14:27:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132040; cv=none; b=DHtOUhdWcw130Em2BNwHTZ22j+KJX3dsxm2hEOFT+DagSzy5LUmX9X7xq7oozlby371Ui9d/WA4Fae7kAI78Woz7BmnBbbDpwLY9UVoKSamb0ZYTA/kKvYG0laZF0u0uITbs+2m9vILUIIHW1h4gAxRx4LDCQGE9m+5Grt5iqFQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132040; c=relaxed/simple; bh=KKJgRJArtEZnmgn+Mscv9ei4wZaRB5fejXiQda3cJb4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fIjyXEcVIsbNsrGAU+wKj31BSHkWI8XgAAH02LclEVUIynSrbsWWGZ3oPtzNHncjW4uWFyX3C/OMNcpKfQOtZtY11pNAL/p2difE8bSW6FvMW5vFIHpVxqnCMHNp4CXi7czSiCcrTfQ0J+OxOHYVIQ25sXnc/DvASZuJnG6cGKk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=0b3eZDwH; arc=none smtp.client-ip=209.85.221.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="0b3eZDwH" Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-3c79f0a606fso1203915f8f.0 for ; Mon, 25 Aug 2025 07:27:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1756132034; x=1756736834; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=OUky9lqttrbpUCvILYpHg9Z0/QzSnBTRvjKKimO9Xdo=; b=0b3eZDwHjWXs3xhu6y9JtfuQbTuYINmlssZjl9qfPg2abkovdhrnHnGVmA+psLVaec EiVtWp5Wid9dCFwn9X4nL2YZcgJsXbggc5v7inJH0RV5mP0+Lyvk2pUVmok+eKPSB3ga p+qfumfUOrq0re/Q6X4Sljvj9iAKBQV2Hwi+VQDBNVx+4AMgt83V3tG1lBLA5V6QOfGE Jd6QeyWlsUfSOD+xluFmwNSdWPWR9kg/tLD70O4NWL7iZLKDTRiFHVP4pHMQugWlH7f8 uZj6+WxRm/EuPG8dlbCx2BsjTCB1LR6uiddo/jSOczrrobM7xOphTF374eUtnWZESlVQ XuLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756132034; x=1756736834; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OUky9lqttrbpUCvILYpHg9Z0/QzSnBTRvjKKimO9Xdo=; b=qz8zXnlxdTvP0EOqBed+KS+RHAbFsu8WLup6chESclUAtVkMaNsLBCdFKXlNb6IATT 7GQQNzhSeyugzwYMz7slw7S2JVdefc+33AQxRPUMRn/ZwwQeqSwMitqRX8U1nN9yomKI +Zoi7hN388h1rUNdcJODDxx1BOIKJfPKB8QTFqvDPVOfFD1/dzSff6PFMVZ4AW/QJiE2 fqwkRzw2GkkSVjYlEaQnHvc/TElfyt0d47+Q2ZtCA9PkUvqPdPqMqX4Ajj49RsdLx3/z x6bYBr79C+SVr+ZlZ6wLk1k2wup7UbQrCZTa6mSNr9e5hWJHpcnvScviRSGQP2wfHgVQ vW4w== X-Forwarded-Encrypted: i=1; AJvYcCWiOB6SVl8CHsMCWMK0Vam3vfULCzkc9kO3p++wE4w40m4NwTkOZ49cEoRj4JzOp84uCj+Y4a/ECUFlf0c=@vger.kernel.org X-Gm-Message-State: AOJu0YyjIACPrWeudcWsTFPTYXetOMJj9J3m7GHCLUeTKa+Eb1Drazd9 /LNog4wVXgVhpzgHzxi45FMeUKX3F7B/K0gAsb50VKkHZV+D82rVaHbmoGCJf4hcTlo= X-Gm-Gg: ASbGncuad3uEh8zvoO1K3Oayh2nJ4WYUS610qs5GMNU2I9aE0Zqj7w8I/es0l75QtZG kCtCpglUwS0NkC26Gm996865u8QcM2PGSMTDFlCpbY5GwJFMYILnOI8mrYnZpu7vahqYazT2S/X DtGzgFCiKQeDrXvmBnyZpPzgMxTrioJOfroZgKRJH5jkMNzciMq8QDl424QMMLwzfXNs+YJ8rDX ARiEW1z0bnSwbB492r4yST8+05zVIl52VKGFT44OH2b9GF3TSNWH+D9RU9Vb6py6DQMVK028IwT F8A4fcQQQEmSirNSojABZxbzKiI5lAAtILSlyiQ1jpEY4vuOGFoUQFgDAUifiGLjfHzI8izj9gw nG5jcTtIYIZ+sTqSO887jkrvx6chFx4/NNldL X-Google-Smtp-Source: AGHT+IFyirK+nJVW3TSIPe8IdYzeCN4+xJ95Y/siJ2NO5IGM9xDzrIhZnHpMmswZS9kHh+gZ03v77w== X-Received: by 2002:a05:6000:4022:b0:3ca:a190:c45a with SMTP id ffacd0b85a97d-3caa190c847mr1129222f8f.40.1756132034173; Mon, 25 Aug 2025 07:27:14 -0700 (PDT) Received: from toaster.baylibre.com ([2a01:e0a:3c5:5fb1:b261:baab:ed3d:3cb6]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3c70e4b9e1fsm12634462f8f.14.2025.08.25.07.27.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Aug 2025 07:27:13 -0700 (PDT) From: Jerome Brunet Date: Mon, 25 Aug 2025 16:26:36 +0200 Subject: [PATCH v2 11/12] clk: amlogic: align s4 and c3 pwm clock descriptions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-meson-clk-cleanup-24-v2-11-0f402f01e117@baylibre.com> References: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> In-Reply-To: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet , Chuan Liu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=23845; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=KKJgRJArtEZnmgn+Mscv9ei4wZaRB5fejXiQda3cJb4=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBorHK32MkKZMhtncHhNzkjnsZZFAA/KL4kBfxgZ oR/8jZtjSuJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaKxytwAKCRDm/A8cN/La hcrMD/wKJEBRLsHXNqvrJqmH63n0JoDfvtdVeSwVwXL2ReXRCuoq4Yt61Ei4LdXQCg55TN/SZL2 y1Gd9SsT1Y9bkoD1s22zoiE8PYOHFSNO9l2ejl9LFUPZ669l9WDXjNX/aF5e9/BJCO2xIyx0tGH 010yzihS1Eh6eI6i31O32HBjGyOkKH/WFdpQVqCezS3qi8ikVd/agYTUuB4tuzcCUb/DtA/5Ktl pZTCYZm2oWFb9aLH/DYrfqSdSInx3Wbjiw0gQXPeIGr6gv0ox2CnNlddZMjyhzP8hOobDYLv7pW VjxSGfBtbgqSpFLAkz1v4yvr+n9RmRcWGx3p+DIHtiy5/SPueE3hPiXoFfjhlwgnRtacEBfp3Yg 3raTRDKjfzcqyGXiyWUtpo9Ei4NstyySh8xeEOoeDihtOHMbLeVpDcr00rgOL6qkW8Fn1zA0/M5 wBFcS7fGR42hfilpLGBnwT+r2Wc1RgAqnLcaL1mwju2U68HUog0tZYKwLYVPHkEEMwhmAfhKC9P gwsvkl/ED0WzWgtEpCeQl1BUhf7Plf5me5HjNQ7Uwx/vr1oac6uco7uAom/dnVNRBTJQyZ4Thf/ FjMF1pmznyOmKzU4+CR5KtrybJ4S8LkWiZWwHa19DoXfsLGA3G8wn3tjS1ocvm6uYQEJkHIeyaT sgqM5SgLJfnNFAg== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 s4 and c3 follow exactly the same structure when it comes to PWM clocks but differ in the way these clocks are described, for no obvious reason. Align the description of the pwm clocks of these SoCs with the composite clock helpers. Reviewed-by: Chuan Liu Signed-off-by: Jerome Brunet --- drivers/clk/meson/c3-peripherals.c | 204 +++++---------- drivers/clk/meson/s4-peripherals.c | 508 +++------------------------------= ---- 2 files changed, 103 insertions(+), 609 deletions(-) diff --git a/drivers/clk/meson/c3-peripherals.c b/drivers/clk/meson/c3-peri= pherals.c index 02c9820cd98655e57a290859b595cf09d39e5fe3..fd35f9b7994720d069c5f72142d= 6064790d40b60 100644 --- a/drivers/clk/meson/c3-peripherals.c +++ b/drivers/clk/meson/c3-peripherals.c @@ -48,6 +48,15 @@ #define SPIFC_CLK_CTRL 0x1a0 #define NNA_CLK_CTRL 0x220 =20 +#define C3_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \ + MESON_COMP_SEL(c3_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0) + +#define C3_COMP_DIV(_name, _reg, _shift, _width) \ + MESON_COMP_DIV(c3_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT) + +#define C3_COMP_GATE(_name, _reg, _bit) \ + MESON_COMP_GATE(c3_, _name, _reg, _bit, CLK_SET_RATE_PARENT) + static struct clk_regmap c3_rtc_xtal_clkin =3D { .data =3D &(struct clk_regmap_gate_data) { .offset =3D RTC_BY_OSCIN_CTRL0, @@ -512,146 +521,61 @@ static const struct clk_parent_data c3_pwm_parents[]= =3D { { .fw_name =3D "fdiv3" } }; =20 -#define C3_PWM_CLK_MUX(_name, _reg, _shift) { \ - .data =3D &(struct clk_regmap_mux_data) { \ - .offset =3D _reg, \ - .mask =3D 0x3, \ - .shift =3D _shift, \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D #_name "_sel", \ - .ops =3D &clk_regmap_mux_ops, \ - .parent_data =3D c3_pwm_parents, \ - .num_parents =3D ARRAY_SIZE(c3_pwm_parents), \ - }, \ -} - -#define C3_PWM_CLK_DIV(_name, _reg, _shift) { \ - .data =3D &(struct clk_regmap_div_data) { \ - .offset =3D _reg, \ - .shift =3D _shift, \ - .width =3D 8, \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D #_name "_div", \ - .ops =3D &clk_regmap_divider_ops, \ - .parent_names =3D (const char *[]) { #_name "_sel" },\ - .num_parents =3D 1, \ - .flags =3D CLK_SET_RATE_PARENT, \ - }, \ -} - -#define C3_PWM_CLK_GATE(_name, _reg, _bit) { \ - .data =3D &(struct clk_regmap_gate_data) { \ - .offset =3D _reg, \ - .bit_idx =3D _bit, \ - }, \ - .hw.init =3D &(struct clk_init_data) { \ - .name =3D #_name, \ - .ops =3D &clk_regmap_gate_ops, \ - .parent_names =3D (const char *[]) { #_name "_div" },\ - .num_parents =3D 1, \ - .flags =3D CLK_SET_RATE_PARENT, \ - }, \ -} - -static struct clk_regmap c3_pwm_a_sel =3D - C3_PWM_CLK_MUX(pwm_a, PWM_CLK_AB_CTRL, 9); -static struct clk_regmap c3_pwm_a_div =3D - C3_PWM_CLK_DIV(pwm_a, PWM_CLK_AB_CTRL, 0); -static struct clk_regmap c3_pwm_a =3D - C3_PWM_CLK_GATE(pwm_a, PWM_CLK_AB_CTRL, 8); - -static struct clk_regmap c3_pwm_b_sel =3D - C3_PWM_CLK_MUX(pwm_b, PWM_CLK_AB_CTRL, 25); -static struct clk_regmap c3_pwm_b_div =3D - C3_PWM_CLK_DIV(pwm_b, PWM_CLK_AB_CTRL, 16); -static struct clk_regmap c3_pwm_b =3D - C3_PWM_CLK_GATE(pwm_b, PWM_CLK_AB_CTRL, 24); - -static struct clk_regmap c3_pwm_c_sel =3D - C3_PWM_CLK_MUX(pwm_c, PWM_CLK_CD_CTRL, 9); -static struct clk_regmap c3_pwm_c_div =3D - C3_PWM_CLK_DIV(pwm_c, PWM_CLK_CD_CTRL, 0); -static struct clk_regmap c3_pwm_c =3D - C3_PWM_CLK_GATE(pwm_c, PWM_CLK_CD_CTRL, 8); - -static struct clk_regmap c3_pwm_d_sel =3D - C3_PWM_CLK_MUX(pwm_d, PWM_CLK_CD_CTRL, 25); -static struct clk_regmap c3_pwm_d_div =3D - C3_PWM_CLK_DIV(pwm_d, PWM_CLK_CD_CTRL, 16); -static struct clk_regmap c3_pwm_d =3D - C3_PWM_CLK_GATE(pwm_d, PWM_CLK_CD_CTRL, 24); - -static struct clk_regmap c3_pwm_e_sel =3D - C3_PWM_CLK_MUX(pwm_e, PWM_CLK_EF_CTRL, 9); -static struct clk_regmap c3_pwm_e_div =3D - C3_PWM_CLK_DIV(pwm_e, PWM_CLK_EF_CTRL, 0); -static struct clk_regmap c3_pwm_e =3D - C3_PWM_CLK_GATE(pwm_e, PWM_CLK_EF_CTRL, 8); - -static struct clk_regmap c3_pwm_f_sel =3D - C3_PWM_CLK_MUX(pwm_f, PWM_CLK_EF_CTRL, 25); -static struct clk_regmap c3_pwm_f_div =3D - C3_PWM_CLK_DIV(pwm_f, PWM_CLK_EF_CTRL, 16); -static struct clk_regmap c3_pwm_f =3D - C3_PWM_CLK_GATE(pwm_f, PWM_CLK_EF_CTRL, 24); - -static struct clk_regmap c3_pwm_g_sel =3D - C3_PWM_CLK_MUX(pwm_g, PWM_CLK_GH_CTRL, 9); -static struct clk_regmap c3_pwm_g_div =3D - C3_PWM_CLK_DIV(pwm_g, PWM_CLK_GH_CTRL, 0); -static struct clk_regmap c3_pwm_g =3D - C3_PWM_CLK_GATE(pwm_g, PWM_CLK_GH_CTRL, 8); - -static struct clk_regmap c3_pwm_h_sel =3D - C3_PWM_CLK_MUX(pwm_h, PWM_CLK_GH_CTRL, 25); -static struct clk_regmap c3_pwm_h_div =3D - C3_PWM_CLK_DIV(pwm_h, PWM_CLK_GH_CTRL, 16); -static struct clk_regmap c3_pwm_h =3D - C3_PWM_CLK_GATE(pwm_h, PWM_CLK_GH_CTRL, 24); - -static struct clk_regmap c3_pwm_i_sel =3D - C3_PWM_CLK_MUX(pwm_i, PWM_CLK_IJ_CTRL, 9); -static struct clk_regmap c3_pwm_i_div =3D - C3_PWM_CLK_DIV(pwm_i, PWM_CLK_IJ_CTRL, 0); -static struct clk_regmap c3_pwm_i =3D - C3_PWM_CLK_GATE(pwm_i, PWM_CLK_IJ_CTRL, 8); - -static struct clk_regmap c3_pwm_j_sel =3D - C3_PWM_CLK_MUX(pwm_j, PWM_CLK_IJ_CTRL, 25); -static struct clk_regmap c3_pwm_j_div =3D - C3_PWM_CLK_DIV(pwm_j, PWM_CLK_IJ_CTRL, 16); -static struct clk_regmap c3_pwm_j =3D - C3_PWM_CLK_GATE(pwm_j, PWM_CLK_IJ_CTRL, 24); - -static struct clk_regmap c3_pwm_k_sel =3D - C3_PWM_CLK_MUX(pwm_k, PWM_CLK_KL_CTRL, 9); -static struct clk_regmap c3_pwm_k_div =3D - C3_PWM_CLK_DIV(pwm_k, PWM_CLK_KL_CTRL, 0); -static struct clk_regmap c3_pwm_k =3D - C3_PWM_CLK_GATE(pwm_k, PWM_CLK_KL_CTRL, 8); - -static struct clk_regmap c3_pwm_l_sel =3D - C3_PWM_CLK_MUX(pwm_l, PWM_CLK_KL_CTRL, 25); -static struct clk_regmap c3_pwm_l_div =3D - C3_PWM_CLK_DIV(pwm_l, PWM_CLK_KL_CTRL, 16); -static struct clk_regmap c3_pwm_l =3D - C3_PWM_CLK_GATE(pwm_l, PWM_CLK_KL_CTRL, 24); - -static struct clk_regmap c3_pwm_m_sel =3D - C3_PWM_CLK_MUX(pwm_m, PWM_CLK_MN_CTRL, 9); -static struct clk_regmap c3_pwm_m_div =3D - C3_PWM_CLK_DIV(pwm_m, PWM_CLK_MN_CTRL, 0); -static struct clk_regmap c3_pwm_m =3D - C3_PWM_CLK_GATE(pwm_m, PWM_CLK_MN_CTRL, 8); - -static struct clk_regmap c3_pwm_n_sel =3D - C3_PWM_CLK_MUX(pwm_n, PWM_CLK_MN_CTRL, 25); -static struct clk_regmap c3_pwm_n_div =3D - C3_PWM_CLK_DIV(pwm_n, PWM_CLK_MN_CTRL, 16); -static struct clk_regmap c3_pwm_n =3D - C3_PWM_CLK_GATE(pwm_n, PWM_CLK_MN_CTRL, 24); +static C3_COMP_SEL(pwm_a, PWM_CLK_AB_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_a, PWM_CLK_AB_CTRL, 0, 8); +static C3_COMP_GATE(pwm_a, PWM_CLK_AB_CTRL, 8); + +static C3_COMP_SEL(pwm_b, PWM_CLK_AB_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_b, PWM_CLK_AB_CTRL, 16, 8); +static C3_COMP_GATE(pwm_b, PWM_CLK_AB_CTRL, 24); + +static C3_COMP_SEL(pwm_c, PWM_CLK_CD_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_c, PWM_CLK_CD_CTRL, 0, 8); +static C3_COMP_GATE(pwm_c, PWM_CLK_CD_CTRL, 8); + +static C3_COMP_SEL(pwm_d, PWM_CLK_CD_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_d, PWM_CLK_CD_CTRL, 16, 8); +static C3_COMP_GATE(pwm_d, PWM_CLK_CD_CTRL, 24); + +static C3_COMP_SEL(pwm_e, PWM_CLK_EF_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_e, PWM_CLK_EF_CTRL, 0, 8); +static C3_COMP_GATE(pwm_e, PWM_CLK_EF_CTRL, 8); + +static C3_COMP_SEL(pwm_f, PWM_CLK_EF_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_f, PWM_CLK_EF_CTRL, 16, 8); +static C3_COMP_GATE(pwm_f, PWM_CLK_EF_CTRL, 24); + +static C3_COMP_SEL(pwm_g, PWM_CLK_GH_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_g, PWM_CLK_GH_CTRL, 0, 8); +static C3_COMP_GATE(pwm_g, PWM_CLK_GH_CTRL, 8); + +static C3_COMP_SEL(pwm_h, PWM_CLK_GH_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_h, PWM_CLK_GH_CTRL, 16, 8); +static C3_COMP_GATE(pwm_h, PWM_CLK_GH_CTRL, 24); + +static C3_COMP_SEL(pwm_i, PWM_CLK_IJ_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_i, PWM_CLK_IJ_CTRL, 0, 8); +static C3_COMP_GATE(pwm_i, PWM_CLK_IJ_CTRL, 8); + +static C3_COMP_SEL(pwm_j, PWM_CLK_IJ_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_j, PWM_CLK_IJ_CTRL, 16, 8); +static C3_COMP_GATE(pwm_j, PWM_CLK_IJ_CTRL, 24); + +static C3_COMP_SEL(pwm_k, PWM_CLK_KL_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_k, PWM_CLK_KL_CTRL, 0, 8); +static C3_COMP_GATE(pwm_k, PWM_CLK_KL_CTRL, 8); + +static C3_COMP_SEL(pwm_l, PWM_CLK_KL_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_l, PWM_CLK_KL_CTRL, 16, 8); +static C3_COMP_GATE(pwm_l, PWM_CLK_KL_CTRL, 24); + +static C3_COMP_SEL(pwm_m, PWM_CLK_MN_CTRL, 9, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_m, PWM_CLK_MN_CTRL, 0, 8); +static C3_COMP_GATE(pwm_m, PWM_CLK_MN_CTRL, 8); + +static C3_COMP_SEL(pwm_n, PWM_CLK_MN_CTRL, 25, 0x3, c3_pwm_parents); +static C3_COMP_DIV(pwm_n, PWM_CLK_MN_CTRL, 16, 8); +static C3_COMP_GATE(pwm_n, PWM_CLK_MN_CTRL, 24); =20 static const struct clk_parent_data c3_spicc_parents[] =3D { { .fw_name =3D "oscin" }, diff --git a/drivers/clk/meson/s4-peripherals.c b/drivers/clk/meson/s4-peri= pherals.c index 3e048e645b080f9e5982ef908e3f9c43578a0b5f..6d69b132d1e1f5950d73757c45b= 920c9c9052344 100644 --- a/drivers/clk/meson/s4-peripherals.c +++ b/drivers/clk/meson/s4-peripherals.c @@ -62,6 +62,15 @@ #define CLKCTRL_PWM_CLK_IJ_CTRL 0x190 #define CLKCTRL_DEMOD_CLK_CTRL 0x200 =20 +#define S4_COMP_SEL(_name, _reg, _shift, _mask, _pdata) \ + MESON_COMP_SEL(s4_, _name, _reg, _shift, _mask, _pdata, NULL, 0, 0) + +#define S4_COMP_DIV(_name, _reg, _shift, _width) \ + MESON_COMP_DIV(s4_, _name, _reg, _shift, _width, 0, CLK_SET_RATE_PARENT) + +#define S4_COMP_GATE(_name, _reg, _bit) \ + MESON_COMP_GATE(s4_, _name, _reg, _bit, CLK_SET_RATE_PARENT) + static struct clk_regmap s4_rtc_32k_by_oscin_clkin =3D { .data =3D &(struct clk_regmap_gate_data){ .offset =3D CLKCTRL_RTC_BY_OSCIN_CTRL0, @@ -2559,484 +2568,45 @@ static const struct clk_parent_data s4_pwm_parents= [] =3D { { .fw_name =3D "fclk_div3", }, }; =20 -static struct clk_regmap s4_pwm_a_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_AB_CTRL, - .mask =3D 0x3, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_a_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; - -static struct clk_regmap s4_pwm_a_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_AB_CTRL, - .shift =3D 0, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_a_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_a_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_a =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_AB_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_a_gate", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_a_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_b_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_AB_CTRL, - .mask =3D 0x3, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_b_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; - -static struct clk_regmap s4_pwm_b_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_AB_CTRL, - .shift =3D 16, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_b_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_b_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_b =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_AB_CTRL, - .bit_idx =3D 24, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_b", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_b_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_c_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_CD_CTRL, - .mask =3D 0x3, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_c_mux", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; - -static struct clk_regmap s4_pwm_c_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_CD_CTRL, - .shift =3D 0, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_c_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_c_sel.hw - }, - .num_parents =3D 1, - }, -}; - -static struct clk_regmap s4_pwm_c =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_CD_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_c", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_c_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_d_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_CD_CTRL, - .mask =3D 0x3, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_d_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; - -static struct clk_regmap s4_pwm_d_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_CD_CTRL, - .shift =3D 16, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_d_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_d_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_d =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_CD_CTRL, - .bit_idx =3D 24, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_d", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_d_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_e_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_EF_CTRL, - .mask =3D 0x3, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_e_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; - -static struct clk_regmap s4_pwm_e_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_EF_CTRL, - .shift =3D 0, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_e_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_e_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_e =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_EF_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_e", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_e_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_f_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_EF_CTRL, - .mask =3D 0x3, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_f_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; +static S4_COMP_SEL(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 9, 0x3, s4_pwm_parents); +static S4_COMP_DIV(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 0, 8); +static S4_COMP_GATE(pwm_a, CLKCTRL_PWM_CLK_AB_CTRL, 8); =20 -static struct clk_regmap s4_pwm_f_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_EF_CTRL, - .shift =3D 16, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_f_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_f_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 25, 0x3, s4_pwm_parents= ); +static S4_COMP_DIV(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 16, 8); +static S4_COMP_GATE(pwm_b, CLKCTRL_PWM_CLK_AB_CTRL, 24); =20 -static struct clk_regmap s4_pwm_f =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_EF_CTRL, - .bit_idx =3D 24, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_f", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_f_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 9, 0x3, s4_pwm_parents); +static S4_COMP_DIV(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 0, 8); +static S4_COMP_GATE(pwm_c, CLKCTRL_PWM_CLK_CD_CTRL, 8); =20 -static struct clk_regmap s4_pwm_g_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_GH_CTRL, - .mask =3D 0x3, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_g_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; +static S4_COMP_SEL(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 25, 0x3, s4_pwm_parents= ); +static S4_COMP_DIV(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 16, 8); +static S4_COMP_GATE(pwm_d, CLKCTRL_PWM_CLK_CD_CTRL, 24); =20 -static struct clk_regmap s4_pwm_g_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_GH_CTRL, - .shift =3D 0, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_g_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_g_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 9, 0x3, s4_pwm_parents); +static S4_COMP_DIV(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 0, 8); +static S4_COMP_GATE(pwm_e, CLKCTRL_PWM_CLK_EF_CTRL, 8); =20 -static struct clk_regmap s4_pwm_g =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_GH_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_g", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_g_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 25, 0x3, s4_pwm_parents= ); +static S4_COMP_DIV(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 16, 8); +static S4_COMP_GATE(pwm_f, CLKCTRL_PWM_CLK_EF_CTRL, 24); =20 -static struct clk_regmap s4_pwm_h_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_GH_CTRL, - .mask =3D 0x3, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_h_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; +static S4_COMP_SEL(pwm_g, CLKCTRL_PWM_CLK_GH_CTRL, 9, 0x3, s4_pwm_parents); +static S4_COMP_DIV(pwm_g, CLKCTRL_PWM_CLK_GH_CTRL, 0, 8); +static S4_COMP_GATE(pwm_g, CLKCTRL_PWM_CLK_GH_CTRL, 8); =20 -static struct clk_regmap s4_pwm_h_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_GH_CTRL, - .shift =3D 16, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_h_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_h_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_h, CLKCTRL_PWM_CLK_GH_CTRL, 25, 0x3, s4_pwm_parents= ); +static S4_COMP_DIV(pwm_h, CLKCTRL_PWM_CLK_GH_CTRL, 16, 8); +static S4_COMP_GATE(pwm_h, CLKCTRL_PWM_CLK_GH_CTRL, 24); =20 -static struct clk_regmap s4_pwm_h =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_GH_CTRL, - .bit_idx =3D 24, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_h", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_h_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_i, CLKCTRL_PWM_CLK_IJ_CTRL, 9, 0x3, s4_pwm_parents); +static S4_COMP_DIV(pwm_i, CLKCTRL_PWM_CLK_IJ_CTRL, 0, 8); +static S4_COMP_GATE(pwm_i, CLKCTRL_PWM_CLK_IJ_CTRL, 8); =20 -static struct clk_regmap s4_pwm_i_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_IJ_CTRL, - .mask =3D 0x3, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_i_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; - -static struct clk_regmap s4_pwm_i_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_IJ_CTRL, - .shift =3D 0, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_i_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_i_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_i =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_IJ_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_i", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_i_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_j_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D CLKCTRL_PWM_CLK_IJ_CTRL, - .mask =3D 0x3, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_j_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D s4_pwm_parents, - .num_parents =3D ARRAY_SIZE(s4_pwm_parents), - .flags =3D 0, - }, -}; - -static struct clk_regmap s4_pwm_j_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D CLKCTRL_PWM_CLK_IJ_CTRL, - .shift =3D 16, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_j_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_j_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap s4_pwm_j =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D CLKCTRL_PWM_CLK_IJ_CTRL, - .bit_idx =3D 24, - }, - .hw.init =3D &(struct clk_init_data){ - .name =3D "pwm_j", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &s4_pwm_j_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static S4_COMP_SEL(pwm_j, CLKCTRL_PWM_CLK_IJ_CTRL, 25, 0x3, s4_pwm_parents= ); +static S4_COMP_DIV(pwm_j, CLKCTRL_PWM_CLK_IJ_CTRL, 16, 8); +static S4_COMP_GATE(pwm_j, CLKCTRL_PWM_CLK_IJ_CTRL, 24); =20 static struct clk_regmap s4_saradc_sel =3D { .data =3D &(struct clk_regmap_mux_data) { --=20 2.47.2 From nobody Fri Oct 3 20:30:33 2025 Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 527C3305E1D for ; Mon, 25 Aug 2025 14:27:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132043; cv=none; b=qC2vQzV9iqKHCuv9zV8kKRlKplULvE+Mlab//pW5bljiHsiILKAjZ30Z+mBIrW+3ECRF0PGKEPIqphIdWdqQ4t2RxiwcTQUdu+ZthMcsKFHD1t8Ma8WHugUBvhVgZ9bBQi2cLIpHAgTZ03IMhTOA82mhufbY5Eus8ePvH0x2vtA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756132043; c=relaxed/simple; bh=ps9sLzPPWk2M8ivkTmXUaslXwG8/bmatTRMHNFG1fME=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hrfzN4MaxBtae83jB9pN2iVGu/0B+fh37Tp/W6PBrhrK1fsaDHPhk7NXo/fSZWqRCHVqQPxa+MgeSAMYJvxECjih3b30ktUYY9mZ1yJHVo2aFHUoJOV0zqO1M2sgx32XbfGYPaSSbLq5dTM/MBG34EqbAw5DY78TlbMDWvpnhgQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=GwYgvgXE; arc=none smtp.client-ip=209.85.221.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="GwYgvgXE" Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-3c8fe6bd1a2so429613f8f.1 for ; Mon, 25 Aug 2025 07:27:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1756132035; x=1756736835; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ztmX1UDMK5rFccXy1oFM7d/s55AHNRDE1K8M0+F4fD8=; b=GwYgvgXEuCdmuBiCuD8TSEMhxeZat/mKZzXPkF5uTP6ryX9HP4yZ0VkzHNIddp8DpP HWpJDetJypDWuVPZN+wJml9Jz+s4tWooTo90+NVZ7btJ1onMz8akN9dArVDe9t7+PV04 e+oh2AXlK1l0X1vdZFL80/EhX5+ZXaJG6e+JxCIIlKcn0AE5gwfycbFpHbaTYaVbckIH n8G17RKyvZw9jIXY9LLaiVmKh+nLhxD/lUv0iaZAJFGETSZIv7hDdWvBTeF2D1nkeWqP IcnL7U8E07+24psTmpke1Pp724a3U30g4wGjCFBE/kasKkYgDX2g0JwSy4OnILlfE5sG zFyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756132035; x=1756736835; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ztmX1UDMK5rFccXy1oFM7d/s55AHNRDE1K8M0+F4fD8=; b=MJkc8EcPZBL6CBUuPjXkmJ2NS2EWvOAFJbAZgxP9wluTH9TJo5J4Y5OGNdjluLXoDW vwxhKKqRZDtjO9XS7t+sXcSKgVyPbaQMGQlN1TIG+T2cDeEh4szvQb5JBuPdan3qM7kX jitjP5l0oONvb5wVdLlxmR3DJz6vxM45rJivvmGk9+lvpW9E0BGvUkw9OhBc28v8xGj4 /B0XAFVduuNA5P+xEoG6HuWPNBmo0WR/HV8WmX5+uaEu70/smCVCX4UYZao6pA9rI2pB m4b/ePcnY9Gw3RJ1GnItOkib08g5sfE1H33k/ll96hbitxzPKYgoBZZJ80OQD8dZzuzb gVSQ== X-Forwarded-Encrypted: i=1; AJvYcCVqVDD+eYek947o/EzTHEfoc/+0Hkdna9mgtEORJik5NO5cOTn4Ly614qy3tGdSnU4URWEIeuIGWT/7L2Y=@vger.kernel.org X-Gm-Message-State: AOJu0YwZZ9rAB0tuTSNvLjQQfpe8lPvv1WoMUylBQHf17MCxeEjVBo0k T6US2V2H+N7zB4a52is8Dy1pjbvwuGcUxN46Sb5LRjJ93kusPqkn6K3i3FkCXM8pbLE= X-Gm-Gg: ASbGncsH7RQyagMYzrWbVWFenNsqLb0v5OpbjnTef5j1ReEyrdbQy7n89XjcTZ/DsRq oY7i4rVgmw3eWrYYQtqO6eL8L49Vqj2/F/xc9H25G74ygJMtCJPn8clYVRFBP8VrS9W7C39yz7z yPpt7kEKnhonL+On4qa2tb3MgwQpcrWnUBh5WKTx3yndLhME9I9/d1ABH6jVo3+reY+TKnVpOCl qMJT9YODJAX4iU4DMEG/NMvzBCVR3wFRop3gaY3CVNxFsj1zNkcWru0eSKChU9JCgFXjpJoNxgw 89oRdvzmaXuMDl4bgHEuT9MC14hvBO22SUWwnjYghCrnm/NJiuhFCQAeljkhMNAUjhRKLi0v+ic 0Z1818xyQQrkGp282IjPyWtjiI/hHUuaL/w88 X-Google-Smtp-Source: AGHT+IFnC0MUZSq/sl9kL/TcEekI5S6Ch+nzFMuQT2QCGnMv7MVM3STVdYmSZ5zm0xBhJbPzwkXGqQ== X-Received: by 2002:a05:6000:238a:b0:3b8:d79a:6a60 with SMTP id ffacd0b85a97d-3c5daa27b08mr9526344f8f.3.1756132034951; Mon, 25 Aug 2025 07:27:14 -0700 (PDT) Received: from toaster.baylibre.com ([2a01:e0a:3c5:5fb1:b261:baab:ed3d:3cb6]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-3c70e4b9e1fsm12634462f8f.14.2025.08.25.07.27.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Aug 2025 07:27:14 -0700 (PDT) From: Jerome Brunet Date: Mon, 25 Aug 2025 16:26:37 +0200 Subject: [PATCH v2 12/12] clk: amlogic: c3-peripherals: use helper for basic composite clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-meson-clk-cleanup-24-v2-12-0f402f01e117@baylibre.com> References: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> In-Reply-To: <20250825-meson-clk-cleanup-24-v2-0-0f402f01e117@baylibre.com> To: Neil Armstrong , Michael Turquette , Stephen Boyd , Kevin Hilman , Martin Blumenstingl Cc: linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Jerome Brunet , Chuan Liu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=32323; i=jbrunet@baylibre.com; h=from:subject:message-id; bh=ps9sLzPPWk2M8ivkTmXUaslXwG8/bmatTRMHNFG1fME=; b=owEBbQKS/ZANAwAKAeb8Dxw38tqFAcsmYgBorHK4qpXm7JmpvPobuRaQvfv+8Nfs2wLyI4+RD dk9RSaqFQCJAjMEAAEKAB0WIQT04VmuGPP1bV8btxvm/A8cN/LahQUCaKxyuAAKCRDm/A8cN/La hRGoEACDZa/T4n3cZ+Et6j5Ca+v57X1x5SyuJ2iXWhlDxHe0rIZIRSBjD5FqDgNP8mePJIPqeOy 2YaS4wC25muwGthDedfsI6xl7XNhwxlCgKZ5h4CPT04FFyzHM3lXJtGqD4dkg07zLCTTfCz8Wdm WA7eRVBgKHlhd1ZBzjvkTyy1z1dwcHEegWC2tydllMeTYuLRViF+Tn+VHr8+7h8GwjuqOUNpMz6 ePO23AlWSuH7g6YssXUqKMLjhuijjzDlY1uZSvr9pxgWRR7YVz7O5FFV6qtSFCRJlEMywEl6DER mxWzs/7yug9/r40V4AAOgJm+jdwWkeshUssX6XcEUkYbtLlhB7+CpTUzgY/4jHVh/lZ9dI42aOZ Tu1ytx2J34WeRVMO3QcL8QmkXWzJA/AyAB6bRWXYohgCKprY4byIfuQnaWTpaJm2tuiGLLrItRz sOj2AS73uipN0gd2VJMelZ81x30d6g2MS8cJF2p883WZ6kCTbrXcAww3rU+ZKlSEg37WtE6Bj7J 92osANTpGYvFn49R1taeZOGT++1gKomnKByigaVhRiATOY+7AHatcRtAZb9IUzwt61UKAMEG8Bp z72ZPSjjHi28E4/zIJJnCIXF8XwZxn8+rbm5cT9k8XSNSk/8MPlJBhsdazQ6s33okylcFquTCHB NnnmDwwLOOG3xWA== X-Developer-Key: i=jbrunet@baylibre.com; a=openpgp; fpr=F29F26CF27BAE1A9719AE6BDC3C92AAF3E60AED9 Use the composite clock helpers to define simple composite clocks of the c3-peripherals clock controller. This reduces the verbosity of the controller code on these very simple parts, making maintenance simpler. Reviewed-by: Chuan Liu Signed-off-by: Jerome Brunet --- drivers/clk/meson/c3-peripherals.c | 1029 +++-----------------------------= ---- 1 file changed, 63 insertions(+), 966 deletions(-) diff --git a/drivers/clk/meson/c3-peripherals.c b/drivers/clk/meson/c3-peri= pherals.c index fd35f9b7994720d069c5f72142d6064790d40b60..b158756cfee4dd4bad5c0c9576d= a02d2cb8ee515 100644 --- a/drivers/clk/meson/c3-peripherals.c +++ b/drivers/clk/meson/c3-peripherals.c @@ -467,52 +467,9 @@ static const struct clk_parent_data c3_saradc_parents[= ] =3D { { .fw_name =3D "sysclk" } }; =20 -static struct clk_regmap c3_saradc_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D SAR_CLK_CTRL0, - .mask =3D 0x1, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "saradc_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_saradc_parents, - .num_parents =3D ARRAY_SIZE(c3_saradc_parents), - }, -}; - -static struct clk_regmap c3_saradc_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D SAR_CLK_CTRL0, - .shift =3D 0, - .width =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "saradc_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_saradc_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_saradc =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D SAR_CLK_CTRL0, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "saradc", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_saradc_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(saradc, SAR_CLK_CTRL0, 9, 0x1, c3_saradc_parents); +static C3_COMP_DIV(saradc, SAR_CLK_CTRL0, 0, 8); +static C3_COMP_GATE(saradc, SAR_CLK_CTRL0, 8); =20 static const struct clk_parent_data c3_pwm_parents[] =3D { { .fw_name =3D "oscin" }, @@ -588,99 +545,13 @@ static const struct clk_parent_data c3_spicc_parents[= ] =3D { { .fw_name =3D "gp1" } }; =20 -static struct clk_regmap c3_spicc_a_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D SPICC_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "spicc_a_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_spicc_parents, - .num_parents =3D ARRAY_SIZE(c3_spicc_parents), - }, -}; - -static struct clk_regmap c3_spicc_a_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D SPICC_CLK_CTRL, - .shift =3D 0, - .width =3D 6, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "spicc_a_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_spicc_a_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_spicc_a =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D SPICC_CLK_CTRL, - .bit_idx =3D 6, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "spicc_a", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_spicc_a_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_spicc_b_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D SPICC_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 23, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "spicc_b_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_spicc_parents, - .num_parents =3D ARRAY_SIZE(c3_spicc_parents), - }, -}; - -static struct clk_regmap c3_spicc_b_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D SPICC_CLK_CTRL, - .shift =3D 16, - .width =3D 6, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "spicc_b_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_spicc_b_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(spicc_a, SPICC_CLK_CTRL, 7, 0x7, c3_spicc_parents); +static C3_COMP_DIV(spicc_a, SPICC_CLK_CTRL, 0, 6); +static C3_COMP_GATE(spicc_a, SPICC_CLK_CTRL, 6); =20 -static struct clk_regmap c3_spicc_b =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D SPICC_CLK_CTRL, - .bit_idx =3D 22, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "spicc_b", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_spicc_b_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(spicc_b, SPICC_CLK_CTRL, 23, 0x7, c3_spicc_parents); +static C3_COMP_DIV(spicc_b, SPICC_CLK_CTRL, 16, 6); +static C3_COMP_GATE(spicc_b, SPICC_CLK_CTRL, 22); =20 static const struct clk_parent_data c3_spifc_parents[] =3D { { .fw_name =3D "gp0" }, @@ -693,52 +564,9 @@ static const struct clk_parent_data c3_spifc_parents[]= =3D { { .fw_name =3D "fdiv7" } }; =20 -static struct clk_regmap c3_spifc_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D SPIFC_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "spifc_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_spifc_parents, - .num_parents =3D ARRAY_SIZE(c3_spifc_parents), - }, -}; - -static struct clk_regmap c3_spifc_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D SPIFC_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "spifc_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_spifc_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_spifc =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D SPIFC_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "spifc", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_spifc_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(spifc, SPIFC_CLK_CTRL, 9, 0x7, c3_spifc_parents); +static C3_COMP_DIV(spifc, SPIFC_CLK_CTRL, 0, 7); +static C3_COMP_GATE(spifc, SPIFC_CLK_CTRL, 8); =20 static const struct clk_parent_data c3_sd_emmc_parents[] =3D { { .fw_name =3D "oscin" }, @@ -751,146 +579,17 @@ static const struct clk_parent_data c3_sd_emmc_paren= ts[] =3D { { .fw_name =3D "gp0" } }; =20 -static struct clk_regmap c3_sd_emmc_a_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D SD_EMMC_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "sd_emmc_a_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_sd_emmc_parents, - .num_parents =3D ARRAY_SIZE(c3_sd_emmc_parents), - }, -}; - -static struct clk_regmap c3_sd_emmc_a_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D SD_EMMC_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "sd_emmc_a_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_sd_emmc_a_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_sd_emmc_a =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D SD_EMMC_CLK_CTRL, - .bit_idx =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "sd_emmc_a", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_sd_emmc_a_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_sd_emmc_b_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D SD_EMMC_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "sd_emmc_b_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_sd_emmc_parents, - .num_parents =3D ARRAY_SIZE(c3_sd_emmc_parents), - }, -}; - -static struct clk_regmap c3_sd_emmc_b_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D SD_EMMC_CLK_CTRL, - .shift =3D 16, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "sd_emmc_b_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_sd_emmc_b_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_sd_emmc_b =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D SD_EMMC_CLK_CTRL, - .bit_idx =3D 23, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "sd_emmc_b", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_sd_emmc_b_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_sd_emmc_c_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D NAND_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "sd_emmc_c_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_sd_emmc_parents, - .num_parents =3D ARRAY_SIZE(c3_sd_emmc_parents), - }, -}; +static C3_COMP_SEL(sd_emmc_a, SD_EMMC_CLK_CTRL, 9, 0x7, c3_sd_emmc_parents= ); +static C3_COMP_DIV(sd_emmc_a, SD_EMMC_CLK_CTRL, 0, 7); +static C3_COMP_GATE(sd_emmc_a, SD_EMMC_CLK_CTRL, 7); =20 -static struct clk_regmap c3_sd_emmc_c_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D NAND_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "sd_emmc_c_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_sd_emmc_c_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(sd_emmc_b, SD_EMMC_CLK_CTRL, 25, 0x7, c3_sd_emmc_parent= s); +static C3_COMP_DIV(sd_emmc_b, SD_EMMC_CLK_CTRL, 16, 7); +static C3_COMP_GATE(sd_emmc_b, SD_EMMC_CLK_CTRL, 23); =20 -static struct clk_regmap c3_sd_emmc_c =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D NAND_CLK_CTRL, - .bit_idx =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "sd_emmc_c", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_sd_emmc_c_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(sd_emmc_c, NAND_CLK_CTRL, 9, 0x7, c3_sd_emmc_parents); +static C3_COMP_DIV(sd_emmc_c, NAND_CLK_CTRL, 0, 7); +static C3_COMP_GATE(sd_emmc_c, NAND_CLK_CTRL, 7); =20 static struct clk_regmap c3_ts_div =3D { .data =3D &(struct clk_regmap_div_data) { @@ -996,52 +695,9 @@ static const struct clk_parent_data c3_mipi_dsi_meas_p= arents[] =3D { { .fw_name =3D "fdiv7" } }; =20 -static struct clk_regmap c3_mipi_dsi_meas_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D VDIN_MEAS_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 21, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "mipi_dsi_meas_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_mipi_dsi_meas_parents, - .num_parents =3D ARRAY_SIZE(c3_mipi_dsi_meas_parents), - }, -}; - -static struct clk_regmap c3_mipi_dsi_meas_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D VDIN_MEAS_CLK_CTRL, - .shift =3D 12, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "mipi_dsi_meas_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_mipi_dsi_meas_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_mipi_dsi_meas =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D VDIN_MEAS_CLK_CTRL, - .bit_idx =3D 20, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "mipi_dsi_meas", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_mipi_dsi_meas_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(mipi_dsi_meas, VDIN_MEAS_CLK_CTRL, 21, 0x7, c3_mipi_dsi= _meas_parents); +static C3_COMP_DIV(mipi_dsi_meas, VDIN_MEAS_CLK_CTRL, 12, 7); +static C3_COMP_GATE(mipi_dsi_meas, VDIN_MEAS_CLK_CTRL, 20); =20 static const struct clk_parent_data c3_dsi_phy_parents[] =3D { { .fw_name =3D "gp1" }, @@ -1054,52 +710,9 @@ static const struct clk_parent_data c3_dsi_phy_parent= s[] =3D { { .fw_name =3D "fdiv7" } }; =20 -static struct clk_regmap c3_dsi_phy_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D MIPIDSI_PHY_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 12, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "dsi_phy_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_dsi_phy_parents, - .num_parents =3D ARRAY_SIZE(c3_dsi_phy_parents), - }, -}; - -static struct clk_regmap c3_dsi_phy_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D MIPIDSI_PHY_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "dsi_phy_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_dsi_phy_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_dsi_phy =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D MIPIDSI_PHY_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "dsi_phy", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_dsi_phy_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(dsi_phy, MIPIDSI_PHY_CLK_CTRL, 12, 0x7, c3_dsi_phy_pare= nts); +static C3_COMP_DIV(dsi_phy, MIPIDSI_PHY_CLK_CTRL, 0, 7); +static C3_COMP_GATE(dsi_phy, MIPIDSI_PHY_CLK_CTRL, 8); =20 static const struct clk_parent_data c3_vout_mclk_parents[] =3D { { .fw_name =3D "fdiv2p5" }, @@ -1112,52 +725,9 @@ static const struct clk_parent_data c3_vout_mclk_pare= nts[] =3D { { .fw_name =3D "fdiv7" } }; =20 -static struct clk_regmap c3_vout_mclk_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D VOUTENC_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vout_mclk_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_vout_mclk_parents, - .num_parents =3D ARRAY_SIZE(c3_vout_mclk_parents), - }, -}; - -static struct clk_regmap c3_vout_mclk_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D VOUTENC_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vout_mclk_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vout_mclk_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_vout_mclk =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D VOUTENC_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vout_mclk", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vout_mclk_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(vout_mclk, VOUTENC_CLK_CTRL, 9, 0x7, c3_vout_mclk_paren= ts); +static C3_COMP_DIV(vout_mclk, VOUTENC_CLK_CTRL, 0, 7); +static C3_COMP_GATE(vout_mclk, VOUTENC_CLK_CTRL, 8); =20 static const struct clk_parent_data c3_vout_enc_parents[] =3D { { .fw_name =3D "gp1" }, @@ -1170,52 +740,9 @@ static const struct clk_parent_data c3_vout_enc_paren= ts[] =3D { { .fw_name =3D "fdiv7" } }; =20 -static struct clk_regmap c3_vout_enc_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D VOUTENC_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vout_enc_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_vout_enc_parents, - .num_parents =3D ARRAY_SIZE(c3_vout_enc_parents), - }, -}; - -static struct clk_regmap c3_vout_enc_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D VOUTENC_CLK_CTRL, - .shift =3D 16, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vout_enc_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vout_enc_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_vout_enc =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D VOUTENC_CLK_CTRL, - .bit_idx =3D 24, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vout_enc", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vout_enc_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(vout_enc, VOUTENC_CLK_CTRL, 25, 0x7, c3_vout_enc_parent= s); +static C3_COMP_DIV(vout_enc, VOUTENC_CLK_CTRL, 16, 7); +static C3_COMP_GATE(vout_enc, VOUTENC_CLK_CTRL, 24); =20 static const struct clk_parent_data c3_hcodec_pre_parents[] =3D { { .fw_name =3D "fdiv2p5" }, @@ -1228,99 +755,13 @@ static const struct clk_parent_data c3_hcodec_pre_pa= rents[] =3D { { .fw_name =3D "oscin" } }; =20 -static struct clk_regmap c3_hcodec_0_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D VDEC_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "hcodec_0_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_hcodec_pre_parents, - .num_parents =3D ARRAY_SIZE(c3_hcodec_pre_parents), - }, -}; +static C3_COMP_SEL(hcodec_0, VDEC_CLK_CTRL, 9, 0x7, c3_hcodec_pre_parents= ); +static C3_COMP_DIV(hcodec_0, VDEC_CLK_CTRL, 0, 7); +static C3_COMP_GATE(hcodec_0, VDEC_CLK_CTRL, 8); =20 -static struct clk_regmap c3_hcodec_0_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D VDEC_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "hcodec_0_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_hcodec_0_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_hcodec_0 =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D VDEC_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "hcodec_0", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_hcodec_0_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_hcodec_1_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D VDEC3_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "hcodec_1_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_hcodec_pre_parents, - .num_parents =3D ARRAY_SIZE(c3_hcodec_pre_parents), - }, -}; - -static struct clk_regmap c3_hcodec_1_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D VDEC3_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "hcodec_1_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_hcodec_1_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_hcodec_1 =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D VDEC3_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "hcodec_1", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_hcodec_1_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(hcodec_1, VDEC3_CLK_CTRL, 9, 0x7, c3_hcodec_pre_parents= ); +static C3_COMP_DIV(hcodec_1, VDEC3_CLK_CTRL, 0, 7); +static C3_COMP_GATE(hcodec_1, VDEC3_CLK_CTRL, 8); =20 static const struct clk_parent_data c3_hcodec_parents[] =3D { { .hw =3D &c3_hcodec_0.hw }, @@ -1353,99 +794,13 @@ static const struct clk_parent_data c3_vc9000e_paren= ts[] =3D { { .fw_name =3D "gp0" } }; =20 -static struct clk_regmap c3_vc9000e_aclk_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D VC9000E_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vc9000e_aclk_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_vc9000e_parents, - .num_parents =3D ARRAY_SIZE(c3_vc9000e_parents), - }, -}; - -static struct clk_regmap c3_vc9000e_aclk_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D VC9000E_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vc9000e_aclk_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vc9000e_aclk_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_vc9000e_aclk =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D VC9000E_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vc9000e_aclk", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vc9000e_aclk_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_vc9000e_core_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D VC9000E_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vc9000e_core_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_vc9000e_parents, - .num_parents =3D ARRAY_SIZE(c3_vc9000e_parents), - }, -}; - -static struct clk_regmap c3_vc9000e_core_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D VC9000E_CLK_CTRL, - .shift =3D 16, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vc9000e_core_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vc9000e_core_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(vc9000e_aclk, VC9000E_CLK_CTRL, 9, 0x7, c3_vc9000e_pare= nts); +static C3_COMP_DIV(vc9000e_aclk, VC9000E_CLK_CTRL, 0, 7); +static C3_COMP_GATE(vc9000e_aclk, VC9000E_CLK_CTRL, 8); =20 -static struct clk_regmap c3_vc9000e_core =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D VC9000E_CLK_CTRL, - .bit_idx =3D 24, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vc9000e_core", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vc9000e_core_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(vc9000e_core, VC9000E_CLK_CTRL, 25, 0x7, c3_vc9000e_par= ents); +static C3_COMP_DIV(vc9000e_core, VC9000E_CLK_CTRL, 16, 7); +static C3_COMP_GATE(vc9000e_core, VC9000E_CLK_CTRL, 24); =20 static const struct clk_parent_data c3_csi_phy_parents[] =3D { { .fw_name =3D "fdiv2p5" }, @@ -1458,52 +813,9 @@ static const struct clk_parent_data c3_csi_phy_parent= s[] =3D { { .fw_name =3D "oscin" } }; =20 -static struct clk_regmap c3_csi_phy0_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D ISP0_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 25, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "csi_phy0_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_csi_phy_parents, - .num_parents =3D ARRAY_SIZE(c3_csi_phy_parents), - }, -}; - -static struct clk_regmap c3_csi_phy0_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D ISP0_CLK_CTRL, - .shift =3D 16, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "csi_phy0_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_csi_phy0_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_csi_phy0 =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D ISP0_CLK_CTRL, - .bit_idx =3D 24, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "csi_phy0", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_csi_phy0_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(csi_phy0, ISP0_CLK_CTRL, 25, 0x7, c3_csi_phy_parents); +static C3_COMP_DIV(csi_phy0, ISP0_CLK_CTRL, 16, 7); +static C3_COMP_GATE(csi_phy0, ISP0_CLK_CTRL, 24); =20 static const struct clk_parent_data c3_dewarpa_parents[] =3D { { .fw_name =3D "fdiv2p5" }, @@ -1516,52 +828,9 @@ static const struct clk_parent_data c3_dewarpa_parent= s[] =3D { { .fw_name =3D "fdiv7" } }; =20 -static struct clk_regmap c3_dewarpa_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D DEWARPA_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "dewarpa_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_dewarpa_parents, - .num_parents =3D ARRAY_SIZE(c3_dewarpa_parents), - }, -}; - -static struct clk_regmap c3_dewarpa_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D DEWARPA_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "dewarpa_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_dewarpa_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_dewarpa =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D DEWARPA_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "dewarpa", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_dewarpa_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(dewarpa, DEWARPA_CLK_CTRL, 9, 0x7, c3_dewarpa_parents); +static C3_COMP_DIV(dewarpa, DEWARPA_CLK_CTRL, 0, 7); +static C3_COMP_GATE(dewarpa, DEWARPA_CLK_CTRL, 8); =20 static const struct clk_parent_data c3_isp_parents[] =3D { { .fw_name =3D "fdiv2p5" }, @@ -1574,52 +843,9 @@ static const struct clk_parent_data c3_isp_parents[] = =3D { { .fw_name =3D "oscin" } }; =20 -static struct clk_regmap c3_isp0_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D ISP0_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "isp0_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_isp_parents, - .num_parents =3D ARRAY_SIZE(c3_isp_parents), - }, -}; - -static struct clk_regmap c3_isp0_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D ISP0_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "isp0_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_isp0_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_isp0 =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D ISP0_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "isp0", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_isp0_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(isp0, ISP0_CLK_CTRL, 9, 0x7, c3_isp_parents); +static C3_COMP_DIV(isp0, ISP0_CLK_CTRL, 0, 7); +static C3_COMP_GATE(isp0, ISP0_CLK_CTRL, 8); =20 static const struct clk_parent_data c3_nna_core_parents[] =3D { { .fw_name =3D "oscin" }, @@ -1632,52 +858,9 @@ static const struct clk_parent_data c3_nna_core_paren= ts[] =3D { { .fw_name =3D "hifi" } }; =20 -static struct clk_regmap c3_nna_core_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D NNA_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "nna_core_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_nna_core_parents, - .num_parents =3D ARRAY_SIZE(c3_nna_core_parents), - }, -}; - -static struct clk_regmap c3_nna_core_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D NNA_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "nna_core_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_nna_core_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_nna_core =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D NNA_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "nna_core", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_nna_core_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(nna_core, NNA_CLK_CTRL, 9, 0x7, c3_nna_core_parents); +static C3_COMP_DIV(nna_core, NNA_CLK_CTRL, 0, 7); +static C3_COMP_GATE(nna_core, NNA_CLK_CTRL, 8); =20 static const struct clk_parent_data c3_ge2d_parents[] =3D { { .fw_name =3D "oscin" }, @@ -1690,52 +873,9 @@ static const struct clk_parent_data c3_ge2d_parents[]= =3D { { .hw =3D &c3_rtc_clk.hw } }; =20 -static struct clk_regmap c3_ge2d_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D GE2D_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "ge2d_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_ge2d_parents, - .num_parents =3D ARRAY_SIZE(c3_ge2d_parents), - }, -}; - -static struct clk_regmap c3_ge2d_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D GE2D_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "ge2d_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_ge2d_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_ge2d =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D GE2D_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "ge2d", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_ge2d_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(ge2d, GE2D_CLK_CTRL, 9, 0x7, c3_ge2d_parents); +static C3_COMP_DIV(ge2d, GE2D_CLK_CTRL, 0, 7); +static C3_COMP_GATE(ge2d, GE2D_CLK_CTRL, 8); =20 static const struct clk_parent_data c3_vapb_parents[] =3D { { .fw_name =3D "fdiv2p5" }, @@ -1748,52 +888,9 @@ static const struct clk_parent_data c3_vapb_parents[]= =3D { { .fw_name =3D "oscin" }, }; =20 -static struct clk_regmap c3_vapb_sel =3D { - .data =3D &(struct clk_regmap_mux_data) { - .offset =3D VAPB_CLK_CTRL, - .mask =3D 0x7, - .shift =3D 9, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vapb_sel", - .ops =3D &clk_regmap_mux_ops, - .parent_data =3D c3_vapb_parents, - .num_parents =3D ARRAY_SIZE(c3_vapb_parents), - }, -}; - -static struct clk_regmap c3_vapb_div =3D { - .data =3D &(struct clk_regmap_div_data) { - .offset =3D VAPB_CLK_CTRL, - .shift =3D 0, - .width =3D 7, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vapb_div", - .ops =3D &clk_regmap_divider_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vapb_sel.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; - -static struct clk_regmap c3_vapb =3D { - .data =3D &(struct clk_regmap_gate_data) { - .offset =3D VAPB_CLK_CTRL, - .bit_idx =3D 8, - }, - .hw.init =3D &(struct clk_init_data) { - .name =3D "vapb", - .ops =3D &clk_regmap_gate_ops, - .parent_hws =3D (const struct clk_hw *[]) { - &c3_vapb_div.hw - }, - .num_parents =3D 1, - .flags =3D CLK_SET_RATE_PARENT, - }, -}; +static C3_COMP_SEL(vapb, VAPB_CLK_CTRL, 9, 0x7, c3_vapb_parents); +static C3_COMP_DIV(vapb, VAPB_CLK_CTRL, 0, 7); +static C3_COMP_GATE(vapb, VAPB_CLK_CTRL, 8); =20 static struct clk_hw *c3_peripherals_hw_clks[] =3D { [CLKID_RTC_XTAL_CLKIN] =3D &c3_rtc_xtal_clkin.hw, --=20 2.47.2