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Mon, 25 Aug 2025 07:00:44 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 57P70hT0016681 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Aug 2025 07:00:43 GMT Received: from hu-dikshita-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.24; Mon, 25 Aug 2025 00:00:39 -0700 From: Dikshita Agarwal Date: Mon, 25 Aug 2025 12:30:25 +0530 Subject: [PATCH v4 01/26] media: iris: Fix buffer count reporting in internal buffer check Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250825-iris-video-encoder-v4-1-84aa2bc0a46b@quicinc.com> References: <20250825-iris-video-encoder-v4-0-84aa2bc0a46b@quicinc.com> In-Reply-To: <20250825-iris-video-encoder-v4-0-84aa2bc0a46b@quicinc.com> To: Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Stefan Schmidt , Vedang Nagar , "Hans Verkuil" , Hans Verkuil CC: , , , Renjiang Han , Wangao Wang , Dikshita Agarwal , Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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This prevents stale values from previous iterations and ensures accurate error reporting for each buffer type. Without this initialization, the count could accumulate across types, leading to incorrect log messages. Fixes: d2abb1ff5a3c ("media: iris: Verify internal buffer release on close") Reviewed-by: Vikash Garodia Tested-by: Vikash Garodia # X1E80100 Reviewed-by: Bryan O'Donoghue Tested-by: Neil Armstrong # on SM8550-HDK Tested-by: Neil Armstrong # on SM8650-HDK Signed-off-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e80100-crd --- drivers/media/platform/qcom/iris/iris_vidc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/p= latform/qcom/iris/iris_vidc.c index 541ae86f7892ab7ca89e9d5856ef10d189b2fb32..cf150b32d6c2f9c7e1da7abfd52= 11fdfc469d96f 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -239,6 +239,7 @@ static void iris_check_num_queued_internal_buffers(stru= ct iris_inst *inst, u32 p =20 for (i =3D 0; i < internal_buffer_count; i++) { buffers =3D &inst->buffers[internal_buf_type[i]]; + count =3D 0; list_for_each_entry_safe(buf, next, &buffers->list, list) count++; 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This ensures all buffer types are checked and logged if not freed during session close, helping to detect memory leaks and improve driver robustness. No change to buffer lifecycle or allocation logic. Reviewed-by: Vikash Garodia Tested-by: Vikash Garodia # X1E80100 Tested-by: Neil Armstrong # on SM8550-HDK Tested-by: Neil Armstrong # on SM8650-HDK Signed-off-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e80100-crd --- drivers/media/platform/qcom/iris/iris_vidc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/p= latform/qcom/iris/iris_vidc.c index cf150b32d6c2f9c7e1da7abfd5211fdfc469d96f..5fe7699c611583463231a60058d= 6960b6749edf5 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -246,6 +246,14 @@ static void iris_check_num_queued_internal_buffers(str= uct iris_inst *inst, u32 p dev_err(inst->core->dev, "%d buffer of type %d not released", count, internal_buf_type[i]); } + + buffers =3D &inst->buffers[BUF_PERSIST]; + + count =3D 0; + list_for_each_entry_safe(buf, next, &buffers->list, list) + count++; + if (count) + dev_err(inst->core->dev, "%d buffer of type BUF_PERSIST not released", c= ount); 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Add the necessary logic to explicitly free the untracked internal buffer during session close to ensure all allocated memory is released properly. Fixes: 73702f45db81 ("media: iris: allocate, initialize and queue internal = buffers") Reviewed-by: Vikash Garodia Tested-by: Vikash Garodia # X1E80100 Tested-by: Neil Armstrong # on SM8550-HDK Tested-by: Neil Armstrong # on SM8650-HDK Signed-off-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e80100-crd --- drivers/media/platform/qcom/iris/iris_buffer.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media= /platform/qcom/iris/iris_buffer.c index 6425e4919e3b0b849ba801ca9e01921c114144cd..9f664c241149362d44d3a8fa65e= 2266f9c2e80e0 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -413,6 +413,16 @@ static int iris_destroy_internal_buffers(struct iris_i= nst *inst, u32 plane, bool } } =20 + if (force) { + buffers =3D &inst->buffers[BUF_PERSIST]; + + list_for_each_entry_safe(buf, next, &buffers->list, list) { + ret =3D iris_destroy_internal_buffer(inst, buf); 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While removing that check allows capture port to enter streaming independently, it also introduced firmware errors due to premature queuing of DPB buffers before the firmware session was fully started which happens only when streamon is called on output port. Fix this by deferring DPB buffer queuing to the firmware until both capture and output are streaming and state is 'STREAMING'. Fixes: 11712ce70f8e ("media: iris: implement vb2 streaming ops") Reviewed-by: Vikash Garodia Tested-by: Vikash Garodia # X1E80100 Reviewed-by: Bryan O'Donoghue Tested-by: Neil Armstrong # on SM8550-HDK Tested-by: Neil Armstrong # on SM8650-HDK Signed-off-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e80100-crd --- drivers/media/platform/qcom/iris/iris_buffer.c | 27 ++++++++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_buffer.h | 1 + drivers/media/platform/qcom/iris/iris_vb2.c | 8 ++++---- 3 files changed, 32 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media= /platform/qcom/iris/iris_buffer.c index 9f664c241149362d44d3a8fa65e2266f9c2e80e0..23cac5d1312913b8dac44347ae6= 6cb80a6a15deb 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -334,6 +334,29 @@ int iris_queue_buffer(struct iris_inst *inst, struct i= ris_buffer *buf) return 0; } =20 +int iris_queue_internal_deferred_buffers(struct iris_inst *inst, enum iris= _buffer_type buffer_type) +{ + struct iris_buffer *buffer, *next; + struct iris_buffers *buffers; + int ret =3D 0; + + buffers =3D &inst->buffers[buffer_type]; + list_for_each_entry_safe(buffer, next, &buffers->list, list) { + if (buffer->attr & BUF_ATTR_PENDING_RELEASE) + continue; + if (buffer->attr & BUF_ATTR_QUEUED) + continue; + + if (buffer->attr & BUF_ATTR_DEFERRED) { + ret =3D iris_queue_buffer(inst, buffer); + if (ret) + return ret; + } + } + + return ret; +} + int iris_queue_internal_buffers(struct iris_inst *inst, u32 plane) { const struct iris_platform_data *platform_data =3D inst->core->iris_platf= orm_data; @@ -358,6 +381,10 @@ int iris_queue_internal_buffers(struct iris_inst *inst= , u32 plane) continue; if (buffer->attr & BUF_ATTR_QUEUED) continue; + if (buffer->type =3D=3D BUF_DPB && inst->state !=3D IRIS_INST_STREAMING= ) { + buffer->attr |=3D BUF_ATTR_DEFERRED; + continue; + } ret =3D iris_queue_buffer(inst, buffer); if (ret) return ret; diff --git a/drivers/media/platform/qcom/iris/iris_buffer.h b/drivers/media= /platform/qcom/iris/iris_buffer.h index 00825ad2dc3a4bd1ace32d7e95d15b95276315b0..b9b011faa13ae72e08545c191cd= cc2f1bcaf9e0a 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.h +++ b/drivers/media/platform/qcom/iris/iris_buffer.h @@ -105,6 +105,7 @@ int iris_get_buffer_size(struct iris_inst *inst, enum i= ris_buffer_type buffer_ty void iris_get_internal_buffers(struct iris_inst *inst, u32 plane); int iris_create_internal_buffers(struct iris_inst *inst, u32 plane); int iris_queue_internal_buffers(struct iris_inst *inst, u32 plane); +int iris_queue_internal_deferred_buffers(struct iris_inst *inst, enum iris= _buffer_type buffer_type); int iris_destroy_internal_buffer(struct iris_inst *inst, struct iris_buffe= r *buffer); int iris_destroy_all_internal_buffers(struct iris_inst *inst, u32 plane); int iris_destroy_dequeued_internal_buffers(struct iris_inst *inst, u32 pla= ne); diff --git a/drivers/media/platform/qcom/iris/iris_vb2.c b/drivers/media/pl= atform/qcom/iris/iris_vb2.c index 8b17c7c3948798326ed4732ca50ebd98b833401f..e62ed7a57df2debf0a930ad8307= e6d945f589922 100644 --- a/drivers/media/platform/qcom/iris/iris_vb2.c +++ b/drivers/media/platform/qcom/iris/iris_vb2.c @@ -173,9 +173,6 @@ int iris_vb2_start_streaming(struct vb2_queue *q, unsig= ned int count) =20 inst =3D vb2_get_drv_priv(q); =20 - if (V4L2_TYPE_IS_CAPTURE(q->type) && inst->state =3D=3D IRIS_INST_INIT) - return 0; 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Mon, 25 Aug 2025 07:01:03 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 57P713a4008449 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Aug 2025 07:01:03 GMT Received: from hu-dikshita-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.24; Mon, 25 Aug 2025 00:00:58 -0700 From: Dikshita Agarwal Date: Mon, 25 Aug 2025 12:30:29 +0530 Subject: [PATCH v4 05/26] media: iris: Allow substate transition to load resources during output streaming Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250825-iris-video-encoder-v4-5-84aa2bc0a46b@quicinc.com> References: <20250825-iris-video-encoder-v4-0-84aa2bc0a46b@quicinc.com> In-Reply-To: <20250825-iris-video-encoder-v4-0-84aa2bc0a46b@quicinc.com> To: Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Stefan Schmidt , Vedang Nagar , "Hans Verkuil" , Hans Verkuil CC: , , , Renjiang Han , Wangao Wang , Dikshita Agarwal , Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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When streaming is subsequently started on the output port, the instance state advances to STREAMING, and the substate should transition to LOAD_RESOURCES. Previously, the code blocked the substate transition to LOAD_RESOURCES if the instance state was OUTPUT_STREAMING. This update modifies the logic to permit the substate transition to LOAD_RESOURCES when the instance state is OUTPUT_STREAMING, thereby supporting this client streaming sequence. Fixes: 547f7b8c5090 ("media: iris: add check to allow sub states transition= s") Reviewed-by: Vikash Garodia Tested-by: Vikash Garodia # X1E80100 Tested-by: Neil Armstrong # on SM8550-HDK Tested-by: Neil Armstrong # on SM8650-HDK Signed-off-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e80100-crd --- drivers/media/platform/qcom/iris/iris_state.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_state.c b/drivers/media/= platform/qcom/iris/iris_state.c index 104e1687ad39dab93ff66450ba3a97c309b1e1e1..a21238d2818f9606871953bd0be= e25382cca0474 100644 --- a/drivers/media/platform/qcom/iris/iris_state.c +++ b/drivers/media/platform/qcom/iris/iris_state.c @@ -122,7 +122,8 @@ static bool iris_inst_allow_sub_state(struct iris_inst = *inst, enum iris_inst_sub return false; case IRIS_INST_OUTPUT_STREAMING: if (sub_state & (IRIS_INST_SUB_DRC_LAST | - IRIS_INST_SUB_DRAIN_LAST | IRIS_INST_SUB_OUTPUT_PAUSE)) + IRIS_INST_SUB_DRAIN_LAST | IRIS_INST_SUB_OUTPUT_PAUSE | + IRIS_INST_SUB_LOAD_RESOURCES)) return true; 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Mon, 25 Aug 2025 07:01:08 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 57P717jV008623 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Aug 2025 07:01:07 GMT Received: from hu-dikshita-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.24; Mon, 25 Aug 2025 00:01:03 -0700 From: Dikshita Agarwal Date: Mon, 25 Aug 2025 12:30:30 +0530 Subject: [PATCH v4 06/26] media: iris: Always destroy internal buffers on firmware release response Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250825-iris-video-encoder-v4-6-84aa2bc0a46b@quicinc.com> References: <20250825-iris-video-encoder-v4-0-84aa2bc0a46b@quicinc.com> In-Reply-To: <20250825-iris-video-encoder-v4-0-84aa2bc0a46b@quicinc.com> To: Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Stefan Schmidt , Vedang Nagar , "Hans Verkuil" , Hans Verkuil CC: , , , Renjiang Han , Wangao Wang , Dikshita Agarwal , Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Internal buffers should always be destroyed when the firmware explicitly releases it, regardless of whether the 'PENDING_RELEASE' flag was set by the driver. This is specially important during force-stop scenarios, where the firmware may release buffers without driver marking them for release. Fix this by removing the incorrect check and ensuring all buffers are properly cleaned up. Fixes: 73702f45db81 ("media: iris: allocate, initialize and queue internal = buffers") Reviewed-by: Vikash Garodia Tested-by: Vikash Garodia # X1E80100 Reviewed-by: Bryan O'Donoghue Tested-by: Neil Armstrong # on SM8550-HDK Tested-by: Neil Armstrong # on SM8650-HDK Signed-off-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e80100-crd --- drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen2_response.c index a8c30fc5c0d0668cc9980f2fcfcf21072cf9ef0a..dda775d463e916f70da0b879702= d96df18ea8bf7 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c @@ -424,7 +424,6 @@ static int iris_hfi_gen2_handle_release_internal_buffer= (struct iris_inst *inst, struct iris_buffers *buffers =3D &inst->buffers[buf_type]; struct iris_buffer *buf, *iter; bool found =3D false; - int ret =3D 0; =20 list_for_each_entry(iter, &buffers->list, list) { if (iter->device_addr =3D=3D buffer->base_address) { @@ -437,10 +436,8 @@ static int iris_hfi_gen2_handle_release_internal_buffe= r(struct iris_inst *inst, return -EINVAL; =20 buf->attr &=3D ~BUF_ATTR_QUEUED; - if (buf->attr & BUF_ATTR_PENDING_RELEASE) - ret =3D iris_destroy_internal_buffer(inst, buf); =20 - return ret; + return iris_destroy_internal_buffer(inst, buf); } =20 static int iris_hfi_gen2_handle_session_stop(struct iris_inst *inst, --=20 2.34.1 From nobody Fri Oct 3 20:48:35 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B74928467B; Mon, 25 Aug 2025 07:01:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; 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Previously, the flag update was skippied in error scenario, which could result in incorrect state reporting for buffers. Fixes: 17f2a485ca67 ("media: iris: implement vb2 ops for buf_queue and firm= ware response") Reviewed-by: Vikash Garodia Tested-by: Vikash Garodia # X1E80100 Reviewed-by: Bryan O'Donoghue Tested-by: Neil Armstrong # on SM8550-HDK Tested-by: Neil Armstrong # on SM8650-HDK Signed-off-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e80100-crd --- drivers/media/platform/qcom/iris/iris_buffer.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media= /platform/qcom/iris/iris_buffer.c index 23cac5d1312913b8dac44347ae66cb80a6a15deb..38548ee4749ea7dd1addf2c9d06= 77cf5217e3546 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -651,6 +651,8 @@ int iris_vb2_buffer_done(struct iris_inst *inst, struct= iris_buffer *buf) =20 vb2 =3D &vbuf->vb2_buf; =20 + vbuf->flags |=3D buf->flags; + if (buf->flags & V4L2_BUF_FLAG_ERROR) { state =3D VB2_BUF_STATE_ERROR; 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These explicit checks are redundant, as vb2 already ensures that stop is only called on ports that have been started, maintaining correct buffer state management. Fixes: 11712ce70f8e ("media: iris: implement vb2 streaming ops") Reviewed-by: Vikash Garodia Tested-by: Vikash Garodia # X1E80100 Tested-by: Neil Armstrong # on SM8550-HDK Tested-by: Neil Armstrong # on SM8650-HDK Signed-off-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e80100-crd --- .../platform/qcom/iris/iris_hfi_gen1_command.c | 42 ++++++++++--------= ---- 1 file changed, 19 insertions(+), 23 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_command.c index 5fc30d54af4dc34616cfd08813940aa0b7044a20..3e41c8cb620ebe51636a4cc5202= 909bb043ed4ab 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -184,11 +184,25 @@ static int iris_hfi_gen1_session_stop(struct iris_ins= t *inst, u32 plane) u32 flush_type =3D 0; int ret =3D 0; =20 - if ((V4L2_TYPE_IS_OUTPUT(plane) && - inst->state =3D=3D IRIS_INST_INPUT_STREAMING) || - (V4L2_TYPE_IS_CAPTURE(plane) && - inst->state =3D=3D IRIS_INST_OUTPUT_STREAMING) || - inst->state =3D=3D IRIS_INST_ERROR) { + if (inst->state =3D=3D IRIS_INST_STREAMING) { + if (V4L2_TYPE_IS_OUTPUT(plane)) + flush_type =3D HFI_FLUSH_ALL; + else if (V4L2_TYPE_IS_CAPTURE(plane)) + flush_type =3D HFI_FLUSH_OUTPUT; + + reinit_completion(&inst->flush_completion); + + flush_pkt.shdr.hdr.size =3D sizeof(struct hfi_session_flush_pkt); + flush_pkt.shdr.hdr.pkt_type =3D HFI_CMD_SESSION_FLUSH; + flush_pkt.shdr.session_id =3D inst->session_id; + flush_pkt.flush_type =3D flush_type; + + ret =3D iris_hfi_queue_cmd_write(core, &flush_pkt, flush_pkt.shdr.hdr.si= ze); + if (!ret) { + inst->flush_responses_pending++; + ret =3D iris_wait_for_session_response(inst, true); + } + } else { reinit_completion(&inst->completion); iris_hfi_gen1_packet_session_cmd(inst, &pkt, HFI_CMD_SESSION_STOP); ret =3D iris_hfi_queue_cmd_write(core, &pkt, pkt.shdr.hdr.size); @@ -207,24 +221,6 @@ static int iris_hfi_gen1_session_stop(struct iris_inst= *inst, u32 plane) VB2_BUF_STATE_ERROR); iris_helper_buffers_done(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, VB2_BUF_STATE_ERROR); - } else if (inst->state =3D=3D IRIS_INST_STREAMING) { - if (V4L2_TYPE_IS_OUTPUT(plane)) - flush_type =3D HFI_FLUSH_ALL; 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Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250825-iris-video-encoder-v4-9-84aa2bc0a46b@quicinc.com> References: <20250825-iris-video-encoder-v4-0-84aa2bc0a46b@quicinc.com> In-Reply-To: <20250825-iris-video-encoder-v4-0-84aa2bc0a46b@quicinc.com> To: Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Stefan Schmidt , Vedang Nagar , "Hans Verkuil" , Hans Verkuil CC: , , , Renjiang Han , Wangao Wang , Dikshita Agarwal , Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756105234; l=1643; i=quic_dikshita@quicinc.com; s=20240917; h=from:subject:message-id; bh=hzF3OAntQFHfarfsOELgP2CZziChyfn8qdvNP/9xvr8=; b=i5ftHgiB5y6qkw4CiahU9VCIyDIev2zUqrbqRwz2Z2vvJlxvX/PMrqi9X8XYW79Zy2BvVsLEd NwUyz8zoJX1D/steUOiySEkxUo2Q1MiDl3iaUUa1ONu5U/pUuaxufYq X-Developer-Key: i=quic_dikshita@quicinc.com; a=ed25519; pk=EEvKY6Ar1OI5SWf44FJ1Ebo1KuQEVbbf5UNPO+UHVhM= X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODIzMDAzNCBTYWx0ZWRfX1q9bZQP7I9B9 Ke5q4U7ruRcS3Wkd4qtwFYVNwNDlaLR0PPRv+WSdIAAkQJGVWMl6VqsIn+W5j529G3ABlkuwH/z c18ccRyqIlNT5Voc4yJBDAh9eo6n89f6HFDzkQW8oSu/ZuVYt7RUSviAUp1B0rFFNNIbag5Vo5p FJoSAw17m80WS2Wx4Rq2laU8z3ScE910NwKLWJYkXS9KJP4E95tOx5zugoyfzdLomEltiO9nc+1 WuBOpi+2SKfRKNB8OTcTsduBITxYNNJIoFhCFDPzGth1ZzmuwMn+O28Xq34r73v1+zowsnup0Em d1CpsmYPN4Zz5OryUPgQz35WsRImF8p+gzujluLvIL327/tVC/ziU9te0vReV8sYfyPy+uJvrSY gV48L/FK X-Proofpoint-GUID: _UrEgBB1ZCjwvlBRmkhp7U29yAPYqCfC X-Authority-Analysis: v=2.4 cv=K+AiHzWI c=1 sm=1 tr=0 ts=68ac0a40 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=qy3FSly7IIgnPcZaVksA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: _UrEgBB1ZCjwvlBRmkhp7U29yAPYqCfC X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-25_03,2025-08-20_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 bulkscore=0 clxscore=1015 adultscore=0 impostorscore=0 priorityscore=1501 phishscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508230034 For HFI Gen1, the instances substate is changed to LOAD_RESOURCES only when a START command is issues to the firmware. If STOP is called without a prior START, the firmware may reject the command and throw some erros. Handle this by adding a substate check before issuing STOP command to the firmware. Fixes: 11712ce70f8e ("media: iris: implement vb2 streaming ops") Reviewed-by: Vikash Garodia Tested-by: Vikash Garodia # X1E80100 Tested-by: Neil Armstrong # on SM8550-HDK Tested-by: Neil Armstrong # on SM8650-HDK Signed-off-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e80100-crd --- drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_command.c index 3e41c8cb620ebe51636a4cc5202909bb043ed4ab..a3461ccf170ab1abb3a9ce70c4d= 93415773b2772 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -202,7 +202,7 @@ static int iris_hfi_gen1_session_stop(struct iris_inst = *inst, u32 plane) inst->flush_responses_pending++; ret =3D iris_wait_for_session_response(inst, true); } - } else { + } else if (inst->sub_state & IRIS_INST_SUB_LOAD_RESOURCES) { reinit_completion(&inst->completion); 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Mon, 25 Aug 2025 07:01:23 GMT Received: from hu-dikshita-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.24; Mon, 25 Aug 2025 00:01:19 -0700 From: Dikshita Agarwal Date: Mon, 25 Aug 2025 12:30:34 +0530 Subject: [PATCH v4 10/26] media: iris: Send dummy buffer address for all codecs during drain Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250825-iris-video-encoder-v4-10-84aa2bc0a46b@quicinc.com> References: <20250825-iris-video-encoder-v4-0-84aa2bc0a46b@quicinc.com> In-Reply-To: <20250825-iris-video-encoder-v4-0-84aa2bc0a46b@quicinc.com> To: Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Stefan Schmidt , Vedang Nagar , "Hans Verkuil" , Hans Verkuil CC: , , , Renjiang Han , Wangao Wang , Dikshita Agarwal , Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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To ensure consistent behavior across all codecs, update the drain command to always send a dummy buffer address. This makes the drain handling uniform and avoids any codec specific assumptions. Fixes: 478c4478610d ("media: iris: Add codec specific check for VP9 decoder= drain handling") Reviewed-by: Vikash Garodia Tested-by: Vikash Garodia # X1E80100 Reviewed-by: Bryan O'Donoghue Tested-by: Neil Armstrong # on SM8550-HDK Tested-by: Neil Armstrong # on SM8650-HDK Signed-off-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e80100-crd --- drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_command.c index a3461ccf170ab1abb3a9ce70c4d93415773b2772..3f4f93b779ced5d2c7f646006ba= d936658be1b24 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -397,8 +397,7 @@ static int iris_hfi_gen1_session_drain(struct iris_inst= *inst, u32 plane) ip_pkt.shdr.hdr.pkt_type =3D HFI_CMD_SESSION_EMPTY_BUFFER; ip_pkt.shdr.session_id =3D inst->session_id; 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Previously, the driver failed to attach the V4L2_BUF_FLAG_LAST flag when a drain response was received from the firmware, relying on userspace to mark the next queued buffer as LAST. This update fixes the issue by checking the pending drain status, attaching the LAST flag to the capture buffer received from the firmware (with EOS attached), and returning it to the V4L2 layer correctly. Fixes: d09100763bed ("media: iris: add support for drain sequence") Reviewed-by: Vikash Garodia Tested-by: Vikash Garodia # X1E80100 Reviewed-by: Bryan O'Donoghue Tested-by: Neil Armstrong # on SM8550-HDK Tested-by: Neil Armstrong # on SM8650-HDK Signed-off-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e80100-crd --- drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c | 4 +--- drivers/media/platform/qcom/iris/iris_state.c | 2 +- drivers/media/platform/qcom/iris/iris_state.h | 1 + 3 files changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen1_response.c index 8d1ce8a19a45ebb2b29457e0fef7d72c1c0d9785..2a96458833835422d30c9386d15= cc1e4fb226e3d 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c @@ -416,8 +416,6 @@ static void iris_hfi_gen1_session_ftb_done(struct iris_= inst *inst, void *packet) inst->flush_responses_pending++; =20 iris_inst_sub_state_change_drain_last(inst); - - return; } =20 if (iris_split_mode_enabled(inst) && pkt->stream_id =3D=3D 0) { @@ -462,7 +460,7 @@ static void iris_hfi_gen1_session_ftb_done(struct iris_= inst *inst, void *packet) timestamp_us =3D (timestamp_us << 32) | timestamp_lo; } else { if (pkt->stream_id =3D=3D 1 && !inst->last_buffer_dequeued) { - if (iris_drc_pending(inst)) { + if (iris_drc_pending(inst) || iris_drain_pending(inst)) { flags |=3D V4L2_BUF_FLAG_LAST; inst->last_buffer_dequeued =3D true; } diff --git a/drivers/media/platform/qcom/iris/iris_state.c b/drivers/media/= platform/qcom/iris/iris_state.c index a21238d2818f9606871953bd0bee25382cca0474..d1dc1a863da0b0b1af60974e9ed= 2ef68ea225cdd 100644 --- a/drivers/media/platform/qcom/iris/iris_state.c +++ b/drivers/media/platform/qcom/iris/iris_state.c @@ -252,7 +252,7 @@ bool iris_drc_pending(struct iris_inst *inst) inst->sub_state & IRIS_INST_SUB_DRC_LAST; } =20 -static inline bool iris_drain_pending(struct iris_inst *inst) +bool iris_drain_pending(struct iris_inst *inst) { return inst->sub_state & IRIS_INST_SUB_DRAIN && inst->sub_state & IRIS_INST_SUB_DRAIN_LAST; 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This caused failures when validating formats for the CAPTURE plane. Update the check to validate against the only supported format on the CAPTURE plane, which is NV12. Fixes: fde6161d91bb ("media: iris: Add HEVC and VP9 formats for decoder") Reviewed-by: Vikash Garodia Tested-by: Vikash Garodia # X1E80100 Tested-by: Neil Armstrong # on SM8550-HDK Tested-by: Neil Armstrong # on SM8650-HDK Signed-off-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e80100-crd --- drivers/media/platform/qcom/iris/iris_vdec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/p= latform/qcom/iris/iris_vdec.c index d670b51c5839d1fad54d34f373cf71d5f3973a96..0f5adaac829f2263fae9ff0fa49= bb17bad2edecb 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.c +++ b/drivers/media/platform/qcom/iris/iris_vdec.c @@ -158,7 +158,7 @@ int iris_vdec_try_fmt(struct iris_inst *inst, struct v4= l2_format *f) } break; case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: - if (!fmt) { + if (f->fmt.pix_mp.pixelformat !=3D V4L2_PIX_FMT_NV12) { f_inst =3D inst->fmt_dst; f->fmt.pix_mp.pixelformat =3D f_inst->fmt.pix_mp.pixelformat; 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The encoder device is registered with the name "qcom-iris-encoder". Tested-by: Vikash Garodia # X1E80100 Reviewed-by: Bryan O'Donoghue Reviewed-by: Vikash Garodia Tested-by: Neil Armstrong # on SM8550-HDK Tested-by: Neil Armstrong # on SM8650-HDK Signed-off-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e80100-crd --- drivers/media/platform/qcom/iris/iris_core.h | 7 +++++++ drivers/media/platform/qcom/iris/iris_probe.c | 30 ++++++++++++++++++++---= ---- 2 files changed, 30 insertions(+), 7 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/p= latform/qcom/iris/iris_core.h index aeeac32a1f6d9a9fa7027e8e3db4d95f021c552e..09e83be4e00efb456b7098a499b= 6cce850134a06 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -25,6 +25,11 @@ struct icc_info { #define IRIS_FW_VERSION_LENGTH 128 #define IFACEQ_CORE_PKT_SIZE (1024 * 4) =20 +enum domain_type { + ENCODER =3D BIT(0), + DECODER =3D BIT(1), +}; + /** * struct iris_core - holds core parameters valid for all instances * @@ -33,6 +38,7 @@ struct icc_info { * @irq: iris irq * @v4l2_dev: a holder for v4l2 device structure * @vdev_dec: iris video device structure for decoder + * @vdev_enc: iris video device structure for encoder * @iris_v4l2_file_ops: iris v4l2 file ops * @iris_v4l2_ioctl_ops: iris v4l2 ioctl ops * @iris_vb2_ops: iris vb2 ops @@ -73,6 +79,7 @@ struct iris_core { int irq; struct v4l2_device v4l2_dev; struct video_device *vdev_dec; + struct video_device *vdev_enc; const struct v4l2_file_operations *iris_v4l2_file_ops; const struct v4l2_ioctl_ops *iris_v4l2_ioctl_ops; const struct vb2_ops *iris_vb2_ops; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index 4e6e92357968d7419f114cc0ffa9b571bad19e46..324ffc5035bc0ecfd9d7491ee07= fd9333917455b 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -146,7 +146,7 @@ static int iris_init_resources(struct iris_core *core) return iris_init_resets(core); } =20 -static int iris_register_video_device(struct iris_core *core) +static int iris_register_video_device(struct iris_core *core, enum domain_= type type) { struct video_device *vdev; int ret; @@ -155,7 +155,6 @@ static int iris_register_video_device(struct iris_core = *core) if (!vdev) return -ENOMEM; =20 - strscpy(vdev->name, "qcom-iris-decoder", sizeof(vdev->name)); vdev->release =3D video_device_release; vdev->fops =3D core->iris_v4l2_file_ops; vdev->ioctl_ops =3D core->iris_v4l2_ioctl_ops; @@ -163,11 +162,21 @@ static int iris_register_video_device(struct iris_cor= e *core) vdev->v4l2_dev =3D &core->v4l2_dev; vdev->device_caps =3D V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING; =20 + if (type =3D=3D DECODER) { + strscpy(vdev->name, "qcom-iris-decoder", sizeof(vdev->name)); + core->vdev_dec =3D vdev; + } else if (type =3D=3D ENCODER) { + strscpy(vdev->name, "qcom-iris-encoder", sizeof(vdev->name)); + core->vdev_enc =3D vdev; + } else { + ret =3D -EINVAL; + goto err_vdev_release; + } + ret =3D video_register_device(vdev, VFL_TYPE_VIDEO, -1); if (ret) goto err_vdev_release; =20 - core->vdev_dec =3D vdev; video_set_drvdata(vdev, core); =20 return 0; @@ -189,6 +198,7 @@ static void iris_remove(struct platform_device *pdev) iris_core_deinit(core); =20 video_unregister_device(core->vdev_dec); + video_unregister_device(core->vdev_enc); =20 v4l2_device_unregister(&core->v4l2_dev); =20 @@ -258,17 +268,21 @@ static int iris_probe(struct platform_device *pdev) if (ret) return ret; =20 - ret =3D iris_register_video_device(core); + ret =3D iris_register_video_device(core, DECODER); if (ret) goto err_v4l2_unreg; =20 + ret =3D iris_register_video_device(core, ENCODER); + if (ret) + goto err_vdev_unreg_dec; + platform_set_drvdata(pdev, core); =20 dma_mask =3D core->iris_platform_data->dma_mask; =20 ret =3D dma_set_mask_and_coherent(dev, dma_mask); if (ret) - goto err_vdev_unreg; + goto err_vdev_unreg_enc; =20 dma_set_max_seg_size(&pdev->dev, DMA_BIT_MASK(32)); dma_set_seg_boundary(&pdev->dev, DMA_BIT_MASK(32)); @@ -277,11 +291,13 @@ static int iris_probe(struct platform_device *pdev) pm_runtime_use_autosuspend(core->dev); ret =3D devm_pm_runtime_enable(core->dev); if (ret) - goto err_vdev_unreg; + goto err_vdev_unreg_enc; =20 return 0; =20 -err_vdev_unreg: +err_vdev_unreg_enc: + video_unregister_device(core->vdev_enc); +err_vdev_unreg_dec: video_unregister_device(core->vdev_dec); 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Tested-by: Vikash Garodia # X1E80100 Reviewed-by: Vikash Garodia Reviewed-by: Bryan O'Donoghue Tested-by: Neil Armstrong # on SM8550-HDK Tested-by: Neil Armstrong # on SM8650-HDK Signed-off-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e80100-crd --- drivers/media/platform/qcom/iris/Makefile | 1 + drivers/media/platform/qcom/iris/iris_buffer.c | 59 ++++++++++++++++--= -- .../platform/qcom/iris/iris_hfi_gen1_command.c | 7 ++- .../platform/qcom/iris/iris_hfi_gen1_defines.h | 1 + drivers/media/platform/qcom/iris/iris_instance.h | 7 +++ drivers/media/platform/qcom/iris/iris_vdec.c | 2 - drivers/media/platform/qcom/iris/iris_venc.c | 65 ++++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_venc.h | 14 +++++ drivers/media/platform/qcom/iris/iris_vidc.c | 27 ++++++++- drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 5 +- 10 files changed, 170 insertions(+), 18 deletions(-) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/plat= form/qcom/iris/Makefile index e86d00ee6f15dda8bae2f25f726feb0d427b7684..ec32145e081b1fc3538dfa7d511= 3162a76a6068c 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -19,6 +19,7 @@ qcom-iris-objs +=3D \ iris_vidc.o \ iris_vb2.o \ iris_vdec.o \ + iris_venc.o \ iris_vpu2.o \ iris_vpu3x.o \ iris_vpu_buffer.o \ diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media= /platform/qcom/iris/iris_buffer.c index 38548ee4749ea7dd1addf2c9d0677cf5217e3546..6bf9b0b35d206d51b927c824d5a= 5b327596251c6 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -63,7 +63,12 @@ static u32 iris_yuv_buffer_size_nv12(struct iris_inst *inst) { u32 y_plane, uv_plane, y_stride, uv_stride, y_scanlines, uv_scanlines; - struct v4l2_format *f =3D inst->fmt_dst; + struct v4l2_format *f; + + if (inst->domain =3D=3D DECODER) + f =3D inst->fmt_dst; + else + f =3D inst->fmt_src; =20 y_stride =3D ALIGN(f->fmt.pix_mp.width, Y_STRIDE_ALIGN); uv_stride =3D ALIGN(f->fmt.pix_mp.width, UV_STRIDE_ALIGN); @@ -194,7 +199,7 @@ static u32 iris_yuv_buffer_size_qc08c(struct iris_inst = *inst) return ALIGN(y_meta_plane + y_plane + uv_meta_plane + uv_plane, PIXELS_4K= ); } =20 -static u32 iris_bitstream_buffer_size(struct iris_inst *inst) +static u32 iris_dec_bitstream_buffer_size(struct iris_inst *inst) { struct platform_inst_caps *caps =3D inst->core->iris_platform_data->inst_= caps; u32 base_res_mbs =3D NUM_MBS_4K; @@ -219,18 +224,50 @@ static u32 iris_bitstream_buffer_size(struct iris_ins= t *inst) return ALIGN(frame_size, PIXELS_4K); } =20 +static u32 iris_enc_bitstream_buffer_size(struct iris_inst *inst) +{ + u32 aligned_width, aligned_height, bitstream_size, yuv_size; + struct v4l2_format *f; + + f =3D inst->fmt_dst; + + aligned_width =3D ALIGN(f->fmt.pix_mp.width, 32); + aligned_height =3D ALIGN(f->fmt.pix_mp.height, 32); + bitstream_size =3D aligned_width * aligned_height * 3; + yuv_size =3D (aligned_width * aligned_height * 3) >> 1; + if (aligned_width * aligned_height > (4096 * 2176)) + /* bitstream_size =3D 0.25 * yuv_size; */ + bitstream_size =3D (bitstream_size >> 3); + else if (aligned_width * aligned_height > (1280 * 720)) + /* bitstream_size =3D 0.5 * yuv_size; */ + bitstream_size =3D (bitstream_size >> 2); + + return ALIGN(bitstream_size, 4096); +} + int iris_get_buffer_size(struct iris_inst *inst, enum iris_buffer_type buffer_type) { - switch (buffer_type) { - case BUF_INPUT: - return iris_bitstream_buffer_size(inst); - case BUF_OUTPUT: - return iris_yuv_buffer_size_nv12(inst); - case BUF_DPB: - return iris_yuv_buffer_size_qc08c(inst); - default: - return 0; + if (inst->domain =3D=3D DECODER) { + switch (buffer_type) { + case BUF_INPUT: + return iris_dec_bitstream_buffer_size(inst); + case BUF_OUTPUT: + return iris_yuv_buffer_size_nv12(inst); + case BUF_DPB: + return iris_yuv_buffer_size_qc08c(inst); + default: + return 0; + } + } else { + switch (buffer_type) { + case BUF_INPUT: + return iris_yuv_buffer_size_nv12(inst); + case BUF_OUTPUT: + return iris_enc_bitstream_buffer_size(inst); + default: + return 0; + } } } =20 diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_command.c index 3f4f93b779ced5d2c7f646006bad936658be1b24..86ed414861e58c7c8567e725992= 4b2efe6f76e07 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -109,7 +109,12 @@ static int iris_hfi_gen1_session_open(struct iris_inst= *inst) packet.shdr.hdr.size =3D sizeof(struct hfi_session_open_pkt); packet.shdr.hdr.pkt_type =3D HFI_CMD_SYS_SESSION_INIT; packet.shdr.session_id =3D inst->session_id; - packet.session_domain =3D HFI_SESSION_TYPE_DEC; + + if (inst->domain =3D=3D DECODER) + packet.session_domain =3D HFI_SESSION_TYPE_DEC; + else + packet.session_domain =3D HFI_SESSION_TYPE_ENC; + packet.session_codec =3D codec; =20 reinit_completion(&inst->completion); diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_defines.h index d4d119ca98b0cb313db351f3794bf278216bd539..5b7c641b727a16c3aa7196a6d49= 786133653279f 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h @@ -10,6 +10,7 @@ =20 #define HFI_VIDEO_ARCH_OX 0x1 =20 +#define HFI_SESSION_TYPE_ENC 1 #define HFI_SESSION_TYPE_DEC 2 =20 #define HFI_VIDEO_CODEC_H264 0x00000002 diff --git a/drivers/media/platform/qcom/iris/iris_instance.h b/drivers/med= ia/platform/qcom/iris/iris_instance.h index 0e1f5799b72d993b25820608969e0011eabdb6bc..ff90f010f1d36690cbadeff0787= b1fb7458d7f75 100644 --- a/drivers/media/platform/qcom/iris/iris_instance.h +++ b/drivers/media/platform/qcom/iris/iris_instance.h @@ -12,6 +12,9 @@ #include "iris_core.h" #include "iris_utils.h" =20 +#define DEFAULT_WIDTH 320 +#define DEFAULT_HEIGHT 240 + /** * struct iris_inst - holds per video instance parameters * @@ -24,7 +27,9 @@ * @fmt_src: structure of v4l2_format for source * @fmt_dst: structure of v4l2_format for destination * @ctrl_handler: reference of v4l2 ctrl handler + * @domain: domain type: encoder or decoder * @crop: structure of crop info + * @compose: structure of compose info * @completion: structure of signal completions * @flush_completion: structure of signal completions for flush cmd * @flush_responses_pending: counter to track number of pending flush resp= onses @@ -57,7 +62,9 @@ struct iris_inst { struct v4l2_format *fmt_src; struct v4l2_format *fmt_dst; struct v4l2_ctrl_handler ctrl_handler; + enum domain_type domain; struct iris_hfi_rect_desc crop; + struct iris_hfi_rect_desc compose; struct completion completion; struct completion flush_completion; u32 flush_responses_pending; diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/p= latform/qcom/iris/iris_vdec.c index 0f5adaac829f2263fae9ff0fa49bb17bad2edecb..b4ad5df62bcd1ee390ce4f7c1c5= 8c8693d0ab0ca 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.c +++ b/drivers/media/platform/qcom/iris/iris_vdec.c @@ -13,8 +13,6 @@ #include "iris_vdec.h" #include "iris_vpu_buffer.h" =20 -#define DEFAULT_WIDTH 320 -#define DEFAULT_HEIGHT 240 #define DEFAULT_CODEC_ALIGNMENT 16 =20 int iris_vdec_inst_init(struct iris_inst *inst) diff --git a/drivers/media/platform/qcom/iris/iris_venc.c b/drivers/media/p= latform/qcom/iris/iris_venc.c new file mode 100644 index 0000000000000000000000000000000000000000..e418d347ac111c1bc48304adafa= 259d697e49fed --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_venc.c @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights res= erved. + */ + +#include "iris_buffer.h" +#include "iris_instance.h" +#include "iris_venc.h" +#include "iris_vpu_buffer.h" + +int iris_venc_inst_init(struct iris_inst *inst) +{ + struct v4l2_format *f; + + inst->fmt_src =3D kzalloc(sizeof(*inst->fmt_src), GFP_KERNEL); + inst->fmt_dst =3D kzalloc(sizeof(*inst->fmt_dst), GFP_KERNEL); + if (!inst->fmt_src || !inst->fmt_dst) + return -ENOMEM; + + f =3D inst->fmt_dst; + f->type =3D V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; + f->fmt.pix_mp.width =3D DEFAULT_WIDTH; + f->fmt.pix_mp.height =3D DEFAULT_HEIGHT; + f->fmt.pix_mp.pixelformat =3D V4L2_PIX_FMT_H264; + inst->codec =3D f->fmt.pix_mp.pixelformat; + f->fmt.pix_mp.num_planes =3D 1; + f->fmt.pix_mp.plane_fmt[0].bytesperline =3D 0; + f->fmt.pix_mp.plane_fmt[0].sizeimage =3D iris_get_buffer_size(inst, BUF_O= UTPUT); + f->fmt.pix_mp.field =3D V4L2_FIELD_NONE; + f->fmt.pix_mp.colorspace =3D V4L2_COLORSPACE_DEFAULT; + f->fmt.pix_mp.xfer_func =3D V4L2_XFER_FUNC_DEFAULT; + f->fmt.pix_mp.ycbcr_enc =3D V4L2_YCBCR_ENC_DEFAULT; + f->fmt.pix_mp.quantization =3D V4L2_QUANTIZATION_DEFAULT; + inst->buffers[BUF_OUTPUT].min_count =3D iris_vpu_buf_count(inst, BUF_OUTP= UT); + inst->buffers[BUF_OUTPUT].size =3D f->fmt.pix_mp.plane_fmt[0].sizeimage; + + f =3D inst->fmt_src; + f->type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; + f->fmt.pix_mp.pixelformat =3D V4L2_PIX_FMT_NV12; + f->fmt.pix_mp.width =3D ALIGN(DEFAULT_WIDTH, 128); + f->fmt.pix_mp.height =3D ALIGN(DEFAULT_HEIGHT, 32); + f->fmt.pix_mp.num_planes =3D 1; + f->fmt.pix_mp.plane_fmt[0].bytesperline =3D ALIGN(DEFAULT_WIDTH, 128); + f->fmt.pix_mp.plane_fmt[0].sizeimage =3D iris_get_buffer_size(inst, BUF_I= NPUT); + f->fmt.pix_mp.field =3D V4L2_FIELD_NONE; + f->fmt.pix_mp.colorspace =3D V4L2_COLORSPACE_DEFAULT; + f->fmt.pix_mp.xfer_func =3D V4L2_XFER_FUNC_DEFAULT; + f->fmt.pix_mp.ycbcr_enc =3D V4L2_YCBCR_ENC_DEFAULT; + f->fmt.pix_mp.quantization =3D V4L2_QUANTIZATION_DEFAULT; + inst->buffers[BUF_INPUT].min_count =3D iris_vpu_buf_count(inst, BUF_INPUT= ); + inst->buffers[BUF_INPUT].size =3D f->fmt.pix_mp.plane_fmt[0].sizeimage; + + inst->crop.left =3D 0; + inst->crop.top =3D 0; + inst->crop.width =3D f->fmt.pix_mp.width; + inst->crop.height =3D f->fmt.pix_mp.height; + + return 0; +} + +void iris_venc_inst_deinit(struct iris_inst *inst) +{ + kfree(inst->fmt_dst); + kfree(inst->fmt_src); +} diff --git a/drivers/media/platform/qcom/iris/iris_venc.h b/drivers/media/p= latform/qcom/iris/iris_venc.h new file mode 100644 index 0000000000000000000000000000000000000000..8a4cbddd0114b6d0e4ea895362b= 01c302250c78b --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_venc.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights res= erved. + */ + +#ifndef _IRIS_VENC_H_ +#define _IRIS_VENC_H_ + +struct iris_inst; + +int iris_venc_inst_init(struct iris_inst *inst); +void iris_venc_inst_deinit(struct iris_inst *inst); + +#endif diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/p= latform/qcom/iris/iris_vidc.c index 5fe7699c611583463231a60058d6960b6749edf5..cecc41a137271762d7622ab2637= c4cce2c74a506 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -12,6 +12,7 @@ #include "iris_vidc.h" #include "iris_instance.h" #include "iris_vdec.h" +#include "iris_venc.h" #include "iris_vb2.h" #include "iris_vpu_buffer.h" #include "iris_platform_common.h" @@ -23,7 +24,10 @@ =20 static void iris_v4l2_fh_init(struct iris_inst *inst, struct file *filp) { - v4l2_fh_init(&inst->fh, inst->core->vdev_dec); + if (inst->domain =3D=3D ENCODER) + v4l2_fh_init(&inst->fh, inst->core->vdev_enc); + else if (inst->domain =3D=3D DECODER) + v4l2_fh_init(&inst->fh, inst->core->vdev_dec); inst->fh.ctrl_handler =3D &inst->ctrl_handler; v4l2_fh_add(&inst->fh, filp); } @@ -126,9 +130,19 @@ iris_m2m_queue_init(void *priv, struct vb2_queue *src_= vq, struct vb2_queue *dst_ int iris_open(struct file *filp) { struct iris_core *core =3D video_drvdata(filp); + struct video_device *vdev; struct iris_inst *inst; + u32 session_type; int ret; =20 + vdev =3D video_devdata(filp); + if (strcmp(vdev->name, "qcom-iris-decoder") =3D=3D 0) + session_type =3D DECODER; + else if (strcmp(vdev->name, "qcom-iris-encoder") =3D=3D 0) + session_type =3D ENCODER; + else + return -EINVAL; + ret =3D pm_runtime_resume_and_get(core->dev); if (ret < 0) return ret; @@ -147,6 +161,7 @@ int iris_open(struct file *filp) return -ENOMEM; =20 inst->core =3D core; + inst->domain =3D session_type; inst->session_id =3D hash32_ptr(inst); inst->state =3D IRIS_INST_DEINIT; =20 @@ -178,7 +193,10 @@ int iris_open(struct file *filp) goto fail_m2m_release; } =20 - ret =3D iris_vdec_inst_init(inst); + if (inst->domain =3D=3D DECODER) + ret =3D iris_vdec_inst_init(inst); + else if (inst->domain =3D=3D ENCODER) + ret =3D iris_venc_inst_init(inst); if (ret) goto fail_m2m_ctx_release; =20 @@ -264,7 +282,10 @@ int iris_close(struct file *filp) v4l2_m2m_ctx_release(inst->m2m_ctx); v4l2_m2m_release(inst->m2m_dev); mutex_lock(&inst->lock); - iris_vdec_inst_deinit(inst); + if (inst->domain =3D=3D DECODER) + iris_vdec_inst_deinit(inst); + else if (inst->domain =3D=3D ENCODER) + iris_venc_inst_deinit(inst); iris_session_close(inst); iris_inst_change_state(inst, IRIS_INST_DEINIT); iris_v4l2_fh_deinit(inst, filp); diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_buffer.c index f92fd39fe310b9661f892dcf1ff036ebbc102270..06d5afc3c641f0dfca3967e5527= 3c4fa2614fdff 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c @@ -628,7 +628,10 @@ int iris_vpu_buf_count(struct iris_inst *inst, enum ir= is_buffer_type buffer_type case BUF_INPUT: return MIN_BUFFERS; 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Mon, 25 Aug 2025 07:01:45 GMT Received: from hu-dikshita-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.24; Mon, 25 Aug 2025 00:01:40 -0700 From: Dikshita Agarwal Date: Mon, 25 Aug 2025 12:30:39 +0530 Subject: [PATCH v4 15/26] media: iris: Add support for ENUM_FMT, S/G/TRY_FMT encoder Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250825-iris-video-encoder-v4-15-84aa2bc0a46b@quicinc.com> References: <20250825-iris-video-encoder-v4-0-84aa2bc0a46b@quicinc.com> In-Reply-To: <20250825-iris-video-encoder-v4-0-84aa2bc0a46b@quicinc.com> To: Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Stefan Schmidt , Vedang Nagar , "Hans Verkuil" , Hans Verkuil CC: , , , Renjiang Han , Wangao Wang , Dikshita Agarwal , Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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This ensures that the encoder supports format negotiation consistent with V4L2 expectation, enabling userspace applications to configure resolution, pixel format and buffer layout properly. Tested-by: Vikash Garodia # X1E80100 Reviewed-by: Vikash Garodia Tested-by: Neil Armstrong # on SM8550-HDK Tested-by: Neil Armstrong # on SM8650-HDK Signed-off-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e80100-crd --- drivers/media/platform/qcom/iris/iris_core.h | 6 +- drivers/media/platform/qcom/iris/iris_instance.h | 11 ++ drivers/media/platform/qcom/iris/iris_probe.c | 3 +- drivers/media/platform/qcom/iris/iris_vdec.h | 11 -- drivers/media/platform/qcom/iris/iris_venc.c | 212 +++++++++++++++++++= +++- drivers/media/platform/qcom/iris/iris_venc.h | 3 + drivers/media/platform/qcom/iris/iris_vidc.c | 41 ++++- 7 files changed, 265 insertions(+), 22 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/p= latform/qcom/iris/iris_core.h index 09e83be4e00efb456b7098a499b6cce850134a06..827aee8dcec3ee17af5a90f5594= b9315f663c0b3 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -40,7 +40,8 @@ enum domain_type { * @vdev_dec: iris video device structure for decoder * @vdev_enc: iris video device structure for encoder * @iris_v4l2_file_ops: iris v4l2 file ops - * @iris_v4l2_ioctl_ops: iris v4l2 ioctl ops + * @iris_v4l2_ioctl_ops_dec: iris v4l2 ioctl ops for decoder + * @iris_v4l2_ioctl_ops_enc: iris v4l2 ioctl ops for encoder * @iris_vb2_ops: iris vb2 ops * @icc_tbl: table of iris interconnects * @icc_count: count of iris interconnects @@ -81,7 +82,8 @@ struct iris_core { struct video_device *vdev_dec; struct video_device *vdev_enc; const struct v4l2_file_operations *iris_v4l2_file_ops; - const struct v4l2_ioctl_ops *iris_v4l2_ioctl_ops; + const struct v4l2_ioctl_ops *iris_v4l2_ioctl_ops_dec; + const struct v4l2_ioctl_ops *iris_v4l2_ioctl_ops_enc; const struct vb2_ops *iris_vb2_ops; struct icc_bulk_data *icc_tbl; u32 icc_count; diff --git a/drivers/media/platform/qcom/iris/iris_instance.h b/drivers/med= ia/platform/qcom/iris/iris_instance.h index ff90f010f1d36690cbadeff0787b1fb7458d7f75..55cf9702111829ef24189986ba5= 245c7684bfe11 100644 --- a/drivers/media/platform/qcom/iris/iris_instance.h +++ b/drivers/media/platform/qcom/iris/iris_instance.h @@ -15,6 +15,17 @@ #define DEFAULT_WIDTH 320 #define DEFAULT_HEIGHT 240 =20 +enum iris_fmt_type { + IRIS_FMT_H264, + IRIS_FMT_HEVC, + IRIS_FMT_VP9, +}; + +struct iris_fmt { + u32 pixfmt; + u32 type; +}; + /** * struct iris_inst - holds per video instance parameters * diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index 324ffc5035bc0ecfd9d7491ee07fd9333917455b..85b34a649c70597bcbc4747de55= 3ccd09c09923a 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -157,16 +157,17 @@ static int iris_register_video_device(struct iris_cor= e *core, enum domain_type t =20 vdev->release =3D video_device_release; vdev->fops =3D core->iris_v4l2_file_ops; - vdev->ioctl_ops =3D core->iris_v4l2_ioctl_ops; vdev->vfl_dir =3D VFL_DIR_M2M; vdev->v4l2_dev =3D &core->v4l2_dev; vdev->device_caps =3D V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING; =20 if (type =3D=3D DECODER) { strscpy(vdev->name, "qcom-iris-decoder", sizeof(vdev->name)); + vdev->ioctl_ops =3D core->iris_v4l2_ioctl_ops_dec; core->vdev_dec =3D vdev; } else if (type =3D=3D ENCODER) { strscpy(vdev->name, "qcom-iris-encoder", sizeof(vdev->name)); + vdev->ioctl_ops =3D core->iris_v4l2_ioctl_ops_enc; core->vdev_enc =3D vdev; } else { ret =3D -EINVAL; diff --git a/drivers/media/platform/qcom/iris/iris_vdec.h b/drivers/media/p= latform/qcom/iris/iris_vdec.h index cd7aab66dc7c82dc50acef9e654a3d6c1ddb088f..b24932dc511a65017b1cadbcb98= 4544475bd0723 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.h +++ b/drivers/media/platform/qcom/iris/iris_vdec.h @@ -8,17 +8,6 @@ =20 struct iris_inst; =20 -enum iris_fmt_type { - IRIS_FMT_H264, - IRIS_FMT_HEVC, - IRIS_FMT_VP9, -}; - -struct iris_fmt { - u32 pixfmt; - u32 type; -}; - int iris_vdec_inst_init(struct iris_inst *inst); void iris_vdec_inst_deinit(struct iris_inst *inst); int iris_vdec_enum_fmt(struct iris_inst *inst, struct v4l2_fmtdesc *f); diff --git a/drivers/media/platform/qcom/iris/iris_venc.c b/drivers/media/p= latform/qcom/iris/iris_venc.c index e418d347ac111c1bc48304adafa259d697e49fed..40f7990cd162ad400711d729917= b7e2577d562b2 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.c +++ b/drivers/media/platform/qcom/iris/iris_venc.c @@ -3,6 +3,8 @@ * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights res= erved. */ =20 +#include + #include "iris_buffer.h" #include "iris_instance.h" #include "iris_venc.h" @@ -14,8 +16,11 @@ int iris_venc_inst_init(struct iris_inst *inst) =20 inst->fmt_src =3D kzalloc(sizeof(*inst->fmt_src), GFP_KERNEL); inst->fmt_dst =3D kzalloc(sizeof(*inst->fmt_dst), GFP_KERNEL); - if (!inst->fmt_src || !inst->fmt_dst) + if (!inst->fmt_src || !inst->fmt_dst) { + kfree(inst->fmt_src); + kfree(inst->fmt_dst); return -ENOMEM; + } =20 f =3D inst->fmt_dst; f->type =3D V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; @@ -63,3 +68,208 @@ void iris_venc_inst_deinit(struct iris_inst *inst) kfree(inst->fmt_dst); kfree(inst->fmt_src); } + +static const struct iris_fmt iris_venc_formats[] =3D { + [IRIS_FMT_H264] =3D { + .pixfmt =3D V4L2_PIX_FMT_H264, + .type =3D V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, + }, + [IRIS_FMT_HEVC] =3D { + .pixfmt =3D V4L2_PIX_FMT_HEVC, + .type =3D V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, + }, +}; + +static const struct iris_fmt * +find_format(struct iris_inst *inst, u32 pixfmt, u32 type) +{ + const struct iris_fmt *fmt =3D iris_venc_formats; + unsigned int size =3D ARRAY_SIZE(iris_venc_formats); + unsigned int i; + + for (i =3D 0; i < size; i++) { + if (fmt[i].pixfmt =3D=3D pixfmt) + break; + } + + if (i =3D=3D size || fmt[i].type !=3D type) + return NULL; + + return &fmt[i]; +} + +static const struct iris_fmt * +find_format_by_index(struct iris_inst *inst, u32 index, u32 type) +{ + const struct iris_fmt *fmt =3D iris_venc_formats; + unsigned int size =3D ARRAY_SIZE(iris_venc_formats); + + if (index >=3D size || fmt[index].type !=3D type) + return NULL; + + return &fmt[index]; +} + +int iris_venc_enum_fmt(struct iris_inst *inst, struct v4l2_fmtdesc *f) +{ + const struct iris_fmt *fmt; + + switch (f->type) { + case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE: + if (f->index) + return -EINVAL; + f->pixelformat =3D V4L2_PIX_FMT_NV12; + break; + case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: + fmt =3D find_format_by_index(inst, f->index, f->type); + if (!fmt) + return -EINVAL; + + f->pixelformat =3D fmt->pixfmt; + f->flags =3D V4L2_FMT_FLAG_COMPRESSED | V4L2_FMT_FLAG_ENC_CAP_FRAME_INTE= RVAL; + break; + default: + return -EINVAL; + } + + return 0; +} + +int iris_venc_try_fmt(struct iris_inst *inst, struct v4l2_format *f) +{ + struct v4l2_pix_format_mplane *pixmp =3D &f->fmt.pix_mp; + const struct iris_fmt *fmt; + struct v4l2_format *f_inst; + + memset(pixmp->reserved, 0, sizeof(pixmp->reserved)); + fmt =3D find_format(inst, pixmp->pixelformat, f->type); + switch (f->type) { + case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE: + if (f->fmt.pix_mp.pixelformat !=3D V4L2_PIX_FMT_NV12) { + f_inst =3D inst->fmt_src; + f->fmt.pix_mp.width =3D f_inst->fmt.pix_mp.width; + f->fmt.pix_mp.height =3D f_inst->fmt.pix_mp.height; + f->fmt.pix_mp.pixelformat =3D f_inst->fmt.pix_mp.pixelformat; + } + break; + case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: + if (!fmt) { + f_inst =3D inst->fmt_dst; + f->fmt.pix_mp.width =3D f_inst->fmt.pix_mp.width; + f->fmt.pix_mp.height =3D f_inst->fmt.pix_mp.height; + f->fmt.pix_mp.pixelformat =3D f_inst->fmt.pix_mp.pixelformat; + } + break; + default: + return -EINVAL; + } + + if (pixmp->field =3D=3D V4L2_FIELD_ANY) + pixmp->field =3D V4L2_FIELD_NONE; + + pixmp->num_planes =3D 1; + + return 0; +} + +static int iris_venc_s_fmt_output(struct iris_inst *inst, struct v4l2_form= at *f) +{ + struct v4l2_format *fmt; + + iris_venc_try_fmt(inst, f); + + if (!(find_format(inst, f->fmt.pix_mp.pixelformat, f->type))) + return -EINVAL; + + fmt =3D inst->fmt_dst; + fmt->type =3D V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; + fmt->fmt.pix_mp.num_planes =3D 1; + fmt->fmt.pix_mp.plane_fmt[0].bytesperline =3D 0; + fmt->fmt.pix_mp.plane_fmt[0].sizeimage =3D iris_get_buffer_size(inst, BUF= _OUTPUT); + + if (f->fmt.pix_mp.colorspace !=3D V4L2_COLORSPACE_DEFAULT && + f->fmt.pix_mp.colorspace !=3D V4L2_COLORSPACE_REC709) + f->fmt.pix_mp.colorspace =3D V4L2_COLORSPACE_DEFAULT; + fmt->fmt.pix_mp.colorspace =3D f->fmt.pix_mp.colorspace; + fmt->fmt.pix_mp.xfer_func =3D f->fmt.pix_mp.xfer_func; + fmt->fmt.pix_mp.ycbcr_enc =3D f->fmt.pix_mp.ycbcr_enc; + fmt->fmt.pix_mp.quantization =3D f->fmt.pix_mp.quantization; + + inst->buffers[BUF_OUTPUT].min_count =3D iris_vpu_buf_count(inst, BUF_OUTP= UT); + inst->buffers[BUF_OUTPUT].size =3D fmt->fmt.pix_mp.plane_fmt[0].sizeimage; + fmt->fmt.pix_mp.pixelformat =3D f->fmt.pix_mp.pixelformat; + inst->codec =3D f->fmt.pix_mp.pixelformat; + memcpy(f, fmt, sizeof(struct v4l2_format)); + + return 0; +} + +static int iris_venc_s_fmt_input(struct iris_inst *inst, struct v4l2_forma= t *f) +{ + struct v4l2_format *fmt, *output_fmt; + + iris_venc_try_fmt(inst, f); + + if (f->fmt.pix_mp.pixelformat !=3D V4L2_PIX_FMT_NV12) + return -EINVAL; + + fmt =3D inst->fmt_src; + fmt->type =3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; + fmt->fmt.pix_mp.width =3D ALIGN(f->fmt.pix_mp.width, 128); + fmt->fmt.pix_mp.height =3D ALIGN(f->fmt.pix_mp.height, 32); + fmt->fmt.pix_mp.num_planes =3D 1; + fmt->fmt.pix_mp.pixelformat =3D f->fmt.pix_mp.pixelformat; + fmt->fmt.pix_mp.plane_fmt[0].bytesperline =3D ALIGN(f->fmt.pix_mp.width, = 128); + fmt->fmt.pix_mp.plane_fmt[0].sizeimage =3D iris_get_buffer_size(inst, BUF= _INPUT); + + fmt->fmt.pix_mp.colorspace =3D f->fmt.pix_mp.colorspace; + fmt->fmt.pix_mp.xfer_func =3D f->fmt.pix_mp.xfer_func; + fmt->fmt.pix_mp.ycbcr_enc =3D f->fmt.pix_mp.ycbcr_enc; + fmt->fmt.pix_mp.quantization =3D f->fmt.pix_mp.quantization; + + output_fmt =3D inst->fmt_dst; + output_fmt->fmt.pix_mp.width =3D fmt->fmt.pix_mp.width; + output_fmt->fmt.pix_mp.height =3D fmt->fmt.pix_mp.height; + output_fmt->fmt.pix_mp.colorspace =3D fmt->fmt.pix_mp.colorspace; + output_fmt->fmt.pix_mp.xfer_func =3D fmt->fmt.pix_mp.xfer_func; + output_fmt->fmt.pix_mp.ycbcr_enc =3D fmt->fmt.pix_mp.ycbcr_enc; + output_fmt->fmt.pix_mp.quantization =3D fmt->fmt.pix_mp.quantization; + + inst->buffers[BUF_INPUT].min_count =3D iris_vpu_buf_count(inst, BUF_INPUT= ); + inst->buffers[BUF_INPUT].size =3D fmt->fmt.pix_mp.plane_fmt[0].sizeimage; + + if (f->fmt.pix_mp.width !=3D inst->crop.width || + f->fmt.pix_mp.height !=3D inst->crop.height) { + inst->crop.top =3D 0; + inst->crop.left =3D 0; + inst->crop.width =3D fmt->fmt.pix_mp.width; + inst->crop.height =3D fmt->fmt.pix_mp.height; + + iris_venc_s_fmt_output(inst, output_fmt); + } + + memcpy(f, fmt, sizeof(struct v4l2_format)); + + return 0; +} + +int iris_venc_s_fmt(struct iris_inst *inst, struct v4l2_format *f) +{ + struct vb2_queue *q; + + q =3D v4l2_m2m_get_vq(inst->m2m_ctx, f->type); + if (!q) + return -EINVAL; + + if (vb2_is_busy(q)) + return -EBUSY; + + switch (f->type) { + case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE: + return iris_venc_s_fmt_input(inst, f); + case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: + return iris_venc_s_fmt_output(inst, f); + default: + return -EINVAL; + } +} diff --git a/drivers/media/platform/qcom/iris/iris_venc.h b/drivers/media/p= latform/qcom/iris/iris_venc.h index 8a4cbddd0114b6d0e4ea895362b01c302250c78b..eb26a3ecbd98b3f02dfdea0dfc4= 1bcd3a90904b6 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.h +++ b/drivers/media/platform/qcom/iris/iris_venc.h @@ -10,5 +10,8 @@ struct iris_inst; =20 int iris_venc_inst_init(struct iris_inst *inst); void iris_venc_inst_deinit(struct iris_inst *inst); +int iris_venc_enum_fmt(struct iris_inst *inst, struct v4l2_fmtdesc *f); +int iris_venc_try_fmt(struct iris_inst *inst, struct v4l2_format *f); +int iris_venc_s_fmt(struct iris_inst *inst, struct v4l2_format *f); =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/p= latform/qcom/iris/iris_vidc.c index cecc41a137271762d7622ab2637c4cce2c74a506..7adb82186cac540919463fd6d6b= e85b42eeb73db 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -306,16 +306,26 @@ static int iris_enum_fmt(struct file *filp, void *fh,= struct v4l2_fmtdesc *f) { struct iris_inst *inst =3D iris_get_inst(filp); =20 - return iris_vdec_enum_fmt(inst, f); + if (inst->domain =3D=3D DECODER) + return iris_vdec_enum_fmt(inst, f); + else if (inst->domain =3D=3D ENCODER) + return iris_venc_enum_fmt(inst, f); + else + return -EINVAL; } =20 static int iris_try_fmt_vid_mplane(struct file *filp, void *fh, struct v4l= 2_format *f) { struct iris_inst *inst =3D iris_get_inst(filp); - int ret; + int ret =3D 0; =20 mutex_lock(&inst->lock); - ret =3D iris_vdec_try_fmt(inst, f); + + if (inst->domain =3D=3D DECODER) + ret =3D iris_vdec_try_fmt(inst, f); + else if (inst->domain =3D=3D ENCODER) + ret =3D iris_venc_try_fmt(inst, f); + mutex_unlock(&inst->lock); =20 return ret; @@ -324,10 +334,15 @@ static int iris_try_fmt_vid_mplane(struct file *filp,= void *fh, struct v4l2_form static int iris_s_fmt_vid_mplane(struct file *filp, void *fh, struct v4l2_= format *f) { struct iris_inst *inst =3D iris_get_inst(filp); - int ret; + int ret =3D 0; =20 mutex_lock(&inst->lock); - ret =3D iris_vdec_s_fmt(inst, f); + + if (inst->domain =3D=3D DECODER) + ret =3D iris_vdec_s_fmt(inst, f); + else if (inst->domain =3D=3D ENCODER) + ret =3D iris_venc_s_fmt(inst, f); + mutex_unlock(&inst->lock); =20 return ret; @@ -471,7 +486,7 @@ static const struct vb2_ops iris_vb2_ops =3D { .buf_queue =3D iris_vb2_buf_queue, }; =20 -static const struct v4l2_ioctl_ops iris_v4l2_ioctl_ops =3D { +static const struct v4l2_ioctl_ops iris_v4l2_ioctl_ops_dec =3D { .vidioc_enum_fmt_vid_cap =3D iris_enum_fmt, .vidioc_enum_fmt_vid_out =3D iris_enum_fmt, .vidioc_try_fmt_vid_cap_mplane =3D iris_try_fmt_vid_mplane, @@ -499,9 +514,21 @@ static const struct v4l2_ioctl_ops iris_v4l2_ioctl_ops= =3D { .vidioc_decoder_cmd =3D iris_dec_cmd, }; =20 +static const struct v4l2_ioctl_ops iris_v4l2_ioctl_ops_enc =3D { + .vidioc_enum_fmt_vid_cap =3D iris_enum_fmt, + .vidioc_enum_fmt_vid_out =3D iris_enum_fmt, + .vidioc_try_fmt_vid_cap_mplane =3D iris_try_fmt_vid_mplane, + .vidioc_try_fmt_vid_out_mplane =3D iris_try_fmt_vid_mplane, + .vidioc_s_fmt_vid_cap_mplane =3D iris_s_fmt_vid_mplane, + .vidioc_s_fmt_vid_out_mplane =3D iris_s_fmt_vid_mplane, + .vidioc_g_fmt_vid_cap_mplane =3D iris_g_fmt_vid_mplane, + .vidioc_g_fmt_vid_out_mplane =3D iris_g_fmt_vid_mplane, +}; + void iris_init_ops(struct iris_core *core) { core->iris_v4l2_file_ops =3D &iris_v4l2_file_ops; core->iris_vb2_ops =3D &iris_vb2_ops; - core->iris_v4l2_ioctl_ops =3D &iris_v4l2_ioctl_ops; + core->iris_v4l2_ioctl_ops_dec =3D &iris_v4l2_ioctl_ops_dec; + core->iris_v4l2_ioctl_ops_enc =3D &iris_v4l2_ioctl_ops_enc; } --=20 2.34.1 From nobody Fri Oct 3 20:48:35 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C25529D275; 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Mon, 25 Aug 2025 07:01:50 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 57P71nQT020360 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Aug 2025 07:01:49 GMT Received: from hu-dikshita-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.24; Mon, 25 Aug 2025 00:01:45 -0700 From: Dikshita Agarwal Date: Mon, 25 Aug 2025 12:30:40 +0530 Subject: [PATCH v4 16/26] media: iris: Add support for ENUM_FRAMESIZES/FRAMEINTERVALS for encoder Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250825-iris-video-encoder-v4-16-84aa2bc0a46b@quicinc.com> References: <20250825-iris-video-encoder-v4-0-84aa2bc0a46b@quicinc.com> In-Reply-To: <20250825-iris-video-encoder-v4-0-84aa2bc0a46b@quicinc.com> To: Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Stefan Schmidt , Vedang Nagar , "Hans Verkuil" , Hans Verkuil CC: , , , Renjiang Han , Wangao Wang , Dikshita Agarwal , Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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This allows userspace application to query encoder capabilities and adapt encoding configurations accordingly. Tested-by: Vikash Garodia # X1E80100 Reviewed-by: Vikash Garodia Tested-by: Neil Armstrong # on SM8550-HDK Tested-by: Neil Armstrong # on SM8650-HDK Signed-off-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e80100-crd --- .../platform/qcom/iris/iris_platform_common.h | 5 +- .../media/platform/qcom/iris/iris_platform_gen2.c | 3 ++ .../platform/qcom/iris/iris_platform_sm8250.c | 1 + drivers/media/platform/qcom/iris/iris_vdec.c | 13 +++++ drivers/media/platform/qcom/iris/iris_vdec.h | 1 + drivers/media/platform/qcom/iris/iris_venc.c | 13 +++++ drivers/media/platform/qcom/iris/iris_venc.h | 1 + drivers/media/platform/qcom/iris/iris_vidc.c | 58 ++++++++++++++++++= ++-- 8 files changed, 91 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index adafdce8a856f9c661aabc5ca28f0faceaa93551..792f46e2e34fd564a1ed61523f7= 2826fc8f74582 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -21,7 +21,8 @@ struct iris_inst; #define DEFAULT_MAX_HOST_BUF_COUNT 64 #define DEFAULT_MAX_HOST_BURST_BUF_COUNT 256 #define DEFAULT_FPS 30 -#define NUM_MBS_8K ((8192 * 4352) / 256) +#define MAXIMUM_FPS 480 +#define NUM_MBS_8K ((8192 * 4352) / 256) =20 enum stage_type { STAGE_1 =3D 1, @@ -179,6 +180,8 @@ struct iris_platform_data { u32 max_session_count; /* max number of macroblocks per frame supported */ u32 max_core_mbpf; + /* max number of macroblocks per second supported */ + u32 max_core_mbps; const u32 *input_config_params_default; unsigned int input_config_params_default_size; const u32 *input_config_params_hevc; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index d3026b2bcb708c7ec31f134f628df7e57b54af4f..d5f7eb904569d4e3ae9c33e1436= c8151cac5355d 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -354,6 +354,7 @@ struct iris_platform_data sm8550_data =3D { .num_vpp_pipe =3D 4, .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K * 2, + .max_core_mbps =3D ((7680 * 4320) / 256) * 60, .input_config_params_default =3D sm8550_vdec_input_config_params_default, .input_config_params_default_size =3D @@ -429,6 +430,7 @@ struct iris_platform_data sm8650_data =3D { .num_vpp_pipe =3D 4, .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K * 2, + .max_core_mbps =3D ((7680 * 4320) / 256) * 60, .input_config_params_default =3D sm8550_vdec_input_config_params_default, .input_config_params_default_size =3D @@ -500,6 +502,7 @@ struct iris_platform_data qcs8300_data =3D { .num_vpp_pipe =3D 2, .max_session_count =3D 16, .max_core_mbpf =3D ((4096 * 2176) / 256) * 4, + .max_core_mbps =3D (((3840 * 2176) / 256) * 120), .input_config_params_default =3D sm8550_vdec_input_config_params_default, .input_config_params_default_size =3D diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/driv= ers/media/platform/qcom/iris/iris_platform_sm8250.c index 8d0816a67ae0b6886204ce93fa5ccafaac10392a..2a3cbe1f2d4b27d3cce9e9cdad1= 525801d71a041 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c @@ -128,6 +128,7 @@ struct iris_platform_data sm8250_data =3D { .num_vpp_pipe =3D 4, .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K, + .max_core_mbps =3D ((7680 * 4320) / 256) * 60, .input_config_params_default =3D sm8250_vdec_input_config_param_default, .input_config_params_default_size =3D diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/p= latform/qcom/iris/iris_vdec.c index b4ad5df62bcd1ee390ce4f7c1c58c8693d0ab0ca..f1bc928043acea9aae7bbb96044= 8adec9e7a4880 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.c +++ b/drivers/media/platform/qcom/iris/iris_vdec.c @@ -263,6 +263,19 @@ int iris_vdec_s_fmt(struct iris_inst *inst, struct v4l= 2_format *f) return 0; } =20 +int iris_vdec_validate_format(struct iris_inst *inst, u32 pixelformat) +{ + const struct iris_fmt *fmt =3D NULL; + + if (pixelformat !=3D V4L2_PIX_FMT_NV12) { + fmt =3D find_format(inst, pixelformat, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE= ); + if (!fmt) + return -EINVAL; + } + + return 0; +} + int iris_vdec_subscribe_event(struct iris_inst *inst, const struct v4l2_ev= ent_subscription *sub) { int ret =3D 0; diff --git a/drivers/media/platform/qcom/iris/iris_vdec.h b/drivers/media/p= latform/qcom/iris/iris_vdec.h index b24932dc511a65017b1cadbcb984544475bd0723..097e02bfa72b5ac4e46e66c6184= 2df1d9dd4565b 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.h +++ b/drivers/media/platform/qcom/iris/iris_vdec.h @@ -13,6 +13,7 @@ void iris_vdec_inst_deinit(struct iris_inst *inst); int iris_vdec_enum_fmt(struct iris_inst *inst, struct v4l2_fmtdesc *f); int iris_vdec_try_fmt(struct iris_inst *inst, struct v4l2_format *f); int iris_vdec_s_fmt(struct iris_inst *inst, struct v4l2_format *f); +int iris_vdec_validate_format(struct iris_inst *inst, u32 pixelformat); int iris_vdec_subscribe_event(struct iris_inst *inst, const struct v4l2_ev= ent_subscription *sub); void iris_vdec_src_change(struct iris_inst *inst); int iris_vdec_streamon_input(struct iris_inst *inst); diff --git a/drivers/media/platform/qcom/iris/iris_venc.c b/drivers/media/p= latform/qcom/iris/iris_venc.c index 40f7990cd162ad400711d729917b7e2577d562b2..55938050249fa1a041b835214e7= 9028ae0b35e36 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.c +++ b/drivers/media/platform/qcom/iris/iris_venc.c @@ -273,3 +273,16 @@ int iris_venc_s_fmt(struct iris_inst *inst, struct v4l= 2_format *f) return -EINVAL; } } + +int iris_venc_validate_format(struct iris_inst *inst, u32 pixelformat) +{ + const struct iris_fmt *fmt =3D NULL; + + if (pixelformat !=3D V4L2_PIX_FMT_NV12) { + fmt =3D find_format(inst, pixelformat, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLAN= E); + if (!fmt) + return -EINVAL; + } + + return 0; +} diff --git a/drivers/media/platform/qcom/iris/iris_venc.h b/drivers/media/p= latform/qcom/iris/iris_venc.h index eb26a3ecbd98b3f02dfdea0dfc41bcd3a90904b6..04fd41275547c40c359c6ea04df= e4ee31d2d0df6 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.h +++ b/drivers/media/platform/qcom/iris/iris_venc.h @@ -13,5 +13,6 @@ void iris_venc_inst_deinit(struct iris_inst *inst); int iris_venc_enum_fmt(struct iris_inst *inst, struct v4l2_fmtdesc *f); int iris_venc_try_fmt(struct iris_inst *inst, struct v4l2_format *f); int iris_venc_s_fmt(struct iris_inst *inst, struct v4l2_format *f); +int iris_venc_validate_format(struct iris_inst *inst, u32 pixelformat); =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/p= latform/qcom/iris/iris_vidc.c index 7adb82186cac540919463fd6d6be85b42eeb73db..3f641782e932a30af46c631003a= 72d7dd2b4386e 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -371,13 +371,18 @@ static int iris_enum_framesizes(struct file *filp, vo= id *fh, { struct iris_inst *inst =3D iris_get_inst(filp); struct platform_inst_caps *caps; + int ret =3D 0; =20 if (fsize->index) return -EINVAL; =20 - if (fsize->pixel_format !=3D V4L2_PIX_FMT_H264 && - fsize->pixel_format !=3D V4L2_PIX_FMT_NV12) - return -EINVAL; + if (inst->domain =3D=3D DECODER) + ret =3D iris_vdec_validate_format(inst, fsize->pixel_format); + else + ret =3D iris_venc_validate_format(inst, fsize->pixel_format); + + if (ret) + return ret; =20 caps =3D inst->core->iris_platform_data->inst_caps; =20 @@ -389,6 +394,51 @@ static int iris_enum_framesizes(struct file *filp, voi= d *fh, fsize->stepwise.max_height =3D caps->max_frame_height; fsize->stepwise.step_height =3D STEP_HEIGHT; =20 + return ret; +} + +static int iris_enum_frameintervals(struct file *filp, void *fh, + struct v4l2_frmivalenum *fival) + +{ + struct iris_inst *inst =3D iris_get_inst(filp); + struct iris_core *core =3D inst->core; + struct platform_inst_caps *caps; + u32 fps, mbpf; + int ret =3D 0; + + if (inst->domain =3D=3D DECODER) + return -ENOTTY; + + if (fival->index) + return -EINVAL; + + ret =3D iris_venc_validate_format(inst, fival->pixel_format); + if (ret) + return ret; + + if (!fival->width || !fival->height) + return -EINVAL; + + caps =3D inst->core->iris_platform_data->inst_caps; + if (fival->width > caps->max_frame_width || + fival->width < caps->min_frame_width || + fival->height > caps->max_frame_height || + fival->height < caps->min_frame_height) + return -EINVAL; + + mbpf =3D NUM_MBS_PER_FRAME(fival->height, fival->width); + fps =3D DIV_ROUND_UP(core->iris_platform_data->max_core_mbps, mbpf); + + fival->type =3D V4L2_FRMIVAL_TYPE_STEPWISE; + fival->stepwise.min.numerator =3D 1; + fival->stepwise.min.denominator =3D + min_t(u32, fps, MAXIMUM_FPS); + fival->stepwise.max.numerator =3D 1; + fival->stepwise.max.denominator =3D 1; + fival->stepwise.step.numerator =3D 1; + fival->stepwise.step.denominator =3D MAXIMUM_FPS; + return 0; } =20 @@ -523,6 +573,8 @@ static const struct v4l2_ioctl_ops iris_v4l2_ioctl_ops_= enc =3D { .vidioc_s_fmt_vid_out_mplane =3D iris_s_fmt_vid_mplane, .vidioc_g_fmt_vid_cap_mplane =3D iris_g_fmt_vid_mplane, .vidioc_g_fmt_vid_out_mplane =3D iris_g_fmt_vid_mplane, + .vidioc_enum_framesizes =3D iris_enum_framesizes, + .vidioc_enum_frameintervals =3D iris_enum_frameintervals, }; =20 void iris_init_ops(struct iris_core *core) --=20 2.34.1 From nobody Fri Oct 3 20:48:35 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 845082BD590; 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Tested-by: Vikash Garodia # X1E80100 Reviewed-by: Vikash Garodia Tested-by: Neil Armstrong # on SM8550-HDK Tested-by: Neil Armstrong # on SM8650-HDK Signed-off-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e80100-crd --- drivers/media/platform/qcom/iris/iris_vidc.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/p= latform/qcom/iris/iris_vidc.c index 3f641782e932a30af46c631003a72d7dd2b4386e..92a616787a30a51f4fbf4760bad= ffd6fabc48cc6 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -444,8 +444,14 @@ static int iris_enum_frameintervals(struct file *filp,= void *fh, =20 static int iris_querycap(struct file *filp, void *fh, struct v4l2_capabili= ty *cap) { + struct iris_inst *inst =3D iris_get_inst(filp); + strscpy(cap->driver, IRIS_DRV_NAME, sizeof(cap->driver)); - strscpy(cap->card, "Iris Decoder", sizeof(cap->card)); + + if (inst->domain =3D=3D DECODER) + strscpy(cap->card, "Iris Decoder", sizeof(cap->card)); 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This enables userspace applications to subscribe to V4L2 events, allowing asynchronous notification mechanisms. Tested-by: Vikash Garodia # X1E80100 Reviewed-by: Vikash Garodia Tested-by: Neil Armstrong # on SM8550-HDK Tested-by: Neil Armstrong # on SM8650-HDK Signed-off-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e80100-crd --- drivers/media/platform/qcom/iris/iris_venc.c | 14 ++++++++++++++ drivers/media/platform/qcom/iris/iris_venc.h | 1 + drivers/media/platform/qcom/iris/iris_vidc.c | 9 ++++++++- 3 files changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/iris_venc.c b/drivers/media/p= latform/qcom/iris/iris_venc.c index 55938050249fa1a041b835214e79028ae0b35e36..384b30555546f2a0677e49400f1= 77b96611f866b 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.c +++ b/drivers/media/platform/qcom/iris/iris_venc.c @@ -3,6 +3,7 @@ * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights res= erved. */ =20 +#include #include =20 #include "iris_buffer.h" @@ -286,3 +287,16 @@ int iris_venc_validate_format(struct iris_inst *inst, = u32 pixelformat) =20 return 0; } + +int iris_venc_subscribe_event(struct iris_inst *inst, + const struct v4l2_event_subscription *sub) +{ + switch (sub->type) { + case V4L2_EVENT_EOS: + return v4l2_event_subscribe(&inst->fh, sub, 0, NULL); + case V4L2_EVENT_CTRL: + return v4l2_ctrl_subscribe_event(&inst->fh, sub); + default: + return -EINVAL; + } +} diff --git a/drivers/media/platform/qcom/iris/iris_venc.h b/drivers/media/p= latform/qcom/iris/iris_venc.h index 04fd41275547c40c359c6ea04dfe4ee31d2d0df6..2d9614ae18e8a2318df6673fbea= e5ee33c99b596 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.h +++ b/drivers/media/platform/qcom/iris/iris_venc.h @@ -14,5 +14,6 @@ int iris_venc_enum_fmt(struct iris_inst *inst, struct v4l= 2_fmtdesc *f); int iris_venc_try_fmt(struct iris_inst *inst, struct v4l2_format *f); int iris_venc_s_fmt(struct iris_inst *inst, struct v4l2_format *f); int iris_venc_validate_format(struct iris_inst *inst, u32 pixelformat); +int iris_venc_subscribe_event(struct iris_inst *inst, const struct v4l2_ev= ent_subscription *sub); =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/p= latform/qcom/iris/iris_vidc.c index 92a616787a30a51f4fbf4760badffd6fabc48cc6..5d9b36858e9317b1eddac120044= 32229e18967a7 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -487,7 +487,12 @@ static int iris_subscribe_event(struct v4l2_fh *fh, co= nst struct v4l2_event_subs { struct iris_inst *inst =3D container_of(fh, struct iris_inst, fh); =20 - return iris_vdec_subscribe_event(inst, sub); + if (inst->domain =3D=3D DECODER) + return iris_vdec_subscribe_event(inst, sub); + else if (inst->domain =3D=3D ENCODER) + return iris_venc_subscribe_event(inst, sub); + + return -EINVAL; } =20 static int iris_dec_cmd(struct file *filp, void *fh, @@ -582,6 +587,8 @@ static const struct v4l2_ioctl_ops iris_v4l2_ioctl_ops_= enc =3D { .vidioc_enum_framesizes =3D iris_enum_framesizes, .vidioc_enum_frameintervals =3D iris_enum_frameintervals, .vidioc_querycap =3D iris_querycap, + .vidioc_subscribe_event =3D iris_subscribe_event, + .vidioc_unsubscribe_event =3D v4l2_event_unsubscribe, }; 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This allows userspace to query and configure rectangular selection areas such as crop. Tested-by: Vikash Garodia # X1E80100 Reviewed-by: Vikash Garodia Tested-by: Neil Armstrong # on SM8550-HDK Tested-by: Neil Armstrong # on SM8650-HDK Signed-off-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e80100-crd --- drivers/media/platform/qcom/iris/iris_venc.c | 26 +++++++++++ drivers/media/platform/qcom/iris/iris_venc.h | 1 + drivers/media/platform/qcom/iris/iris_vidc.c | 65 ++++++++++++++++++++++--= ---- 3 files changed, 78 insertions(+), 14 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_venc.c b/drivers/media/p= latform/qcom/iris/iris_venc.c index 384b30555546f2a0677e49400f177b96611f866b..71960a0e903d114be7a9e797089= c3dee2fab2545 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.c +++ b/drivers/media/platform/qcom/iris/iris_venc.c @@ -300,3 +300,29 @@ int iris_venc_subscribe_event(struct iris_inst *inst, return -EINVAL; } } + +int iris_venc_s_selection(struct iris_inst *inst, struct v4l2_selection *s) +{ + if (s->type !=3D V4L2_BUF_TYPE_VIDEO_OUTPUT) + return -EINVAL; + + switch (s->target) { + case V4L2_SEL_TGT_CROP: + s->r.left =3D 0; + s->r.top =3D 0; + + if (s->r.width > inst->fmt_src->fmt.pix_mp.width || + s->r.height > inst->fmt_src->fmt.pix_mp.height) + return -EINVAL; + + inst->crop.left =3D s->r.left; + inst->crop.top =3D s->r.top; + inst->crop.width =3D s->r.width; + inst->crop.height =3D s->r.height; + inst->fmt_dst->fmt.pix_mp.width =3D inst->crop.width; + inst->fmt_dst->fmt.pix_mp.height =3D inst->crop.height; + return iris_venc_s_fmt_output(inst, inst->fmt_dst); + default: + return -EINVAL; + } +} diff --git a/drivers/media/platform/qcom/iris/iris_venc.h b/drivers/media/p= latform/qcom/iris/iris_venc.h index 2d9614ae18e8a2318df6673fbeae5ee33c99b596..72c6e25d87113baa6d2219ae478= b7d7df1aed7bf 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.h +++ b/drivers/media/platform/qcom/iris/iris_venc.h @@ -15,5 +15,6 @@ int iris_venc_try_fmt(struct iris_inst *inst, struct v4l2= _format *f); int iris_venc_s_fmt(struct iris_inst *inst, struct v4l2_format *f); int iris_venc_validate_format(struct iris_inst *inst, u32 pixelformat); int iris_venc_subscribe_event(struct iris_inst *inst, const struct v4l2_ev= ent_subscription *sub); +int iris_venc_s_selection(struct iris_inst *inst, struct v4l2_selection *s= ); =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/p= latform/qcom/iris/iris_vidc.c index 5d9b36858e9317b1eddac12004432229e18967a7..b134ae710d9e1d02bc52db2e935= 6fdc4f668a387 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -460,29 +460,64 @@ static int iris_g_selection(struct file *filp, void *= fh, struct v4l2_selection * { struct iris_inst *inst =3D iris_get_inst(filp); =20 - if (s->type !=3D V4L2_BUF_TYPE_VIDEO_CAPTURE) + if (s->type !=3D V4L2_BUF_TYPE_VIDEO_CAPTURE && + inst->domain =3D=3D DECODER) return -EINVAL; =20 - switch (s->target) { - case V4L2_SEL_TGT_CROP_BOUNDS: - case V4L2_SEL_TGT_CROP_DEFAULT: - case V4L2_SEL_TGT_CROP: - case V4L2_SEL_TGT_COMPOSE_BOUNDS: - case V4L2_SEL_TGT_COMPOSE_PADDED: - case V4L2_SEL_TGT_COMPOSE_DEFAULT: - case V4L2_SEL_TGT_COMPOSE: + if (s->type !=3D V4L2_BUF_TYPE_VIDEO_OUTPUT && + inst->domain =3D=3D ENCODER) + return -EINVAL; + + if (inst->domain =3D=3D DECODER) { + switch (s->target) { + case V4L2_SEL_TGT_CROP_BOUNDS: + case V4L2_SEL_TGT_CROP_DEFAULT: + case V4L2_SEL_TGT_CROP: + case V4L2_SEL_TGT_COMPOSE_BOUNDS: + case V4L2_SEL_TGT_COMPOSE_PADDED: + case V4L2_SEL_TGT_COMPOSE_DEFAULT: + case V4L2_SEL_TGT_COMPOSE: + s->r.left =3D inst->crop.left; + s->r.top =3D inst->crop.top; + s->r.width =3D inst->crop.width; + s->r.height =3D inst->crop.height; + break; + default: + return -EINVAL; + } + } else if (inst->domain =3D=3D ENCODER) { + switch (s->target) { + case V4L2_SEL_TGT_CROP_BOUNDS: + case V4L2_SEL_TGT_CROP_DEFAULT: + s->r.width =3D inst->fmt_src->fmt.pix_mp.width; + s->r.height =3D inst->fmt_src->fmt.pix_mp.height; + break; + case V4L2_SEL_TGT_CROP: + s->r.width =3D inst->crop.width; + s->r.height =3D inst->crop.height; + break; + default: + return -EINVAL; + } s->r.left =3D inst->crop.left; s->r.top =3D inst->crop.top; - s->r.width =3D inst->crop.width; - s->r.height =3D inst->crop.height; - break; - default: - return -EINVAL; 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Mon, 25 Aug 2025 07:02:07 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 57P726tj020046 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Aug 2025 07:02:06 GMT Received: from hu-dikshita-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.24; Mon, 25 Aug 2025 00:02:02 -0700 From: Dikshita Agarwal Date: Mon, 25 Aug 2025 12:30:44 +0530 Subject: [PATCH v4 20/26] media: iris: Add support for G/S_PARM for encoder video device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250825-iris-video-encoder-v4-20-84aa2bc0a46b@quicinc.com> References: <20250825-iris-video-encoder-v4-0-84aa2bc0a46b@quicinc.com> In-Reply-To: <20250825-iris-video-encoder-v4-0-84aa2bc0a46b@quicinc.com> To: Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Stefan Schmidt , Vedang Nagar , "Hans Verkuil" , Hans Verkuil CC: , , , Renjiang Han , Wangao Wang , Dikshita Agarwal , Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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This allows userspace to query the current streaming parameters such as frame intervals and set desired streaming parameters primarily the frame rate. Tested-by: Vikash Garodia # X1E80100 Reviewed-by: Vikash Garodia Tested-by: Neil Armstrong # on SM8550-HDK Tested-by: Neil Armstrong # on SM8650-HDK Signed-off-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e80100-crd --- drivers/media/platform/qcom/iris/iris_instance.h | 5 ++ .../platform/qcom/iris/iris_platform_common.h | 2 + .../media/platform/qcom/iris/iris_platform_gen2.c | 2 + .../platform/qcom/iris/iris_platform_qcs8300.h | 2 + .../platform/qcom/iris/iris_platform_sm8250.c | 2 + drivers/media/platform/qcom/iris/iris_utils.c | 36 +++++++++ drivers/media/platform/qcom/iris/iris_utils.h | 2 + drivers/media/platform/qcom/iris/iris_vb2.c | 17 ---- drivers/media/platform/qcom/iris/iris_venc.c | 94 ++++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_venc.h | 2 + drivers/media/platform/qcom/iris/iris_vidc.c | 30 +++++++ 11 files changed, 177 insertions(+), 17 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_instance.h b/drivers/med= ia/platform/qcom/iris/iris_instance.h index 55cf9702111829ef24189986ba5245c7684bfe11..b75549718df3c87cd85aecfc74c= 873c60cd4bde5 100644 --- a/drivers/media/platform/qcom/iris/iris_instance.h +++ b/drivers/media/platform/qcom/iris/iris_instance.h @@ -61,6 +61,9 @@ struct iris_fmt { * @metadata_idx: index for metadata buffer * @codec: codec type * @last_buffer_dequeued: a flag to indicate that last buffer is sent by d= river + * @frame_rate: frame rate of current instance + * @operating_rate: operating rate of current instance + */ =20 struct iris_inst { @@ -96,6 +99,8 @@ struct iris_inst { u32 metadata_idx; u32 codec; bool last_buffer_dequeued; + u32 frame_rate; + u32 operating_rate; }; =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 792f46e2e34fd564a1ed61523f72826fc8f74582..d0b84c93aef409b51a767ba11f9= 1c6ce2533f27f 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -79,6 +79,8 @@ struct platform_inst_caps { u32 mb_cycles_fw; u32 mb_cycles_fw_vpp; u32 num_comv; + u32 max_frame_rate; + u32 max_operating_rate; }; =20 enum platform_inst_fw_cap_type { diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index d5f7eb904569d4e3ae9c33e1436c8151cac5355d..a245fce04b3a901cf2eb06fb35c= 15c0176199c11 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -209,6 +209,8 @@ static struct platform_inst_caps platform_inst_cap_sm85= 50 =3D { .mb_cycles_fw =3D 489583, .mb_cycles_fw_vpp =3D 66234, .num_comv =3D 0, + .max_frame_rate =3D MAXIMUM_FPS, + .max_operating_rate =3D MAXIMUM_FPS, }; =20 static void iris_set_sm8550_preset_registers(struct iris_core *core) diff --git a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h b/dri= vers/media/platform/qcom/iris/iris_platform_qcs8300.h index a8d66ed388a34e6bb45d4a089d981bb7d135fb50..64331b705fca541e0547afc01ec= 108759529c9d8 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h +++ b/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h @@ -197,4 +197,6 @@ static struct platform_inst_caps platform_inst_cap_qcs8= 300 =3D { .mb_cycles_fw =3D 326389, .mb_cycles_fw_vpp =3D 44156, .num_comv =3D 0, + .max_frame_rate =3D MAXIMUM_FPS, + .max_operating_rate =3D MAXIMUM_FPS, }; diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/driv= ers/media/platform/qcom/iris/iris_platform_sm8250.c index 2a3cbe1f2d4b27d3cce9e9cdad1525801d71a041..4ff72109c6001cc47d746d366f4= 58c0ff0a8924a 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c @@ -40,6 +40,8 @@ static struct platform_inst_caps platform_inst_cap_sm8250= =3D { .max_mbpf =3D 138240, .mb_cycles_vsp =3D 25, .mb_cycles_vpp =3D 200, + .max_frame_rate =3D MAXIMUM_FPS, + .max_operating_rate =3D MAXIMUM_FPS, }; =20 static void iris_set_sm8250_preset_registers(struct iris_core *core) diff --git a/drivers/media/platform/qcom/iris/iris_utils.c b/drivers/media/= platform/qcom/iris/iris_utils.c index 83c70d6a2d9092615dcf1b7d0fc85110f0df1aa0..85c70a62b1fd2c409fc18b28f64= 771cb0097a7fd 100644 --- a/drivers/media/platform/qcom/iris/iris_utils.c +++ b/drivers/media/platform/qcom/iris/iris_utils.c @@ -88,3 +88,39 @@ struct iris_inst *iris_get_instance(struct iris_core *co= re, u32 session_id) mutex_unlock(&core->lock); return NULL; } + +int iris_check_core_mbpf(struct iris_inst *inst) +{ + struct iris_core *core =3D inst->core; + struct iris_inst *instance; + u32 total_mbpf =3D 0; + + mutex_lock(&core->lock); + list_for_each_entry(instance, &core->instances, list) + total_mbpf +=3D iris_get_mbpf(instance); + mutex_unlock(&core->lock); + + if (total_mbpf > core->iris_platform_data->max_core_mbpf) + return -ENOMEM; + + return 0; +} + +int iris_check_core_mbps(struct iris_inst *inst) +{ + struct iris_core *core =3D inst->core; + struct iris_inst *instance; + u32 total_mbps =3D 0, fps =3D 0; + + mutex_lock(&core->lock); + list_for_each_entry(instance, &core->instances, list) { + fps =3D max(instance->frame_rate, instance->operating_rate); + total_mbps +=3D iris_get_mbpf(instance) * fps; + } + mutex_unlock(&core->lock); + + if (total_mbps > core->iris_platform_data->max_core_mbps) + return -ENOMEM; + + return 0; +} diff --git a/drivers/media/platform/qcom/iris/iris_utils.h b/drivers/media/= platform/qcom/iris/iris_utils.h index 49869cf7a376880a026f44ff3883a6b13c6fcfbb..75740181122f5bdf93d64d3f43b= 3a26a9fe97919 100644 --- a/drivers/media/platform/qcom/iris/iris_utils.h +++ b/drivers/media/platform/qcom/iris/iris_utils.h @@ -49,5 +49,7 @@ struct iris_inst *iris_get_instance(struct iris_core *cor= e, u32 session_id); void iris_helper_buffers_done(struct iris_inst *inst, unsigned int type, enum vb2_buffer_state state); int iris_wait_for_session_response(struct iris_inst *inst, bool is_flush); +int iris_check_core_mbpf(struct iris_inst *inst); +int iris_check_core_mbps(struct iris_inst *inst); =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_vb2.c b/drivers/media/pl= atform/qcom/iris/iris_vb2.c index e62ed7a57df2debf0a930ad8307e6d945f589922..e32f7e1f007228a3b2b51cd76cd= 193d852f16080 100644 --- a/drivers/media/platform/qcom/iris/iris_vb2.c +++ b/drivers/media/platform/qcom/iris/iris_vb2.c @@ -12,23 +12,6 @@ #include "iris_vdec.h" #include "iris_power.h" =20 -static int iris_check_core_mbpf(struct iris_inst *inst) -{ - struct iris_core *core =3D inst->core; - struct iris_inst *instance; - u32 total_mbpf =3D 0; - - mutex_lock(&core->lock); - list_for_each_entry(instance, &core->instances, list) - total_mbpf +=3D iris_get_mbpf(instance); - mutex_unlock(&core->lock); - - if (total_mbpf > core->iris_platform_data->max_core_mbpf) - return -ENOMEM; - - return 0; -} - static int iris_check_inst_mbpf(struct iris_inst *inst) { struct platform_inst_caps *caps; diff --git a/drivers/media/platform/qcom/iris/iris_venc.c b/drivers/media/p= latform/qcom/iris/iris_venc.c index 71960a0e903d114be7a9e797089c3dee2fab2545..967db02ed27f31498e0f5c3245a= 37473022f4be5 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.c +++ b/drivers/media/platform/qcom/iris/iris_venc.c @@ -61,6 +61,9 @@ int iris_venc_inst_init(struct iris_inst *inst) inst->crop.width =3D f->fmt.pix_mp.width; inst->crop.height =3D f->fmt.pix_mp.height; =20 + inst->operating_rate =3D DEFAULT_FPS; + inst->frame_rate =3D DEFAULT_FPS; + return 0; } =20 @@ -326,3 +329,94 @@ int iris_venc_s_selection(struct iris_inst *inst, stru= ct v4l2_selection *s) return -EINVAL; } } + +int iris_venc_s_param(struct iris_inst *inst, struct v4l2_streamparm *s_pa= rm) +{ + struct platform_inst_caps *caps =3D inst->core->iris_platform_data->inst_= caps; + struct vb2_queue *src_q =3D v4l2_m2m_get_src_vq(inst->m2m_ctx); + struct vb2_queue *dst_q =3D v4l2_m2m_get_dst_vq(inst->m2m_ctx); + struct v4l2_fract *timeperframe =3D NULL; + u32 default_rate =3D DEFAULT_FPS; + bool is_frame_rate =3D false; + u64 us_per_frame, fps; + u32 max_rate; + + int ret =3D 0; + + if (s_parm->type =3D=3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + timeperframe =3D &s_parm->parm.output.timeperframe; + max_rate =3D caps->max_operating_rate; + s_parm->parm.output.capability =3D V4L2_CAP_TIMEPERFRAME; + } else { + timeperframe =3D &s_parm->parm.capture.timeperframe; + is_frame_rate =3D true; + max_rate =3D caps->max_frame_rate; + s_parm->parm.capture.capability =3D V4L2_CAP_TIMEPERFRAME; + } + + if (!timeperframe->denominator || !timeperframe->numerator) { + if (!timeperframe->numerator) + timeperframe->numerator =3D 1; + if (!timeperframe->denominator) + timeperframe->denominator =3D default_rate; + } + + us_per_frame =3D timeperframe->numerator * (u64)USEC_PER_SEC; + do_div(us_per_frame, timeperframe->denominator); + + if (!us_per_frame) + return -EINVAL; + + fps =3D (u64)USEC_PER_SEC; + do_div(fps, us_per_frame); + if (fps > max_rate) { + ret =3D -ENOMEM; + goto reset_rate; + } + + if (is_frame_rate) + inst->frame_rate =3D (u32)fps; + else + inst->operating_rate =3D (u32)fps; + + if ((s_parm->type =3D=3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE && vb2_is_stre= aming(src_q)) || + (s_parm->type =3D=3D V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE && vb2_is_str= eaming(dst_q))) { + ret =3D iris_check_core_mbpf(inst); + if (ret) + goto reset_rate; + ret =3D iris_check_core_mbps(inst); + if (ret) + goto reset_rate; + } + + return 0; + +reset_rate: + if (ret) { + if (is_frame_rate) + inst->frame_rate =3D default_rate; + else + inst->operating_rate =3D default_rate; + } + + return ret; +} + +int iris_venc_g_param(struct iris_inst *inst, struct v4l2_streamparm *s_pa= rm) +{ + struct v4l2_fract *timeperframe =3D NULL; + + if (s_parm->type =3D=3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) { + timeperframe =3D &s_parm->parm.output.timeperframe; + timeperframe->numerator =3D 1; + timeperframe->denominator =3D inst->operating_rate; + s_parm->parm.output.capability =3D V4L2_CAP_TIMEPERFRAME; + } else { + timeperframe =3D &s_parm->parm.capture.timeperframe; + timeperframe->numerator =3D 1; + timeperframe->denominator =3D inst->frame_rate; + s_parm->parm.capture.capability =3D V4L2_CAP_TIMEPERFRAME; + } + + return 0; +} diff --git a/drivers/media/platform/qcom/iris/iris_venc.h b/drivers/media/p= latform/qcom/iris/iris_venc.h index 72c6e25d87113baa6d2219ae478b7d7df1aed7bf..0d566b7fc89b96b8fbc62a35b2b= a795ca0bcf460 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.h +++ b/drivers/media/platform/qcom/iris/iris_venc.h @@ -16,5 +16,7 @@ int iris_venc_s_fmt(struct iris_inst *inst, struct v4l2_f= ormat *f); int iris_venc_validate_format(struct iris_inst *inst, u32 pixelformat); int iris_venc_subscribe_event(struct iris_inst *inst, const struct v4l2_ev= ent_subscription *sub); int iris_venc_s_selection(struct iris_inst *inst, struct v4l2_selection *s= ); +int iris_venc_g_param(struct iris_inst *inst, struct v4l2_streamparm *s_pa= rm); +int iris_venc_s_param(struct iris_inst *inst, struct v4l2_streamparm *s_pa= rm); =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/p= latform/qcom/iris/iris_vidc.c index b134ae710d9e1d02bc52db2e9356fdc4f668a387..6e3bd02afe44534a8f36cc22d9c= 8cda4a53a05cd 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -530,6 +530,34 @@ static int iris_subscribe_event(struct v4l2_fh *fh, co= nst struct v4l2_event_subs return -EINVAL; } =20 +static int iris_s_parm(struct file *filp, void *fh, struct v4l2_streamparm= *a) +{ + struct iris_inst *inst =3D container_of(fh, struct iris_inst, fh); + + if (a->type !=3D V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE && + a->type !=3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) + return -EINVAL; + + if (inst->domain =3D=3D ENCODER) + return iris_venc_s_param(inst, a); + else + return -EINVAL; +} + +static int iris_g_parm(struct file *filp, void *fh, struct v4l2_streamparm= *a) +{ + struct iris_inst *inst =3D container_of(fh, struct iris_inst, fh); + + if (a->type !=3D V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE && + a->type !=3D V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) + return -EINVAL; + + if (inst->domain =3D=3D ENCODER) + return iris_venc_g_param(inst, a); + else + return -EINVAL; +} + static int iris_dec_cmd(struct file *filp, void *fh, struct v4l2_decoder_cmd *dec) { @@ -626,6 +654,8 @@ static const struct v4l2_ioctl_ops iris_v4l2_ioctl_ops_= enc =3D { .vidioc_unsubscribe_event =3D v4l2_event_unsubscribe, .vidioc_g_selection =3D iris_g_selection, .vidioc_s_selection =3D iris_s_selection, + .vidioc_s_parm =3D iris_s_parm, + .vidioc_g_parm =3D iris_g_parm, }; =20 void iris_init_ops(struct iris_core *core) --=20 2.34.1 From nobody Fri Oct 3 20:48:35 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 591A92BE7A3; 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This enables proper configuration and handling of encoder-specific features based on platform requirements. Co-developed-by: Wangao Wang Signed-off-by: Wangao Wang Tested-by: Vikash Garodia # X1E80100 Reviewed-by: Vikash Garodia Tested-by: Neil Armstrong # on SM8550-HDK Tested-by: Neil Armstrong # on SM8650-HDK Signed-off-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e80100-crd --- drivers/media/platform/qcom/iris/iris_core.h | 7 +- drivers/media/platform/qcom/iris/iris_ctrls.c | 175 +++++++++- .../platform/qcom/iris/iris_hfi_gen1_defines.h | 7 + .../platform/qcom/iris/iris_hfi_gen2_defines.h | 9 + .../platform/qcom/iris/iris_platform_common.h | 43 ++- .../media/platform/qcom/iris/iris_platform_gen2.c | 385 +++++++++++++++++= +++- .../platform/qcom/iris/iris_platform_qcs8300.h | 350 +++++++++++++++++= +- .../platform/qcom/iris/iris_platform_sm8250.c | 185 +++++++++- drivers/media/platform/qcom/iris/iris_vdec.c | 2 +- drivers/media/platform/qcom/iris/iris_venc.c | 7 +- 10 files changed, 1140 insertions(+), 30 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/p= latform/qcom/iris/iris_core.h index 827aee8dcec3ee17af5a90f5594b9315f663c0b3..fb194c967ad4f9b5e00cd74f0d4= 1e0b827ef14db 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -71,7 +71,8 @@ enum domain_type { * @intr_status: interrupt status * @sys_error_handler: a delayed work for handling system fatal error * @instances: a list_head of all instances - * @inst_fw_caps: an array of supported instance capabilities + * @inst_fw_caps_dec: an array of supported instance capabilities by decod= er + * @inst_fw_caps_enc: an array of supported instance capabilities by encod= er */ =20 struct iris_core { @@ -113,7 +114,9 @@ struct iris_core { u32 intr_status; struct delayed_work sys_error_handler; struct list_head instances; - struct platform_inst_fw_cap inst_fw_caps[INST_FW_CAP_MAX]; + /* encoder and decoder have overlapping caps, so two different arrays are= required */ + struct platform_inst_fw_cap inst_fw_caps_dec[INST_FW_CAP_MAX]; + struct platform_inst_fw_cap inst_fw_caps_enc[INST_FW_CAP_MAX]; }; =20 int iris_core_init(struct iris_core *core); diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/= platform/qcom/iris/iris_ctrls.c index 9136b723c0f2a3d5833af32ae2735ccdb244f60f..797386cb96ab1d24be6cc1819e2= f9202ab4cc224 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.c +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c @@ -31,6 +31,68 @@ static enum platform_inst_fw_cap_type iris_get_cap_id(u3= 2 id) return LEVEL_VP9; case V4L2_CID_MPEG_VIDEO_HEVC_TIER: return TIER; + case V4L2_CID_MPEG_VIDEO_HEADER_MODE: + return HEADER_MODE; + case V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR: + return PREPEND_SPSPPS_TO_IDR; + case V4L2_CID_MPEG_VIDEO_BITRATE: + return BITRATE; + case V4L2_CID_MPEG_VIDEO_BITRATE_PEAK: + return BITRATE_PEAK; + case V4L2_CID_MPEG_VIDEO_BITRATE_MODE: + return BITRATE_MODE; + case V4L2_CID_MPEG_VIDEO_FRAME_SKIP_MODE: + return FRAME_SKIP_MODE; + case V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE: + return FRAME_RC_ENABLE; + case V4L2_CID_MPEG_VIDEO_GOP_SIZE: + return GOP_SIZE; + case V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE: + return ENTROPY_MODE; + case V4L2_CID_MPEG_VIDEO_H264_MIN_QP: + return MIN_FRAME_QP_H264; + case V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP: + return MIN_FRAME_QP_HEVC; + case V4L2_CID_MPEG_VIDEO_H264_MAX_QP: + return MAX_FRAME_QP_H264; + case V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP: + return MAX_FRAME_QP_HEVC; + case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP: + return I_FRAME_MIN_QP_H264; + case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MIN_QP: + return I_FRAME_MIN_QP_HEVC; + case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP: + return P_FRAME_MIN_QP_H264; + case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MIN_QP: + return P_FRAME_MIN_QP_HEVC; + case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP: + return B_FRAME_MIN_QP_H264; + case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MIN_QP: + return B_FRAME_MIN_QP_HEVC; + case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP: + return I_FRAME_MAX_QP_H264; + case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MAX_QP: + return I_FRAME_MAX_QP_HEVC; + case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP: + return P_FRAME_MAX_QP_H264; + case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MAX_QP: + return P_FRAME_MAX_QP_HEVC; + case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP: + return B_FRAME_MAX_QP_H264; + case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MAX_QP: + return B_FRAME_MAX_QP_HEVC; + case V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP: + return I_FRAME_QP_H264; + case V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP: + return I_FRAME_QP_HEVC; + case V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP: + return P_FRAME_QP_H264; + case V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP: + return P_FRAME_QP_HEVC; + case V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP: + return B_FRAME_QP_H264; + case V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP: + return B_FRAME_QP_HEVC; default: return INST_FW_CAP_MAX; } @@ -56,6 +118,68 @@ static u32 iris_get_v4l2_id(enum platform_inst_fw_cap_t= ype cap_id) return V4L2_CID_MPEG_VIDEO_VP9_LEVEL; case TIER: return V4L2_CID_MPEG_VIDEO_HEVC_TIER; + case HEADER_MODE: + return V4L2_CID_MPEG_VIDEO_HEADER_MODE; + case PREPEND_SPSPPS_TO_IDR: + return V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR; + case BITRATE: + return V4L2_CID_MPEG_VIDEO_BITRATE; + case BITRATE_PEAK: + return V4L2_CID_MPEG_VIDEO_BITRATE_PEAK; + case BITRATE_MODE: + return V4L2_CID_MPEG_VIDEO_BITRATE_MODE; + case FRAME_SKIP_MODE: + return V4L2_CID_MPEG_VIDEO_FRAME_SKIP_MODE; + case FRAME_RC_ENABLE: + return V4L2_CID_MPEG_VIDEO_FRAME_RC_ENABLE; + case GOP_SIZE: + return V4L2_CID_MPEG_VIDEO_GOP_SIZE; + case ENTROPY_MODE: + return V4L2_CID_MPEG_VIDEO_H264_ENTROPY_MODE; + case MIN_FRAME_QP_H264: + return V4L2_CID_MPEG_VIDEO_H264_MIN_QP; + case MIN_FRAME_QP_HEVC: + return V4L2_CID_MPEG_VIDEO_HEVC_MIN_QP; + case MAX_FRAME_QP_H264: + return V4L2_CID_MPEG_VIDEO_H264_MAX_QP; + case MAX_FRAME_QP_HEVC: + return V4L2_CID_MPEG_VIDEO_HEVC_MAX_QP; + case I_FRAME_MIN_QP_H264: + return V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP; + case I_FRAME_MIN_QP_HEVC: + return V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MIN_QP; + case P_FRAME_MIN_QP_H264: + return V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP; + case P_FRAME_MIN_QP_HEVC: + return V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MIN_QP; + case B_FRAME_MIN_QP_H264: + return V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MIN_QP; + case B_FRAME_MIN_QP_HEVC: + return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MIN_QP; + case I_FRAME_MAX_QP_H264: + return V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MAX_QP; + case I_FRAME_MAX_QP_HEVC: + return V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_MAX_QP; + case P_FRAME_MAX_QP_H264: + return V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MAX_QP; + case P_FRAME_MAX_QP_HEVC: + return V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_MAX_QP; + case B_FRAME_MAX_QP_H264: + return V4L2_CID_MPEG_VIDEO_H264_B_FRAME_MAX_QP; + case B_FRAME_MAX_QP_HEVC: + return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_MAX_QP; + case I_FRAME_QP_H264: + return V4L2_CID_MPEG_VIDEO_H264_I_FRAME_QP; + case I_FRAME_QP_HEVC: + return V4L2_CID_MPEG_VIDEO_HEVC_I_FRAME_QP; + case P_FRAME_QP_H264: + return V4L2_CID_MPEG_VIDEO_H264_P_FRAME_QP; + case P_FRAME_QP_HEVC: + return V4L2_CID_MPEG_VIDEO_HEVC_P_FRAME_QP; + case B_FRAME_QP_H264: + return V4L2_CID_MPEG_VIDEO_H264_B_FRAME_QP; + case B_FRAME_QP_HEVC: + return V4L2_CID_MPEG_VIDEO_HEVC_B_FRAME_QP; default: return 0; } @@ -101,7 +225,10 @@ int iris_ctrls_init(struct iris_inst *inst) num_ctrls++; } =20 - /* Adding 1 to num_ctrls to include V4L2_CID_MIN_BUFFERS_FOR_CAPTURE */ + /* Adding 1 to num_ctrls to include + * V4L2_CID_MIN_BUFFERS_FOR_CAPTURE for decoder and + * V4L2_CID_MIN_BUFFERS_FOR_OUTPUT for encoder + */ =20 ret =3D v4l2_ctrl_handler_init(&inst->ctrl_handler, num_ctrls + 1); if (ret) @@ -143,8 +270,13 @@ int iris_ctrls_init(struct iris_inst *inst) ctrl_idx++; } =20 - v4l2_ctrl_new_std(&inst->ctrl_handler, NULL, - V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, 1, 32, 1, 4); + if (inst->domain =3D=3D DECODER) { + v4l2_ctrl_new_std(&inst->ctrl_handler, NULL, + V4L2_CID_MIN_BUFFERS_FOR_CAPTURE, 1, 32, 1, 4); + } else { + v4l2_ctrl_new_std(&inst->ctrl_handler, NULL, + V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, 1, 32, 1, 4); + } =20 ret =3D inst->ctrl_handler.error; if (ret) @@ -162,22 +294,39 @@ void iris_session_init_caps(struct iris_core *core) struct platform_inst_fw_cap *caps; u32 i, num_cap, cap_id; =20 - caps =3D core->iris_platform_data->inst_fw_caps; - num_cap =3D core->iris_platform_data->inst_fw_caps_size; + caps =3D core->iris_platform_data->inst_fw_caps_dec; + num_cap =3D core->iris_platform_data->inst_fw_caps_dec_size; + + for (i =3D 0; i < num_cap; i++) { + cap_id =3D caps[i].cap_id; + if (!iris_valid_cap_id(cap_id)) + continue; + + core->inst_fw_caps_dec[cap_id].cap_id =3D caps[i].cap_id; + core->inst_fw_caps_dec[cap_id].min =3D caps[i].min; + core->inst_fw_caps_dec[cap_id].max =3D caps[i].max; + core->inst_fw_caps_dec[cap_id].step_or_mask =3D caps[i].step_or_mask; + core->inst_fw_caps_dec[cap_id].value =3D caps[i].value; + core->inst_fw_caps_dec[cap_id].flags =3D caps[i].flags; + core->inst_fw_caps_dec[cap_id].hfi_id =3D caps[i].hfi_id; + core->inst_fw_caps_dec[cap_id].set =3D caps[i].set; + } + + caps =3D core->iris_platform_data->inst_fw_caps_enc; + num_cap =3D core->iris_platform_data->inst_fw_caps_enc_size; =20 for (i =3D 0; i < num_cap; i++) { cap_id =3D caps[i].cap_id; if (!iris_valid_cap_id(cap_id)) continue; =20 - core->inst_fw_caps[cap_id].cap_id =3D caps[i].cap_id; - core->inst_fw_caps[cap_id].min =3D caps[i].min; - core->inst_fw_caps[cap_id].max =3D caps[i].max; - core->inst_fw_caps[cap_id].step_or_mask =3D caps[i].step_or_mask; - core->inst_fw_caps[cap_id].value =3D caps[i].value; - core->inst_fw_caps[cap_id].flags =3D caps[i].flags; - core->inst_fw_caps[cap_id].hfi_id =3D caps[i].hfi_id; - core->inst_fw_caps[cap_id].set =3D caps[i].set; + core->inst_fw_caps_enc[cap_id].cap_id =3D caps[i].cap_id; + core->inst_fw_caps_enc[cap_id].min =3D caps[i].min; + core->inst_fw_caps_enc[cap_id].max =3D caps[i].max; + core->inst_fw_caps_enc[cap_id].step_or_mask =3D caps[i].step_or_mask; + core->inst_fw_caps_enc[cap_id].value =3D caps[i].value; + core->inst_fw_caps_enc[cap_id].flags =3D caps[i].flags; + core->inst_fw_caps_enc[cap_id].hfi_id =3D caps[i].hfi_id; } } =20 diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_defines.h index 5b7c641b727a16c3aa7196a6d49786133653279f..a7f4379c5973fdc4366969139be= f25472e8f11a5 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h @@ -121,6 +121,13 @@ #define HFI_UNUSED_PICT 0x10000000 #define HFI_BUFFERFLAG_DATACORRUPT 0x00000008 #define HFI_BUFFERFLAG_DROP_FRAME 0x20000000 +#define HFI_PROPERTY_PARAM_VENC_H264_ENTROPY_CONTROL 0x2005002 +#define HFI_PROPERTY_PARAM_VENC_H264_DEBLOCK_CONTROL 0x2005003 +#define HFI_PROPERTY_PARAM_VENC_RATE_CONTROL 0x2005004 +#define HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2 0x2005009 +#define HFI_PROPERTY_PARAM_VENC_MAX_NUM_B_FRAMES 0x2005020 +#define HFI_PROPERTY_CONFIG_VENC_TARGET_BITRATE 0x2006001 +#define HFI_PROPERTY_CONFIG_VENC_SYNC_FRAME_SEQUENCE_HEADER 0x2006008 =20 struct hfi_pkt_hdr { u32 size; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_defines.h index 5f13dc11bea532600cc9b15db57e8981a1f3eb93..fb6724d7f95ff8858aa9ba093fe= fb642e89de279 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h @@ -55,12 +55,21 @@ #define HFI_PROP_BUFFER_HOST_MAX_COUNT 0x03000123 #define HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT 0x03000124 #define HFI_PROP_PIC_ORDER_CNT_TYPE 0x03000128 +#define HFI_PROP_RATE_CONTROL 0x0300012a +#define HFI_PROP_QP_PACKED 0x0300012e +#define HFI_PROP_MIN_QP_PACKED 0x0300012f +#define HFI_PROP_MAX_QP_PACKED 0x03000130 +#define HFI_PROP_TOTAL_BITRATE 0x0300013b +#define HFI_PROP_MAX_GOP_FRAMES 0x03000146 +#define HFI_PROP_MAX_B_FRAMES 0x03000147 #define HFI_PROP_QUALITY_MODE 0x03000148 +#define HFI_PROP_SEQ_HEADER_MODE 0x03000149 #define HFI_PROP_SIGNAL_COLOR_INFO 0x03000155 #define HFI_PROP_PICTURE_TYPE 0x03000162 #define HFI_PROP_DEC_DEFAULT_HEADER 0x03000168 #define HFI_PROP_DEC_START_FROM_RAP_FRAME 0x03000169 #define HFI_PROP_NO_OUTPUT 0x0300016a +#define HFI_PROP_TOTAL_PEAK_BITRATE 0x0300017C #define HFI_PROP_COMV_BUFFER_COUNT 0x03000193 #define HFI_PROP_END 0x03FFFFFF =20 diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index d0b84c93aef409b51a767ba11f91c6ce2533f27f..6d6a8f3b38271d928d753dd180e= 6e9a991991d24 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -23,6 +23,11 @@ struct iris_inst; #define DEFAULT_FPS 30 #define MAXIMUM_FPS 480 #define NUM_MBS_8K ((8192 * 4352) / 256) +#define MIN_QP_8BIT 1 +#define MAX_QP 51 +#define MAX_QP_HEVC 63 +#define DEFAULT_QP 20 +#define BITRATE_DEFAULT 20000000 =20 enum stage_type { STAGE_1 =3D 1, @@ -91,6 +96,7 @@ enum platform_inst_fw_cap_type { LEVEL_HEVC, LEVEL_VP9, INPUT_BUF_HOST_MAX_COUNT, + OUTPUT_BUF_HOST_MAX_COUNT, STAGE, PIPE, POC, @@ -98,6 +104,37 @@ enum platform_inst_fw_cap_type { BIT_DEPTH, RAP_FRAME, TIER, + HEADER_MODE, + PREPEND_SPSPPS_TO_IDR, + BITRATE, + BITRATE_PEAK, + BITRATE_MODE, + FRAME_SKIP_MODE, + FRAME_RC_ENABLE, + GOP_SIZE, + ENTROPY_MODE, + MIN_FRAME_QP_H264, + MIN_FRAME_QP_HEVC, + MAX_FRAME_QP_H264, + MAX_FRAME_QP_HEVC, + I_FRAME_MIN_QP_H264, + I_FRAME_MIN_QP_HEVC, + P_FRAME_MIN_QP_H264, + P_FRAME_MIN_QP_HEVC, + B_FRAME_MIN_QP_H264, + B_FRAME_MIN_QP_HEVC, + I_FRAME_MAX_QP_H264, + I_FRAME_MAX_QP_HEVC, + P_FRAME_MAX_QP_H264, + P_FRAME_MAX_QP_HEVC, + B_FRAME_MAX_QP_H264, + B_FRAME_MAX_QP_HEVC, + I_FRAME_QP_H264, + I_FRAME_QP_HEVC, + P_FRAME_QP_H264, + P_FRAME_QP_HEVC, + B_FRAME_QP_H264, + B_FRAME_QP_HEVC, INST_FW_CAP_MAX, }; =20 @@ -172,8 +209,10 @@ struct iris_platform_data { const char *fwname; u32 pas_id; struct platform_inst_caps *inst_caps; - struct platform_inst_fw_cap *inst_fw_caps; - u32 inst_fw_caps_size; + struct platform_inst_fw_cap *inst_fw_caps_dec; + u32 inst_fw_caps_dec_size; + struct platform_inst_fw_cap *inst_fw_caps_enc; + u32 inst_fw_caps_enc_size; struct tz_cp_config *tz_cp_config_data; u32 core_arch; u32 hw_response_timeout; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index a245fce04b3a901cf2eb06fb35c15c0176199c11..4b98c149dc627f37930e6b98e4a= da407f6ba637f 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -14,8 +14,9 @@ #include "iris_platform_sm8650.h" =20 #define VIDEO_ARCH_LX 1 +#define BITRATE_MAX 245000000 =20 -static struct platform_inst_fw_cap inst_fw_cap_sm8550[] =3D { +static struct platform_inst_fw_cap inst_fw_cap_sm8550_dec[] =3D { { .cap_id =3D PROFILE_H264, .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, @@ -199,6 +200,370 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550= [] =3D { }, }; =20 +static struct platform_inst_fw_cap inst_fw_cap_sm8550_enc[] =3D { + { + .cap_id =3D PROFILE_H264, + .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, + .max =3D V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH), + .value =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + .hfi_id =3D HFI_PROP_PROFILE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D PROFILE_HEVC, + .min =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE) | + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10), + .value =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .hfi_id =3D HFI_PROP_PROFILE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D LEVEL_H264, + .min =3D V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + .max =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_0, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0), + .value =3D V4L2_MPEG_VIDEO_H264_LEVEL_5_0, + .hfi_id =3D HFI_PROP_LEVEL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D LEVEL_HEVC, + .min =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + .max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2), + .value =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5, + .hfi_id =3D HFI_PROP_LEVEL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D STAGE, + .min =3D STAGE_1, + .max =3D STAGE_2, + .step_or_mask =3D 1, + .value =3D STAGE_2, + .hfi_id =3D HFI_PROP_STAGE, + }, + { + .cap_id =3D HEADER_MODE, + .min =3D V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE, + .max =3D V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) | + BIT(V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME), + .value =3D V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, + .hfi_id =3D HFI_PROP_SEQ_HEADER_MODE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D PREPEND_SPSPPS_TO_IDR, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 0, + }, + { + .cap_id =3D BITRATE, + .min =3D 1, + .max =3D BITRATE_MAX, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT, + .hfi_id =3D HFI_PROP_TOTAL_BITRATE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + }, + { + .cap_id =3D BITRATE_PEAK, + .min =3D 1, + .max =3D BITRATE_MAX, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT, + .hfi_id =3D HFI_PROP_TOTAL_PEAK_BITRATE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + }, + { + .cap_id =3D BITRATE_MODE, + .min =3D V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, + .max =3D V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) | + BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CBR), + .value =3D V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, + .hfi_id =3D HFI_PROP_RATE_CONTROL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D FRAME_SKIP_MODE, + .min =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED, + .max =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED) | + BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT) | + BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT), + .value =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D FRAME_RC_ENABLE, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 1, + }, + { + .cap_id =3D GOP_SIZE, + .min =3D 0, + .max =3D INT_MAX, + .step_or_mask =3D 1, + .value =3D 2 * DEFAULT_FPS - 1, + .hfi_id =3D HFI_PROP_MAX_GOP_FRAMES, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + }, + { + .cap_id =3D ENTROPY_MODE, + .min =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC, + .max =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) | + BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC), + .value =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, + .hfi_id =3D HFI_PROP_CABAC_SESSION, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D MIN_FRAME_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT, + .hfi_id =3D HFI_PROP_MIN_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT, + }, + { + .cap_id =3D MIN_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT, + .hfi_id =3D HFI_PROP_MIN_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT, + }, + { + .cap_id =3D MAX_FRAME_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + .hfi_id =3D HFI_PROP_MAX_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT, + }, + { + .cap_id =3D MAX_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + .hfi_id =3D HFI_PROP_MAX_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT, + }, + { + .cap_id =3D I_FRAME_MIN_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT, + }, + { + .cap_id =3D I_FRAME_MIN_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT, + }, + { + .cap_id =3D P_FRAME_MIN_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT, + }, + { + .cap_id =3D P_FRAME_MIN_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT, + }, + { + .cap_id =3D B_FRAME_MIN_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT, + }, + { + .cap_id =3D B_FRAME_MIN_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT, + }, + { + .cap_id =3D I_FRAME_MAX_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D I_FRAME_MAX_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D P_FRAME_MAX_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D P_FRAME_MAX_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D B_FRAME_MAX_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D B_FRAME_MAX_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D I_FRAME_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + }, + { + .cap_id =3D I_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + }, + { + .cap_id =3D P_FRAME_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + }, + { + .cap_id =3D P_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + }, + { + .cap_id =3D B_FRAME_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + }, + { + .cap_id =3D B_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + }, + { + .cap_id =3D INPUT_BUF_HOST_MAX_COUNT, + .min =3D DEFAULT_MAX_HOST_BUF_COUNT, + .max =3D DEFAULT_MAX_HOST_BURST_BUF_COUNT, + .step_or_mask =3D 1, + .value =3D DEFAULT_MAX_HOST_BUF_COUNT, + .hfi_id =3D HFI_PROP_BUFFER_HOST_MAX_COUNT, + .flags =3D CAP_FLAG_INPUT_PORT, + }, + { + .cap_id =3D OUTPUT_BUF_HOST_MAX_COUNT, + .min =3D DEFAULT_MAX_HOST_BUF_COUNT, + .max =3D DEFAULT_MAX_HOST_BURST_BUF_COUNT, + .step_or_mask =3D 1, + .value =3D DEFAULT_MAX_HOST_BUF_COUNT, + .hfi_id =3D HFI_PROP_BUFFER_HOST_MAX_COUNT, + .flags =3D CAP_FLAG_OUTPUT_PORT, + }, +}; + static struct platform_inst_caps platform_inst_cap_sm8550 =3D { .min_frame_width =3D 96, .max_frame_width =3D 8192, @@ -347,8 +712,10 @@ struct iris_platform_data sm8550_data =3D { .fwname =3D "qcom/vpu/vpu30_p4.mbn", .pas_id =3D IRIS_PAS_ID, .inst_caps =3D &platform_inst_cap_sm8550, - .inst_fw_caps =3D inst_fw_cap_sm8550, - .inst_fw_caps_size =3D ARRAY_SIZE(inst_fw_cap_sm8550), + .inst_fw_caps_dec =3D inst_fw_cap_sm8550_dec, + .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_dec), + .inst_fw_caps_enc =3D inst_fw_cap_sm8550_enc, + .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_enc), .tz_cp_config_data =3D &tz_cp_config_sm8550, .core_arch =3D VIDEO_ARCH_LX, .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, @@ -423,8 +790,10 @@ struct iris_platform_data sm8650_data =3D { .fwname =3D "qcom/vpu/vpu33_p4.mbn", .pas_id =3D IRIS_PAS_ID, .inst_caps =3D &platform_inst_cap_sm8550, - .inst_fw_caps =3D inst_fw_cap_sm8550, - .inst_fw_caps_size =3D ARRAY_SIZE(inst_fw_cap_sm8550), + .inst_fw_caps_dec =3D inst_fw_cap_sm8550_dec, + .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_dec), + .inst_fw_caps_enc =3D inst_fw_cap_sm8550_enc, + .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8550_enc), .tz_cp_config_data =3D &tz_cp_config_sm8550, .core_arch =3D VIDEO_ARCH_LX, .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, @@ -495,8 +864,10 @@ struct iris_platform_data qcs8300_data =3D { .fwname =3D "qcom/vpu/vpu30_p4_s6.mbn", .pas_id =3D IRIS_PAS_ID, .inst_caps =3D &platform_inst_cap_qcs8300, - .inst_fw_caps =3D inst_fw_cap_qcs8300, - .inst_fw_caps_size =3D ARRAY_SIZE(inst_fw_cap_qcs8300), + .inst_fw_caps_dec =3D inst_fw_cap_qcs8300_dec, + .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_qcs8300_dec), + .inst_fw_caps_enc =3D inst_fw_cap_qcs8300_enc, + .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_qcs8300_enc), .tz_cp_config_data =3D &tz_cp_config_sm8550, .core_arch =3D VIDEO_ARCH_LX, .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, diff --git a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h b/dri= vers/media/platform/qcom/iris/iris_platform_qcs8300.h index 64331b705fca541e0547afc01ec108759529c9d8..35ea0efade73caa687d300779c5= b1dc3b17a0128 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h +++ b/drivers/media/platform/qcom/iris/iris_platform_qcs8300.h @@ -3,7 +3,9 @@ * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights res= erved. */ =20 -static struct platform_inst_fw_cap inst_fw_cap_qcs8300[] =3D { +#define BITRATE_MAX 245000000 + +static struct platform_inst_fw_cap inst_fw_cap_qcs8300_dec[] =3D { { .cap_id =3D PROFILE_H264, .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, @@ -187,6 +189,352 @@ static struct platform_inst_fw_cap inst_fw_cap_qcs830= 0[] =3D { }, }; =20 +static struct platform_inst_fw_cap inst_fw_cap_qcs8300_enc[] =3D { + { + .cap_id =3D PROFILE_H264, + .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, + .max =3D V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH), + .value =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + .hfi_id =3D HFI_PROP_PROFILE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D PROFILE_HEVC, + .min =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE) | + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10), + .value =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .hfi_id =3D HFI_PROP_PROFILE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D LEVEL_H264, + .min =3D V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + .max =3D V4L2_MPEG_VIDEO_H264_LEVEL_6_0, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_6_0), + .value =3D V4L2_MPEG_VIDEO_H264_LEVEL_5_0, + .hfi_id =3D HFI_PROP_LEVEL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D LEVEL_HEVC, + .min =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + .max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2), + .value =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5, + .hfi_id =3D HFI_PROP_LEVEL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D STAGE, + .min =3D STAGE_1, + .max =3D STAGE_2, + .step_or_mask =3D 1, + .value =3D STAGE_2, + .hfi_id =3D HFI_PROP_STAGE, + }, + { + .cap_id =3D HEADER_MODE, + .min =3D V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE, + .max =3D V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) | + BIT(V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME), + .value =3D V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, + .hfi_id =3D HFI_PROP_SEQ_HEADER_MODE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D PREPEND_SPSPPS_TO_IDR, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 0, + }, + { + .cap_id =3D BITRATE, + .min =3D 1, + .max =3D BITRATE_MAX, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT, + .hfi_id =3D HFI_PROP_TOTAL_BITRATE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + }, + { + .cap_id =3D BITRATE_PEAK, + .min =3D 1, + .max =3D BITRATE_MAX, + .step_or_mask =3D 1, + .value =3D BITRATE_DEFAULT, + .hfi_id =3D HFI_PROP_TOTAL_PEAK_BITRATE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + }, + { + .cap_id =3D BITRATE_MODE, + .min =3D V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, + .max =3D V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) | + BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CBR), + .value =3D V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, + .hfi_id =3D HFI_PROP_RATE_CONTROL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D FRAME_SKIP_MODE, + .min =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED, + .max =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED) | + BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_LEVEL_LIMIT) | + BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT), + .value =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D FRAME_RC_ENABLE, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 1, + }, + { + .cap_id =3D GOP_SIZE, + .min =3D 0, + .max =3D INT_MAX, + .step_or_mask =3D 1, + .value =3D 2 * DEFAULT_FPS - 1, + .hfi_id =3D HFI_PROP_MAX_GOP_FRAMES, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + }, + { + .cap_id =3D ENTROPY_MODE, + .min =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC, + .max =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) | + BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC), + .value =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, + .hfi_id =3D HFI_PROP_CABAC_SESSION, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D MIN_FRAME_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT, + .hfi_id =3D HFI_PROP_MIN_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT, + }, + { + .cap_id =3D MIN_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT, + .hfi_id =3D HFI_PROP_MIN_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT, + }, + { + .cap_id =3D MAX_FRAME_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + .hfi_id =3D HFI_PROP_MAX_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT, + }, + { + .cap_id =3D MAX_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + .hfi_id =3D HFI_PROP_MAX_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT, + }, + { + .cap_id =3D I_FRAME_MIN_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT, + }, + { + .cap_id =3D I_FRAME_MIN_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT, + }, + { + .cap_id =3D P_FRAME_MIN_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT, + }, + { + .cap_id =3D P_FRAME_MIN_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT, + }, + { + .cap_id =3D B_FRAME_MIN_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT, + }, + { + .cap_id =3D B_FRAME_MIN_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT, + }, + { + .cap_id =3D I_FRAME_MAX_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D I_FRAME_MAX_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D P_FRAME_MAX_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D P_FRAME_MAX_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D B_FRAME_MAX_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D B_FRAME_MAX_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + }, + { + .cap_id =3D I_FRAME_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + }, + { + .cap_id =3D I_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + }, + { + .cap_id =3D P_FRAME_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + }, + { + .cap_id =3D P_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + }, + { + .cap_id =3D B_FRAME_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + }, + { + .cap_id =3D B_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D DEFAULT_QP, + .hfi_id =3D HFI_PROP_QP_PACKED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + }, +}; + static struct platform_inst_caps platform_inst_cap_qcs8300 =3D { .min_frame_width =3D 96, .max_frame_width =3D 4096, diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/driv= ers/media/platform/qcom/iris/iris_platform_sm8250.c index 4ff72109c6001cc47d746d366f458c0ff0a8924a..49947d8c58a94cc6caf7e10ca03= 93dd733e27919 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c @@ -11,7 +11,12 @@ #include "iris_hfi_gen1_defines.h" #include "iris_vpu_common.h" =20 -static struct platform_inst_fw_cap inst_fw_cap_sm8250[] =3D { +#define BITRATE_MIN 32000 +#define BITRATE_MAX 160000000 +#define BITRATE_PEAK_DEFAULT (BITRATE_DEFAULT * 2) +#define BITRATE_STEP 100 + +static struct platform_inst_fw_cap inst_fw_cap_sm8250_dec[] =3D { { .cap_id =3D PIPE, .min =3D PIPE_1, @@ -32,6 +37,178 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8250[]= =3D { }, }; =20 +static struct platform_inst_fw_cap inst_fw_cap_sm8250_enc[] =3D { + { + .cap_id =3D PROFILE_H264, + .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, + .max =3D V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_HIGH) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_STEREO_HIGH) | + BIT(V4L2_MPEG_VIDEO_H264_PROFILE_MULTIVIEW_HIGH), + .value =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, + .hfi_id =3D HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D PROFILE_HEVC, + .min =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .max =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN) | + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_STILL_PICTURE) | + BIT(V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10), + .value =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, + .hfi_id =3D HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D LEVEL_H264, + .min =3D V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + .max =3D V4L2_MPEG_VIDEO_H264_LEVEL_5_1, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1B) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_1_3) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_2_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_3_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_4_2) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_0) | + BIT(V4L2_MPEG_VIDEO_H264_LEVEL_5_1), + .value =3D V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + .hfi_id =3D HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D LEVEL_HEVC, + .min =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + .max =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_2_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_3_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_4_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_5_2) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_1) | + BIT(V4L2_MPEG_VIDEO_HEVC_LEVEL_6_2), + .value =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_1, + .hfi_id =3D HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D HEADER_MODE, + .min =3D V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE, + .max =3D V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) | + BIT(V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME), + .value =3D V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, + .hfi_id =3D HFI_PROPERTY_CONFIG_VENC_SYNC_FRAME_SEQUENCE_HEADER, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D BITRATE, + .min =3D BITRATE_MIN, + .max =3D BITRATE_MAX, + .step_or_mask =3D BITRATE_STEP, + .value =3D BITRATE_DEFAULT, + .hfi_id =3D HFI_PROPERTY_CONFIG_VENC_TARGET_BITRATE, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | + CAP_FLAG_DYNAMIC_ALLOWED, + }, + { + .cap_id =3D BITRATE_MODE, + .min =3D V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, + .max =3D V4L2_MPEG_VIDEO_BITRATE_MODE_CBR, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) | + BIT(V4L2_MPEG_VIDEO_BITRATE_MODE_CBR), + .value =3D V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, + .hfi_id =3D HFI_PROPERTY_PARAM_VENC_RATE_CONTROL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D FRAME_SKIP_MODE, + .min =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED, + .max =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED) | + BIT(V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT), + .value =3D V4L2_MPEG_VIDEO_FRAME_SKIP_MODE_DISABLED, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D FRAME_RC_ENABLE, + .min =3D 0, + .max =3D 1, + .step_or_mask =3D 1, + .value =3D 1, + }, + { + .cap_id =3D GOP_SIZE, + .min =3D 0, + .max =3D (1 << 16) - 1, + .step_or_mask =3D 1, + .value =3D 30, + }, + { + .cap_id =3D ENTROPY_MODE, + .min =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC, + .max =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, + .step_or_mask =3D BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) | + BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC), + .value =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC, + .hfi_id =3D HFI_PROPERTY_PARAM_VENC_H264_ENTROPY_CONTROL, + .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + }, + { + .cap_id =3D MIN_FRAME_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT, + .hfi_id =3D HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2, + .flags =3D CAP_FLAG_OUTPUT_PORT, + }, + { + .cap_id =3D MIN_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP_HEVC, + .step_or_mask =3D 1, + .value =3D MIN_QP_8BIT, + .hfi_id =3D HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2, + .flags =3D CAP_FLAG_OUTPUT_PORT, + }, + { + .cap_id =3D MAX_FRAME_QP_H264, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP, + .step_or_mask =3D 1, + .value =3D MAX_QP, + .hfi_id =3D HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2, + .flags =3D CAP_FLAG_OUTPUT_PORT, + }, + { + .cap_id =3D MAX_FRAME_QP_HEVC, + .min =3D MIN_QP_8BIT, + .max =3D MAX_QP_HEVC, + .step_or_mask =3D 1, + .value =3D MAX_QP_HEVC, + .hfi_id =3D HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2, + .flags =3D CAP_FLAG_OUTPUT_PORT, + }, +}; + static struct platform_inst_caps platform_inst_cap_sm8250 =3D { .min_frame_width =3D 128, .max_frame_width =3D 8192, @@ -123,8 +300,10 @@ struct iris_platform_data sm8250_data =3D { .fwname =3D "qcom/vpu-1.0/venus.mbn", .pas_id =3D IRIS_PAS_ID, .inst_caps =3D &platform_inst_cap_sm8250, - .inst_fw_caps =3D inst_fw_cap_sm8250, - .inst_fw_caps_size =3D ARRAY_SIZE(inst_fw_cap_sm8250), + .inst_fw_caps_dec =3D inst_fw_cap_sm8250_dec, + .inst_fw_caps_dec_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_dec), + .inst_fw_caps_enc =3D inst_fw_cap_sm8250_enc, + .inst_fw_caps_enc_size =3D ARRAY_SIZE(inst_fw_cap_sm8250_enc), .tz_cp_config_data =3D &tz_cp_config_sm8250, .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, .num_vpp_pipe =3D 4, diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/p= latform/qcom/iris/iris_vdec.c index f1bc928043acea9aae7bbb960448adec9e7a4880..338c7524c19de8456f0f2b0286b= afcd89be52b72 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.c +++ b/drivers/media/platform/qcom/iris/iris_vdec.c @@ -54,7 +54,7 @@ int iris_vdec_inst_init(struct iris_inst *inst) inst->buffers[BUF_OUTPUT].min_count =3D iris_vpu_buf_count(inst, BUF_OUTP= UT); inst->buffers[BUF_OUTPUT].size =3D f->fmt.pix_mp.plane_fmt[0].sizeimage; =20 - memcpy(&inst->fw_caps[0], &core->inst_fw_caps[0], + memcpy(&inst->fw_caps[0], &core->inst_fw_caps_dec[0], INST_FW_CAP_MAX * sizeof(struct platform_inst_fw_cap)); =20 return iris_ctrls_init(inst); diff --git a/drivers/media/platform/qcom/iris/iris_venc.c b/drivers/media/p= latform/qcom/iris/iris_venc.c index 967db02ed27f31498e0f5c3245a37473022f4be5..16cc753bd31aaf51ff29c2578da= 5395925e31ccf 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.c +++ b/drivers/media/platform/qcom/iris/iris_venc.c @@ -7,12 +7,14 @@ #include =20 #include "iris_buffer.h" +#include "iris_ctrls.h" #include "iris_instance.h" #include "iris_venc.h" #include "iris_vpu_buffer.h" =20 int iris_venc_inst_init(struct iris_inst *inst) { + struct iris_core *core =3D inst->core; struct v4l2_format *f; =20 inst->fmt_src =3D kzalloc(sizeof(*inst->fmt_src), GFP_KERNEL); @@ -64,7 +66,10 @@ int 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a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=COk6AnOGAAAA:8 a=KKAkSRfTAAAA:8 a=Q1sPGKC9DDTbYkKOHPIA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-25_03,2025-08-20_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 adultscore=0 bulkscore=0 suspectscore=0 phishscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508230044 Add support for V4L2 streaming operations on the encoder video device. During stream-on, configure mandatory properties on the respective planes and notify the firmware to initiate an encode session. Tested-by: Vikash Garodia # X1E80100 Reviewed-by: Vikash Garodia Tested-by: Neil Armstrong # on SM8550-HDK Tested-by: Neil Armstrong # on SM8650-HDK Signed-off-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e80100-crd --- drivers/media/platform/qcom/iris/Makefile | 4 +- drivers/media/platform/qcom/iris/iris_common.c | 196 +++++++++++++++ drivers/media/platform/qcom/iris/iris_common.h | 16 ++ drivers/media/platform/qcom/iris/iris_hfi_common.h | 2 +- .../platform/qcom/iris/iris_hfi_gen1_command.c | 269 +++++++++++++----= --- .../platform/qcom/iris/iris_hfi_gen1_defines.h | 18 ++ .../platform/qcom/iris/iris_hfi_gen2_command.c | 280 ++++++++++++++---= ---- .../platform/qcom/iris/iris_hfi_gen2_defines.h | 3 + .../platform/qcom/iris/iris_platform_common.h | 20 +- .../media/platform/qcom/iris/iris_platform_gen2.c | 92 +++++-- .../platform/qcom/iris/iris_platform_sm8250.c | 23 +- drivers/media/platform/qcom/iris/iris_vb2.c | 36 ++- drivers/media/platform/qcom/iris/iris_vdec.c | 190 +------------- drivers/media/platform/qcom/iris/iris_vdec.h | 1 - drivers/media/platform/qcom/iris/iris_venc.c | 32 +++ drivers/media/platform/qcom/iris/iris_venc.h | 2 + drivers/media/platform/qcom/iris/iris_vidc.c | 2 + 17 files changed, 778 insertions(+), 408 deletions(-) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/plat= form/qcom/iris/Makefile index ec32145e081b1fc3538dfa7d5113162a76a6068c..13270cd6d899852dded675b33d3= 7f5919b81ccba 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -1,5 +1,5 @@ -qcom-iris-objs +=3D \ - iris_buffer.o \ +qcom-iris-objs +=3D iris_buffer.o \ + iris_common.o \ iris_core.o \ iris_ctrls.o \ iris_firmware.o \ diff --git a/drivers/media/platform/qcom/iris/iris_common.c b/drivers/media= /platform/qcom/iris/iris_common.c new file mode 100644 index 0000000000000000000000000000000000000000..d6a9271bcec77f142919070bf05= 66d0cf8a39562 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_common.c @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights res= erved. + */ + +#include + +#include "iris_common.h" +#include "iris_ctrls.h" +#include "iris_instance.h" +#include "iris_power.h" + +int iris_process_streamon_input(struct iris_inst *inst) +{ + const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + enum iris_inst_sub_state set_sub_state =3D 0; + int ret; + + iris_scale_power(inst); + + ret =3D hfi_ops->session_start(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); + if (ret) + return ret; + + if (inst->sub_state & IRIS_INST_SUB_INPUT_PAUSE) { + ret =3D iris_inst_change_sub_state(inst, IRIS_INST_SUB_INPUT_PAUSE, 0); + if (ret) + return ret; + } + + if (inst->domain =3D=3D DECODER && + (inst->sub_state & IRIS_INST_SUB_DRC || + inst->sub_state & IRIS_INST_SUB_DRAIN || + inst->sub_state & IRIS_INST_SUB_FIRST_IPSC)) { + if (!(inst->sub_state & IRIS_INST_SUB_INPUT_PAUSE)) { + if (hfi_ops->session_pause) { + ret =3D hfi_ops->session_pause(inst, + V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); + if (ret) + return ret; + } + set_sub_state =3D IRIS_INST_SUB_INPUT_PAUSE; + } + } + + ret =3D iris_inst_state_change_streamon(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_= MPLANE); + if (ret) + return ret; + + inst->last_buffer_dequeued =3D false; + + return iris_inst_change_sub_state(inst, 0, set_sub_state); +} + +int iris_process_streamon_output(struct iris_inst *inst) +{ + const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + bool drain_active =3D false, drc_active =3D false; + enum iris_inst_sub_state clear_sub_state =3D 0; + int ret =3D 0; + + iris_scale_power(inst); + + drain_active =3D inst->sub_state & IRIS_INST_SUB_DRAIN && + inst->sub_state & IRIS_INST_SUB_DRAIN_LAST; + + drc_active =3D inst->sub_state & IRIS_INST_SUB_DRC && + inst->sub_state & IRIS_INST_SUB_DRC_LAST; + + if (drc_active) + clear_sub_state =3D IRIS_INST_SUB_DRC | IRIS_INST_SUB_DRC_LAST; + else if (drain_active) + clear_sub_state =3D IRIS_INST_SUB_DRAIN | IRIS_INST_SUB_DRAIN_LAST; + + if (inst->domain =3D=3D DECODER && inst->sub_state & IRIS_INST_SUB_INPUT_= PAUSE) { + ret =3D iris_alloc_and_queue_input_int_bufs(inst); + if (ret) + return ret; + ret =3D iris_set_stage(inst, STAGE); + if (ret) + return ret; + ret =3D iris_set_pipe(inst, PIPE); + if (ret) + return ret; + } + + if (inst->state =3D=3D IRIS_INST_INPUT_STREAMING && + inst->sub_state & IRIS_INST_SUB_INPUT_PAUSE) { + if (!drain_active) + ret =3D hfi_ops->session_resume_drc(inst, + V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); + else if (hfi_ops->session_resume_drain) + ret =3D hfi_ops->session_resume_drain(inst, + V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); + if (ret) + return ret; + clear_sub_state |=3D IRIS_INST_SUB_INPUT_PAUSE; + } + + if (inst->sub_state & IRIS_INST_SUB_FIRST_IPSC) + clear_sub_state |=3D IRIS_INST_SUB_FIRST_IPSC; + + ret =3D hfi_ops->session_start(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); + if (ret) + return ret; + + if (inst->sub_state & IRIS_INST_SUB_OUTPUT_PAUSE) + clear_sub_state |=3D IRIS_INST_SUB_OUTPUT_PAUSE; + + ret =3D iris_inst_state_change_streamon(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE= _MPLANE); + if (ret) + return ret; + + inst->last_buffer_dequeued =3D false; + + return iris_inst_change_sub_state(inst, clear_sub_state, 0); +} + +static void iris_flush_deferred_buffers(struct iris_inst *inst, + enum iris_buffer_type type) +{ + struct v4l2_m2m_ctx *m2m_ctx =3D inst->m2m_ctx; + struct v4l2_m2m_buffer *buffer, *n; + struct iris_buffer *buf; + + if (type =3D=3D BUF_INPUT) { + v4l2_m2m_for_each_src_buf_safe(m2m_ctx, buffer, n) { + buf =3D to_iris_buffer(&buffer->vb); + if (buf->attr & BUF_ATTR_DEFERRED) { + if (!(buf->attr & BUF_ATTR_BUFFER_DONE)) { + buf->attr |=3D BUF_ATTR_BUFFER_DONE; + buf->data_size =3D 0; + iris_vb2_buffer_done(inst, buf); + } + } + } + } else { + v4l2_m2m_for_each_dst_buf_safe(m2m_ctx, buffer, n) { + buf =3D to_iris_buffer(&buffer->vb); + if (buf->attr & BUF_ATTR_DEFERRED) { + if (!(buf->attr & BUF_ATTR_BUFFER_DONE)) { + buf->attr |=3D BUF_ATTR_BUFFER_DONE; + buf->data_size =3D 0; + iris_vb2_buffer_done(inst, buf); + } + } + } + } +} + +static void iris_kill_session(struct iris_inst *inst) +{ + const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + + if (!inst->session_id) + return; + + hfi_ops->session_close(inst); + iris_inst_change_state(inst, IRIS_INST_ERROR); +} + +int iris_session_streamoff(struct iris_inst *inst, u32 plane) +{ + const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + enum iris_buffer_type buffer_type; + int ret; + + switch (plane) { + case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE: + buffer_type =3D BUF_INPUT; + break; + case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: + buffer_type =3D BUF_OUTPUT; + break; + default: + return -EINVAL; + } + + ret =3D hfi_ops->session_stop(inst, plane); + if (ret) + goto error; + + ret =3D iris_inst_state_change_streamoff(inst, plane); + if (ret) + goto error; + + iris_flush_deferred_buffers(inst, buffer_type); + + return 0; + +error: + iris_kill_session(inst); + iris_flush_deferred_buffers(inst, buffer_type); + + return ret; +} diff --git a/drivers/media/platform/qcom/iris/iris_common.h b/drivers/media= /platform/qcom/iris/iris_common.h new file mode 100644 index 0000000000000000000000000000000000000000..f385eeb53910555f17602f3951e= 7a6e9636a9ba2 --- /dev/null +++ b/drivers/media/platform/qcom/iris/iris_common.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022-2025 Qualcomm Innovation Center, Inc. All rights res= erved. + */ + +#ifndef __IRIS_COMMON_H__ +#define __IRIS_COMMON_H__ + +struct iris_inst; +struct iris_buffer; + +int iris_process_streamon_input(struct iris_inst *inst); +int iris_process_streamon_output(struct iris_inst *inst); +int iris_session_streamoff(struct iris_inst *inst, u32 plane); + +#endif diff --git a/drivers/media/platform/qcom/iris/iris_hfi_common.h b/drivers/m= edia/platform/qcom/iris/iris_hfi_common.h index 9e6aadb837830b46e4a68865583e28fc427cef0d..b51471fb32c70acee44c37f8e9d= ce0c6bc0b6ccc 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_common.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_common.h @@ -102,7 +102,7 @@ enum hfi_matrix_coefficients { =20 struct iris_hfi_prop_type_handle { u32 type; - int (*handle)(struct iris_inst *inst); + int (*handle)(struct iris_inst *inst, u32 plane); }; =20 struct iris_hfi_command_ops { diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_command.c index 86ed414861e58c7c8567e7259924b2efe6f76e07..cd1dc9575f592cc3b5f10f9aab9= a1ff86adb1dd2 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -189,38 +189,65 @@ static int iris_hfi_gen1_session_stop(struct iris_ins= t *inst, u32 plane) u32 flush_type =3D 0; int ret =3D 0; =20 - if (inst->state =3D=3D IRIS_INST_STREAMING) { - if (V4L2_TYPE_IS_OUTPUT(plane)) - flush_type =3D HFI_FLUSH_ALL; - else if (V4L2_TYPE_IS_CAPTURE(plane)) - flush_type =3D HFI_FLUSH_OUTPUT; - - reinit_completion(&inst->flush_completion); - - flush_pkt.shdr.hdr.size =3D sizeof(struct hfi_session_flush_pkt); - flush_pkt.shdr.hdr.pkt_type =3D HFI_CMD_SESSION_FLUSH; - flush_pkt.shdr.session_id =3D inst->session_id; - flush_pkt.flush_type =3D flush_type; - - ret =3D iris_hfi_queue_cmd_write(core, &flush_pkt, flush_pkt.shdr.hdr.si= ze); - if (!ret) { - inst->flush_responses_pending++; - ret =3D iris_wait_for_session_response(inst, true); + if (inst->domain =3D=3D DECODER) { + if (inst->state =3D=3D IRIS_INST_STREAMING) { + if (V4L2_TYPE_IS_OUTPUT(plane)) + flush_type =3D HFI_FLUSH_ALL; + else if (V4L2_TYPE_IS_CAPTURE(plane)) + flush_type =3D HFI_FLUSH_OUTPUT; + + reinit_completion(&inst->flush_completion); + + flush_pkt.shdr.hdr.size =3D sizeof(struct hfi_session_flush_pkt); + flush_pkt.shdr.hdr.pkt_type =3D HFI_CMD_SESSION_FLUSH; + flush_pkt.shdr.session_id =3D inst->session_id; + flush_pkt.flush_type =3D flush_type; + + ret =3D iris_hfi_queue_cmd_write(core, &flush_pkt, flush_pkt.shdr.hdr.s= ize); + if (!ret) { + inst->flush_responses_pending++; + ret =3D iris_wait_for_session_response(inst, true); + } + } else if (inst->sub_state & IRIS_INST_SUB_LOAD_RESOURCES) { + reinit_completion(&inst->completion); + iris_hfi_gen1_packet_session_cmd(inst, &pkt, HFI_CMD_SESSION_STOP); + ret =3D iris_hfi_queue_cmd_write(core, &pkt, pkt.shdr.hdr.size); + if (!ret) + ret =3D iris_wait_for_session_response(inst, false); + + reinit_completion(&inst->completion); + iris_hfi_gen1_packet_session_cmd(inst, &pkt, + HFI_CMD_SESSION_RELEASE_RESOURCES); + ret =3D iris_hfi_queue_cmd_write(core, &pkt, pkt.shdr.hdr.size); + if (!ret) + ret =3D iris_wait_for_session_response(inst, false); + + iris_inst_change_sub_state(inst, IRIS_INST_SUB_LOAD_RESOURCES, 0); + + iris_helper_buffers_done(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, + VB2_BUF_STATE_ERROR); + iris_helper_buffers_done(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE, + VB2_BUF_STATE_ERROR); + } + } else { + if (inst->state =3D=3D IRIS_INST_STREAMING || + inst->state =3D=3D IRIS_INST_INPUT_STREAMING || + inst->state =3D=3D IRIS_INST_ERROR) { + reinit_completion(&inst->completion); + iris_hfi_gen1_packet_session_cmd(inst, &pkt, HFI_CMD_SESSION_STOP); + ret =3D iris_hfi_queue_cmd_write(core, &pkt, pkt.shdr.hdr.size); + if (!ret) + ret =3D iris_wait_for_session_response(inst, false); + + reinit_completion(&inst->completion); + iris_hfi_gen1_packet_session_cmd(inst, &pkt, + HFI_CMD_SESSION_RELEASE_RESOURCES); + ret =3D iris_hfi_queue_cmd_write(core, &pkt, pkt.shdr.hdr.size); + if (!ret) + ret =3D iris_wait_for_session_response(inst, false); + + iris_inst_change_sub_state(inst, IRIS_INST_SUB_LOAD_RESOURCES, 0); } - } else if (inst->sub_state & IRIS_INST_SUB_LOAD_RESOURCES) { - reinit_completion(&inst->completion); - iris_hfi_gen1_packet_session_cmd(inst, &pkt, HFI_CMD_SESSION_STOP); - ret =3D iris_hfi_queue_cmd_write(core, &pkt, pkt.shdr.hdr.size); - if (!ret) - ret =3D iris_wait_for_session_response(inst, false); - - reinit_completion(&inst->completion); - iris_hfi_gen1_packet_session_cmd(inst, &pkt, HFI_CMD_SESSION_RELEASE_RES= OURCES); - ret =3D iris_hfi_queue_cmd_write(core, &pkt, pkt.shdr.hdr.size); - if (!ret) - ret =3D iris_wait_for_session_response(inst, false); - - iris_inst_change_sub_state(inst, IRIS_INST_SUB_LOAD_RESOURCES, 0); =20 iris_helper_buffers_done(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE, VB2_BUF_STATE_ERROR); @@ -549,7 +576,7 @@ static int iris_hfi_gen1_session_set_property(struct ir= is_inst *inst, u32 packet return hfi_gen1_set_property(inst, packet_type, payload, payload_size); } =20 -static int iris_hfi_gen1_set_resolution(struct iris_inst *inst) +static int iris_hfi_gen1_set_resolution(struct iris_inst *inst, u32 plane) { u32 ptype =3D HFI_PROPERTY_PARAM_FRAME_SIZE; struct hfi_framesize fs; @@ -564,14 +591,18 @@ static int iris_hfi_gen1_set_resolution(struct iris_i= nst *inst) if (ret) return ret; } - fs.buffer_type =3D HFI_BUFFER_OUTPUT2; + if (inst->domain =3D=3D DECODER) + fs.buffer_type =3D HFI_BUFFER_OUTPUT2; + else + fs.buffer_type =3D HFI_BUFFER_OUTPUT; + fs.width =3D inst->fmt_dst->fmt.pix_mp.width; fs.height =3D inst->fmt_dst->fmt.pix_mp.height; =20 return hfi_gen1_set_property(inst, ptype, &fs, sizeof(fs)); } =20 -static int iris_hfi_gen1_decide_core(struct iris_inst *inst) +static int iris_hfi_gen1_decide_core(struct iris_inst *inst, u32 plane) { const u32 ptype =3D HFI_PROPERTY_CONFIG_VIDEOCORES_USAGE; struct hfi_videocores_usage_type cu; @@ -581,36 +612,45 @@ static int iris_hfi_gen1_decide_core(struct iris_inst= *inst) return hfi_gen1_set_property(inst, ptype, &cu, sizeof(cu)); } =20 -static int iris_hfi_gen1_set_raw_format(struct iris_inst *inst) +static int iris_hfi_gen1_set_raw_format(struct iris_inst *inst, u32 plane) { const u32 ptype =3D HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SELECT; - u32 pixelformat =3D inst->fmt_dst->fmt.pix_mp.pixelformat; struct hfi_uncompressed_format_select fmt; + u32 pixelformat; int ret; =20 - if (iris_split_mode_enabled(inst)) { - fmt.buffer_type =3D HFI_BUFFER_OUTPUT; - fmt.format =3D pixelformat =3D=3D V4L2_PIX_FMT_NV12 ? HFI_COLOR_FORMAT_N= V12_UBWC : 0; + if (inst->domain =3D=3D DECODER) { + pixelformat =3D inst->fmt_dst->fmt.pix_mp.pixelformat; + if (iris_split_mode_enabled(inst)) { + fmt.buffer_type =3D HFI_BUFFER_OUTPUT; + fmt.format =3D pixelformat =3D=3D V4L2_PIX_FMT_NV12 ? + HFI_COLOR_FORMAT_NV12_UBWC : 0; =20 - ret =3D hfi_gen1_set_property(inst, ptype, &fmt, sizeof(fmt)); - if (ret) - return ret; + ret =3D hfi_gen1_set_property(inst, ptype, &fmt, sizeof(fmt)); + if (ret) + return ret; =20 - fmt.buffer_type =3D HFI_BUFFER_OUTPUT2; - fmt.format =3D pixelformat =3D=3D V4L2_PIX_FMT_NV12 ? HFI_COLOR_FORMAT_N= V12 : 0; + fmt.buffer_type =3D HFI_BUFFER_OUTPUT2; + fmt.format =3D pixelformat =3D=3D V4L2_PIX_FMT_NV12 ? HFI_COLOR_FORMAT_= NV12 : 0; =20 - ret =3D hfi_gen1_set_property(inst, ptype, &fmt, sizeof(fmt)); + ret =3D hfi_gen1_set_property(inst, ptype, &fmt, sizeof(fmt)); + } else { + fmt.buffer_type =3D HFI_BUFFER_OUTPUT; + fmt.format =3D pixelformat =3D=3D V4L2_PIX_FMT_NV12 ? HFI_COLOR_FORMAT_= NV12 : 0; + + ret =3D hfi_gen1_set_property(inst, ptype, &fmt, sizeof(fmt)); + } } else { - fmt.buffer_type =3D HFI_BUFFER_OUTPUT; + pixelformat =3D inst->fmt_src->fmt.pix_mp.pixelformat; + fmt.buffer_type =3D HFI_BUFFER_INPUT; fmt.format =3D pixelformat =3D=3D V4L2_PIX_FMT_NV12 ? HFI_COLOR_FORMAT_N= V12 : 0; - ret =3D hfi_gen1_set_property(inst, ptype, &fmt, sizeof(fmt)); } =20 return ret; } =20 -static int iris_hfi_gen1_set_format_constraints(struct iris_inst *inst) +static int iris_hfi_gen1_set_format_constraints(struct iris_inst *inst, u3= 2 plane) { const u32 ptype =3D HFI_PROPERTY_PARAM_UNCOMPRESSED_PLANE_ACTUAL_CONSTRAI= NTS_INFO; struct hfi_uncompressed_plane_actual_constraints_info pconstraint; @@ -630,7 +670,7 @@ static int iris_hfi_gen1_set_format_constraints(struct = iris_inst *inst) return hfi_gen1_set_property(inst, ptype, &pconstraint, sizeof(pconstrain= t)); } =20 -static int iris_hfi_gen1_set_num_bufs(struct iris_inst *inst) +static int iris_hfi_gen1_set_num_bufs(struct iris_inst *inst, u32 plane) { u32 ptype =3D HFI_PROPERTY_PARAM_BUFFER_COUNT_ACTUAL; struct hfi_buffer_count_actual buf_count; @@ -644,20 +684,28 @@ static int iris_hfi_gen1_set_num_bufs(struct iris_ins= t *inst) if (ret) return ret; =20 - if (iris_split_mode_enabled(inst)) { - buf_count.type =3D HFI_BUFFER_OUTPUT; - buf_count.count_actual =3D VIDEO_MAX_FRAME; - buf_count.count_min_host =3D VIDEO_MAX_FRAME; + if (inst->domain =3D=3D DECODER) { + if (iris_split_mode_enabled(inst)) { + buf_count.type =3D HFI_BUFFER_OUTPUT; + buf_count.count_actual =3D VIDEO_MAX_FRAME; + buf_count.count_min_host =3D VIDEO_MAX_FRAME; =20 - ret =3D hfi_gen1_set_property(inst, ptype, &buf_count, sizeof(buf_count)= ); - if (ret) - return ret; + ret =3D hfi_gen1_set_property(inst, ptype, &buf_count, sizeof(buf_count= )); + if (ret) + return ret; =20 - buf_count.type =3D HFI_BUFFER_OUTPUT2; - buf_count.count_actual =3D iris_vpu_buf_count(inst, BUF_DPB); - buf_count.count_min_host =3D iris_vpu_buf_count(inst, BUF_DPB); + buf_count.type =3D HFI_BUFFER_OUTPUT2; + buf_count.count_actual =3D iris_vpu_buf_count(inst, BUF_DPB); + buf_count.count_min_host =3D iris_vpu_buf_count(inst, BUF_DPB); =20 - ret =3D hfi_gen1_set_property(inst, ptype, &buf_count, sizeof(buf_count)= ); + ret =3D hfi_gen1_set_property(inst, ptype, &buf_count, sizeof(buf_count= )); + } else { + buf_count.type =3D HFI_BUFFER_OUTPUT; + buf_count.count_actual =3D VIDEO_MAX_FRAME; + buf_count.count_min_host =3D VIDEO_MAX_FRAME; + + ret =3D hfi_gen1_set_property(inst, ptype, &buf_count, sizeof(buf_count= )); + } } else { buf_count.type =3D HFI_BUFFER_OUTPUT; buf_count.count_actual =3D VIDEO_MAX_FRAME; @@ -669,7 +717,7 @@ static int iris_hfi_gen1_set_num_bufs(struct iris_inst = *inst) return ret; } =20 -static int iris_hfi_gen1_set_multistream(struct iris_inst *inst) +static int iris_hfi_gen1_set_multistream(struct iris_inst *inst, u32 plane) { u32 ptype =3D HFI_PROPERTY_PARAM_VDEC_MULTI_STREAM; struct hfi_multi_stream multi =3D {0}; @@ -704,7 +752,7 @@ static int iris_hfi_gen1_set_multistream(struct iris_in= st *inst) return ret; } =20 -static int iris_hfi_gen1_set_bufsize(struct iris_inst *inst) +static int iris_hfi_gen1_set_bufsize(struct iris_inst *inst, u32 plane) { const u32 ptype =3D HFI_PROPERTY_PARAM_BUFFER_SIZE_ACTUAL; struct hfi_buffer_size_actual bufsz; @@ -739,14 +787,49 @@ static int iris_hfi_gen1_set_bufsize(struct iris_inst= *inst) return ret; } =20 +static int iris_hfi_gen1_set_frame_rate(struct iris_inst *inst, u32 plane) +{ + const u32 ptype =3D HFI_PROPERTY_CONFIG_FRAME_RATE; + struct hfi_framerate frate; + + if (V4L2_TYPE_IS_OUTPUT(plane)) + return 0; + + frate.buffer_type =3D HFI_BUFFER_OUTPUT; + frate.framerate =3D inst->frame_rate << 16; + + return hfi_gen1_set_property(inst, ptype, &frate, sizeof(frate)); +} + +static int iris_hfi_gen1_set_stride(struct iris_inst *inst, u32 plane) +{ + const u32 ptype =3D HFI_PROPERTY_PARAM_UNCOMPRESSED_PLANE_ACTUAL_INFO; + struct hfi_uncompressed_plane_actual_info plane_actual_info; + + plane_actual_info.buffer_type =3D HFI_BUFFER_INPUT; + plane_actual_info.num_planes =3D 2; + plane_actual_info.plane_format[0].actual_stride =3D + ALIGN(inst->fmt_src->fmt.pix_mp.width, 128); + plane_actual_info.plane_format[0].actual_plane_buffer_height =3D + ALIGN(inst->fmt_src->fmt.pix_mp.height, 32); + plane_actual_info.plane_format[1].actual_stride =3D + ALIGN(inst->fmt_src->fmt.pix_mp.width, 128); + plane_actual_info.plane_format[1].actual_plane_buffer_height =3D + (ALIGN(inst->fmt_src->fmt.pix_mp.height, 32)) / 2; + + return hfi_gen1_set_property(inst, ptype, &plane_actual_info, sizeof(plan= e_actual_info)); +} + static int iris_hfi_gen1_session_set_config_params(struct iris_inst *inst,= u32 plane) { + struct iris_hfi_prop_type_handle const *handler =3D NULL; + u32 handler_size =3D 0; struct iris_core *core =3D inst->core; u32 config_params_size, i, j; const u32 *config_params; int ret; =20 - static const struct iris_hfi_prop_type_handle prop_type_handle_inp_arr[] = =3D { + static const struct iris_hfi_prop_type_handle vdec_prop_type_handle_inp_a= rr[] =3D { {HFI_PROPERTY_PARAM_FRAME_SIZE, iris_hfi_gen1_set_resolution}, {HFI_PROPERTY_CONFIG_VIDEOCORES_USAGE, @@ -763,7 +846,7 @@ static int iris_hfi_gen1_session_set_config_params(stru= ct iris_inst *inst, u32 p iris_hfi_gen1_set_bufsize}, }; =20 - static const struct iris_hfi_prop_type_handle prop_type_handle_out_arr[] = =3D { + static const struct iris_hfi_prop_type_handle vdec_prop_type_handle_out_a= rr[] =3D { {HFI_PROPERTY_PARAM_FRAME_SIZE, iris_hfi_gen1_set_resolution}, {HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SELECT, @@ -778,29 +861,43 @@ static int iris_hfi_gen1_session_set_config_params(st= ruct iris_inst *inst, u32 p iris_hfi_gen1_set_bufsize}, }; =20 - config_params =3D core->iris_platform_data->input_config_params_default; - config_params_size =3D core->iris_platform_data->input_config_params_defa= ult_size; - - if (V4L2_TYPE_IS_OUTPUT(plane)) { - for (i =3D 0; i < config_params_size; i++) { - for (j =3D 0; j < ARRAY_SIZE(prop_type_handle_inp_arr); j++) { - if (prop_type_handle_inp_arr[j].type =3D=3D config_params[i]) { - ret =3D prop_type_handle_inp_arr[j].handle(inst); - if (ret) - return ret; - break; - } - } + static const struct iris_hfi_prop_type_handle venc_prop_type_handle_inp_a= rr[] =3D { + {HFI_PROPERTY_CONFIG_FRAME_RATE, + iris_hfi_gen1_set_frame_rate}, + {HFI_PROPERTY_PARAM_UNCOMPRESSED_PLANE_ACTUAL_INFO, + iris_hfi_gen1_set_stride}, + {HFI_PROPERTY_PARAM_FRAME_SIZE, + iris_hfi_gen1_set_resolution}, + {HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SELECT, + iris_hfi_gen1_set_raw_format}, + {HFI_PROPERTY_PARAM_BUFFER_COUNT_ACTUAL, + iris_hfi_gen1_set_num_bufs}, + }; + + if (inst->domain =3D=3D DECODER) { + config_params =3D core->iris_platform_data->dec_input_config_params_defa= ult; + config_params_size =3D core->iris_platform_data->dec_input_config_params= _default_size; + if (V4L2_TYPE_IS_OUTPUT(plane)) { + handler =3D vdec_prop_type_handle_inp_arr; + handler_size =3D ARRAY_SIZE(vdec_prop_type_handle_inp_arr); + } else if (V4L2_TYPE_IS_CAPTURE(plane)) { + handler =3D vdec_prop_type_handle_out_arr; + handler_size =3D ARRAY_SIZE(vdec_prop_type_handle_out_arr); } - } else if (V4L2_TYPE_IS_CAPTURE(plane)) { - for (i =3D 0; i < config_params_size; i++) { - for (j =3D 0; j < ARRAY_SIZE(prop_type_handle_out_arr); j++) { - if (prop_type_handle_out_arr[j].type =3D=3D config_params[i]) { - ret =3D prop_type_handle_out_arr[j].handle(inst); - if (ret) - return ret; - break; - } + } else { + config_params =3D core->iris_platform_data->enc_input_config_params; + config_params_size =3D core->iris_platform_data->enc_input_config_params= _size; + handler =3D venc_prop_type_handle_inp_arr; + handler_size =3D ARRAY_SIZE(venc_prop_type_handle_inp_arr); + } + + for (i =3D 0; i < config_params_size; i++) { + for (j =3D 0; j < handler_size; j++) { + if (handler[j].type =3D=3D config_params[i]) { + ret =3D handler[j].handle(inst, plane); + if (ret) + return ret; + break; } } } diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_defines.h index a7f4379c5973fdc4366969139bef25472e8f11a5..81116420b6a3d86cca7229bdd3a= 875d95c1a7936 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h @@ -82,10 +82,12 @@ #define HFI_PROPERTY_SYS_IMAGE_VERSION 0x6 =20 #define HFI_PROPERTY_PARAM_FRAME_SIZE 0x1001 +#define HFI_PROPERTY_PARAM_UNCOMPRESSED_PLANE_ACTUAL_INFO 0x1002 #define HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SELECT 0x1003 #define HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT 0x1005 #define HFI_PROPERTY_PARAM_WORK_MODE 0x1015 #define HFI_PROPERTY_PARAM_WORK_ROUTE 0x1017 +#define HFI_PROPERTY_CONFIG_FRAME_RATE 0x2001 #define HFI_PROPERTY_CONFIG_VIDEOCORES_USAGE 0x2002 =20 #define HFI_PROPERTY_PARAM_VDEC_MULTI_STREAM 0x1003001 @@ -348,6 +350,17 @@ struct hfi_uncompressed_plane_actual_constraints_info { struct hfi_uncompressed_plane_constraints plane_format[2]; }; =20 +struct hfi_uncompressed_plane_actual { + int actual_stride; + u32 actual_plane_buffer_height; +}; + +struct hfi_uncompressed_plane_actual_info { + u32 buffer_type; + u32 num_planes; + struct hfi_uncompressed_plane_actual plane_format[2]; +}; + struct hfi_buffer_count_actual { u32 type; u32 count_actual; @@ -375,6 +388,11 @@ struct hfi_buffer_requirements { u32 alignment; }; =20 +struct hfi_framerate { + u32 buffer_type; + u32 framerate; +}; + struct hfi_event_data { u32 error; u32 height; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 7ca5ae13d62b95fdcf71ef70cb6abf446b2c6e5a..3a7bff092846db8469bc746f2e4= f8bf338b6380d 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -88,15 +88,26 @@ static int iris_hfi_gen2_sys_pc_prep(struct iris_core *= core) return ret; } =20 -static u32 iris_hfi_gen2_get_port(u32 plane) +static u32 iris_hfi_gen2_get_port(struct iris_inst *inst, u32 plane) { - switch (plane) { - case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE: - return HFI_PORT_BITSTREAM; - case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: - return HFI_PORT_RAW; - default: - return HFI_PORT_NONE; + if (inst->domain =3D=3D DECODER) { + switch (plane) { + case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE: + return HFI_PORT_BITSTREAM; + case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: + return HFI_PORT_RAW; + default: + return HFI_PORT_NONE; + } + } else { + switch (plane) { + case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE: + return HFI_PORT_RAW; + case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: + return HFI_PORT_BITSTREAM; + default: + return HFI_PORT_NONE; + } } } =20 @@ -136,34 +147,77 @@ static int iris_hfi_gen2_session_set_property(struct = iris_inst *inst, u32 packet inst_hfi_gen2->packet->size); } =20 -static int iris_hfi_gen2_set_bitstream_resolution(struct iris_inst *inst) +static int iris_hfi_gen2_set_raw_resolution(struct iris_inst *inst, u32 pl= ane) { - struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); - u32 port =3D iris_hfi_gen2_get_port(V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); u32 resolution =3D inst->fmt_src->fmt.pix_mp.width << 16 | inst->fmt_src->fmt.pix_mp.height; + u32 port =3D iris_hfi_gen2_get_port(inst, plane); =20 - inst_hfi_gen2->src_subcr_params.bitstream_resolution =3D resolution; + return iris_hfi_gen2_session_set_property(inst, + HFI_PROP_RAW_RESOLUTION, + HFI_HOST_FLAGS_NONE, + port, + HFI_PAYLOAD_32_PACKED, + &resolution, + sizeof(u32)); +} + +static int iris_hfi_gen2_set_bitstream_resolution(struct iris_inst *inst, = u32 plane) +{ + struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); + u32 port =3D iris_hfi_gen2_get_port(inst, plane); + enum hfi_packet_payload_info payload_type; + u32 resolution, codec_align; + + if (inst->domain =3D=3D DECODER) { + resolution =3D inst->fmt_src->fmt.pix_mp.width << 16 | + inst->fmt_src->fmt.pix_mp.height; + inst_hfi_gen2->src_subcr_params.bitstream_resolution =3D resolution; + payload_type =3D HFI_PAYLOAD_U32; + } else { + codec_align =3D inst->codec =3D=3D V4L2_PIX_FMT_HEVC ? 32 : 16; + resolution =3D ALIGN(inst->fmt_dst->fmt.pix_mp.width, codec_align) << 16= | + ALIGN(inst->fmt_dst->fmt.pix_mp.height, codec_align); + inst_hfi_gen2->dst_subcr_params.bitstream_resolution =3D resolution; + payload_type =3D HFI_PAYLOAD_32_PACKED; + } =20 return iris_hfi_gen2_session_set_property(inst, HFI_PROP_BITSTREAM_RESOLUTION, HFI_HOST_FLAGS_NONE, port, - HFI_PAYLOAD_U32, + payload_type, &resolution, sizeof(u32)); } =20 -static int iris_hfi_gen2_set_crop_offsets(struct iris_inst *inst) +static int iris_hfi_gen2_set_crop_offsets(struct iris_inst *inst, u32 plan= e) { - u32 bottom_offset =3D (inst->fmt_src->fmt.pix_mp.height - inst->crop.heig= ht); - u32 right_offset =3D (inst->fmt_src->fmt.pix_mp.width - inst->crop.width); struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); - u32 port =3D iris_hfi_gen2_get_port(V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); - u32 left_offset =3D inst->crop.left; - u32 top_offset =3D inst->crop.top; + u32 port =3D iris_hfi_gen2_get_port(inst, plane); + u32 bottom_offset, right_offset; + u32 left_offset, top_offset; u32 payload[2]; =20 + if (inst->domain =3D=3D DECODER) { + if (V4L2_TYPE_IS_OUTPUT(plane)) { + bottom_offset =3D (inst->fmt_src->fmt.pix_mp.height - inst->crop.height= ); + right_offset =3D (inst->fmt_src->fmt.pix_mp.width - inst->crop.width); + left_offset =3D inst->crop.left; + top_offset =3D inst->crop.top; + } else { + bottom_offset =3D (inst->fmt_dst->fmt.pix_mp.height - inst->compose.hei= ght); + right_offset =3D (inst->fmt_dst->fmt.pix_mp.width - inst->compose.width= ); + left_offset =3D inst->compose.left; + top_offset =3D inst->compose.top; + } + } else { + bottom_offset =3D (inst->fmt_src->fmt.pix_mp.height - inst->crop.height); + right_offset =3D (inst->fmt_src->fmt.pix_mp.width - inst->crop.width); + left_offset =3D inst->crop.left; + top_offset =3D inst->crop.top; + } + payload[0] =3D FIELD_PREP(GENMASK(31, 16), left_offset) | top_offset; payload[1] =3D FIELD_PREP(GENMASK(31, 16), right_offset) | bottom_offset; inst_hfi_gen2->src_subcr_params.crop_offsets[0] =3D payload[0]; @@ -178,10 +232,10 @@ static int iris_hfi_gen2_set_crop_offsets(struct iris= _inst *inst) sizeof(u64)); } =20 -static int iris_hfi_gen2_set_bit_depth(struct iris_inst *inst) +static int iris_hfi_gen2_set_bit_depth(struct iris_inst *inst, u32 plane) { struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); - u32 port =3D iris_hfi_gen2_get_port(V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); + u32 port =3D iris_hfi_gen2_get_port(inst, plane); u32 bitdepth =3D BIT_DEPTH_8; =20 inst_hfi_gen2->src_subcr_params.bit_depth =3D bitdepth; @@ -195,10 +249,10 @@ static int iris_hfi_gen2_set_bit_depth(struct iris_in= st *inst) sizeof(u32)); } =20 -static int iris_hfi_gen2_set_coded_frames(struct iris_inst *inst) +static int iris_hfi_gen2_set_coded_frames(struct iris_inst *inst, u32 plan= e) { struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); - u32 port =3D iris_hfi_gen2_get_port(V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); + u32 port =3D iris_hfi_gen2_get_port(inst, plane); u32 coded_frames =3D 0; =20 if (inst->fw_caps[CODED_FRAMES].value =3D=3D CODED_FRAMES_PROGRESSIVE) @@ -214,11 +268,11 @@ static int iris_hfi_gen2_set_coded_frames(struct iris= _inst *inst) sizeof(u32)); } =20 -static int iris_hfi_gen2_set_min_output_count(struct iris_inst *inst) +static int iris_hfi_gen2_set_min_output_count(struct iris_inst *inst, u32 = plane) { struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); - u32 port =3D iris_hfi_gen2_get_port(V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); u32 min_output =3D inst->buffers[BUF_OUTPUT].min_count; + u32 port =3D iris_hfi_gen2_get_port(inst, plane); =20 inst_hfi_gen2->src_subcr_params.fw_min_count =3D min_output; =20 @@ -231,10 +285,10 @@ static int iris_hfi_gen2_set_min_output_count(struct = iris_inst *inst) sizeof(u32)); } =20 -static int iris_hfi_gen2_set_picture_order_count(struct iris_inst *inst) +static int iris_hfi_gen2_set_picture_order_count(struct iris_inst *inst, u= 32 plane) { struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); - u32 port =3D iris_hfi_gen2_get_port(V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); + u32 port =3D iris_hfi_gen2_get_port(inst, plane); u32 poc =3D 0; =20 inst_hfi_gen2->src_subcr_params.pic_order_cnt =3D poc; @@ -248,16 +302,16 @@ static int iris_hfi_gen2_set_picture_order_count(stru= ct iris_inst *inst) sizeof(u32)); } =20 -static int iris_hfi_gen2_set_colorspace(struct iris_inst *inst) +static int iris_hfi_gen2_set_colorspace(struct iris_inst *inst, u32 plane) { struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); - u32 port =3D iris_hfi_gen2_get_port(V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); struct v4l2_pix_format_mplane *pixmp =3D &inst->fmt_src->fmt.pix_mp; u32 video_signal_type_present_flag =3D 0, color_info; u32 matrix_coeff =3D HFI_MATRIX_COEFF_RESERVED; u32 video_format =3D UNSPECIFIED_COLOR_FORMAT; u32 full_range =3D V4L2_QUANTIZATION_DEFAULT; u32 transfer_char =3D HFI_TRANSFER_RESERVED; + u32 port =3D iris_hfi_gen2_get_port(inst, plane); u32 colour_description_present_flag =3D 0; u32 primaries =3D HFI_PRIMARIES_RESERVED; =20 @@ -291,10 +345,10 @@ static int iris_hfi_gen2_set_colorspace(struct iris_i= nst *inst) sizeof(u32)); } =20 -static int iris_hfi_gen2_set_profile(struct iris_inst *inst) +static int iris_hfi_gen2_set_profile(struct iris_inst *inst, u32 plane) { struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); - u32 port =3D iris_hfi_gen2_get_port(V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); + u32 port =3D iris_hfi_gen2_get_port(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLA= NE); u32 profile =3D 0; =20 switch (inst->codec) { @@ -320,10 +374,10 @@ static int iris_hfi_gen2_set_profile(struct iris_inst= *inst) sizeof(u32)); } =20 -static int iris_hfi_gen2_set_level(struct iris_inst *inst) +static int iris_hfi_gen2_set_level(struct iris_inst *inst, u32 plane) { struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); - u32 port =3D iris_hfi_gen2_get_port(V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); + u32 port =3D iris_hfi_gen2_get_port(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLA= NE); u32 level =3D 0; =20 switch (inst->codec) { @@ -349,33 +403,47 @@ static int iris_hfi_gen2_set_level(struct iris_inst *= inst) sizeof(u32)); } =20 -static int iris_hfi_gen2_set_colorformat(struct iris_inst *inst) +static int iris_hfi_gen2_set_colorformat(struct iris_inst *inst, u32 plane) { - u32 port =3D iris_hfi_gen2_get_port(V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); + u32 port =3D iris_hfi_gen2_get_port(inst, plane); u32 hfi_colorformat, pixelformat; =20 - pixelformat =3D inst->fmt_dst->fmt.pix_mp.pixelformat; - hfi_colorformat =3D pixelformat =3D=3D V4L2_PIX_FMT_NV12 ? HFI_COLOR_FMT_= NV12 : 0; + if (inst->domain =3D=3D DECODER) { + pixelformat =3D inst->fmt_dst->fmt.pix_mp.pixelformat; + hfi_colorformat =3D pixelformat =3D=3D V4L2_PIX_FMT_NV12 ? HFI_COLOR_FMT= _NV12 : 0; + } else { + pixelformat =3D inst->fmt_src->fmt.pix_mp.pixelformat; + hfi_colorformat =3D pixelformat =3D=3D V4L2_PIX_FMT_NV12 ? HFI_COLOR_FMT= _NV12 : 0; + } =20 return iris_hfi_gen2_session_set_property(inst, HFI_PROP_COLOR_FORMAT, HFI_HOST_FLAGS_NONE, port, - HFI_PAYLOAD_U32, + HFI_PAYLOAD_U32_ENUM, &hfi_colorformat, sizeof(u32)); } =20 -static int iris_hfi_gen2_set_linear_stride_scanline(struct iris_inst *inst) +static int iris_hfi_gen2_set_linear_stride_scanline(struct iris_inst *inst= , u32 plane) { - u32 port =3D iris_hfi_gen2_get_port(V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); - u32 pixelformat =3D inst->fmt_dst->fmt.pix_mp.pixelformat; - u32 scanline_y =3D inst->fmt_dst->fmt.pix_mp.height; - u32 stride_y =3D inst->fmt_dst->fmt.pix_mp.width; - u32 scanline_uv =3D scanline_y / 2; - u32 stride_uv =3D stride_y; + u32 pixelformat, stride_y, stride_uv, scanline_y, scanline_uv; + u32 port =3D iris_hfi_gen2_get_port(inst, plane); u32 payload[2]; =20 + if (inst->domain =3D=3D DECODER) { + pixelformat =3D inst->fmt_dst->fmt.pix_mp.pixelformat; + stride_y =3D inst->fmt_dst->fmt.pix_mp.width; + scanline_y =3D inst->fmt_dst->fmt.pix_mp.height; + } else { + pixelformat =3D inst->fmt_src->fmt.pix_mp.pixelformat; + stride_y =3D ALIGN(inst->fmt_src->fmt.pix_mp.width, 128); + scanline_y =3D ALIGN(inst->fmt_src->fmt.pix_mp.height, 32); + } + + stride_uv =3D stride_y; + scanline_uv =3D scanline_y / 2; + if (pixelformat !=3D V4L2_PIX_FMT_NV12) return 0; =20 @@ -386,15 +454,15 @@ static int iris_hfi_gen2_set_linear_stride_scanline(s= truct iris_inst *inst) HFI_PROP_LINEAR_STRIDE_SCANLINE, HFI_HOST_FLAGS_NONE, port, - HFI_PAYLOAD_U64, + HFI_PAYLOAD_64_PACKED, &payload, sizeof(u64)); } =20 -static int iris_hfi_gen2_set_tier(struct iris_inst *inst) +static int iris_hfi_gen2_set_tier(struct iris_inst *inst, u32 plane) { struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); - u32 port =3D iris_hfi_gen2_get_port(V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); + u32 port =3D iris_hfi_gen2_get_port(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLA= NE); u32 tier =3D inst->fw_caps[TIER].value; =20 inst_hfi_gen2->src_subcr_params.tier =3D tier; @@ -408,14 +476,29 @@ static int iris_hfi_gen2_set_tier(struct iris_inst *i= nst) sizeof(u32)); } =20 +static int iris_hfi_gen2_set_frame_rate(struct iris_inst *inst, u32 plane) +{ + u32 port =3D iris_hfi_gen2_get_port(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPL= ANE); + u32 frame_rate =3D inst->frame_rate << 16; + + return iris_hfi_gen2_session_set_property(inst, + HFI_PROP_FRAME_RATE, + HFI_HOST_FLAGS_NONE, + port, + HFI_PAYLOAD_Q16, + &frame_rate, + sizeof(u32)); +} + static int iris_hfi_gen2_session_set_config_params(struct iris_inst *inst,= u32 plane) { - struct iris_core *core =3D inst->core; + const struct iris_platform_data *pdata =3D inst->core->iris_platform_data; u32 config_params_size =3D 0, i, j; const u32 *config_params =3D NULL; int ret; =20 static const struct iris_hfi_prop_type_handle prop_type_handle_arr[] =3D { + {HFI_PROP_RAW_RESOLUTION, iris_hfi_gen2_set_raw_resolution = }, {HFI_PROP_BITSTREAM_RESOLUTION, iris_hfi_gen2_set_bitstream_resolu= tion }, {HFI_PROP_CROP_OFFSETS, iris_hfi_gen2_set_crop_offsets = }, {HFI_PROP_CODED_FRAMES, iris_hfi_gen2_set_coded_frames = }, @@ -428,29 +511,35 @@ static int iris_hfi_gen2_session_set_config_params(st= ruct iris_inst *inst, u32 p {HFI_PROP_COLOR_FORMAT, iris_hfi_gen2_set_colorformat = }, {HFI_PROP_LINEAR_STRIDE_SCANLINE, iris_hfi_gen2_set_linear_stride_sc= anline }, {HFI_PROP_TIER, iris_hfi_gen2_set_tier = }, + {HFI_PROP_FRAME_RATE, iris_hfi_gen2_set_frame_rate = }, }; =20 - if (V4L2_TYPE_IS_OUTPUT(plane)) { - switch (inst->codec) { - case V4L2_PIX_FMT_H264: - config_params =3D core->iris_platform_data->input_config_params_default; - config_params_size =3D - core->iris_platform_data->input_config_params_default_size; - break; - case V4L2_PIX_FMT_HEVC: - config_params =3D core->iris_platform_data->input_config_params_hevc; - config_params_size =3D - core->iris_platform_data->input_config_params_hevc_size; - break; - case V4L2_PIX_FMT_VP9: - config_params =3D core->iris_platform_data->input_config_params_vp9; - config_params_size =3D - core->iris_platform_data->input_config_params_vp9_size; - break; + if (inst->domain =3D=3D DECODER) { + if (V4L2_TYPE_IS_OUTPUT(plane)) { + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) { + config_params =3D pdata->dec_input_config_params_default; + config_params_size =3D pdata->dec_input_config_params_default_size; + } else if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) { + config_params =3D pdata->dec_input_config_params_hevc; + config_params_size =3D pdata->dec_input_config_params_hevc_size; + } else if (inst->codec =3D=3D V4L2_PIX_FMT_VP9) { + config_params =3D pdata->dec_input_config_params_vp9; + config_params_size =3D pdata->dec_input_config_params_vp9_size; + } else { + return -EINVAL; + } + } else { + config_params =3D pdata->dec_output_config_params; + config_params_size =3D pdata->dec_output_config_params_size; } } else { - config_params =3D core->iris_platform_data->output_config_params; - config_params_size =3D core->iris_platform_data->output_config_params_si= ze; + if (V4L2_TYPE_IS_OUTPUT(plane)) { + config_params =3D pdata->enc_input_config_params; + config_params_size =3D pdata->enc_input_config_params_size; + } else { + config_params =3D pdata->enc_output_config_params; + config_params_size =3D pdata->enc_output_config_params_size; + } } =20 if (!config_params || !config_params_size) @@ -459,7 +548,7 @@ static int iris_hfi_gen2_session_set_config_params(stru= ct iris_inst *inst, u32 p for (i =3D 0; i < config_params_size; i++) { for (j =3D 0; j < ARRAY_SIZE(prop_type_handle_arr); j++) { if (prop_type_handle_arr[j].type =3D=3D config_params[i]) { - ret =3D prop_type_handle_arr[j].handle(inst); + ret =3D prop_type_handle_arr[j].handle(inst, plane); if (ret) return ret; break; @@ -477,14 +566,19 @@ static int iris_hfi_gen2_session_set_codec(struct iri= s_inst *inst) =20 switch (inst->codec) { case V4L2_PIX_FMT_H264: - codec =3D HFI_CODEC_DECODE_AVC; + if (inst->domain =3D=3D ENCODER) + codec =3D HFI_CODEC_ENCODE_AVC; + else + codec =3D HFI_CODEC_DECODE_AVC; break; case V4L2_PIX_FMT_HEVC: - codec =3D HFI_CODEC_DECODE_HEVC; + if (inst->domain =3D=3D ENCODER) + codec =3D HFI_CODEC_ENCODE_HEVC; + else + codec =3D HFI_CODEC_DECODE_HEVC; break; case V4L2_PIX_FMT_VP9: codec =3D HFI_CODEC_DECODE_VP9; - break; } =20 iris_hfi_gen2_packet_session_property(inst, @@ -550,9 +644,11 @@ static int iris_hfi_gen2_session_open(struct iris_inst= *inst) if (ret) goto fail_free_packet; =20 - ret =3D iris_hfi_gen2_session_set_default_header(inst); - if (ret) - goto fail_free_packet; + if (inst->domain =3D=3D DECODER) { + ret =3D iris_hfi_gen2_session_set_default_header(inst); + if (ret) + goto fail_free_packet; + } =20 return 0; =20 @@ -601,7 +697,7 @@ static int iris_hfi_gen2_session_subscribe_mode(struct = iris_inst *inst, cmd, (HFI_HOST_FLAGS_RESPONSE_REQUIRED | HFI_HOST_FLAGS_INTR_REQUIRED), - iris_hfi_gen2_get_port(plane), + iris_hfi_gen2_get_port(inst, plane), inst->session_id, payload_type, payload, @@ -623,6 +719,9 @@ static int iris_hfi_gen2_subscribe_change_param(struct = iris_inst *inst, u32 plan u32 hfi_port =3D 0, i; int ret; =20 + if (inst->domain =3D=3D ENCODER) + return 0; + if ((V4L2_TYPE_IS_OUTPUT(plane) && inst_hfi_gen2->ipsc_properties_set) || (V4L2_TYPE_IS_CAPTURE(plane) && inst_hfi_gen2->opsc_properties_set)) { dev_err(core->dev, "invalid plane\n"); @@ -631,19 +730,19 @@ static int iris_hfi_gen2_subscribe_change_param(struc= t iris_inst *inst, u32 plan =20 switch (inst->codec) { case V4L2_PIX_FMT_H264: - change_param =3D core->iris_platform_data->input_config_params_default; + change_param =3D core->iris_platform_data->dec_input_config_params_defau= lt; change_param_size =3D - core->iris_platform_data->input_config_params_default_size; + core->iris_platform_data->dec_input_config_params_default_size; break; case V4L2_PIX_FMT_HEVC: - change_param =3D core->iris_platform_data->input_config_params_hevc; + change_param =3D core->iris_platform_data->dec_input_config_params_hevc; change_param_size =3D - core->iris_platform_data->input_config_params_hevc_size; + core->iris_platform_data->dec_input_config_params_hevc_size; break; case V4L2_PIX_FMT_VP9: - change_param =3D core->iris_platform_data->input_config_params_vp9; + change_param =3D core->iris_platform_data->dec_input_config_params_vp9; change_param_size =3D - core->iris_platform_data->input_config_params_vp9_size; + core->iris_platform_data->dec_input_config_params_vp9_size; break; } =20 @@ -664,7 +763,7 @@ static int iris_hfi_gen2_subscribe_change_param(struct = iris_inst *inst, u32 plan if (V4L2_TYPE_IS_OUTPUT(plane)) { inst_hfi_gen2->ipsc_properties_set =3D true; } else { - hfi_port =3D iris_hfi_gen2_get_port(V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); + hfi_port =3D iris_hfi_gen2_get_port(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MP= LANE); memcpy(&inst_hfi_gen2->dst_subcr_params, &inst_hfi_gen2->src_subcr_params, sizeof(inst_hfi_gen2->src_subcr_params)); @@ -759,6 +858,9 @@ static int iris_hfi_gen2_subscribe_property(struct iris= _inst *inst, u32 plane) =20 payload[0] =3D HFI_MODE_PROPERTY; =20 + if (inst->domain =3D=3D ENCODER) + return 0; + if (V4L2_TYPE_IS_OUTPUT(plane)) { subscribe_prop_size =3D core->iris_platform_data->dec_input_prop_size; subcribe_prop =3D core->iris_platform_data->dec_input_prop; @@ -810,7 +912,7 @@ static int iris_hfi_gen2_session_start(struct iris_inst= *inst, u32 plane) HFI_CMD_START, (HFI_HOST_FLAGS_RESPONSE_REQUIRED | HFI_HOST_FLAGS_INTR_REQUIRED), - iris_hfi_gen2_get_port(plane), + iris_hfi_gen2_get_port(inst, plane), inst->session_id, HFI_PAYLOAD_NONE, NULL, @@ -832,7 +934,7 @@ static int iris_hfi_gen2_session_stop(struct iris_inst = *inst, u32 plane) (HFI_HOST_FLAGS_RESPONSE_REQUIRED | HFI_HOST_FLAGS_INTR_REQUIRED | HFI_HOST_FLAGS_NON_DISCARDABLE), - iris_hfi_gen2_get_port(plane), + iris_hfi_gen2_get_port(inst, plane), inst->session_id, HFI_PAYLOAD_NONE, NULL, @@ -854,7 +956,7 @@ static int iris_hfi_gen2_session_pause(struct iris_inst= *inst, u32 plane) HFI_CMD_PAUSE, (HFI_HOST_FLAGS_RESPONSE_REQUIRED | HFI_HOST_FLAGS_INTR_REQUIRED), - iris_hfi_gen2_get_port(plane), + iris_hfi_gen2_get_port(inst, plane), inst->session_id, HFI_PAYLOAD_NONE, NULL, @@ -873,7 +975,7 @@ static int iris_hfi_gen2_session_resume_drc(struct iris= _inst *inst, u32 plane) HFI_CMD_RESUME, (HFI_HOST_FLAGS_RESPONSE_REQUIRED | HFI_HOST_FLAGS_INTR_REQUIRED), - iris_hfi_gen2_get_port(plane), + iris_hfi_gen2_get_port(inst, plane), inst->session_id, HFI_PAYLOAD_U32, &payload, @@ -892,7 +994,7 @@ static int iris_hfi_gen2_session_resume_drain(struct ir= is_inst *inst, u32 plane) HFI_CMD_RESUME, (HFI_HOST_FLAGS_RESPONSE_REQUIRED | HFI_HOST_FLAGS_INTR_REQUIRED), - iris_hfi_gen2_get_port(plane), + iris_hfi_gen2_get_port(inst, plane), inst->session_id, HFI_PAYLOAD_U32, &payload, @@ -914,7 +1016,7 @@ static int iris_hfi_gen2_session_drain(struct iris_ins= t *inst, u32 plane) (HFI_HOST_FLAGS_RESPONSE_REQUIRED | HFI_HOST_FLAGS_INTR_REQUIRED | HFI_HOST_FLAGS_NON_DISCARDABLE), - iris_hfi_gen2_get_port(plane), + iris_hfi_gen2_get_port(inst, plane), inst->session_id, HFI_PAYLOAD_NONE, NULL, diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_defines.h index fb6724d7f95ff8858aa9ba093fefb642e89de279..b3d1c966958e516d940a7795e5c= be2f8e8bada57 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h @@ -49,6 +49,7 @@ #define HFI_PROP_TIER 0x03000109 #define HFI_PROP_STAGE 0x0300010a #define HFI_PROP_PIPE 0x0300010b +#define HFI_PROP_FRAME_RATE 0x0300010c #define HFI_PROP_LUMA_CHROMA_BIT_DEPTH 0x0300010f #define HFI_PROP_CODED_FRAMES 0x03000120 #define HFI_PROP_CABAC_SESSION 0x03000121 @@ -69,6 +70,8 @@ #define HFI_PROP_DEC_DEFAULT_HEADER 0x03000168 #define HFI_PROP_DEC_START_FROM_RAP_FRAME 0x03000169 #define HFI_PROP_NO_OUTPUT 0x0300016a +#define HFI_PROP_BUFFER_MARK 0x0300016c +#define HFI_PROP_RAW_RESOLUTION 0x03000178 #define HFI_PROP_TOTAL_PEAK_BITRATE 0x0300017C #define HFI_PROP_COMV_BUFFER_COUNT 0x03000193 #define HFI_PROP_END 0x03FFFFFF diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 6d6a8f3b38271d928d753dd180e6e9a991991d24..0064a90e0e111075341d389fef7= adb8f6b46b46f 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -223,14 +223,18 @@ struct iris_platform_data { u32 max_core_mbpf; /* max number of macroblocks per second supported */ u32 max_core_mbps; - const u32 *input_config_params_default; - unsigned int input_config_params_default_size; - const u32 *input_config_params_hevc; - unsigned int input_config_params_hevc_size; - const u32 *input_config_params_vp9; - unsigned int input_config_params_vp9_size; - const u32 *output_config_params; - unsigned int output_config_params_size; + const u32 *dec_input_config_params_default; + unsigned int dec_input_config_params_default_size; + const u32 *dec_input_config_params_hevc; + unsigned int dec_input_config_params_hevc_size; + const u32 *dec_input_config_params_vp9; + unsigned int dec_input_config_params_vp9_size; + const u32 *dec_output_config_params; + unsigned int dec_output_config_params_size; + const u32 *enc_input_config_params; + unsigned int enc_input_config_params_size; + const u32 *enc_output_config_params; + unsigned int enc_output_config_params_size; const u32 *dec_input_prop; unsigned int dec_input_prop_size; const u32 *dec_output_prop_avc; diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index 4b98c149dc627f37930e6b98e4ada407f6ba637f..d8b818ccd5a512f66f194b24b5f= 6d6609c8c838f 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -656,11 +656,25 @@ static const u32 sm8550_vdec_input_config_param_vp9[]= =3D { HFI_PROP_LEVEL, }; =20 +static const u32 sm8550_venc_input_config_params[] =3D { + HFI_PROP_COLOR_FORMAT, + HFI_PROP_RAW_RESOLUTION, + HFI_PROP_CROP_OFFSETS, + HFI_PROP_LINEAR_STRIDE_SCANLINE, + HFI_PROP_SIGNAL_COLOR_INFO, +}; + static const u32 sm8550_vdec_output_config_params[] =3D { HFI_PROP_COLOR_FORMAT, HFI_PROP_LINEAR_STRIDE_SCANLINE, }; =20 +static const u32 sm8550_venc_output_config_params[] =3D { + HFI_PROP_BITSTREAM_RESOLUTION, + HFI_PROP_CROP_OFFSETS, + HFI_PROP_FRAME_RATE, +}; + static const u32 sm8550_vdec_subscribe_input_properties[] =3D { HFI_PROP_NO_OUTPUT, }; @@ -724,22 +738,32 @@ struct iris_platform_data sm8550_data =3D { .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K * 2, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, - .input_config_params_default =3D + .dec_input_config_params_default =3D sm8550_vdec_input_config_params_default, - .input_config_params_default_size =3D + .dec_input_config_params_default_size =3D ARRAY_SIZE(sm8550_vdec_input_config_params_default), - .input_config_params_hevc =3D + .dec_input_config_params_hevc =3D sm8550_vdec_input_config_param_hevc, - .input_config_params_hevc_size =3D + .dec_input_config_params_hevc_size =3D ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), - .input_config_params_vp9 =3D + .dec_input_config_params_vp9 =3D sm8550_vdec_input_config_param_vp9, - .input_config_params_vp9_size =3D + .dec_input_config_params_vp9_size =3D ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), - .output_config_params =3D + .dec_output_config_params =3D sm8550_vdec_output_config_params, - .output_config_params_size =3D + .dec_output_config_params_size =3D ARRAY_SIZE(sm8550_vdec_output_config_params), + + .enc_input_config_params =3D + sm8550_venc_input_config_params, + .enc_input_config_params_size =3D + ARRAY_SIZE(sm8550_venc_input_config_params), + .enc_output_config_params =3D + sm8550_venc_output_config_params, + .enc_output_config_params_size =3D + ARRAY_SIZE(sm8550_venc_output_config_params), + .dec_input_prop =3D sm8550_vdec_subscribe_input_properties, .dec_input_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_input_propertie= s), .dec_output_prop_avc =3D sm8550_vdec_subscribe_output_properties_avc, @@ -802,22 +826,32 @@ struct iris_platform_data sm8650_data =3D { .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K * 2, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, - .input_config_params_default =3D + .dec_input_config_params_default =3D sm8550_vdec_input_config_params_default, - .input_config_params_default_size =3D + .dec_input_config_params_default_size =3D ARRAY_SIZE(sm8550_vdec_input_config_params_default), - .input_config_params_hevc =3D + .dec_input_config_params_hevc =3D sm8550_vdec_input_config_param_hevc, - .input_config_params_hevc_size =3D + .dec_input_config_params_hevc_size =3D ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), - .input_config_params_vp9 =3D + .dec_input_config_params_vp9 =3D sm8550_vdec_input_config_param_vp9, - .input_config_params_vp9_size =3D + .dec_input_config_params_vp9_size =3D ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), - .output_config_params =3D + .dec_output_config_params =3D sm8550_vdec_output_config_params, - .output_config_params_size =3D + .dec_output_config_params_size =3D ARRAY_SIZE(sm8550_vdec_output_config_params), + + .enc_input_config_params =3D + sm8550_venc_input_config_params, + .enc_input_config_params_size =3D + ARRAY_SIZE(sm8550_venc_input_config_params), + .enc_output_config_params =3D + sm8550_venc_output_config_params, + .enc_output_config_params_size =3D + ARRAY_SIZE(sm8550_venc_output_config_params), + .dec_input_prop =3D sm8550_vdec_subscribe_input_properties, .dec_input_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_input_propertie= s), .dec_output_prop_avc =3D sm8550_vdec_subscribe_output_properties_avc, @@ -876,22 +910,32 @@ struct iris_platform_data qcs8300_data =3D { .max_session_count =3D 16, .max_core_mbpf =3D ((4096 * 2176) / 256) * 4, .max_core_mbps =3D (((3840 * 2176) / 256) * 120), - .input_config_params_default =3D + .dec_input_config_params_default =3D sm8550_vdec_input_config_params_default, - .input_config_params_default_size =3D + .dec_input_config_params_default_size =3D ARRAY_SIZE(sm8550_vdec_input_config_params_default), - .input_config_params_hevc =3D + .dec_input_config_params_hevc =3D sm8550_vdec_input_config_param_hevc, - .input_config_params_hevc_size =3D + .dec_input_config_params_hevc_size =3D ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), - .input_config_params_vp9 =3D + .dec_input_config_params_vp9 =3D sm8550_vdec_input_config_param_vp9, - .input_config_params_vp9_size =3D + .dec_input_config_params_vp9_size =3D ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), - .output_config_params =3D + .dec_output_config_params =3D sm8550_vdec_output_config_params, - .output_config_params_size =3D + .dec_output_config_params_size =3D ARRAY_SIZE(sm8550_vdec_output_config_params), + + .enc_input_config_params =3D + sm8550_venc_input_config_params, + .enc_input_config_params_size =3D + ARRAY_SIZE(sm8550_venc_input_config_params), + .enc_output_config_params =3D + sm8550_venc_output_config_params, + .enc_output_config_params_size =3D + ARRAY_SIZE(sm8550_venc_output_config_params), + .dec_input_prop =3D sm8550_vdec_subscribe_input_properties, .dec_input_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_input_propertie= s), .dec_output_prop_avc =3D sm8550_vdec_subscribe_output_properties_avc, diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/driv= ers/media/platform/qcom/iris/iris_platform_sm8250.c index 49947d8c58a94cc6caf7e10ca0393dd733e27919..746b201ededbdb194e833f339e4= 9c24d24b58981 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c @@ -38,6 +38,14 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8250_de= c[] =3D { }; =20 static struct platform_inst_fw_cap inst_fw_cap_sm8250_enc[] =3D { + { + .cap_id =3D STAGE, + .min =3D STAGE_1, + .max =3D STAGE_2, + .step_or_mask =3D 1, + .value =3D STAGE_2, + .hfi_id =3D HFI_PROPERTY_PARAM_WORK_MODE, + }, { .cap_id =3D PROFILE_H264, .min =3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, @@ -268,6 +276,14 @@ static const u32 sm8250_vdec_input_config_param_defaul= t[] =3D { HFI_PROPERTY_PARAM_BUFFER_ALLOC_MODE, }; =20 +static const u32 sm8250_venc_input_config_param[] =3D { + HFI_PROPERTY_CONFIG_FRAME_RATE, + HFI_PROPERTY_PARAM_UNCOMPRESSED_PLANE_ACTUAL_INFO, + HFI_PROPERTY_PARAM_FRAME_SIZE, + HFI_PROPERTY_PARAM_UNCOMPRESSED_FORMAT_SELECT, + HFI_PROPERTY_PARAM_BUFFER_COUNT_ACTUAL, +}; + static const u32 sm8250_dec_ip_int_buf_tbl[] =3D { BUF_BIN, BUF_SCRATCH_1, @@ -310,10 +326,13 @@ struct iris_platform_data sm8250_data =3D { .max_session_count =3D 16, .max_core_mbpf =3D NUM_MBS_8K, .max_core_mbps =3D ((7680 * 4320) / 256) * 60, - .input_config_params_default =3D + .dec_input_config_params_default =3D sm8250_vdec_input_config_param_default, - .input_config_params_default_size =3D + .dec_input_config_params_default_size =3D ARRAY_SIZE(sm8250_vdec_input_config_param_default), + .enc_input_config_params =3D sm8250_venc_input_config_param, + .enc_input_config_params_size =3D + ARRAY_SIZE(sm8250_venc_input_config_param), =20 .dec_ip_int_buf_tbl =3D sm8250_dec_ip_int_buf_tbl, .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl), diff --git a/drivers/media/platform/qcom/iris/iris_vb2.c b/drivers/media/pl= atform/qcom/iris/iris_vb2.c index e32f7e1f007228a3b2b51cd76cd193d852f16080..fbf8ebb74193284dc847c54f76f= 908656b3098c9 100644 --- a/drivers/media/platform/qcom/iris/iris_vb2.c +++ b/drivers/media/platform/qcom/iris/iris_vb2.c @@ -7,9 +7,11 @@ #include #include =20 +#include "iris_common.h" #include "iris_instance.h" #include "iris_vb2.h" #include "iris_vdec.h" +#include "iris_venc.h" #include "iris_power.h" =20 static int iris_check_inst_mbpf(struct iris_inst *inst) @@ -174,19 +176,35 @@ int iris_vb2_start_streaming(struct vb2_queue *q, uns= igned int count) if (ret) goto error; =20 - if (V4L2_TYPE_IS_OUTPUT(q->type)) - ret =3D iris_vdec_streamon_input(inst); - else if (V4L2_TYPE_IS_CAPTURE(q->type)) - ret =3D iris_vdec_streamon_output(inst); + if (V4L2_TYPE_IS_OUTPUT(q->type)) { + if (inst->domain =3D=3D DECODER) + ret =3D iris_vdec_streamon_input(inst); + else + ret =3D iris_venc_streamon_input(inst); + } else if (V4L2_TYPE_IS_CAPTURE(q->type)) { + if (inst->domain =3D=3D DECODER) + ret =3D iris_vdec_streamon_output(inst); + else + ret =3D iris_venc_streamon_output(inst); + } if (ret) goto error; =20 buf_type =3D iris_v4l2_type_to_driver(q->type); =20 - if (inst->state =3D=3D IRIS_INST_STREAMING) - ret =3D iris_queue_internal_deferred_buffers(inst, BUF_DPB); - if (!ret) - ret =3D iris_queue_deferred_buffers(inst, buf_type); + if (inst->domain =3D=3D DECODER) { + if (inst->state =3D=3D IRIS_INST_STREAMING) + ret =3D iris_queue_internal_deferred_buffers(inst, BUF_DPB); + if (!ret) + ret =3D iris_queue_deferred_buffers(inst, buf_type); + } else { + if (inst->state =3D=3D IRIS_INST_STREAMING) { + ret =3D iris_queue_deferred_buffers(inst, BUF_INPUT); + if (!ret) + ret =3D iris_queue_deferred_buffers(inst, BUF_OUTPUT); + } + } + if (ret) goto error; =20 @@ -218,7 +236,7 @@ void iris_vb2_stop_streaming(struct vb2_queue *q) !V4L2_TYPE_IS_CAPTURE(q->type)) goto exit; =20 - ret =3D iris_vdec_session_streamoff(inst, q->type); + ret =3D iris_session_streamoff(inst, q->type); if (ret) goto exit; =20 diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/p= latform/qcom/iris/iris_vdec.c index 338c7524c19de8456f0f2b0286bafcd89be52b72..92142a452be630c5e5226cea0f4= 81c2d9f8b765f 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.c +++ b/drivers/media/platform/qcom/iris/iris_vdec.c @@ -7,6 +7,7 @@ #include =20 #include "iris_buffer.h" +#include "iris_common.h" #include "iris_ctrls.h" #include "iris_instance.h" #include "iris_power.h" @@ -312,125 +313,6 @@ void iris_vdec_src_change(struct iris_inst *inst) v4l2_event_queue_fh(&inst->fh, &event); } =20 - -static void iris_vdec_flush_deferred_buffers(struct iris_inst *inst, - enum iris_buffer_type type) -{ - struct v4l2_m2m_ctx *m2m_ctx =3D inst->m2m_ctx; - struct v4l2_m2m_buffer *buffer, *n; - struct iris_buffer *buf; - - if (type =3D=3D BUF_INPUT) { - v4l2_m2m_for_each_src_buf_safe(m2m_ctx, buffer, n) { - buf =3D to_iris_buffer(&buffer->vb); - if (buf->attr & BUF_ATTR_DEFERRED) { - if (!(buf->attr & BUF_ATTR_BUFFER_DONE)) { - buf->attr |=3D BUF_ATTR_BUFFER_DONE; - buf->data_size =3D 0; - iris_vb2_buffer_done(inst, buf); - } - } - } - } else { - v4l2_m2m_for_each_dst_buf_safe(m2m_ctx, buffer, n) { - buf =3D to_iris_buffer(&buffer->vb); - if (buf->attr & BUF_ATTR_DEFERRED) { - if (!(buf->attr & BUF_ATTR_BUFFER_DONE)) { - buf->attr |=3D BUF_ATTR_BUFFER_DONE; - buf->data_size =3D 0; - iris_vb2_buffer_done(inst, buf); - } - } - } - } -} - -static void iris_vdec_kill_session(struct iris_inst *inst) -{ - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; - - if (!inst->session_id) - return; - - hfi_ops->session_close(inst); - iris_inst_change_state(inst, IRIS_INST_ERROR); -} - -int iris_vdec_session_streamoff(struct iris_inst *inst, u32 plane) -{ - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; - enum iris_buffer_type buffer_type; - int ret; - - switch (plane) { - case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE: - buffer_type =3D BUF_INPUT; - break; - case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE: - buffer_type =3D BUF_OUTPUT; - break; - default: - return -EINVAL; - } - - ret =3D hfi_ops->session_stop(inst, plane); - if (ret) - goto error; - - ret =3D iris_inst_state_change_streamoff(inst, plane); - if (ret) - goto error; - - iris_vdec_flush_deferred_buffers(inst, buffer_type); - - return 0; - -error: - iris_vdec_kill_session(inst); - iris_vdec_flush_deferred_buffers(inst, buffer_type); - - return ret; -} - -static int iris_vdec_process_streamon_input(struct iris_inst *inst) -{ - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; - enum iris_inst_sub_state set_sub_state =3D 0; - int ret; - - iris_scale_power(inst); - - ret =3D hfi_ops->session_start(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); - if (ret) - return ret; - - if (inst->sub_state & IRIS_INST_SUB_INPUT_PAUSE) { - ret =3D iris_inst_change_sub_state(inst, IRIS_INST_SUB_INPUT_PAUSE, 0); - if (ret) - return ret; - } - - if (inst->sub_state & IRIS_INST_SUB_DRC || - inst->sub_state & IRIS_INST_SUB_DRAIN || - inst->sub_state & IRIS_INST_SUB_FIRST_IPSC) { - if (!(inst->sub_state & IRIS_INST_SUB_INPUT_PAUSE)) { - if (hfi_ops->session_pause) { - ret =3D hfi_ops->session_pause(inst, - V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); - if (ret) - return ret; - } - set_sub_state =3D IRIS_INST_SUB_INPUT_PAUSE; - } - } - - ret =3D iris_inst_state_change_streamon(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_= MPLANE); - if (ret) - return ret; - - return iris_inst_change_sub_state(inst, 0, set_sub_state); -} - int iris_vdec_streamon_input(struct iris_inst *inst) { int ret; @@ -457,71 +339,7 @@ int iris_vdec_streamon_input(struct iris_inst *inst) if (ret) return ret; =20 - return iris_vdec_process_streamon_input(inst); -} - -static int iris_vdec_process_streamon_output(struct iris_inst *inst) -{ - const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; - bool drain_active =3D false, drc_active =3D false; - enum iris_inst_sub_state clear_sub_state =3D 0; - int ret =3D 0; - - iris_scale_power(inst); - - drain_active =3D inst->sub_state & IRIS_INST_SUB_DRAIN && - inst->sub_state & IRIS_INST_SUB_DRAIN_LAST; - - drc_active =3D inst->sub_state & IRIS_INST_SUB_DRC && - inst->sub_state & IRIS_INST_SUB_DRC_LAST; - - if (drc_active) - clear_sub_state =3D IRIS_INST_SUB_DRC | IRIS_INST_SUB_DRC_LAST; - else if (drain_active) - clear_sub_state =3D IRIS_INST_SUB_DRAIN | IRIS_INST_SUB_DRAIN_LAST; - - if (inst->sub_state & IRIS_INST_SUB_INPUT_PAUSE) { - ret =3D iris_alloc_and_queue_input_int_bufs(inst); - if (ret) - return ret; - ret =3D iris_set_stage(inst, STAGE); - if (ret) - return ret; - ret =3D iris_set_pipe(inst, PIPE); - if (ret) - return ret; - } - - if (inst->state =3D=3D IRIS_INST_INPUT_STREAMING && - inst->sub_state & IRIS_INST_SUB_INPUT_PAUSE) { - if (!drain_active) - ret =3D hfi_ops->session_resume_drc(inst, - V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); - else if (hfi_ops->session_resume_drain) - ret =3D hfi_ops->session_resume_drain(inst, - V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); - if (ret) - return ret; - clear_sub_state |=3D IRIS_INST_SUB_INPUT_PAUSE; - } - - if (inst->sub_state & IRIS_INST_SUB_FIRST_IPSC) - clear_sub_state |=3D IRIS_INST_SUB_FIRST_IPSC; - - ret =3D hfi_ops->session_start(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); - if (ret) - return ret; - - if (inst->sub_state & IRIS_INST_SUB_OUTPUT_PAUSE) - clear_sub_state |=3D IRIS_INST_SUB_OUTPUT_PAUSE; - - ret =3D iris_inst_state_change_streamon(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE= _MPLANE); - if (ret) - return ret; - - inst->last_buffer_dequeued =3D false; - - return iris_inst_change_sub_state(inst, clear_sub_state, 0); + return iris_process_streamon_input(inst); } =20 int iris_vdec_streamon_output(struct iris_inst *inst) @@ -543,7 +361,7 @@ int iris_vdec_streamon_output(struct iris_inst *inst) if (ret) return ret; =20 - ret =3D iris_vdec_process_streamon_output(inst); + ret =3D iris_process_streamon_output(inst); if (ret) goto error; =20 @@ -554,7 +372,7 @@ int iris_vdec_streamon_output(struct iris_inst *inst) return ret; =20 error: - iris_vdec_session_streamoff(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); + iris_session_streamoff(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); =20 return ret; } diff --git a/drivers/media/platform/qcom/iris/iris_vdec.h b/drivers/media/p= latform/qcom/iris/iris_vdec.h index 097e02bfa72b5ac4e46e66c61842df1d9dd4565b..ec1ce55d1375fd6518983baae2a= cf0fc43b6cabd 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.h +++ b/drivers/media/platform/qcom/iris/iris_vdec.h @@ -21,6 +21,5 @@ int iris_vdec_streamon_output(struct iris_inst *inst); int iris_vdec_qbuf(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf); int iris_vdec_start_cmd(struct iris_inst *inst); int iris_vdec_stop_cmd(struct iris_inst *inst); -int iris_vdec_session_streamoff(struct iris_inst *inst, u32 plane); =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_venc.c b/drivers/media/p= latform/qcom/iris/iris_venc.c index 16cc753bd31aaf51ff29c2578da5395925e31ccf..d5c5c28bf2b0c734451461f573c= 2cc6130686361 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.c +++ b/drivers/media/platform/qcom/iris/iris_venc.c @@ -7,6 +7,7 @@ #include =20 #include "iris_buffer.h" +#include "iris_common.h" #include "iris_ctrls.h" #include "iris_instance.h" #include "iris_venc.h" @@ -425,3 +426,34 @@ int iris_venc_g_param(struct iris_inst *inst, struct v= 4l2_streamparm *s_parm) =20 return 0; } + +int iris_venc_streamon_input(struct iris_inst *inst) +{ + int ret; + + ret =3D iris_set_properties(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); + if (ret) + return ret; + + return iris_process_streamon_input(inst); +} + +int iris_venc_streamon_output(struct iris_inst *inst) +{ + int ret; + + ret =3D iris_set_properties(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); + if (ret) + goto error; + + ret =3D iris_process_streamon_output(inst); + if (ret) + goto error; + + return ret; + +error: + iris_session_streamoff(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); + + return ret; +} diff --git a/drivers/media/platform/qcom/iris/iris_venc.h b/drivers/media/p= latform/qcom/iris/iris_venc.h index 0d566b7fc89b96b8fbc62a35b2ba795ca0bcf460..941b5c186e4550e3eb6325d5ae3= eeac4fcee4675 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.h +++ b/drivers/media/platform/qcom/iris/iris_venc.h @@ -18,5 +18,7 @@ int iris_venc_subscribe_event(struct iris_inst *inst, con= st struct v4l2_event_su int iris_venc_s_selection(struct iris_inst *inst, struct v4l2_selection *s= ); int iris_venc_g_param(struct iris_inst *inst, struct v4l2_streamparm *s_pa= rm); int iris_venc_s_param(struct iris_inst *inst, struct v4l2_streamparm *s_pa= rm); +int iris_venc_streamon_input(struct iris_inst *inst); +int iris_venc_streamon_output(struct iris_inst *inst); =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/p= latform/qcom/iris/iris_vidc.c index 6e3bd02afe44534a8f36cc22d9c8cda4a53a05cd..7bea310e68dcd811e873005df56= 2fef24a2ec3f0 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -656,6 +656,8 @@ static const struct v4l2_ioctl_ops iris_v4l2_ioctl_ops_= enc =3D { .vidioc_s_selection =3D iris_s_selection, .vidioc_s_parm =3D iris_s_parm, .vidioc_g_parm =3D iris_g_parm, + .vidioc_streamon =3D v4l2_m2m_ioctl_streamon, + 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definitions=2025-08-25_03,2025-08-20_03,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 bulkscore=0 clxscore=1015 adultscore=0 impostorscore=0 priorityscore=1501 phishscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508230034 Initialize and configure platform-specific capabilities for the encoder in the firmware during stream-on, to tailor encoding behavior to the current session's requirements. Some of these capabilities can also be updated dynamically when V4L2 controls are modified by the client after stream-on. Tested-by: Vikash Garodia # X1E80100 Reviewed-by: Vikash Garodia Tested-by: Neil Armstrong # on SM8550-HDK Tested-by: Neil Armstrong # on SM8650-HDK Signed-off-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e80100-crd --- drivers/media/platform/qcom/iris/iris_buffer.c | 8 + drivers/media/platform/qcom/iris/iris_ctrls.c | 500 +++++++++++++++++= +++- drivers/media/platform/qcom/iris/iris_ctrls.h | 15 + .../platform/qcom/iris/iris_hfi_gen1_command.c | 108 +++++ .../platform/qcom/iris/iris_hfi_gen1_defines.h | 47 +- .../platform/qcom/iris/iris_hfi_gen1_response.c | 8 +- .../platform/qcom/iris/iris_hfi_gen2_defines.h | 32 +- .../platform/qcom/iris/iris_hfi_gen2_response.c | 9 +- drivers/media/platform/qcom/iris/iris_instance.h | 3 +- .../media/platform/qcom/iris/iris_platform_gen2.c | 23 + .../platform/qcom/iris/iris_platform_sm8250.c | 14 + 11 files changed, 737 insertions(+), 30 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media= /platform/qcom/iris/iris_buffer.c index 6bf9b0b35d206d51b927c824d5a5b327596251c6..8811174bfdc0ad5288aa4eb5fab= 9d9df876c78c9 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -227,10 +227,14 @@ static u32 iris_dec_bitstream_buffer_size(struct iris= _inst *inst) static u32 iris_enc_bitstream_buffer_size(struct iris_inst *inst) { u32 aligned_width, aligned_height, bitstream_size, yuv_size; + int bitrate_mode, frame_rc; struct v4l2_format *f; =20 f =3D inst->fmt_dst; =20 + bitrate_mode =3D inst->fw_caps[BITRATE_MODE].value; + frame_rc =3D inst->fw_caps[FRAME_RC_ENABLE].value; + aligned_width =3D ALIGN(f->fmt.pix_mp.width, 32); aligned_height =3D ALIGN(f->fmt.pix_mp.height, 32); bitstream_size =3D aligned_width * aligned_height * 3; @@ -242,6 +246,10 @@ static u32 iris_enc_bitstream_buffer_size(struct iris_= inst *inst) /* bitstream_size =3D 0.5 * yuv_size; */ bitstream_size =3D (bitstream_size >> 2); =20 + if ((!frame_rc || bitrate_mode =3D=3D V4L2_MPEG_VIDEO_BITRATE_MODE_CQ) && + bitstream_size < yuv_size) + bitstream_size =3D (bitstream_size << 1); + return ALIGN(bitstream_size, 4096); } =20 diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.c b/drivers/media/= platform/qcom/iris/iris_ctrls.c index 797386cb96ab1d24be6cc1819e2f9202ab4cc224..754a5ad718bc37630bb86101230= 1df7a2e7342a1 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.c +++ b/drivers/media/platform/qcom/iris/iris_ctrls.c @@ -7,8 +7,13 @@ #include =20 #include "iris_ctrls.h" +#include "iris_hfi_gen1_defines.h" +#include "iris_hfi_gen2_defines.h" #include "iris_instance.h" =20 +#define CABAC_MAX_BITRATE 160000000 +#define CAVLC_MAX_BITRATE 220000000 + static inline bool iris_valid_cap_id(enum platform_inst_fw_cap_type cap_id) { return cap_id >=3D 1 && cap_id < INST_FW_CAP_MAX; @@ -185,7 +190,7 @@ static u32 iris_get_v4l2_id(enum platform_inst_fw_cap_t= ype cap_id) } } =20 -static int iris_vdec_op_s_ctrl(struct v4l2_ctrl *ctrl) +static int iris_op_s_ctrl(struct v4l2_ctrl *ctrl) { struct iris_inst *inst =3D container_of(ctrl->handler, struct iris_inst, = ctrl_handler); enum platform_inst_fw_cap_type cap_id; @@ -206,11 +211,16 @@ static int iris_vdec_op_s_ctrl(struct v4l2_ctrl *ctrl) =20 inst->fw_caps[cap_id].value =3D ctrl->val; =20 + if (vb2_is_streaming(q)) { + if (cap[cap_id].set) + cap[cap_id].set(inst, cap_id); + } + return 0; } =20 static const struct v4l2_ctrl_ops iris_ctrl_ops =3D { - .s_ctrl =3D iris_vdec_op_s_ctrl, + .s_ctrl =3D iris_op_s_ctrl, }; =20 int iris_ctrls_init(struct iris_inst *inst) @@ -327,16 +337,24 @@ void iris_session_init_caps(struct iris_core *core) core->inst_fw_caps_enc[cap_id].value =3D caps[i].value; core->inst_fw_caps_enc[cap_id].flags =3D caps[i].flags; core->inst_fw_caps_enc[cap_id].hfi_id =3D caps[i].hfi_id; + core->inst_fw_caps_enc[cap_id].set =3D caps[i].set; } } =20 static u32 iris_get_port_info(struct iris_inst *inst, enum platform_inst_fw_cap_type cap_id) { - if (inst->fw_caps[cap_id].flags & CAP_FLAG_INPUT_PORT) - return HFI_PORT_BITSTREAM; - else if (inst->fw_caps[cap_id].flags & CAP_FLAG_OUTPUT_PORT) - return HFI_PORT_RAW; + if (inst->domain =3D=3D DECODER) { + if (inst->fw_caps[cap_id].flags & CAP_FLAG_INPUT_PORT) + return HFI_PORT_BITSTREAM; + else if (inst->fw_caps[cap_id].flags & CAP_FLAG_OUTPUT_PORT) + return HFI_PORT_RAW; + } else { + if (inst->fw_caps[cap_id].flags & CAP_FLAG_INPUT_PORT) + return HFI_PORT_RAW; + else if (inst->fw_caps[cap_id].flags & CAP_FLAG_OUTPUT_PORT) + return HFI_PORT_BITSTREAM; + } =20 return HFI_PORT_NONE; } @@ -376,8 +394,10 @@ int iris_set_stage(struct iris_inst *inst, enum platfo= rm_inst_fw_cap_type cap_id u32 width =3D inp_f->fmt.pix_mp.width; u32 work_mode =3D STAGE_2; =20 - if (iris_res_is_less_than(width, height, 1280, 720)) - work_mode =3D STAGE_1; + if (inst->domain =3D=3D DECODER) { + if (iris_res_is_less_than(width, height, 1280, 720)) + work_mode =3D STAGE_1; + } =20 return hfi_ops->session_set_property(inst, hfi_id, HFI_HOST_FLAGS_NONE, @@ -399,6 +419,470 @@ int iris_set_pipe(struct iris_inst *inst, enum platfo= rm_inst_fw_cap_type cap_id) &work_route, sizeof(u32)); } =20 +int iris_set_profile(struct iris_inst *inst, enum platform_inst_fw_cap_typ= e cap_id) +{ + const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + u32 hfi_id, hfi_value; + + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) { + hfi_id =3D inst->fw_caps[PROFILE_H264].hfi_id; + hfi_value =3D inst->fw_caps[PROFILE_H264].value; + } else { + hfi_id =3D inst->fw_caps[PROFILE_HEVC].hfi_id; + hfi_value =3D inst->fw_caps[PROFILE_HEVC].value; + } + + return hfi_ops->session_set_property(inst, hfi_id, + HFI_HOST_FLAGS_NONE, + iris_get_port_info(inst, cap_id), + HFI_PAYLOAD_U32_ENUM, + &hfi_value, sizeof(u32)); +} + +int iris_set_level(struct iris_inst *inst, enum platform_inst_fw_cap_type = cap_id) +{ + const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + u32 hfi_id, hfi_value; + + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) { + hfi_id =3D inst->fw_caps[LEVEL_H264].hfi_id; + hfi_value =3D inst->fw_caps[LEVEL_H264].value; + } else { + hfi_id =3D inst->fw_caps[LEVEL_HEVC].hfi_id; + hfi_value =3D inst->fw_caps[LEVEL_HEVC].value; + } + + return hfi_ops->session_set_property(inst, hfi_id, + HFI_HOST_FLAGS_NONE, + iris_get_port_info(inst, cap_id), + HFI_PAYLOAD_U32_ENUM, + &hfi_value, sizeof(u32)); +} + +int iris_set_profile_level_gen1(struct iris_inst *inst, enum platform_inst= _fw_cap_type cap_id) +{ + const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + struct hfi_profile_level pl; + + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) { + pl.profile =3D inst->fw_caps[PROFILE_H264].value; + pl.level =3D inst->fw_caps[LEVEL_H264].value; + } else { + pl.profile =3D inst->fw_caps[PROFILE_HEVC].value; + pl.level =3D inst->fw_caps[LEVEL_HEVC].value; + } + + return hfi_ops->session_set_property(inst, hfi_id, + HFI_HOST_FLAGS_NONE, + iris_get_port_info(inst, cap_id), + HFI_PAYLOAD_U32_ENUM, + &pl, sizeof(u32)); +} + +int iris_set_header_mode_gen1(struct iris_inst *inst, enum platform_inst_f= w_cap_type cap_id) +{ + const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + u32 header_mode =3D inst->fw_caps[cap_id].value; + u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + u32 hfi_val; + + if (header_mode =3D=3D V4L2_MPEG_VIDEO_HEADER_MODE_SEPARATE) + hfi_val =3D 0; + else + hfi_val =3D 1; + + return hfi_ops->session_set_property(inst, hfi_id, + HFI_HOST_FLAGS_NONE, + iris_get_port_info(inst, cap_id), + HFI_PAYLOAD_U32, + &hfi_val, sizeof(u32)); +} + +int iris_set_header_mode_gen2(struct iris_inst *inst, enum platform_inst_f= w_cap_type cap_id) +{ + const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + u32 prepend_sps_pps =3D inst->fw_caps[PREPEND_SPSPPS_TO_IDR].value; + u32 header_mode =3D inst->fw_caps[cap_id].value; + u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + u32 hfi_val; + + if (prepend_sps_pps) + hfi_val =3D HFI_SEQ_HEADER_PREFIX_WITH_SYNC_FRAME; + else if (header_mode =3D=3D V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_F= RAME) + hfi_val =3D HFI_SEQ_HEADER_JOINED_WITH_1ST_FRAME; + else + hfi_val =3D HFI_SEQ_HEADER_SEPERATE_FRAME; + + return hfi_ops->session_set_property(inst, hfi_id, + HFI_HOST_FLAGS_NONE, + iris_get_port_info(inst, cap_id), + HFI_PAYLOAD_U32_ENUM, + &hfi_val, sizeof(u32)); +} + +int iris_set_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_typ= e cap_id) +{ + const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + u32 entropy_mode =3D inst->fw_caps[ENTROPY_MODE].value; + u32 bitrate =3D inst->fw_caps[cap_id].value; + u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + u32 max_bitrate; + + if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) + max_bitrate =3D CABAC_MAX_BITRATE; + + if (entropy_mode =3D=3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC) + max_bitrate =3D CABAC_MAX_BITRATE; + else + max_bitrate =3D CAVLC_MAX_BITRATE; + + bitrate =3D min(bitrate, max_bitrate); + + return hfi_ops->session_set_property(inst, hfi_id, + HFI_HOST_FLAGS_NONE, + iris_get_port_info(inst, cap_id), + HFI_PAYLOAD_U32, + &bitrate, sizeof(u32)); +} + +int iris_set_peak_bitrate(struct iris_inst *inst, enum platform_inst_fw_ca= p_type cap_id) +{ + const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + u32 rc_mode =3D inst->fw_caps[BITRATE_MODE].value; + u32 peak_bitrate =3D inst->fw_caps[cap_id].value; + u32 bitrate =3D inst->fw_caps[BITRATE].value; + u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + + if (rc_mode !=3D V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) + return 0; + + if (inst->fw_caps[cap_id].flags & CAP_FLAG_CLIENT_SET) { + if (peak_bitrate < bitrate) + peak_bitrate =3D bitrate; + } else { + peak_bitrate =3D bitrate; + } + + inst->fw_caps[cap_id].value =3D peak_bitrate; + + return hfi_ops->session_set_property(inst, hfi_id, + HFI_HOST_FLAGS_NONE, + iris_get_port_info(inst, cap_id), + HFI_PAYLOAD_U32, + &peak_bitrate, sizeof(u32)); +} + +int iris_set_bitrate_mode_gen1(struct iris_inst *inst, enum platform_inst_= fw_cap_type cap_id) +{ + const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + u32 bitrate_mode =3D inst->fw_caps[BITRATE_MODE].value; + u32 frame_rc =3D inst->fw_caps[FRAME_RC_ENABLE].value; + u32 frame_skip =3D inst->fw_caps[FRAME_SKIP_MODE].value; + u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + u32 rc_mode =3D 0; + + if (!frame_rc) + rc_mode =3D HFI_RATE_CONTROL_OFF; + else if (bitrate_mode =3D=3D V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) + rc_mode =3D frame_skip ? HFI_RATE_CONTROL_VBR_VFR : HFI_RATE_CONTROL_VBR= _CFR; + else if (bitrate_mode =3D=3D V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) + rc_mode =3D frame_skip ? HFI_RATE_CONTROL_CBR_VFR : HFI_RATE_CONTROL_CBR= _CFR; + else if (bitrate_mode =3D=3D V4L2_MPEG_VIDEO_BITRATE_MODE_CQ) + rc_mode =3D HFI_RATE_CONTROL_CQ; + + inst->hfi_rc_type =3D rc_mode; + + return hfi_ops->session_set_property(inst, hfi_id, + HFI_HOST_FLAGS_NONE, + iris_get_port_info(inst, cap_id), + HFI_PAYLOAD_U32_ENUM, + &rc_mode, sizeof(u32)); +} + +int iris_set_bitrate_mode_gen2(struct iris_inst *inst, enum platform_inst_= fw_cap_type cap_id) +{ + const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + u32 bitrate_mode =3D inst->fw_caps[BITRATE_MODE].value; + u32 frame_rc =3D inst->fw_caps[FRAME_RC_ENABLE].value; + u32 frame_skip =3D inst->fw_caps[FRAME_SKIP_MODE].value; + u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + u32 rc_mode =3D 0; + + if (!frame_rc) + rc_mode =3D HFI_RC_OFF; + else if (bitrate_mode =3D=3D V4L2_MPEG_VIDEO_BITRATE_MODE_VBR) + rc_mode =3D HFI_RC_VBR_CFR; + else if (bitrate_mode =3D=3D V4L2_MPEG_VIDEO_BITRATE_MODE_CBR) + rc_mode =3D frame_skip ? HFI_RC_CBR_VFR : HFI_RC_CBR_CFR; + else if (bitrate_mode =3D=3D V4L2_MPEG_VIDEO_BITRATE_MODE_CQ) + rc_mode =3D HFI_RC_CQ; + + inst->hfi_rc_type =3D rc_mode; + + return hfi_ops->session_set_property(inst, hfi_id, + HFI_HOST_FLAGS_NONE, + iris_get_port_info(inst, cap_id), + HFI_PAYLOAD_U32_ENUM, + &rc_mode, sizeof(u32)); +} + +int iris_set_entropy_mode_gen1(struct iris_inst *inst, enum platform_inst_= fw_cap_type cap_id) +{ + const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + u32 entropy_mode =3D inst->fw_caps[cap_id].value; + u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + u32 hfi_val; + + if (inst->codec !=3D V4L2_PIX_FMT_H264) + return 0; + + hfi_val =3D (entropy_mode =3D=3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC)= ? + HFI_H264_ENTROPY_CAVLC : HFI_H264_ENTROPY_CABAC; + + return hfi_ops->session_set_property(inst, hfi_id, + HFI_HOST_FLAGS_NONE, + iris_get_port_info(inst, cap_id), + HFI_PAYLOAD_U32, + &hfi_val, sizeof(u32)); +} + +int iris_set_entropy_mode_gen2(struct iris_inst *inst, enum platform_inst_= fw_cap_type cap_id) +{ + const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + u32 entropy_mode =3D inst->fw_caps[cap_id].value; + u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + u32 profile; + + if (inst->codec !=3D V4L2_PIX_FMT_H264) + return 0; + + profile =3D inst->fw_caps[PROFILE_H264].value; + + if (profile =3D=3D V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE || + profile =3D=3D V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_BASELINE) + entropy_mode =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC; + + inst->fw_caps[cap_id].value =3D entropy_mode; + + return hfi_ops->session_set_property(inst, hfi_id, + HFI_HOST_FLAGS_NONE, + iris_get_port_info(inst, cap_id), + HFI_PAYLOAD_U32, + &entropy_mode, sizeof(u32)); +} + +int iris_set_min_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type= cap_id) +{ + const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + u32 i_qp_enable =3D 0, p_qp_enable =3D 0, b_qp_enable =3D 0; + u32 i_frame_qp =3D 0, p_frame_qp =3D 0, b_frame_qp =3D 0; + u32 min_qp_enable =3D 0, client_qp_enable =3D 0; + u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + u32 hfi_val; + + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) { + if (inst->fw_caps[MIN_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) + min_qp_enable =3D 1; + if (min_qp_enable || + (inst->fw_caps[I_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET)) + i_qp_enable =3D 1; + if (min_qp_enable || + (inst->fw_caps[P_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET)) + p_qp_enable =3D 1; + if (min_qp_enable || + (inst->fw_caps[B_FRAME_MIN_QP_H264].flags & CAP_FLAG_CLIENT_SET)) + b_qp_enable =3D 1; + } else { + if (inst->fw_caps[MIN_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) + min_qp_enable =3D 1; + if (min_qp_enable || + (inst->fw_caps[I_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) + i_qp_enable =3D 1; + if (min_qp_enable || + (inst->fw_caps[P_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) + p_qp_enable =3D 1; + if (min_qp_enable || + (inst->fw_caps[B_FRAME_MIN_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) + b_qp_enable =3D 1; + } + + client_qp_enable =3D i_qp_enable | p_qp_enable << 1 | b_qp_enable << 2; + if (!client_qp_enable) + return 0; + + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) { + i_frame_qp =3D max(inst->fw_caps[I_FRAME_MIN_QP_H264].value, + inst->fw_caps[MIN_FRAME_QP_H264].value); + p_frame_qp =3D max(inst->fw_caps[P_FRAME_MIN_QP_H264].value, + inst->fw_caps[MIN_FRAME_QP_H264].value); + b_frame_qp =3D max(inst->fw_caps[B_FRAME_MIN_QP_H264].value, + inst->fw_caps[MIN_FRAME_QP_H264].value); + } else { + i_frame_qp =3D max(inst->fw_caps[I_FRAME_MIN_QP_HEVC].value, + inst->fw_caps[MIN_FRAME_QP_HEVC].value); + p_frame_qp =3D max(inst->fw_caps[P_FRAME_MIN_QP_HEVC].value, + inst->fw_caps[MIN_FRAME_QP_HEVC].value); + b_frame_qp =3D max(inst->fw_caps[B_FRAME_MIN_QP_HEVC].value, + inst->fw_caps[MIN_FRAME_QP_HEVC].value); + } + + hfi_val =3D i_frame_qp | p_frame_qp << 8 | b_frame_qp << 16 | client_qp_e= nable << 24; + + return hfi_ops->session_set_property(inst, hfi_id, + HFI_HOST_FLAGS_NONE, + iris_get_port_info(inst, cap_id), + HFI_PAYLOAD_32_PACKED, + &hfi_val, sizeof(u32)); +} + +int iris_set_max_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type= cap_id) +{ + const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + u32 i_qp_enable =3D 0, p_qp_enable =3D 0, b_qp_enable =3D 0; + u32 max_qp_enable =3D 0, client_qp_enable; + u32 i_frame_qp, p_frame_qp, b_frame_qp; + u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + u32 hfi_val; + + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) { + if (inst->fw_caps[MAX_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) + max_qp_enable =3D 1; + if (max_qp_enable || + (inst->fw_caps[I_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET)) + i_qp_enable =3D 1; + if (max_qp_enable || + (inst->fw_caps[P_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET)) + p_qp_enable =3D 1; + if (max_qp_enable || + (inst->fw_caps[B_FRAME_MAX_QP_H264].flags & CAP_FLAG_CLIENT_SET)) + b_qp_enable =3D 1; + } else { + if (inst->fw_caps[MAX_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) + max_qp_enable =3D 1; + if (max_qp_enable || + (inst->fw_caps[I_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) + i_qp_enable =3D 1; + if (max_qp_enable || + (inst->fw_caps[P_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) + p_qp_enable =3D 1; + if (max_qp_enable || + (inst->fw_caps[B_FRAME_MAX_QP_HEVC].flags & CAP_FLAG_CLIENT_SET)) + b_qp_enable =3D 1; + } + + client_qp_enable =3D i_qp_enable | p_qp_enable << 1 | b_qp_enable << 2; + if (!client_qp_enable) + return 0; + + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) { + i_frame_qp =3D min(inst->fw_caps[I_FRAME_MAX_QP_H264].value, + inst->fw_caps[MAX_FRAME_QP_H264].value); + p_frame_qp =3D min(inst->fw_caps[P_FRAME_MAX_QP_H264].value, + inst->fw_caps[MAX_FRAME_QP_H264].value); + b_frame_qp =3D min(inst->fw_caps[B_FRAME_MAX_QP_H264].value, + inst->fw_caps[MAX_FRAME_QP_H264].value); + } else { + i_frame_qp =3D min(inst->fw_caps[I_FRAME_MAX_QP_HEVC].value, + inst->fw_caps[MAX_FRAME_QP_HEVC].value); + p_frame_qp =3D min(inst->fw_caps[P_FRAME_MAX_QP_HEVC].value, + inst->fw_caps[MAX_FRAME_QP_HEVC].value); + b_frame_qp =3D min(inst->fw_caps[B_FRAME_MAX_QP_HEVC].value, + inst->fw_caps[MAX_FRAME_QP_HEVC].value); + } + + hfi_val =3D i_frame_qp | p_frame_qp << 8 | b_frame_qp << 16 | + client_qp_enable << 24; + + return hfi_ops->session_set_property(inst, hfi_id, + HFI_HOST_FLAGS_NONE, + iris_get_port_info(inst, cap_id), + HFI_PAYLOAD_32_PACKED, + &hfi_val, sizeof(u32)); +} + +int iris_set_frame_qp(struct iris_inst *inst, enum platform_inst_fw_cap_ty= pe cap_id) +{ + const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + u32 i_qp_enable =3D 0, p_qp_enable =3D 0, b_qp_enable =3D 0, client_qp_en= able; + u32 i_frame_qp, p_frame_qp, b_frame_qp; + u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + struct vb2_queue *q; + u32 hfi_val; + + q =3D v4l2_m2m_get_dst_vq(inst->m2m_ctx); + if (vb2_is_streaming(q)) { + if (inst->hfi_rc_type !=3D HFI_RC_OFF) + return 0; + } + + if (inst->hfi_rc_type =3D=3D HFI_RC_OFF) { + i_qp_enable =3D 1; + p_qp_enable =3D 1; + b_qp_enable =3D 1; + } else { + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) { + if (inst->fw_caps[I_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) + i_qp_enable =3D 1; + if (inst->fw_caps[P_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) + p_qp_enable =3D 1; + if (inst->fw_caps[B_FRAME_QP_H264].flags & CAP_FLAG_CLIENT_SET) + b_qp_enable =3D 1; + } else { + if (inst->fw_caps[I_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) + i_qp_enable =3D 1; + if (inst->fw_caps[P_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) + p_qp_enable =3D 1; + if (inst->fw_caps[B_FRAME_QP_HEVC].flags & CAP_FLAG_CLIENT_SET) + b_qp_enable =3D 1; + } + } + + client_qp_enable =3D i_qp_enable | p_qp_enable << 1 | b_qp_enable << 2; + if (!client_qp_enable) + return 0; + + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) { + i_frame_qp =3D inst->fw_caps[I_FRAME_QP_H264].value; + p_frame_qp =3D inst->fw_caps[P_FRAME_QP_H264].value; + b_frame_qp =3D inst->fw_caps[B_FRAME_QP_H264].value; + } else { + i_frame_qp =3D inst->fw_caps[I_FRAME_QP_HEVC].value; + p_frame_qp =3D inst->fw_caps[P_FRAME_QP_HEVC].value; + b_frame_qp =3D inst->fw_caps[B_FRAME_QP_HEVC].value; + } + + hfi_val =3D i_frame_qp | p_frame_qp << 8 | b_frame_qp << 16 | + client_qp_enable << 24; + + return hfi_ops->session_set_property(inst, hfi_id, + HFI_HOST_FLAGS_NONE, + iris_get_port_info(inst, cap_id), + HFI_PAYLOAD_32_PACKED, + &hfi_val, sizeof(u32)); +} + +int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_ty= pe cap_id) +{ + const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + struct hfi_quantization_range_v2 range; + u32 hfi_id =3D inst->fw_caps[cap_id].hfi_id; + + if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) { + range.min_qp.qp_packed =3D inst->fw_caps[MIN_FRAME_QP_HEVC].value; + range.max_qp.qp_packed =3D inst->fw_caps[MAX_FRAME_QP_HEVC].value; + } else { + range.min_qp.qp_packed =3D inst->fw_caps[MIN_FRAME_QP_H264].value; + range.max_qp.qp_packed =3D inst->fw_caps[MAX_FRAME_QP_H264].value; + } + + return hfi_ops->session_set_property(inst, hfi_id, + HFI_HOST_FLAGS_NONE, + iris_get_port_info(inst, cap_id), + HFI_PAYLOAD_32_PACKED, + &range, sizeof(range)); +} + int iris_set_properties(struct iris_inst *inst, u32 plane) { const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; diff --git a/drivers/media/platform/qcom/iris/iris_ctrls.h b/drivers/media/= platform/qcom/iris/iris_ctrls.h index 9b5741868933b08dcefd4868ba89f3c43760d31c..30af333cc4941e737eb1ae83a69= 44b4192896e23 100644 --- a/drivers/media/platform/qcom/iris/iris_ctrls.h +++ b/drivers/media/platform/qcom/iris/iris_ctrls.h @@ -17,6 +17,21 @@ int iris_set_u32_enum(struct iris_inst *inst, enum platf= orm_inst_fw_cap_type cap int iris_set_stage(struct iris_inst *inst, enum platform_inst_fw_cap_type = cap_id); int iris_set_pipe(struct iris_inst *inst, enum platform_inst_fw_cap_type c= ap_id); int iris_set_u32(struct iris_inst *inst, enum platform_inst_fw_cap_type ca= p_id); +int iris_set_profile(struct iris_inst *inst, enum platform_inst_fw_cap_typ= e cap_id); +int iris_set_level(struct iris_inst *inst, enum platform_inst_fw_cap_type = cap_id); +int iris_set_profile_level_gen1(struct iris_inst *inst, enum platform_inst= _fw_cap_type cap_id); +int iris_set_header_mode_gen1(struct iris_inst *inst, enum platform_inst_f= w_cap_type cap_id); +int iris_set_header_mode_gen2(struct iris_inst *inst, enum platform_inst_f= w_cap_type cap_id); +int iris_set_bitrate(struct iris_inst *inst, enum platform_inst_fw_cap_typ= e cap_id); +int iris_set_peak_bitrate(struct iris_inst *inst, enum platform_inst_fw_ca= p_type cap_id); +int iris_set_bitrate_mode_gen1(struct iris_inst *inst, enum platform_inst_= fw_cap_type cap_id); +int iris_set_bitrate_mode_gen2(struct iris_inst *inst, enum platform_inst_= fw_cap_type cap_id); +int iris_set_entropy_mode_gen1(struct iris_inst *inst, enum platform_inst_= fw_cap_type cap_id); +int iris_set_entropy_mode_gen2(struct iris_inst *inst, enum platform_inst_= fw_cap_type cap_id); +int iris_set_min_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type= cap_id); +int iris_set_max_qp(struct iris_inst *inst, enum platform_inst_fw_cap_type= cap_id); +int iris_set_frame_qp(struct iris_inst *inst, enum platform_inst_fw_cap_ty= pe cap_id); +int iris_set_qp_range(struct iris_inst *inst, enum platform_inst_fw_cap_ty= pe cap_id); int iris_set_properties(struct iris_inst *inst, u32 plane); =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_command.c index cd1dc9575f592cc3b5f10f9aab9a1ff86adb1dd2..690c439430a750e146e41f3feea= e3c33039b61b8 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -534,6 +534,114 @@ iris_hfi_gen1_packet_session_set_property(struct hfi_= session_set_property_pkt *p packet->shdr.hdr.size +=3D sizeof(u32) + sizeof(*wm); break; } + case HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT: { + struct hfi_profile_level *in =3D pdata, *pl =3D prop_data; + + pl->level =3D in->level; + pl->profile =3D in->profile; + if (pl->profile <=3D 0) + /* Profile not supported, falling back to high */ + pl->profile =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH; + + if (!pl->level) + /* Level not supported, falling back to 1 */ + pl->level =3D 1; + + packet->shdr.hdr.size +=3D sizeof(u32) + sizeof(*pl); + break; + } + case HFI_PROPERTY_CONFIG_VENC_SYNC_FRAME_SEQUENCE_HEADER: { + struct hfi_enable *en =3D prop_data; + u32 *in =3D pdata; + + en->enable =3D *in; + packet->shdr.hdr.size +=3D sizeof(u32) + sizeof(*en); + break; + } + case HFI_PROPERTY_CONFIG_VENC_TARGET_BITRATE: { + struct hfi_bitrate *brate =3D prop_data; + u32 *in =3D pdata; + + brate->bitrate =3D *in; + brate->layer_id =3D 0; + packet->shdr.hdr.size +=3D sizeof(u32) + sizeof(*brate); + break; + } + case HFI_PROPERTY_PARAM_VENC_RATE_CONTROL: { + u32 *in =3D pdata; + + switch (*in) { + case HFI_RATE_CONTROL_OFF: + case HFI_RATE_CONTROL_CBR_CFR: + case HFI_RATE_CONTROL_CBR_VFR: + case HFI_RATE_CONTROL_VBR_CFR: + case HFI_RATE_CONTROL_VBR_VFR: + case HFI_RATE_CONTROL_CQ: + break; + default: + return -EINVAL; + } + + packet->data[1] =3D *in; + packet->shdr.hdr.size +=3D sizeof(u32) * 2; + break; + } + case HFI_PROPERTY_PARAM_VENC_H264_ENTROPY_CONTROL: { + struct hfi_h264_entropy_control *entropy =3D prop_data; + u32 *in =3D pdata; + + entropy->entropy_mode =3D *in; + if (entropy->entropy_mode =3D=3D HFI_H264_ENTROPY_CABAC) + entropy->cabac_model =3D HFI_H264_CABAC_MODEL_0; + packet->shdr.hdr.size +=3D sizeof(u32) + sizeof(*entropy); + break; + } + case HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2: { + struct hfi_quantization_range_v2 *range =3D prop_data; + struct hfi_quantization_range_v2 *in =3D pdata; + u32 min_qp, max_qp; + + min_qp =3D in->min_qp.qp_packed; + max_qp =3D in->max_qp.qp_packed; + + /* We'll be packing in the qp, so make sure we + * won't be losing data when masking + */ + if (min_qp > 0xff || max_qp > 0xff) + return -ERANGE; + + range->min_qp.layer_id =3D 0xFF; + range->max_qp.layer_id =3D 0xFF; + range->min_qp.qp_packed =3D (min_qp & 0xFF) | ((min_qp & 0xFF) << 8) | + ((min_qp & 0xFF) << 16); + range->max_qp.qp_packed =3D (max_qp & 0xFF) | ((max_qp & 0xFF) << 8) | + ((max_qp & 0xFF) << 16); + range->min_qp.enable =3D 7; + range->max_qp.enable =3D 7; + packet->shdr.hdr.size +=3D sizeof(u32) + sizeof(*range); + break; + } + case HFI_PROPERTY_CONFIG_FRAME_RATE: { + struct hfi_framerate *frate =3D prop_data; + struct hfi_framerate *in =3D pdata; + + frate->buffer_type =3D in->buffer_type; + frate->framerate =3D in->framerate; + packet->shdr.hdr.size +=3D sizeof(u32) + sizeof(*frate); + break; + } + case HFI_PROPERTY_PARAM_UNCOMPRESSED_PLANE_ACTUAL_INFO: { + struct hfi_uncompressed_plane_actual_info *plane_actual_info =3D prop_da= ta; + struct hfi_uncompressed_plane_actual_info *in =3D pdata; + + plane_actual_info->buffer_type =3D in->buffer_type; + plane_actual_info->num_planes =3D in->num_planes; + plane_actual_info->plane_format[0] =3D in->plane_format[0]; + if (in->num_planes > 1) + plane_actual_info->plane_format[1] =3D in->plane_format[1]; + packet->shdr.hdr.size +=3D sizeof(u32) + sizeof(*plane_actual_info); + break; + } default: return -EINVAL; } diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_defines.h index 81116420b6a3d86cca7229bdd3a875d95c1a7936..d7bbcfce6941229aedb558d24d4= cd6c7a8a1aa32 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h @@ -114,15 +114,25 @@ #define HFI_MSG_SESSION_RELEASE_RESOURCES 0x22100a #define HFI_MSG_SESSION_RELEASE_BUFFERS 0x22100c =20 -#define HFI_PICTURE_I 0x00000001 -#define HFI_PICTURE_P 0x00000002 -#define HFI_PICTURE_B 0x00000004 -#define HFI_PICTURE_IDR 0x00000008 +#define HFI_GEN1_PICTURE_I 0x00000001 +#define HFI_GEN1_PICTURE_P 0x00000002 +#define HFI_GEN1_PICTURE_B 0x00000004 +#define HFI_GEN1_PICTURE_IDR 0x00000008 #define HFI_FRAME_NOTCODED 0x7f002000 #define HFI_FRAME_YUV 0x7f004000 #define HFI_UNUSED_PICT 0x10000000 -#define HFI_BUFFERFLAG_DATACORRUPT 0x00000008 -#define HFI_BUFFERFLAG_DROP_FRAME 0x20000000 +#define HFI_BUFFERFLAG_DATACORRUPT 0x00000008 +#define HFI_BUFFERFLAG_DROP_FRAME 0x20000000 +#define HFI_RATE_CONTROL_OFF 0x1000001 +#define HFI_RATE_CONTROL_VBR_VFR 0x1000002 +#define HFI_RATE_CONTROL_VBR_CFR 0x1000003 +#define HFI_RATE_CONTROL_CBR_VFR 0x1000004 +#define HFI_RATE_CONTROL_CBR_CFR 0x1000005 +#define HFI_RATE_CONTROL_CQ 0x1000008 + +#define HFI_H264_ENTROPY_CAVLC 0x1 +#define HFI_H264_ENTROPY_CABAC 0x2 + #define HFI_PROPERTY_PARAM_VENC_H264_ENTROPY_CONTROL 0x2005002 #define HFI_PROPERTY_PARAM_VENC_H264_DEBLOCK_CONTROL 0x2005003 #define HFI_PROPERTY_PARAM_VENC_RATE_CONTROL 0x2005004 @@ -388,6 +398,31 @@ struct hfi_buffer_requirements { u32 alignment; }; =20 +struct hfi_bitrate { + u32 bitrate; + u32 layer_id; +}; + +#define HFI_H264_CABAC_MODEL_0 0x1 + +struct hfi_h264_entropy_control { + u32 entropy_mode; + u32 cabac_model; +}; + +struct hfi_quantization_v2 { + u32 qp_packed; + u32 layer_id; + u32 enable; + u32 reserved[3]; +}; + +struct hfi_quantization_range_v2 { + struct hfi_quantization_v2 min_qp; + struct hfi_quantization_v2 max_qp; + u32 reserved[4]; +}; + struct hfi_framerate { u32 buffer_type; u32 framerate; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen1_response.c index 2a96458833835422d30c9386d15cc1e4fb226e3d..82d3e8de7bff0ac53a971b4763a= e848ff8c61ff2 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c @@ -469,14 +469,14 @@ static void iris_hfi_gen1_session_ftb_done(struct iri= s_inst *inst, void *packet) buf->timestamp =3D timestamp_us; =20 switch (pic_type) { - case HFI_PICTURE_IDR: - case HFI_PICTURE_I: + case HFI_GEN1_PICTURE_IDR: + case HFI_GEN1_PICTURE_I: flags |=3D V4L2_BUF_FLAG_KEYFRAME; break; - case HFI_PICTURE_P: + case HFI_GEN1_PICTURE_P: flags |=3D V4L2_BUF_FLAG_PFRAME; break; - case HFI_PICTURE_B: + case HFI_GEN1_PICTURE_B: flags |=3D V4L2_BUF_FLAG_BFRAME; break; case HFI_FRAME_NOTCODED: diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_defines.h index b3d1c966958e516d940a7795e5cbe2f8e8bada57..aa1f795f5626c1f76a32dd65030= 2633877ce67be 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_defines.h @@ -56,6 +56,16 @@ #define HFI_PROP_BUFFER_HOST_MAX_COUNT 0x03000123 #define HFI_PROP_BUFFER_FW_MIN_OUTPUT_COUNT 0x03000124 #define HFI_PROP_PIC_ORDER_CNT_TYPE 0x03000128 + +enum hfi_rate_control { + HFI_RC_VBR_CFR =3D 0x00000000, + HFI_RC_CBR_CFR =3D 0x00000001, + HFI_RC_CQ =3D 0x00000002, + HFI_RC_OFF =3D 0x00000003, + HFI_RC_CBR_VFR =3D 0x00000004, + HFI_RC_LOSSLESS =3D 0x00000005, +}; + #define HFI_PROP_RATE_CONTROL 0x0300012a #define HFI_PROP_QP_PACKED 0x0300012e #define HFI_PROP_MIN_QP_PACKED 0x0300012f @@ -64,6 +74,14 @@ #define HFI_PROP_MAX_GOP_FRAMES 0x03000146 #define HFI_PROP_MAX_B_FRAMES 0x03000147 #define HFI_PROP_QUALITY_MODE 0x03000148 + +enum hfi_seq_header_mode { + HFI_SEQ_HEADER_SEPERATE_FRAME =3D 0x00000001, + HFI_SEQ_HEADER_JOINED_WITH_1ST_FRAME =3D 0x00000002, + HFI_SEQ_HEADER_PREFIX_WITH_SYNC_FRAME =3D 0x00000004, + HFI_SEQ_HEADER_METADATA =3D 0x00000008, +}; + #define HFI_PROP_SEQ_HEADER_MODE 0x03000149 #define HFI_PROP_SIGNAL_COLOR_INFO 0x03000155 #define HFI_PROP_PICTURE_TYPE 0x03000162 @@ -123,13 +141,13 @@ enum hfi_codec_type { }; =20 enum hfi_picture_type { - HFI_PICTURE_IDR =3D 0x00000001, - HFI_PICTURE_P =3D 0x00000002, - HFI_PICTURE_B =3D 0x00000004, - HFI_PICTURE_I =3D 0x00000008, - HFI_PICTURE_CRA =3D 0x00000010, - HFI_PICTURE_BLA =3D 0x00000020, - HFI_PICTURE_NOSHOW =3D 0x00000040, + HFI_GEN2_PICTURE_IDR =3D 0x00000001, + HFI_GEN2_PICTURE_P =3D 0x00000002, + HFI_GEN2_PICTURE_B =3D 0x00000004, + HFI_GEN2_PICTURE_I =3D 0x00000008, + HFI_GEN2_PICTURE_CRA =3D 0x00000010, + HFI_GEN2_PICTURE_BLA =3D 0x00000020, + HFI_GEN2_PICTURE_NOSHOW =3D 0x00000040, }; =20 enum hfi_buffer_type { diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen2_response.c index dda775d463e916f70da0b879702d96df18ea8bf7..4e4fae2359ccf210186397a4170= 49208728b5d53 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c @@ -87,17 +87,18 @@ static bool iris_hfi_gen2_is_valid_hfi_port(u32 port, u= 32 buffer_type) =20 static int iris_hfi_gen2_get_driver_buffer_flags(struct iris_inst *inst, u= 32 hfi_flags) { - u32 keyframe =3D HFI_PICTURE_IDR | HFI_PICTURE_I | HFI_PICTURE_CRA | HFI_= PICTURE_BLA; struct iris_inst_hfi_gen2 *inst_hfi_gen2 =3D to_iris_inst_hfi_gen2(inst); + u32 keyframe =3D HFI_GEN2_PICTURE_IDR | HFI_GEN2_PICTURE_I | + HFI_GEN2_PICTURE_CRA | HFI_GEN2_PICTURE_BLA; u32 driver_flags =3D 0; =20 - if (inst_hfi_gen2->hfi_frame_info.picture_type & HFI_PICTURE_NOSHOW) + if (inst_hfi_gen2->hfi_frame_info.picture_type & HFI_GEN2_PICTURE_NOSHOW) driver_flags |=3D V4L2_BUF_FLAG_ERROR; else if (inst_hfi_gen2->hfi_frame_info.picture_type & keyframe) driver_flags |=3D V4L2_BUF_FLAG_KEYFRAME; - else if (inst_hfi_gen2->hfi_frame_info.picture_type & HFI_PICTURE_P) + else if (inst_hfi_gen2->hfi_frame_info.picture_type & HFI_GEN2_PICTURE_P) driver_flags |=3D V4L2_BUF_FLAG_PFRAME; - else if (inst_hfi_gen2->hfi_frame_info.picture_type & HFI_PICTURE_B) + else if (inst_hfi_gen2->hfi_frame_info.picture_type & HFI_GEN2_PICTURE_B) driver_flags |=3D V4L2_BUF_FLAG_BFRAME; =20 if (inst_hfi_gen2->hfi_frame_info.data_corrupt || inst_hfi_gen2->hfi_fram= e_info.overflow) diff --git a/drivers/media/platform/qcom/iris/iris_instance.h b/drivers/med= ia/platform/qcom/iris/iris_instance.h index b75549718df3c87cd85aecfc74c873c60cd4bde5..5982d7adefeab80905478b32cdd= ba7bd4651a691 100644 --- a/drivers/media/platform/qcom/iris/iris_instance.h +++ b/drivers/media/platform/qcom/iris/iris_instance.h @@ -63,7 +63,7 @@ struct iris_fmt { * @last_buffer_dequeued: a flag to indicate that last buffer is sent by d= river * @frame_rate: frame rate of current instance * @operating_rate: operating rate of current instance - + * @hfi_rc_type: rate control type */ =20 struct iris_inst { @@ -101,6 +101,7 @@ struct iris_inst { bool last_buffer_dequeued; u32 frame_rate; u32 operating_rate; + u32 hfi_rc_type; }; =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index d8b818ccd5a512f66f194b24b5f6d6609c8c838f..8b7e79a794f5ab3d26789050121= dbf44a5a85b89 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -213,6 +213,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_e= nc[] =3D { .value =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, .hfi_id =3D HFI_PROP_PROFILE, .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_profile, }, { .cap_id =3D PROFILE_HEVC, @@ -224,6 +225,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_e= nc[] =3D { .value =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, .hfi_id =3D HFI_PROP_PROFILE, .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_profile, }, { .cap_id =3D LEVEL_H264, @@ -250,6 +252,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_e= nc[] =3D { .value =3D V4L2_MPEG_VIDEO_H264_LEVEL_5_0, .hfi_id =3D HFI_PROP_LEVEL, .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_level, }, { .cap_id =3D LEVEL_HEVC, @@ -271,6 +274,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_e= nc[] =3D { .value =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_5, .hfi_id =3D HFI_PROP_LEVEL, .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_level, }, { .cap_id =3D STAGE, @@ -279,6 +283,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_e= nc[] =3D { .step_or_mask =3D 1, .value =3D STAGE_2, .hfi_id =3D HFI_PROP_STAGE, + .set =3D iris_set_stage, }, { .cap_id =3D HEADER_MODE, @@ -289,6 +294,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_e= nc[] =3D { .value =3D V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, .hfi_id =3D HFI_PROP_SEQ_HEADER_MODE, .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_header_mode_gen2, }, { .cap_id =3D PREPEND_SPSPPS_TO_IDR, @@ -306,6 +312,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_e= nc[] =3D { .hfi_id =3D HFI_PROP_TOTAL_BITRATE, .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_bitrate, }, { .cap_id =3D BITRATE_PEAK, @@ -316,6 +323,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_e= nc[] =3D { .hfi_id =3D HFI_PROP_TOTAL_PEAK_BITRATE, .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_peak_bitrate, }, { .cap_id =3D BITRATE_MODE, @@ -326,6 +334,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_e= nc[] =3D { .value =3D V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, .hfi_id =3D HFI_PROP_RATE_CONTROL, .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_bitrate_mode_gen2, }, { .cap_id =3D FRAME_SKIP_MODE, @@ -353,6 +362,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_e= nc[] =3D { .hfi_id =3D HFI_PROP_MAX_GOP_FRAMES, .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_u32, }, { .cap_id =3D ENTROPY_MODE, @@ -363,6 +373,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_e= nc[] =3D { .value =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC, .hfi_id =3D HFI_PROP_CABAC_SESSION, .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_entropy_mode_gen2, }, { .cap_id =3D MIN_FRAME_QP_H264, @@ -372,6 +383,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_e= nc[] =3D { .value =3D MIN_QP_8BIT, .hfi_id =3D HFI_PROP_MIN_QP_PACKED, .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_min_qp, }, { .cap_id =3D MIN_FRAME_QP_HEVC, @@ -381,6 +393,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_e= nc[] =3D { .value =3D MIN_QP_8BIT, .hfi_id =3D HFI_PROP_MIN_QP_PACKED, .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_min_qp, }, { .cap_id =3D MAX_FRAME_QP_H264, @@ -390,6 +403,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_e= nc[] =3D { .value =3D MAX_QP, .hfi_id =3D HFI_PROP_MAX_QP_PACKED, .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_max_qp, }, { .cap_id =3D MAX_FRAME_QP_HEVC, @@ -399,6 +413,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_e= nc[] =3D { .value =3D MAX_QP, .hfi_id =3D HFI_PROP_MAX_QP_PACKED, .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_max_qp, }, { .cap_id =3D I_FRAME_MIN_QP_H264, @@ -493,6 +508,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_e= nc[] =3D { .hfi_id =3D HFI_PROP_QP_PACKED, .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_frame_qp, }, { .cap_id =3D I_FRAME_QP_HEVC, @@ -503,6 +519,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_e= nc[] =3D { .hfi_id =3D HFI_PROP_QP_PACKED, .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_frame_qp, }, { .cap_id =3D P_FRAME_QP_H264, @@ -513,6 +530,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_e= nc[] =3D { .hfi_id =3D HFI_PROP_QP_PACKED, .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_frame_qp, }, { .cap_id =3D P_FRAME_QP_HEVC, @@ -523,6 +541,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_e= nc[] =3D { .hfi_id =3D HFI_PROP_QP_PACKED, .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_frame_qp, }, { .cap_id =3D B_FRAME_QP_H264, @@ -533,6 +552,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_e= nc[] =3D { .hfi_id =3D HFI_PROP_QP_PACKED, .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_frame_qp, }, { .cap_id =3D B_FRAME_QP_HEVC, @@ -543,6 +563,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_e= nc[] =3D { .hfi_id =3D HFI_PROP_QP_PACKED, .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_frame_qp, }, { .cap_id =3D INPUT_BUF_HOST_MAX_COUNT, @@ -552,6 +573,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_e= nc[] =3D { .value =3D DEFAULT_MAX_HOST_BUF_COUNT, .hfi_id =3D HFI_PROP_BUFFER_HOST_MAX_COUNT, .flags =3D CAP_FLAG_INPUT_PORT, + .set =3D iris_set_u32, }, { .cap_id =3D OUTPUT_BUF_HOST_MAX_COUNT, @@ -561,6 +583,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8550_e= nc[] =3D { .value =3D DEFAULT_MAX_HOST_BUF_COUNT, .hfi_id =3D HFI_PROP_BUFFER_HOST_MAX_COUNT, .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_u32, }, }; =20 diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/driv= ers/media/platform/qcom/iris/iris_platform_sm8250.c index 746b201ededbdb194e833f339e49c24d24b58981..25757d7950aa149b60f6a1c0815= cb0e528c09fc3 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c @@ -45,6 +45,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8250_enc= [] =3D { .step_or_mask =3D 1, .value =3D STAGE_2, .hfi_id =3D HFI_PROPERTY_PARAM_WORK_MODE, + .set =3D iris_set_stage, }, { .cap_id =3D PROFILE_H264, @@ -59,6 +60,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8250_enc= [] =3D { .value =3D V4L2_MPEG_VIDEO_H264_PROFILE_HIGH, .hfi_id =3D HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT, .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_profile_level_gen1, }, { .cap_id =3D PROFILE_HEVC, @@ -70,6 +72,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8250_enc= [] =3D { .value =3D V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN, .hfi_id =3D HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT, .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_profile_level_gen1, }, { .cap_id =3D LEVEL_H264, @@ -94,6 +97,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8250_enc= [] =3D { .value =3D V4L2_MPEG_VIDEO_H264_LEVEL_1_0, .hfi_id =3D HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT, .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_profile_level_gen1, }, { .cap_id =3D LEVEL_HEVC, @@ -115,6 +119,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8250_e= nc[] =3D { .value =3D V4L2_MPEG_VIDEO_HEVC_LEVEL_1, .hfi_id =3D HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT, .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_profile_level_gen1, }, { .cap_id =3D HEADER_MODE, @@ -125,6 +130,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8250_e= nc[] =3D { .value =3D V4L2_MPEG_VIDEO_HEADER_MODE_JOINED_WITH_1ST_FRAME, .hfi_id =3D HFI_PROPERTY_CONFIG_VENC_SYNC_FRAME_SEQUENCE_HEADER, .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_header_mode_gen1, }, { .cap_id =3D BITRATE, @@ -135,6 +141,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8250_e= nc[] =3D { .hfi_id =3D HFI_PROPERTY_CONFIG_VENC_TARGET_BITRATE, .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_INPUT_PORT | CAP_FLAG_DYNAMIC_ALLOWED, + .set =3D iris_set_bitrate, }, { .cap_id =3D BITRATE_MODE, @@ -145,6 +152,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8250_e= nc[] =3D { .value =3D V4L2_MPEG_VIDEO_BITRATE_MODE_VBR, .hfi_id =3D HFI_PROPERTY_PARAM_VENC_RATE_CONTROL, .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_bitrate_mode_gen1, }, { .cap_id =3D FRAME_SKIP_MODE, @@ -168,6 +176,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8250_e= nc[] =3D { .max =3D (1 << 16) - 1, .step_or_mask =3D 1, .value =3D 30, + .set =3D iris_set_u32 }, { .cap_id =3D ENTROPY_MODE, @@ -178,6 +187,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8250_e= nc[] =3D { .value =3D V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC, .hfi_id =3D HFI_PROPERTY_PARAM_VENC_H264_ENTROPY_CONTROL, .flags =3D CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU, + .set =3D iris_set_entropy_mode_gen1, }, { .cap_id =3D MIN_FRAME_QP_H264, @@ -187,6 +197,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8250_e= nc[] =3D { .value =3D MIN_QP_8BIT, .hfi_id =3D HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2, .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_qp_range, }, { .cap_id =3D MIN_FRAME_QP_HEVC, @@ -196,6 +207,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8250_e= nc[] =3D { .value =3D MIN_QP_8BIT, .hfi_id =3D HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2, .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_qp_range, }, { .cap_id =3D MAX_FRAME_QP_H264, @@ -205,6 +217,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8250_e= nc[] =3D { .value =3D MAX_QP, .hfi_id =3D HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2, .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_qp_range, }, { .cap_id =3D MAX_FRAME_QP_HEVC, @@ -214,6 +227,7 @@ static struct platform_inst_fw_cap inst_fw_cap_sm8250_e= nc[] =3D { .value =3D MAX_QP_HEVC, .hfi_id =3D HFI_PROPERTY_PARAM_VENC_SESSION_QP_RANGE_V2, .flags =3D CAP_FLAG_OUTPUT_PORT, + .set =3D iris_set_qp_range, }, }; =20 --=20 2.34.1 From nobody Fri Oct 3 20:48:35 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) 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(version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.24; Mon, 25 Aug 2025 00:02:19 -0700 From: Dikshita Agarwal Date: Mon, 25 Aug 2025 12:30:48 +0530 Subject: [PATCH v4 24/26] media: iris: Allocate and queue internal buffers for encoder video device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250825-iris-video-encoder-v4-24-84aa2bc0a46b@quicinc.com> References: <20250825-iris-video-encoder-v4-0-84aa2bc0a46b@quicinc.com> In-Reply-To: <20250825-iris-video-encoder-v4-0-84aa2bc0a46b@quicinc.com> To: Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Stefan Schmidt , Vedang Nagar , "Hans Verkuil" , Hans Verkuil CC: , , , Renjiang Han , Wangao Wang , Dikshita Agarwal , Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756105234; 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engine=8.19.0-2507300000 definitions=main-2508230034 Add support for allocating and queuing internal buffers required by the encoder. The sizes of these buffers are derived from hardware specifications and are essential to meet the encoder's functional and performance requirements. These buffers are not exposed to userspace; they are allocated and managed internally to ensure correct and efficient hardware operation. Tested-by: Vikash Garodia # X1E80100 Reviewed-by: Vikash Garodia Tested-by: Neil Armstrong # on SM8550-HDK Tested-by: Neil Armstrong # on SM8650-HDK Signed-off-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e80100-crd --- drivers/media/platform/qcom/iris/iris_buffer.c | 114 ++- drivers/media/platform/qcom/iris/iris_buffer.h | 6 +- .../platform/qcom/iris/iris_hfi_gen1_command.c | 6 + .../platform/qcom/iris/iris_hfi_gen1_defines.h | 2 + .../platform/qcom/iris/iris_hfi_gen2_command.c | 56 +- .../platform/qcom/iris/iris_hfi_gen2_response.c | 10 +- .../platform/qcom/iris/iris_platform_common.h | 4 + .../media/platform/qcom/iris/iris_platform_gen2.c | 17 + .../platform/qcom/iris/iris_platform_sm8250.c | 9 + drivers/media/platform/qcom/iris/iris_vdec.c | 2 +- drivers/media/platform/qcom/iris/iris_venc.c | 36 + drivers/media/platform/qcom/iris/iris_vidc.c | 10 +- drivers/media/platform/qcom/iris/iris_vpu_buffer.c | 843 +++++++++++++++++= +++- drivers/media/platform/qcom/iris/iris_vpu_buffer.h | 21 + 14 files changed, 1078 insertions(+), 58 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_buffer.c b/drivers/media= /platform/qcom/iris/iris_buffer.c index 8811174bfdc0ad5288aa4eb5fab9d9df876c78c9..8891a297d384b018b3cc8313ad6= 416db6317798b 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_buffer.c @@ -294,16 +294,30 @@ void iris_get_internal_buffers(struct iris_inst *inst= , u32 plane) const u32 *internal_buf_type; u32 internal_buffer_count, i; =20 - if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_ip_int_buf_tbl_size; - for (i =3D 0; i < internal_buffer_count; i++) - iris_fill_internal_buf_info(inst, internal_buf_type[i]); + if (inst->domain =3D=3D DECODER) { + if (V4L2_TYPE_IS_OUTPUT(plane)) { + internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; + internal_buffer_count =3D platform_data->dec_ip_int_buf_tbl_size; + for (i =3D 0; i < internal_buffer_count; i++) + iris_fill_internal_buf_info(inst, internal_buf_type[i]); + } else { + internal_buf_type =3D platform_data->dec_op_int_buf_tbl; + internal_buffer_count =3D platform_data->dec_op_int_buf_tbl_size; + for (i =3D 0; i < internal_buffer_count; i++) + iris_fill_internal_buf_info(inst, internal_buf_type[i]); + } } else { - internal_buf_type =3D platform_data->dec_op_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_op_int_buf_tbl_size; - for (i =3D 0; i < internal_buffer_count; i++) - iris_fill_internal_buf_info(inst, internal_buf_type[i]); + if (V4L2_TYPE_IS_OUTPUT(plane)) { + internal_buf_type =3D platform_data->enc_ip_int_buf_tbl; + internal_buffer_count =3D platform_data->enc_ip_int_buf_tbl_size; + for (i =3D 0; i < internal_buffer_count; i++) + iris_fill_internal_buf_info(inst, internal_buf_type[i]); + } else { + internal_buf_type =3D platform_data->enc_op_int_buf_tbl; + internal_buffer_count =3D platform_data->enc_op_int_buf_tbl_size; + for (i =3D 0; i < internal_buffer_count; i++) + iris_fill_internal_buf_info(inst, internal_buf_type[i]); + } } } =20 @@ -344,12 +358,22 @@ int iris_create_internal_buffers(struct iris_inst *in= st, u32 plane) const u32 *internal_buf_type; int ret; =20 - if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_ip_int_buf_tbl_size; + if (inst->domain =3D=3D DECODER) { + if (V4L2_TYPE_IS_OUTPUT(plane)) { + internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; + internal_buffer_count =3D platform_data->dec_ip_int_buf_tbl_size; + } else { + internal_buf_type =3D platform_data->dec_op_int_buf_tbl; + internal_buffer_count =3D platform_data->dec_op_int_buf_tbl_size; + } } else { - internal_buf_type =3D platform_data->dec_op_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_op_int_buf_tbl_size; + if (V4L2_TYPE_IS_OUTPUT(plane)) { + internal_buf_type =3D platform_data->enc_ip_int_buf_tbl; + internal_buffer_count =3D platform_data->enc_ip_int_buf_tbl_size; + } else { + internal_buf_type =3D platform_data->enc_op_int_buf_tbl; + internal_buffer_count =3D platform_data->enc_op_int_buf_tbl_size; + } } =20 for (i =3D 0; i < internal_buffer_count; i++) { @@ -411,12 +435,22 @@ int iris_queue_internal_buffers(struct iris_inst *ins= t, u32 plane) u32 internal_buffer_count, i; int ret; =20 - if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_ip_int_buf_tbl_size; + if (inst->domain =3D=3D DECODER) { + if (V4L2_TYPE_IS_OUTPUT(plane)) { + internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; + internal_buffer_count =3D platform_data->dec_ip_int_buf_tbl_size; + } else { + internal_buf_type =3D platform_data->dec_op_int_buf_tbl; + internal_buffer_count =3D platform_data->dec_op_int_buf_tbl_size; + } } else { - internal_buf_type =3D platform_data->dec_op_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_op_int_buf_tbl_size; + if (V4L2_TYPE_IS_OUTPUT(plane)) { + internal_buf_type =3D platform_data->enc_ip_int_buf_tbl; + internal_buffer_count =3D platform_data->enc_ip_int_buf_tbl_size; + } else { + internal_buf_type =3D platform_data->enc_op_int_buf_tbl; + internal_buffer_count =3D platform_data->enc_op_int_buf_tbl_size; + } } =20 for (i =3D 0; i < internal_buffer_count; i++) { @@ -460,12 +494,22 @@ static int iris_destroy_internal_buffers(struct iris_= inst *inst, u32 plane, bool u32 i, len; int ret; =20 - if (V4L2_TYPE_IS_OUTPUT(plane)) { - internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; - len =3D platform_data->dec_ip_int_buf_tbl_size; + if (inst->domain =3D=3D DECODER) { + if (V4L2_TYPE_IS_OUTPUT(plane)) { + internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; + len =3D platform_data->dec_ip_int_buf_tbl_size; + } else { + internal_buf_type =3D platform_data->dec_op_int_buf_tbl; + len =3D platform_data->dec_op_int_buf_tbl_size; + } } else { - internal_buf_type =3D platform_data->dec_op_int_buf_tbl; - len =3D platform_data->dec_op_int_buf_tbl_size; + if (V4L2_TYPE_IS_OUTPUT(plane)) { + internal_buf_type =3D platform_data->enc_ip_int_buf_tbl; + len =3D platform_data->enc_ip_int_buf_tbl_size; + } else { + internal_buf_type =3D platform_data->enc_op_int_buf_tbl; + len =3D platform_data->enc_op_int_buf_tbl_size; + } } =20 for (i =3D 0; i < len; i++) { @@ -486,7 +530,10 @@ static int iris_destroy_internal_buffers(struct iris_i= nst *inst, u32 plane, bool } =20 if (force) { - buffers =3D &inst->buffers[BUF_PERSIST]; + if (inst->domain =3D=3D DECODER) + buffers =3D &inst->buffers[BUF_PERSIST]; + else + buffers =3D &inst->buffers[BUF_ARP]; =20 list_for_each_entry_safe(buf, next, &buffers->list, list) { ret =3D iris_destroy_internal_buffer(inst, buf); @@ -537,8 +584,13 @@ static int iris_release_input_internal_buffers(struct = iris_inst *inst) u32 internal_buffer_count, i; int ret; =20 - internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; - internal_buffer_count =3D platform_data->dec_ip_int_buf_tbl_size; + if (inst->domain =3D=3D DECODER) { + internal_buf_type =3D platform_data->dec_ip_int_buf_tbl; + internal_buffer_count =3D platform_data->dec_ip_int_buf_tbl_size; + } else { + internal_buf_type =3D platform_data->enc_ip_int_buf_tbl; + internal_buffer_count =3D platform_data->enc_ip_int_buf_tbl_size; + } =20 for (i =3D 0; i < internal_buffer_count; i++) { ret =3D iris_release_internal_buffers(inst, internal_buf_type[i]); @@ -549,9 +601,9 @@ static int iris_release_input_internal_buffers(struct i= ris_inst *inst) return 0; } =20 -int iris_alloc_and_queue_persist_bufs(struct iris_inst *inst) +int iris_alloc_and_queue_persist_bufs(struct iris_inst *inst, enum iris_bu= ffer_type buffer_type) { - struct iris_buffers *buffers =3D &inst->buffers[BUF_PERSIST]; + struct iris_buffers *buffers =3D &inst->buffers[buffer_type]; struct iris_buffer *buffer, *next; int ret; u32 i; @@ -559,10 +611,10 @@ int iris_alloc_and_queue_persist_bufs(struct iris_ins= t *inst) if (!list_empty(&buffers->list)) return 0; =20 - iris_fill_internal_buf_info(inst, BUF_PERSIST); + iris_fill_internal_buf_info(inst, buffer_type); =20 for (i =3D 0; i < buffers->min_count; i++) { - ret =3D iris_create_internal_buffer(inst, BUF_PERSIST, i); + ret =3D iris_create_internal_buffer(inst, buffer_type, i); if (ret) return ret; } diff --git a/drivers/media/platform/qcom/iris/iris_buffer.h b/drivers/media= /platform/qcom/iris/iris_buffer.h index b9b011faa13ae72e08545c191cdcc2f1bcaf9e0a..325d30fce5c99185b61ff989fbf= d4de9a56762b2 100644 --- a/drivers/media/platform/qcom/iris/iris_buffer.h +++ b/drivers/media/platform/qcom/iris/iris_buffer.h @@ -25,6 +25,8 @@ struct iris_inst; * @BUF_DPB: buffer to store display picture buffers for reference * @BUF_PERSIST: buffer to store session context data * @BUF_SCRATCH_1: buffer to store decoding/encoding context data for HW + * @BUF_SCRATCH_2: buffer to store encoding context data for HW + * @BUF_VPSS: buffer to store VPSS context data for HW * @BUF_TYPE_MAX: max buffer types */ enum iris_buffer_type { @@ -38,6 +40,8 @@ enum iris_buffer_type { BUF_DPB, BUF_PERSIST, BUF_SCRATCH_1, + BUF_SCRATCH_2, + BUF_VPSS, BUF_TYPE_MAX, }; =20 @@ -109,7 +113,7 @@ int iris_queue_internal_deferred_buffers(struct iris_in= st *inst, enum iris_buffe int iris_destroy_internal_buffer(struct iris_inst *inst, struct iris_buffe= r *buffer); int iris_destroy_all_internal_buffers(struct iris_inst *inst, u32 plane); int iris_destroy_dequeued_internal_buffers(struct iris_inst *inst, u32 pla= ne); -int iris_alloc_and_queue_persist_bufs(struct iris_inst *inst); +int iris_alloc_and_queue_persist_bufs(struct iris_inst *inst, enum iris_bu= ffer_type buf_type); int iris_alloc_and_queue_input_int_bufs(struct iris_inst *inst); int iris_queue_buffer(struct iris_inst *inst, struct iris_buffer *buf); int iris_queue_deferred_buffers(struct iris_inst *inst, enum iris_buffer_t= ype buf_type); diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_command.c index 690c439430a750e146e41f3feeae3c33039b61b8..49173db84b9122655fe0186cfa5= 9497a643226c3 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -21,6 +21,10 @@ static u32 iris_hfi_gen1_buf_type_from_driver(enum iris_= buffer_type buffer_type) return HFI_BUFFER_INTERNAL_SCRATCH; case BUF_SCRATCH_1: return HFI_BUFFER_INTERNAL_SCRATCH_1; + case BUF_SCRATCH_2: + return HFI_BUFFER_INTERNAL_SCRATCH_2; + case BUF_ARP: + return HFI_BUFFER_INTERNAL_PERSIST; default: return -EINVAL; } @@ -358,6 +362,8 @@ static int iris_hfi_gen1_session_queue_buffer(struct ir= is_inst *inst, struct iri case BUF_PERSIST: case BUF_BIN: case BUF_SCRATCH_1: + case BUF_SCRATCH_2: + case BUF_ARP: return iris_hfi_gen1_queue_internal_buffer(inst, buf); default: return -EINVAL; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_defines.h index d7bbcfce6941229aedb558d24d4cd6c7a8a1aa32..21853921483b90604b690010645= 50a50bb9629ad 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h @@ -74,9 +74,11 @@ #define HFI_BUFFER_INPUT 0x1 #define HFI_BUFFER_OUTPUT 0x2 #define HFI_BUFFER_OUTPUT2 0x3 +#define HFI_BUFFER_INTERNAL_PERSIST 0x4 #define HFI_BUFFER_INTERNAL_PERSIST_1 0x5 #define HFI_BUFFER_INTERNAL_SCRATCH 0x6 #define HFI_BUFFER_INTERNAL_SCRATCH_1 0x7 +#define HFI_BUFFER_INTERNAL_SCRATCH_2 0x8 =20 #define HFI_PROPERTY_SYS_CODEC_POWER_PLANE_CTRL 0x5 #define HFI_PROPERTY_SYS_IMAGE_VERSION 0x6 diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 3a7bff092846db8469bc746f2e4f8bf338b6380d..5aae8162ca1c3b969c30e6ea53b= 1de88f5ad51cc 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -111,21 +111,40 @@ static u32 iris_hfi_gen2_get_port(struct iris_inst *i= nst, u32 plane) } } =20 -static u32 iris_hfi_gen2_get_port_from_buf_type(enum iris_buffer_type buff= er_type) +static u32 iris_hfi_gen2_get_port_from_buf_type(struct iris_inst *inst, + enum iris_buffer_type buffer_type) { - switch (buffer_type) { - case BUF_INPUT: - case BUF_BIN: - case BUF_COMV: - case BUF_NON_COMV: - case BUF_LINE: - return HFI_PORT_BITSTREAM; - case BUF_OUTPUT: - case BUF_DPB: - return HFI_PORT_RAW; - case BUF_PERSIST: - default: - return HFI_PORT_NONE; + if (inst->domain =3D=3D DECODER) { + switch (buffer_type) { + case BUF_INPUT: + case BUF_BIN: + case BUF_COMV: + case BUF_NON_COMV: + case BUF_LINE: + return HFI_PORT_BITSTREAM; + case BUF_OUTPUT: + case BUF_DPB: + return HFI_PORT_RAW; + case BUF_PERSIST: + default: + return HFI_PORT_NONE; + } + } else { + switch (buffer_type) { + case BUF_INPUT: + case BUF_VPSS: + return HFI_PORT_RAW; + case BUF_OUTPUT: + case BUF_BIN: + case BUF_COMV: + case BUF_NON_COMV: + case BUF_LINE: + case BUF_SCRATCH_2: + return HFI_PORT_BITSTREAM; + case BUF_ARP: + default: + return HFI_PORT_NONE; + } } } =20 @@ -1042,9 +1061,14 @@ static u32 iris_hfi_gen2_buf_type_from_driver(enum i= ris_buffer_type buffer_type) case BUF_LINE: return HFI_BUFFER_LINE; case BUF_DPB: + case BUF_SCRATCH_2: return HFI_BUFFER_DPB; case BUF_PERSIST: return HFI_BUFFER_PERSIST; + case BUF_ARP: + return HFI_BUFFER_ARP; + case BUF_VPSS: + return HFI_BUFFER_VPSS; default: return 0; } @@ -1100,7 +1124,7 @@ static int iris_hfi_gen2_session_queue_buffer(struct = iris_inst *inst, struct iri return ret; } =20 - port =3D iris_hfi_gen2_get_port_from_buf_type(buffer->type); + port =3D iris_hfi_gen2_get_port_from_buf_type(inst, buffer->type); iris_hfi_gen2_packet_session_command(inst, HFI_CMD_BUFFER, HFI_HOST_FLAGS_INTR_REQUIRED, @@ -1122,7 +1146,7 @@ static int iris_hfi_gen2_session_release_buffer(struc= t iris_inst *inst, struct i =20 iris_hfi_gen2_get_buffer(buffer, &hfi_buffer); hfi_buffer.flags |=3D HFI_BUF_HOST_FLAG_RELEASE; - port =3D iris_hfi_gen2_get_port_from_buf_type(buffer->type); + port =3D iris_hfi_gen2_get_port_from_buf_type(inst, buffer->type); =20 iris_hfi_gen2_packet_session_command(inst, HFI_CMD_BUFFER, diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen2_response.c index 4e4fae2359ccf210186397a417049208728b5d53..6b8e637ac6d82aee8699db59ee2= f04de9e715275 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c @@ -29,7 +29,8 @@ struct iris_hfi_gen2_packet_handle { int (*handle)(struct iris_inst *inst, struct iris_hfi_packet *pkt); }; =20 -static u32 iris_hfi_gen2_buf_type_to_driver(enum hfi_buffer_type buf_type) +static u32 iris_hfi_gen2_buf_type_to_driver(struct iris_inst *inst, + enum hfi_buffer_type buf_type) { switch (buf_type) { case HFI_BUFFER_BITSTREAM: @@ -47,7 +48,10 @@ static u32 iris_hfi_gen2_buf_type_to_driver(enum hfi_buf= fer_type buf_type) case HFI_BUFFER_LINE: return BUF_LINE; case HFI_BUFFER_DPB: - return BUF_DPB; + if (inst->domain =3D=3D DECODER) + return BUF_DPB; + else + return BUF_SCRATCH_2; case HFI_BUFFER_PERSIST: return BUF_PERSIST; default: @@ -421,7 +425,7 @@ static void iris_hfi_gen2_handle_dequeue_buffers(struct= iris_inst *inst) static int iris_hfi_gen2_handle_release_internal_buffer(struct iris_inst *= inst, struct iris_hfi_buffer *buffer) { - u32 buf_type =3D iris_hfi_gen2_buf_type_to_driver(buffer->type); + u32 buf_type =3D iris_hfi_gen2_buf_type_to_driver(inst, buffer->type); struct iris_buffers *buffers =3D &inst->buffers[buf_type]; struct iris_buffer *buf, *iter; bool found =3D false; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index 0064a90e0e111075341d389fef7adb8f6b46b46f..96fa7b1bb592441e85664da408e= a4ba42c9a15b5 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -247,6 +247,10 @@ struct iris_platform_data { unsigned int dec_ip_int_buf_tbl_size; const u32 *dec_op_int_buf_tbl; unsigned int dec_op_int_buf_tbl_size; + const u32 *enc_ip_int_buf_tbl; + unsigned int enc_ip_int_buf_tbl_size; + const u32 *enc_op_int_buf_tbl; + unsigned int enc_op_int_buf_tbl_size; }; =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/driver= s/media/platform/qcom/iris/iris_platform_gen2.c index 8b7e79a794f5ab3d26789050121dbf44a5a85b89..cf4b92f534b272a0a1ac2a0e7bb= 9316501374332 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c @@ -726,6 +726,14 @@ static const u32 sm8550_dec_op_int_buf_tbl[] =3D { BUF_DPB, }; =20 +static const u32 sm8550_enc_op_int_buf_tbl[] =3D { + BUF_BIN, + BUF_COMV, + BUF_NON_COMV, + BUF_LINE, + BUF_SCRATCH_2, +}; + struct iris_platform_data sm8550_data =3D { .get_instance =3D iris_hfi_gen2_get_instance, .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, @@ -803,6 +811,9 @@ struct iris_platform_data sm8550_data =3D { .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), .dec_op_int_buf_tbl =3D sm8550_dec_op_int_buf_tbl, .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), + + .enc_op_int_buf_tbl =3D sm8550_enc_op_int_buf_tbl, + .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; =20 /* @@ -891,6 +902,9 @@ struct iris_platform_data sm8650_data =3D { .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), .dec_op_int_buf_tbl =3D sm8550_dec_op_int_buf_tbl, .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), + + .enc_op_int_buf_tbl =3D sm8550_enc_op_int_buf_tbl, + .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; =20 /* @@ -975,4 +989,7 @@ struct iris_platform_data qcs8300_data =3D { .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), .dec_op_int_buf_tbl =3D sm8550_dec_op_int_buf_tbl, .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), + + .enc_op_int_buf_tbl =3D sm8550_enc_op_int_buf_tbl, + .enc_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), }; diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c b/driv= ers/media/platform/qcom/iris/iris_platform_sm8250.c index 25757d7950aa149b60f6a1c0815cb0e528c09fc3..978d0130d43b5f6febb65430a9b= be3932e8f24df 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8250.c +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8250.c @@ -307,6 +307,12 @@ static const u32 sm8250_dec_op_int_buf_tbl[] =3D { BUF_DPB, }; =20 +static const u32 sm8250_enc_ip_int_buf_tbl[] =3D { + BUF_BIN, + BUF_SCRATCH_1, + BUF_SCRATCH_2, +}; + struct iris_platform_data sm8250_data =3D { .get_instance =3D iris_hfi_gen1_get_instance, .init_hfi_command_ops =3D &iris_hfi_gen1_command_ops_init, @@ -352,4 +358,7 @@ struct iris_platform_data sm8250_data =3D { .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_dec_ip_int_buf_tbl), .dec_op_int_buf_tbl =3D sm8250_dec_op_int_buf_tbl, .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_dec_op_int_buf_tbl), + + .enc_ip_int_buf_tbl =3D sm8250_enc_ip_int_buf_tbl, + .enc_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8250_enc_ip_int_buf_tbl), }; diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/p= latform/qcom/iris/iris_vdec.c index 92142a452be630c5e5226cea0f481c2d9f8b765f..f8d10340f7463490311ab242a44= 957cf2ddcb3bd 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.c +++ b/drivers/media/platform/qcom/iris/iris_vdec.c @@ -321,7 +321,7 @@ int iris_vdec_streamon_input(struct iris_inst *inst) if (ret) return ret; =20 - ret =3D iris_alloc_and_queue_persist_bufs(inst); + ret =3D iris_alloc_and_queue_persist_bufs(inst, BUF_PERSIST); if (ret) return ret; =20 diff --git a/drivers/media/platform/qcom/iris/iris_venc.c b/drivers/media/p= latform/qcom/iris/iris_venc.c index d5c5c28bf2b0c734451461f573c2cc6130686361..9f9565bfc2060fbd3a9ba36cb00= c0595545675dc 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.c +++ b/drivers/media/platform/qcom/iris/iris_venc.c @@ -435,6 +435,24 @@ int iris_venc_streamon_input(struct iris_inst *inst) if (ret) return ret; =20 + ret =3D iris_alloc_and_queue_persist_bufs(inst, BUF_ARP); + if (ret) + return ret; + + iris_get_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); + + ret =3D iris_destroy_dequeued_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_= OUTPUT_MPLANE); + if (ret) + return ret; + + ret =3D iris_create_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPL= ANE); + if (ret) + return ret; + + ret =3D iris_queue_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLA= NE); + if (ret) + return ret; + return iris_process_streamon_input(inst); } =20 @@ -446,6 +464,24 @@ int iris_venc_streamon_output(struct iris_inst *inst) if (ret) goto error; =20 + ret =3D iris_alloc_and_queue_persist_bufs(inst, BUF_ARP); + if (ret) + return ret; + + iris_get_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); + + ret =3D iris_destroy_dequeued_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_= CAPTURE_MPLANE); + if (ret) + goto error; + + ret =3D iris_create_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MP= LANE); + if (ret) + goto error; + + ret =3D iris_queue_internal_buffers(inst, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPL= ANE); + if (ret) + goto error; + ret =3D iris_process_streamon_output(inst); if (ret) goto error; diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/p= latform/qcom/iris/iris_vidc.c index 7bea310e68dcd811e873005df562fef24a2ec3f0..9f2e76a3704fcf3ff5fd10b29c4= 3a6937b9ffe1f 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -176,6 +176,8 @@ int iris_open(struct file *filp) INIT_LIST_HEAD(&inst->buffers[BUF_DPB].list); INIT_LIST_HEAD(&inst->buffers[BUF_PERSIST].list); INIT_LIST_HEAD(&inst->buffers[BUF_SCRATCH_1].list); + INIT_LIST_HEAD(&inst->buffers[BUF_SCRATCH_2].list); + INIT_LIST_HEAD(&inst->buffers[BUF_VPSS].list); init_completion(&inst->completion); init_completion(&inst->flush_completion); =20 @@ -265,13 +267,17 @@ static void iris_check_num_queued_internal_buffers(st= ruct iris_inst *inst, u32 p count, internal_buf_type[i]); } =20 - buffers =3D &inst->buffers[BUF_PERSIST]; + if (inst->domain =3D=3D DECODER) + buffers =3D &inst->buffers[BUF_PERSIST]; + else + buffers =3D &inst->buffers[BUF_ARP]; =20 count =3D 0; list_for_each_entry_safe(buf, next, &buffers->list, list) count++; if (count) - dev_err(inst->core->dev, "%d buffer of type BUF_PERSIST not released", c= ount); + dev_err(inst->core->dev, "%d buffer of type %d not released", + count, inst->domain =3D=3D DECODER ? BUF_PERSIST : BUF_ARP); } =20 int iris_close(struct file *filp) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_buffer.c index 06d5afc3c641f0dfca3967e55273c4fa2614fdff..34a9094201ccd11d30a776f284e= de8248d8017a9 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.c @@ -5,6 +5,14 @@ =20 #include "iris_instance.h" #include "iris_vpu_buffer.h" +#include "iris_hfi_gen1_defines.h" +#include "iris_hfi_gen2_defines.h" + +#define HFI_MAX_COL_FRAME 6 + +#ifndef SYSTEM_LAL_TILE10 +#define SYSTEM_LAL_TILE10 192 +#endif =20 static u32 size_h264d_hw_bin_buffer(u32 frame_width, u32 frame_height, u32= num_vpp_pipes) { @@ -548,6 +556,814 @@ static u32 iris_vpu_dec_scratch1_size(struct iris_ins= t *inst) iris_vpu_dec_line_size(inst); } =20 +static inline +u32 size_enc_single_pipe(u32 rc_type, u32 bitbin_size, u32 num_vpp_pipes, + u32 frame_width, u32 frame_height, u32 lcu_size) +{ + u32 size_aligned_height =3D ALIGN((frame_height), lcu_size); + u32 size_aligned_width =3D ALIGN((frame_width), lcu_size); + u32 size_single_pipe_eval =3D 0, sao_bin_buffer_size =3D 0; + u32 padded_bin_sz; + + if ((size_aligned_width * size_aligned_height) > (3840 * 2160)) + size_single_pipe_eval =3D (bitbin_size / num_vpp_pipes); + else if (num_vpp_pipes > 2) + size_single_pipe_eval =3D bitbin_size / 2; + else + size_single_pipe_eval =3D bitbin_size; + + sao_bin_buffer_size =3D (64 * ((((frame_width) + 32) * ((frame_height) + = 32)) >> 10)) + 384; + padded_bin_sz =3D ALIGN(size_single_pipe_eval, 256); + size_single_pipe_eval =3D sao_bin_buffer_size + padded_bin_sz; + + return ALIGN(size_single_pipe_eval, 256); +} + +static inline u32 size_bin_bitstream_enc(u32 width, u32 height, + u32 rc_type) +{ + u32 aligned_height =3D ALIGN(height, 32); + u32 aligned_width =3D ALIGN(width, 32); + u32 frame_size =3D width * height * 3; + u32 mbs_per_frame; + + /* + * Encoder output size calculation: 32 Align width/height + * For resolution < 720p : YUVsize * 4 + * For resolution > 720p & <=3D 4K : YUVsize / 2 + * For resolution > 4k : YUVsize / 4 + * Initially frame_size =3D YUVsize * 2; + */ + + mbs_per_frame =3D (ALIGN(aligned_height, 16) * ALIGN(aligned_width, 16)) = / 256; + + if (mbs_per_frame < NUM_MBS_720P) + frame_size =3D frame_size << 1; + else if (mbs_per_frame <=3D NUM_MBS_4K) + frame_size =3D frame_size >> 2; + else + frame_size =3D frame_size >> 3; + + if (rc_type =3D=3D HFI_RATE_CONTROL_OFF || rc_type =3D=3D HFI_RATE_CONTRO= L_CQ || + rc_type =3D=3D HFI_RC_OFF || rc_type =3D=3D HFI_RC_CQ) + frame_size =3D frame_size << 1; + + /* + * In case of opaque color format bitdepth will be known + * with first ETB, buffers allocated already with 8 bit + * won't be sufficient for 10 bit + * calculate size considering 10-bit by default + * For 10-bit cases size =3D size * 1.25 + */ + frame_size *=3D 5; + frame_size /=3D 4; + + return ALIGN(frame_size, SZ_4K); +} + +static inline u32 hfi_buffer_bin_enc(u32 width, u32 height, + u32 work_mode, u32 lcu_size, + u32 num_vpp_pipes, u32 rc_type) +{ + u32 sao_bin_buffer_size, padded_bin_size, bitstream_size; + u32 total_bitbin_buffers, size_single_pipe, bitbin_size; + u32 aligned_height =3D ALIGN(height, lcu_size); + u32 aligned_width =3D ALIGN(width, lcu_size); + + bitstream_size =3D size_bin_bitstream_enc(width, height, rc_type); + bitstream_size =3D ALIGN(bitstream_size, 256); + + if (work_mode =3D=3D STAGE_2) { + total_bitbin_buffers =3D 3; + bitbin_size =3D bitstream_size * 17 / 10; + bitbin_size =3D ALIGN(bitbin_size, 256); + } else { + total_bitbin_buffers =3D 1; + bitstream_size =3D aligned_width * aligned_height * 3; + bitbin_size =3D ALIGN(bitstream_size, 256); + } + + if (num_vpp_pipes > 2) + size_single_pipe =3D bitbin_size / 2; + else + size_single_pipe =3D bitbin_size; + + size_single_pipe =3D ALIGN(size_single_pipe, 256); + sao_bin_buffer_size =3D (64 * (((width + 32) * (height + 32)) >> 10)) + 3= 84; + padded_bin_size =3D ALIGN(size_single_pipe, 256); + size_single_pipe =3D sao_bin_buffer_size + padded_bin_size; + size_single_pipe =3D ALIGN(size_single_pipe, 256); + bitbin_size =3D size_single_pipe * num_vpp_pipes; + + return ALIGN(bitbin_size, 256) * total_bitbin_buffers + 512; +} + +static u32 iris_vpu_enc_bin_size(struct iris_inst *inst) +{ + u32 num_vpp_pipes =3D inst->core->iris_platform_data->num_vpp_pipe; + u32 stage =3D inst->fw_caps[STAGE].value; + struct v4l2_format *f =3D inst->fmt_dst; + u32 height =3D f->fmt.pix_mp.height; + u32 width =3D f->fmt.pix_mp.width; + u32 lcu_size; + + if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) + lcu_size =3D 32; + else + lcu_size =3D 16; + + return hfi_buffer_bin_enc(width, height, stage, lcu_size, + num_vpp_pipes, inst->hfi_rc_type); +} + +static inline +u32 hfi_buffer_comv_enc(u32 frame_width, u32 frame_height, u32 lcu_size, + u32 num_recon, u32 standard) +{ + u32 height_in_lcus =3D ((frame_height) + (lcu_size) - 1) / (lcu_size); + u32 width_in_lcus =3D ((frame_width) + (lcu_size) - 1) / (lcu_size); + u32 num_lcu_in_frame =3D width_in_lcus * height_in_lcus; + u32 mb_height =3D ((frame_height) + 15) >> 4; + u32 mb_width =3D ((frame_width) + 15) >> 4; + u32 size_colloc_mv, size_colloc_rc; + + size_colloc_mv =3D (standard =3D=3D HFI_CODEC_ENCODE_HEVC) ? + (16 * ((num_lcu_in_frame << 2) + 32)) : + (3 * 16 * (width_in_lcus * height_in_lcus + 32)); + size_colloc_mv =3D ALIGN(size_colloc_mv, 256) * num_recon; + size_colloc_rc =3D (((mb_width + 7) >> 3) * 16 * 2 * mb_height); + size_colloc_rc =3D ALIGN(size_colloc_rc, 256) * HFI_MAX_COL_FRAME; + + return size_colloc_mv + size_colloc_rc; +} + +static u32 iris_vpu_enc_comv_size(struct iris_inst *inst) +{ + struct v4l2_format *f =3D inst->fmt_dst; + u32 height =3D f->fmt.pix_mp.height; + u32 width =3D f->fmt.pix_mp.width; + u32 num_recon =3D 1; + u32 lcu_size =3D 16; + + if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) { + lcu_size =3D 32; + return hfi_buffer_comv_enc(width, height, lcu_size, + num_recon + 1, HFI_CODEC_ENCODE_HEVC); + } + + return hfi_buffer_comv_enc(width, height, lcu_size, + num_recon + 1, HFI_CODEC_ENCODE_AVC); +} + +static inline +u32 size_frame_rc_buf_size(u32 standard, u32 frame_height_coded, + u32 num_vpp_pipes_enc) +{ + u32 size =3D 0; + + size =3D (standard =3D=3D HFI_CODEC_ENCODE_HEVC) ? + (256 + 16 * (14 + ((((frame_height_coded) >> 5) + 7) >> 3))) : + (256 + 16 * (14 + ((((frame_height_coded) >> 4) + 7) >> 3))); + size *=3D 11; + + if (num_vpp_pipes_enc > 1) + size =3D ALIGN(size, 256) * num_vpp_pipes_enc; + + return ALIGN(size, 512) * HFI_MAX_COL_FRAME; +} + +static inline +u32 size_enc_slice_info_buf(u32 num_lcu_in_frame) +{ + return ALIGN((256 + (num_lcu_in_frame << 4)), 256); +} + +static inline u32 enc_bitcnt_buf_size(u32 num_lcu_in_frame) +{ + return ALIGN((256 + (4 * (num_lcu_in_frame))), 256); +} + +static inline u32 enc_bitmap_buf_size(u32 num_lcu_in_frame) +{ + return ALIGN((256 + ((num_lcu_in_frame) >> 3)), 256); +} + +static inline u32 size_override_buf(u32 num_lcumb) +{ + return ALIGN(((16 * (((num_lcumb) + 7) >> 3))), 256) * 2; +} + +static inline u32 size_ir_buf(u32 num_lcu_in_frame) +{ + return ALIGN((((((num_lcu_in_frame) << 1) + 7) & (~7)) * 3), 256); +} + +static inline +u32 size_linebuff_data(bool is_ten_bit, u32 frame_width_coded) +{ + return is_ten_bit ? + (((((10 * (frame_width_coded) + 1024) + (256 - 1)) & + (~(256 - 1))) * 1) + + (((((10 * (frame_width_coded) + 1024) >> 1) + (256 - 1)) & + (~(256 - 1))) * 2)) : + (((((8 * (frame_width_coded) + 1024) + (256 - 1)) & + (~(256 - 1))) * 1) + + (((((8 * (frame_width_coded) + 1024) >> 1) + (256 - 1)) & + (~(256 - 1))) * 2)); +} + +static inline +u32 size_left_linebuff_ctrl(u32 standard, u32 frame_height_coded, + u32 num_vpp_pipes_enc) +{ + u32 size =3D 0; + + size =3D standard =3D=3D HFI_CODEC_ENCODE_HEVC ? + (((frame_height_coded) + + (32)) / 32 * 4 * 16) : + (((frame_height_coded) + 15) / 16 * 5 * 16); + + if ((num_vpp_pipes_enc) > 1) { + size +=3D 512; + size =3D ALIGN(size, 512) * + num_vpp_pipes_enc; + } + + return ALIGN(size, 256); +} + +static inline +u32 size_left_linebuff_recon_pix(bool is_ten_bit, u32 frame_height_coded, + u32 num_vpp_pipes_enc) +{ + return (((is_ten_bit + 1) * 2 * (frame_height_coded) + 256) + + (256 << (num_vpp_pipes_enc - 1)) - 1) & + (~((256 << (num_vpp_pipes_enc - 1)) - 1)) * 1; +} + +static inline +u32 size_top_linebuff_ctrl_fe(u32 frame_width_coded, u32 standard) +{ + return standard =3D=3D HFI_CODEC_ENCODE_HEVC ? + ALIGN((64 * ((frame_width_coded) >> 5)), 256) : + ALIGN((256 + 16 * ((frame_width_coded) >> 4)), 256); +} + +static inline +u32 size_left_linebuff_ctrl_fe(u32 frame_height_coded, u32 num_vpp_pipes_e= nc) +{ + return (((256 + 64 * ((frame_height_coded) >> 4)) + + (256 << (num_vpp_pipes_enc - 1)) - 1) & + (~((256 << (num_vpp_pipes_enc - 1)) - 1)) * 1) * + num_vpp_pipes_enc; +} + +static inline +u32 size_left_linebuff_metadata_recon_y(u32 frame_height_coded, + bool is_ten_bit, + u32 num_vpp_pipes_enc) +{ + return ALIGN(((256 + 64 * ((frame_height_coded) / + (8 * (is_ten_bit ? 4 : 8))))), 256) * num_vpp_pipes_enc; +} + +static inline +u32 size_left_linebuff_metadata_recon_uv(u32 frame_height_coded, + bool is_ten_bit, + u32 num_vpp_pipes_enc) +{ + return ALIGN(((256 + 64 * ((frame_height_coded) / + (4 * (is_ten_bit ? 4 : 8))))), 256) * num_vpp_pipes_enc; +} + +static inline +u32 size_linebuff_recon_pix(bool is_ten_bit, u32 frame_width_coded) +{ + return ALIGN(((is_ten_bit ? 3 : 2) * (frame_width_coded)), 256); +} + +static inline +u32 size_line_buf_ctrl(u32 frame_width_coded) +{ + return ALIGN(frame_width_coded, 256); +} + +static inline +u32 size_line_buf_ctrl_id2(u32 frame_width_coded) +{ + return ALIGN(frame_width_coded, 256); +} + +static inline u32 size_line_buf_sde(u32 frame_width_coded) +{ + return ALIGN((256 + (16 * ((frame_width_coded) >> 4))), 256); +} + +static inline +u32 size_vpss_line_buf(u32 num_vpp_pipes_enc, u32 frame_height_coded, + u32 frame_width_coded) +{ + return ALIGN(((((((8192) >> 2) << 5) * (num_vpp_pipes_enc)) + 64) + + (((((max_t(u32, (frame_width_coded), + (frame_height_coded)) + 3) >> 2) << 5) + 256) * 16)), 256); +} + +static inline +u32 size_top_line_buf_first_stg_sao(u32 frame_width_coded) +{ + return ALIGN((16 * ((frame_width_coded) >> 5)), 256); +} + +static inline +u32 size_enc_ref_buffer(u32 frame_width, u32 frame_height) +{ + u32 u_chroma_buffer_height =3D ALIGN(frame_height >> 1, 32); + u32 u_buffer_height =3D ALIGN(frame_height, 32); + u32 u_buffer_width =3D ALIGN(frame_width, 32); + + return (u_buffer_height + u_chroma_buffer_height) * u_buffer_width; +} + +static inline +u32 size_enc_ten_bit_ref_buffer(u32 frame_width, u32 frame_height) +{ + u32 ref_luma_stride_in_bytes =3D ((frame_width + SYSTEM_LAL_TILE10 - 1) /= SYSTEM_LAL_TILE10) * + SYSTEM_LAL_TILE10; + u32 ref_buf_height =3D (frame_height + (32 - 1)) & (~(32 - 1)); + u32 u_ref_stride, luma_size; + u32 ref_chrm_height_in_bytes; + u32 chroma_size; + + u_ref_stride =3D 4 * (ref_luma_stride_in_bytes / 3); + u_ref_stride =3D (u_ref_stride + (128 - 1)) & (~(128 - 1)); + luma_size =3D ref_buf_height * u_ref_stride; + luma_size =3D (luma_size + (4096 - 1)) & (~(4096 - 1)); + + ref_chrm_height_in_bytes =3D (((frame_height + 1) >> 1) + (32 - 1)) & (~(= 32 - 1)); + chroma_size =3D u_ref_stride * ref_chrm_height_in_bytes; + chroma_size =3D (chroma_size + (4096 - 1)) & (~(4096 - 1)); + + return luma_size + chroma_size; +} + +static inline +u32 hfi_ubwc_calc_metadata_plane_stride(u32 frame_width, + u32 metadata_stride_multiple, + u32 tile_width_in_pels) +{ + return ALIGN(((frame_width + (tile_width_in_pels - 1)) / tile_width_in_pe= ls), + metadata_stride_multiple); +} + +static inline +u32 hfi_ubwc_metadata_plane_bufheight(u32 frame_height, + u32 metadata_height_multiple, + u32 tile_height_in_pels) +{ + return ALIGN(((frame_height + (tile_height_in_pels - 1)) / tile_height_in= _pels), + metadata_height_multiple); +} + +static inline +u32 hfi_ubwc_metadata_plane_buffer_size(u32 _metadata_tride, u32 _metadata= _buf_height) +{ + return ALIGN(_metadata_tride * _metadata_buf_height, 4096); +} + +static inline +u32 hfi_buffer_non_comv_enc(u32 frame_width, u32 frame_height, + u32 num_vpp_pipes_enc, u32 lcu_size, u32 standard) +{ + u32 height_in_lcus =3D ((frame_height) + (lcu_size) - 1) / (lcu_size); + u32 width_in_lcus =3D ((frame_width) + (lcu_size) - 1) / (lcu_size); + u32 num_lcu_in_frame =3D width_in_lcus * height_in_lcus; + u32 frame_height_coded =3D height_in_lcus * (lcu_size); + u32 frame_width_coded =3D width_in_lcus * (lcu_size); + u32 num_lcumb, frame_rc_buf_size; + + num_lcumb =3D (frame_height_coded / lcu_size) * + ((frame_width_coded + lcu_size * 8) / lcu_size); + frame_rc_buf_size =3D size_frame_rc_buf_size(standard, frame_height_coded, + num_vpp_pipes_enc); + return size_enc_slice_info_buf(num_lcu_in_frame) + + SIZE_SLICE_CMD_BUFFER + + SIZE_SPS_PPS_SLICE_HDR + + frame_rc_buf_size + + enc_bitcnt_buf_size(num_lcu_in_frame) + + enc_bitmap_buf_size(num_lcu_in_frame) + + SIZE_BSE_SLICE_CMD_BUF + + SIZE_LAMBDA_LUT + + size_override_buf(num_lcumb) + + size_ir_buf(num_lcu_in_frame); +} + +static u32 iris_vpu_enc_non_comv_size(struct iris_inst *inst) +{ + u32 num_vpp_pipes =3D inst->core->iris_platform_data->num_vpp_pipe; + struct v4l2_format *f =3D inst->fmt_dst; + u32 height =3D f->fmt.pix_mp.height; + u32 width =3D f->fmt.pix_mp.width; + u32 lcu_size =3D 16; + + if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) { + lcu_size =3D 32; + return hfi_buffer_non_comv_enc(width, height, num_vpp_pipes, + lcu_size, HFI_CODEC_ENCODE_HEVC) + + SIZE_ONE_SLICE_BUF; + } + + return hfi_buffer_non_comv_enc(width, height, num_vpp_pipes, + lcu_size, HFI_CODEC_ENCODE_AVC); +} + +static inline +u32 hfi_buffer_line_enc(u32 frame_width, u32 frame_height, bool is_ten_bit, + u32 num_vpp_pipes_enc, u32 lcu_size, u32 standard) +{ + u32 width_in_lcus =3D ((frame_width) + (lcu_size) - 1) / (lcu_size); + u32 height_in_lcus =3D ((frame_height) + (lcu_size) - 1) / (lcu_size); + u32 frame_height_coded =3D height_in_lcus * (lcu_size); + u32 frame_width_coded =3D width_in_lcus * (lcu_size); + u32 line_buff_data_size, left_line_buff_ctrl_size; + u32 left_line_buff_metadata_recon__uv__size; + u32 left_line_buff_metadata_recon__y__size; + u32 left_line_buff_recon_pix_size; + u32 top_line_buff_ctrl_fe_size; + u32 line_buff_recon_pix_size; + + line_buff_data_size =3D size_linebuff_data(is_ten_bit, frame_width_coded); + left_line_buff_ctrl_size =3D + size_left_linebuff_ctrl(standard, frame_height_coded, num_vpp_pipes_enc); + left_line_buff_recon_pix_size =3D + size_left_linebuff_recon_pix(is_ten_bit, frame_height_coded, + num_vpp_pipes_enc); + top_line_buff_ctrl_fe_size =3D + size_top_linebuff_ctrl_fe(frame_width_coded, standard); + left_line_buff_metadata_recon__y__size =3D + size_left_linebuff_metadata_recon_y(frame_height_coded, is_ten_bit, + num_vpp_pipes_enc); + left_line_buff_metadata_recon__uv__size =3D + size_left_linebuff_metadata_recon_uv(frame_height_coded, is_ten_bit, + num_vpp_pipes_enc); + line_buff_recon_pix_size =3D size_linebuff_recon_pix(is_ten_bit, frame_wi= dth_coded); + + return size_line_buf_ctrl(frame_width_coded) + + size_line_buf_ctrl_id2(frame_width_coded) + + line_buff_data_size + + left_line_buff_ctrl_size + + left_line_buff_recon_pix_size + + top_line_buff_ctrl_fe_size + + left_line_buff_metadata_recon__y__size + + left_line_buff_metadata_recon__uv__size + + line_buff_recon_pix_size + + size_left_linebuff_ctrl_fe(frame_height_coded, num_vpp_pipes_enc) + + size_line_buf_sde(frame_width_coded) + + size_vpss_line_buf(num_vpp_pipes_enc, frame_height_coded, frame_width_co= ded) + + size_top_line_buf_first_stg_sao(frame_width_coded); +} + +static u32 iris_vpu_enc_line_size(struct iris_inst *inst) +{ + u32 num_vpp_pipes =3D inst->core->iris_platform_data->num_vpp_pipe; + struct v4l2_format *f =3D inst->fmt_dst; + u32 height =3D f->fmt.pix_mp.height; + u32 width =3D f->fmt.pix_mp.width; + u32 lcu_size =3D 16; + + if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) { + lcu_size =3D 32; + return hfi_buffer_line_enc(width, height, 0, num_vpp_pipes, + lcu_size, HFI_CODEC_ENCODE_HEVC); + } + + return hfi_buffer_line_enc(width, height, 0, num_vpp_pipes, + lcu_size, HFI_CODEC_ENCODE_AVC); +} + +static inline +u32 hfi_buffer_dpb_enc(u32 frame_width, u32 frame_height, bool is_ten_bit) +{ + u32 metadata_stride, metadata_buf_height, meta_size_y, meta_size_c; + u32 ten_bit_ref_buf_size =3D 0, ref_buf_size =3D 0; + u32 size; + + if (!is_ten_bit) { + ref_buf_size =3D size_enc_ref_buffer(frame_width, frame_height); + metadata_stride =3D + hfi_ubwc_calc_metadata_plane_stride(frame_width, 64, + HFI_COL_FMT_NV12C_Y_TILE_WIDTH); + metadata_buf_height =3D + hfi_ubwc_metadata_plane_bufheight(frame_height, 16, + HFI_COL_FMT_NV12C_Y_TILE_HEIGHT); + meta_size_y =3D + hfi_ubwc_metadata_plane_buffer_size(metadata_stride, metadata_buf_heigh= t); + meta_size_c =3D + hfi_ubwc_metadata_plane_buffer_size(metadata_stride, metadata_buf_heigh= t); + size =3D ref_buf_size + meta_size_y + meta_size_c; + } else { + ten_bit_ref_buf_size =3D size_enc_ten_bit_ref_buffer(frame_width, frame_= height); + metadata_stride =3D + hfi_ubwc_calc_metadata_plane_stride(frame_width, + IRIS_METADATA_STRIDE_MULTIPLE, + HFI_COL_FMT_TP10C_Y_TILE_WIDTH); + metadata_buf_height =3D + hfi_ubwc_metadata_plane_bufheight(frame_height, + IRIS_METADATA_HEIGHT_MULTIPLE, + HFI_COL_FMT_TP10C_Y_TILE_HEIGHT); + meta_size_y =3D + hfi_ubwc_metadata_plane_buffer_size(metadata_stride, metadata_buf_heigh= t); + meta_size_c =3D + hfi_ubwc_metadata_plane_buffer_size(metadata_stride, metadata_buf_heigh= t); + size =3D ten_bit_ref_buf_size + meta_size_y + meta_size_c; + } + + return size; +} + +static u32 iris_vpu_enc_arp_size(struct iris_inst *inst) +{ + return HFI_BUFFER_ARP_ENC; +} + +inline bool is_scaling_enabled(struct iris_inst *inst) +{ + return inst->crop.left !=3D inst->compose.left || + inst->crop.top !=3D inst->compose.top || + inst->crop.width !=3D inst->compose.width || + inst->crop.height !=3D inst->compose.height; +} + +static inline +u32 hfi_buffer_vpss_enc(u32 dswidth, u32 dsheight, bool ds_enable, + u32 blur, bool is_ten_bit) +{ + if (ds_enable || blur) + return hfi_buffer_dpb_enc(dswidth, dsheight, is_ten_bit); + + return 0; +} + +static inline u32 hfi_buffer_scratch1_enc(u32 frame_width, u32 frame_heigh= t, + u32 lcu_size, u32 num_ref, + bool ten_bit, u32 num_vpp_pipes, + bool is_h265) +{ + u32 line_buf_ctrl_size, line_buf_data_size, leftline_buf_ctrl_size; + u32 line_buf_sde_size, sps_pps_slice_hdr, topline_buf_ctrl_size_FE; + u32 leftline_buf_ctrl_size_FE, line_buf_recon_pix_size; + u32 leftline_buf_recon_pix_size, lambda_lut_size, override_buffer_size; + u32 col_mv_buf_size, vpp_reg_buffer_size, ir_buffer_size; + u32 vpss_line_buf, leftline_buf_meta_recony, h265e_colrcbuf_size; + u32 h265e_framerc_bufsize, h265e_lcubitcnt_bufsize; + u32 h265e_lcubitmap_bufsize, se_stats_bufsize; + u32 bse_reg_buffer_size, bse_slice_cmd_buffer_size, slice_info_bufsize; + u32 line_buf_ctrl_size_buffid2, slice_cmd_buffer_size; + u32 width_lcu_num, height_lcu_num, width_coded, height_coded; + u32 frame_num_lcu, linebuf_meta_recon_uv, topline_bufsize_fe_1stg_sao; + u32 vpss_line_buffer_size_1; + u32 bit_depth, num_lcu_mb; + + width_lcu_num =3D (frame_width + lcu_size - 1) / lcu_size; + height_lcu_num =3D (frame_height + lcu_size - 1) / lcu_size; + frame_num_lcu =3D width_lcu_num * height_lcu_num; + width_coded =3D width_lcu_num * lcu_size; + height_coded =3D height_lcu_num * lcu_size; + num_lcu_mb =3D (height_coded / lcu_size) * + ((width_coded + lcu_size * 8) / lcu_size); + slice_info_bufsize =3D 256 + (frame_num_lcu << 4); + slice_info_bufsize =3D ALIGN(slice_info_bufsize, 256); + line_buf_ctrl_size =3D ALIGN(width_coded, 256); + line_buf_ctrl_size_buffid2 =3D ALIGN(width_coded, 256); + + bit_depth =3D ten_bit ? 10 : 8; + line_buf_data_size =3D + (((((bit_depth * width_coded + 1024) + (256 - 1)) & + (~(256 - 1))) * 1) + + (((((bit_depth * width_coded + 1024) >> 1) + (256 - 1)) & + (~(256 - 1))) * 2)); + + leftline_buf_ctrl_size =3D is_h265 ? ((height_coded + 32) / 32 * 4 * 16) : + ((height_coded + 15) / 16 * 5 * 16); + + if (num_vpp_pipes > 1) { + leftline_buf_ctrl_size +=3D 512; + leftline_buf_ctrl_size =3D + ALIGN(leftline_buf_ctrl_size, 512) * num_vpp_pipes; + } + + leftline_buf_ctrl_size =3D ALIGN(leftline_buf_ctrl_size, 256); + leftline_buf_recon_pix_size =3D + (((ten_bit + 1) * 2 * (height_coded) + 256) + + (256 << (num_vpp_pipes - 1)) - 1) & + (~((256 << (num_vpp_pipes - 1)) - 1)) * 1; + + topline_buf_ctrl_size_FE =3D is_h265 ? (64 * (width_coded >> 5)) : + (256 + 16 * (width_coded >> 4)); + topline_buf_ctrl_size_FE =3D ALIGN(topline_buf_ctrl_size_FE, 256); + leftline_buf_ctrl_size_FE =3D + (((256 + 64 * (height_coded >> 4)) + + (256 << (num_vpp_pipes - 1)) - 1) & + (~((256 << (num_vpp_pipes - 1)) - 1)) * 1) * + num_vpp_pipes; + leftline_buf_meta_recony =3D + (256 + 64 * ((height_coded) / (8 * (ten_bit ? 4 : 8)))); + leftline_buf_meta_recony =3D ALIGN(leftline_buf_meta_recony, 256); + leftline_buf_meta_recony =3D leftline_buf_meta_recony * num_vpp_pipes; + linebuf_meta_recon_uv =3D + (256 + 64 * ((height_coded) / (4 * (ten_bit ? 4 : 8)))); + linebuf_meta_recon_uv =3D ALIGN(linebuf_meta_recon_uv, 256); + linebuf_meta_recon_uv =3D linebuf_meta_recon_uv * num_vpp_pipes; + line_buf_recon_pix_size =3D ((ten_bit ? 3 : 2) * width_coded); + line_buf_recon_pix_size =3D ALIGN(line_buf_recon_pix_size, 256); + slice_cmd_buffer_size =3D ALIGN(20480, 256); + sps_pps_slice_hdr =3D 2048 + 4096; + col_mv_buf_size =3D + is_h265 ? (16 * ((frame_num_lcu << 2) + 32)) : + (3 * 16 * (width_lcu_num * height_lcu_num + 32)); + col_mv_buf_size =3D ALIGN(col_mv_buf_size, 256) * (num_ref + 1); + h265e_colrcbuf_size =3D + (((width_lcu_num + 7) >> 3) * 16 * 2 * height_lcu_num); + if (num_vpp_pipes > 1) + h265e_colrcbuf_size =3D + ALIGN(h265e_colrcbuf_size, 256) * num_vpp_pipes; + + h265e_colrcbuf_size =3D + ALIGN(h265e_colrcbuf_size, 256) * HFI_MAX_COL_FRAME; + h265e_framerc_bufsize =3D + (is_h265) ? + (256 + 16 * (14 + (((height_coded >> 5) + 7) >> 3))) : + (256 + 16 * (14 + (((height_coded >> 4) + 7) >> 3))); + h265e_framerc_bufsize *=3D 6; + if (num_vpp_pipes > 1) + h265e_framerc_bufsize =3D + ALIGN(h265e_framerc_bufsize, 256) * num_vpp_pipes; + + h265e_framerc_bufsize =3D + ALIGN(h265e_framerc_bufsize, 512) * HFI_MAX_COL_FRAME; + h265e_lcubitcnt_bufsize =3D 256 + 4 * frame_num_lcu; + h265e_lcubitcnt_bufsize =3D ALIGN(h265e_lcubitcnt_bufsize, 256); + h265e_lcubitmap_bufsize =3D 256 + (frame_num_lcu >> 3); + h265e_lcubitmap_bufsize =3D ALIGN(h265e_lcubitmap_bufsize, 256); + line_buf_sde_size =3D 256 + 16 * (width_coded >> 4); + line_buf_sde_size =3D ALIGN(line_buf_sde_size, 256); + if ((width_coded * height_coded) > (4096 * 2160)) + se_stats_bufsize =3D 0; + else if ((width_coded * height_coded) > (1920 * 1088)) + se_stats_bufsize =3D (40 * 4 * frame_num_lcu + 256 + 256); + else + se_stats_bufsize =3D (1024 * frame_num_lcu + 256 + 256); + + se_stats_bufsize =3D ALIGN(se_stats_bufsize, 256) * 2; + bse_slice_cmd_buffer_size =3D (((8192 << 2) + 7) & (~7)) * 6; + bse_reg_buffer_size =3D (((512 << 3) + 7) & (~7)) * 4; + vpp_reg_buffer_size =3D (((2048 << 3) + 31) & (~31)) * 10; + lambda_lut_size =3D 256 * 11; + override_buffer_size =3D 16 * ((num_lcu_mb + 7) >> 3); + override_buffer_size =3D ALIGN(override_buffer_size, 256) * 2; + ir_buffer_size =3D (((frame_num_lcu << 1) + 7) & (~7)) * 3; + vpss_line_buffer_size_1 =3D (((8192 >> 2) << 5) * num_vpp_pipes) + 64; + vpss_line_buf =3D + (((((max(width_coded, height_coded) + 3) >> 2) << 5) + 256) * + 16) + + vpss_line_buffer_size_1; + topline_bufsize_fe_1stg_sao =3D 16 * (width_coded >> 5); + topline_bufsize_fe_1stg_sao =3D ALIGN(topline_bufsize_fe_1stg_sao, 256); + + return line_buf_ctrl_size + line_buf_data_size + + line_buf_ctrl_size_buffid2 + leftline_buf_ctrl_size + + vpss_line_buf + col_mv_buf_size + topline_buf_ctrl_size_FE + + leftline_buf_ctrl_size_FE + line_buf_recon_pix_size + + leftline_buf_recon_pix_size + leftline_buf_meta_recony + + linebuf_meta_recon_uv + h265e_colrcbuf_size + + h265e_framerc_bufsize + h265e_lcubitcnt_bufsize + + h265e_lcubitmap_bufsize + line_buf_sde_size + + topline_bufsize_fe_1stg_sao + override_buffer_size + + bse_reg_buffer_size + vpp_reg_buffer_size + sps_pps_slice_hdr + + slice_cmd_buffer_size + bse_slice_cmd_buffer_size + + ir_buffer_size + slice_info_bufsize + lambda_lut_size + + se_stats_bufsize + 1024; +} + +static u32 iris_vpu_enc_scratch1_size(struct iris_inst *inst) +{ + u32 num_vpp_pipes =3D inst->core->iris_platform_data->num_vpp_pipe; + struct v4l2_format *f =3D inst->fmt_dst; + u32 frame_height =3D f->fmt.pix_mp.height; + u32 frame_width =3D f->fmt.pix_mp.width; + u32 num_ref =3D 1; + u32 lcu_size; + bool is_h265; + + if (inst->codec =3D=3D V4L2_PIX_FMT_H264) { + lcu_size =3D 16; + is_h265 =3D false; + } else if (inst->codec =3D=3D V4L2_PIX_FMT_HEVC) { + lcu_size =3D 32; + is_h265 =3D true; + } else { + return 0; + } + + return hfi_buffer_scratch1_enc(frame_width, frame_height, lcu_size, + num_ref, false, num_vpp_pipes, is_h265); +} + +static inline u32 ubwc_metadata_plane_stride(u32 width, + u32 metadata_stride_multi, + u32 tile_width_pels) +{ + return ALIGN(((width + (tile_width_pels - 1)) / tile_width_pels), + metadata_stride_multi); +} + +static inline u32 ubwc_metadata_plane_bufheight(u32 height, + u32 metadata_height_multi, + u32 tile_height_pels) +{ + return ALIGN(((height + (tile_height_pels - 1)) / tile_height_pels), + metadata_height_multi); +} + +static inline u32 ubwc_metadata_plane_buffer_size(u32 metadata_stride, + u32 metadata_buf_height) +{ + return ALIGN(metadata_stride * metadata_buf_height, SZ_4K); +} + +static inline u32 hfi_buffer_scratch2_enc(u32 frame_width, u32 frame_heigh= t, + u32 num_ref, bool ten_bit) +{ + u32 aligned_width, aligned_height, chroma_height, ref_buf_height; + u32 metadata_stride, meta_buf_height, meta_size_y, meta_size_c; + u32 ref_luma_stride_bytes, ref_chroma_height_bytes; + u32 ref_buf_size, ref_stride; + u32 luma_size, chroma_size; + u32 size; + + if (!ten_bit) { + aligned_height =3D ALIGN(frame_height, 32); + chroma_height =3D frame_height >> 1; + chroma_height =3D ALIGN(chroma_height, 32); + aligned_width =3D ALIGN(frame_width, 128); + metadata_stride =3D + ubwc_metadata_plane_stride(frame_width, 64, 32); + meta_buf_height =3D + ubwc_metadata_plane_bufheight(frame_height, 16, 8); + meta_size_y =3D ubwc_metadata_plane_buffer_size(metadata_stride, + meta_buf_height); + meta_size_c =3D ubwc_metadata_plane_buffer_size(metadata_stride, + meta_buf_height); + size =3D (aligned_height + chroma_height) * aligned_width + + meta_size_y + meta_size_c; + size =3D (size * (num_ref + 3)) + 4096; + } else { + ref_buf_height =3D (frame_height + (32 - 1)) & (~(32 - 1)); + ref_luma_stride_bytes =3D ((frame_width + 192 - 1) / 192) * 192; + ref_stride =3D 4 * (ref_luma_stride_bytes / 3); + ref_stride =3D (ref_stride + (128 - 1)) & (~(128 - 1)); + luma_size =3D ref_buf_height * ref_stride; + ref_chroma_height_bytes =3D + (((frame_height + 1) >> 1) + (32 - 1)) & (~(32 - 1)); + chroma_size =3D ref_stride * ref_chroma_height_bytes; + luma_size =3D (luma_size + (SZ_4K - 1)) & (~(SZ_4K - 1)); + chroma_size =3D (chroma_size + (SZ_4K - 1)) & (~(SZ_4K - 1)); + ref_buf_size =3D luma_size + chroma_size; + metadata_stride =3D + ubwc_metadata_plane_stride(frame_width, 64, 48); + meta_buf_height =3D + ubwc_metadata_plane_bufheight(frame_height, 16, 4); + meta_size_y =3D ubwc_metadata_plane_buffer_size(metadata_stride, + meta_buf_height); + meta_size_c =3D ubwc_metadata_plane_buffer_size(metadata_stride, + meta_buf_height); + size =3D ref_buf_size + meta_size_y + meta_size_c; + size =3D (size * (num_ref + 3)) + 4096; + } + + return size; +} + +static u32 iris_vpu_enc_scratch2_size(struct iris_inst *inst) +{ + struct v4l2_format *f =3D inst->fmt_dst; + u32 frame_width =3D f->fmt.pix_mp.width; + u32 frame_height =3D f->fmt.pix_mp.height; + u32 num_ref =3D 1; + + return hfi_buffer_scratch2_enc(frame_width, frame_height, num_ref, + false); +} + +static u32 iris_vpu_enc_vpss_size(struct iris_inst *inst) +{ + u32 ds_enable =3D is_scaling_enabled(inst); + struct v4l2_format *f =3D inst->fmt_dst; + u32 height =3D f->fmt.pix_mp.height; + u32 width =3D f->fmt.pix_mp.width; + + return hfi_buffer_vpss_enc(width, height, ds_enable, 0, 0); +} + static int output_min_count(struct iris_inst *inst) { int output_min_count =3D 4; @@ -573,8 +1389,8 @@ struct iris_vpu_buf_type_handle { =20 int iris_vpu_buf_size(struct iris_inst *inst, enum iris_buffer_type buffer= _type) { - const struct iris_vpu_buf_type_handle *buf_type_handle_arr; - u32 size =3D 0, buf_type_handle_size, i; + const struct iris_vpu_buf_type_handle *buf_type_handle_arr =3D NULL; + u32 size =3D 0, buf_type_handle_size =3D 0, i; =20 static const struct iris_vpu_buf_type_handle dec_internal_buf_type_handle= [] =3D { {BUF_BIN, iris_vpu_dec_bin_size }, @@ -586,8 +1402,24 @@ int iris_vpu_buf_size(struct iris_inst *inst, enum ir= is_buffer_type buffer_type) {BUF_SCRATCH_1, iris_vpu_dec_scratch1_size }, }; =20 - buf_type_handle_size =3D ARRAY_SIZE(dec_internal_buf_type_handle); - buf_type_handle_arr =3D dec_internal_buf_type_handle; + static const struct iris_vpu_buf_type_handle enc_internal_buf_type_handle= [] =3D { + {BUF_BIN, iris_vpu_enc_bin_size }, + {BUF_COMV, iris_vpu_enc_comv_size }, + {BUF_NON_COMV, iris_vpu_enc_non_comv_size }, + {BUF_LINE, iris_vpu_enc_line_size }, + {BUF_ARP, iris_vpu_enc_arp_size }, + {BUF_VPSS, iris_vpu_enc_vpss_size }, + {BUF_SCRATCH_1, iris_vpu_enc_scratch1_size }, + {BUF_SCRATCH_2, iris_vpu_enc_scratch2_size }, + }; + + if (inst->domain =3D=3D DECODER) { + buf_type_handle_size =3D ARRAY_SIZE(dec_internal_buf_type_handle); + buf_type_handle_arr =3D dec_internal_buf_type_handle; + } else if (inst->domain =3D=3D ENCODER) { + buf_type_handle_size =3D ARRAY_SIZE(enc_internal_buf_type_handle); + buf_type_handle_arr =3D enc_internal_buf_type_handle; + } =20 for (i =3D 0; i < buf_type_handle_size; i++) { if (buf_type_handle_arr[i].type =3D=3D buffer_type) { @@ -639,6 +1471,9 @@ int iris_vpu_buf_count(struct iris_inst *inst, enum ir= is_buffer_type buffer_type case BUF_PERSIST: return internal_buffer_count(inst, buffer_type); case BUF_SCRATCH_1: + case BUF_SCRATCH_2: + case BUF_VPSS: + case BUF_ARP: return 1; /* internal buffer count needed by firmware is 1 */ case BUF_DPB: return iris_vpu_dpb_count(inst); diff --git a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_buffer.h index ee95fd20b794c52d0070c93224bd4ee5e4e180d5..94668c5b3d15fb6e10d0b5ed6ed= 704cadb5a6534 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_buffer.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_buffer.h @@ -41,6 +41,7 @@ struct iris_inst; #define SIZE_SLIST_BUF_H265 (BIT(10)) #define H265_DISPLAY_BUF_SIZE (3072) #define H265_NUM_FRM_INFO (48) +#define SIZE_ONE_SLICE_BUF 256 =20 #define VP9_NUM_FRAME_INFO_BUF 32 #define VP9_NUM_PROBABILITY_TABLE_BUF (VP9_NUM_FRAME_INFO_BUF + 4) @@ -80,6 +81,26 @@ struct iris_inst; #define MAX_PE_NBR_DATA_LCU64_LINE_BUFFER_SIZE 384 #define MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE 640 =20 +#define SIZE_SLICE_CMD_BUFFER (ALIGN(20480, 256)) +#define SIZE_SPS_PPS_SLICE_HDR (2048 + 4096) +#define SIZE_BSE_SLICE_CMD_BUF ((((8192 << 2) + 7) & (~7)) * 3) +#define SIZE_LAMBDA_LUT (256 * 11) + +#define HFI_COL_FMT_NV12C_Y_TILE_HEIGHT (8) +#define HFI_COL_FMT_NV12C_Y_TILE_WIDTH (32) +#define HFI_COL_FMT_TP10C_Y_TILE_HEIGHT (4) +#define HFI_COL_FMT_TP10C_Y_TILE_WIDTH (48) + +#define IRIS_METADATA_STRIDE_MULTIPLE 64 +#define IRIS_METADATA_HEIGHT_MULTIPLE 16 + +#define HFI_BUFFER_ARP_ENC 204800 + +#define MAX_WIDTH 4096 +#define MAX_HEIGHT 2304 +#define NUM_MBS_4K (DIV_ROUND_UP(MAX_WIDTH, 16) * DIV_ROUND_UP(MAX_HEIGHT,= 16)) +#define NUM_MBS_720P (((ALIGN(1280, 16)) >> 4) * ((ALIGN(736, 16)) >> 4)) + static inline u32 size_h264d_lb_fe_top_data(u32 frame_width) { return MAX_FE_NBR_DATA_LUMA_LINE_BUFFER_SIZE * ALIGN(frame_width, 16) * 3; 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Mon, 25 Aug 2025 07:02:27 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 57P72Rl9006319 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 25 Aug 2025 07:02:27 GMT Received: from hu-dikshita-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.24; Mon, 25 Aug 2025 00:02:23 -0700 From: Dikshita Agarwal Date: Mon, 25 Aug 2025 12:30:49 +0530 Subject: [PATCH v4 25/26] media: iris: Add support for buffer management ioctls for encoder device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250825-iris-video-encoder-v4-25-84aa2bc0a46b@quicinc.com> References: <20250825-iris-video-encoder-v4-0-84aa2bc0a46b@quicinc.com> In-Reply-To: <20250825-iris-video-encoder-v4-0-84aa2bc0a46b@quicinc.com> To: Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Stefan Schmidt , Vedang Nagar , "Hans Verkuil" , Hans Verkuil CC: , , , Renjiang Han , Wangao Wang , Dikshita Agarwal , Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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This enables userspace applications to manage streaming buffers required for encoding operations. Tested-by: Vikash Garodia # X1E80100 Reviewed-by: Vikash Garodia Tested-by: Neil Armstrong # on SM8550-HDK Tested-by: Neil Armstrong # on SM8650-HDK Signed-off-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e80100-crd --- drivers/media/platform/qcom/iris/iris_common.c | 36 +++++++++++++++ drivers/media/platform/qcom/iris/iris_common.h | 2 + .../platform/qcom/iris/iris_hfi_gen1_command.c | 53 +++++++++++++++---= ---- .../platform/qcom/iris/iris_hfi_gen1_defines.h | 37 +++++++++++++++ .../platform/qcom/iris/iris_hfi_gen1_response.c | 43 +++++++++++++----- .../platform/qcom/iris/iris_hfi_gen2_command.c | 23 ++++++---- .../platform/qcom/iris/iris_hfi_gen2_response.c | 22 ++++++--- drivers/media/platform/qcom/iris/iris_vb2.c | 5 +- drivers/media/platform/qcom/iris/iris_vdec.c | 40 +--------------- drivers/media/platform/qcom/iris/iris_venc.c | 26 +++++++++++ drivers/media/platform/qcom/iris/iris_venc.h | 1 + drivers/media/platform/qcom/iris/iris_vidc.c | 8 ++++ 12 files changed, 215 insertions(+), 81 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_common.c b/drivers/media= /platform/qcom/iris/iris_common.c index d6a9271bcec77f142919070bf0566d0cf8a39562..9fc663bdaf3fc989fe1273b4d42= 80a87f68de85d 100644 --- a/drivers/media/platform/qcom/iris/iris_common.c +++ b/drivers/media/platform/qcom/iris/iris_common.c @@ -10,6 +10,42 @@ #include "iris_instance.h" #include "iris_power.h" =20 +int iris_vb2_buffer_to_driver(struct vb2_buffer *vb2, struct iris_buffer *= buf) +{ + struct vb2_v4l2_buffer *vbuf =3D to_vb2_v4l2_buffer(vb2); + + buf->type =3D iris_v4l2_type_to_driver(vb2->type); + buf->index =3D vb2->index; + buf->fd =3D vb2->planes[0].m.fd; + buf->buffer_size =3D vb2->planes[0].length; + buf->data_offset =3D vb2->planes[0].data_offset; + buf->data_size =3D vb2->planes[0].bytesused - vb2->planes[0].data_offset; + buf->flags =3D vbuf->flags; + buf->timestamp =3D vb2->timestamp; + buf->attr =3D 0; + + return 0; +} + +void iris_set_ts_metadata(struct iris_inst *inst, struct vb2_v4l2_buffer *= vbuf) +{ + u32 mask =3D V4L2_BUF_FLAG_TIMECODE | V4L2_BUF_FLAG_TSTAMP_SRC_MASK; + struct vb2_buffer *vb =3D &vbuf->vb2_buf; + u64 ts_us =3D vb->timestamp; + + if (inst->metadata_idx >=3D ARRAY_SIZE(inst->tss)) + inst->metadata_idx =3D 0; + + do_div(ts_us, NSEC_PER_USEC); + + inst->tss[inst->metadata_idx].flags =3D vbuf->flags & mask; + inst->tss[inst->metadata_idx].tc =3D vbuf->timecode; + inst->tss[inst->metadata_idx].ts_us =3D ts_us; + inst->tss[inst->metadata_idx].ts_ns =3D vb->timestamp; + + inst->metadata_idx++; +} + int iris_process_streamon_input(struct iris_inst *inst) { const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; diff --git a/drivers/media/platform/qcom/iris/iris_common.h b/drivers/media= /platform/qcom/iris/iris_common.h index f385eeb53910555f17602f3951e7a6e9636a9ba2..b2a27b781c9aceb60ff43eff855= d759ea95e23d9 100644 --- a/drivers/media/platform/qcom/iris/iris_common.h +++ b/drivers/media/platform/qcom/iris/iris_common.h @@ -9,6 +9,8 @@ struct iris_inst; struct iris_buffer; =20 +int iris_vb2_buffer_to_driver(struct vb2_buffer *vb2, struct iris_buffer *= buf); +void iris_set_ts_metadata(struct iris_inst *inst, struct vb2_v4l2_buffer *= vbuf); int iris_process_streamon_input(struct iris_inst *inst); int iris_process_streamon_output(struct iris_inst *inst); int iris_session_streamoff(struct iris_inst *inst, u32 plane); diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_command.c index 49173db84b9122655fe0186cfa59497a643226c3..d10a23a3d592c2c5eb6c82f67e3= 30957a01baa8a 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -273,23 +273,44 @@ static int iris_hfi_gen1_session_continue(struct iris= _inst *inst, u32 plane) =20 static int iris_hfi_gen1_queue_input_buffer(struct iris_inst *inst, struct= iris_buffer *buf) { - struct hfi_session_empty_buffer_compressed_pkt ip_pkt; + struct hfi_session_empty_buffer_compressed_pkt com_ip_pkt; + struct hfi_session_empty_buffer_uncompressed_pkt uncom_ip_pkt; =20 - ip_pkt.shdr.hdr.size =3D sizeof(struct hfi_session_empty_buffer_compresse= d_pkt); - ip_pkt.shdr.hdr.pkt_type =3D HFI_CMD_SESSION_EMPTY_BUFFER; - ip_pkt.shdr.session_id =3D inst->session_id; - ip_pkt.time_stamp_hi =3D upper_32_bits(buf->timestamp); - ip_pkt.time_stamp_lo =3D lower_32_bits(buf->timestamp); - ip_pkt.flags =3D buf->flags; - ip_pkt.mark_target =3D 0; - ip_pkt.mark_data =3D 0; - ip_pkt.offset =3D buf->data_offset; - ip_pkt.alloc_len =3D buf->buffer_size; - ip_pkt.filled_len =3D buf->data_size; - ip_pkt.input_tag =3D buf->index; - ip_pkt.packet_buffer =3D buf->device_addr; - - return iris_hfi_queue_cmd_write(inst->core, &ip_pkt, ip_pkt.shdr.hdr.size= ); + if (inst->domain =3D=3D DECODER) { + com_ip_pkt.shdr.hdr.size =3D sizeof(struct hfi_session_empty_buffer_comp= ressed_pkt); + com_ip_pkt.shdr.hdr.pkt_type =3D HFI_CMD_SESSION_EMPTY_BUFFER; + com_ip_pkt.shdr.session_id =3D inst->session_id; + com_ip_pkt.time_stamp_hi =3D upper_32_bits(buf->timestamp); + com_ip_pkt.time_stamp_lo =3D lower_32_bits(buf->timestamp); + com_ip_pkt.flags =3D buf->flags; + com_ip_pkt.mark_target =3D 0; + com_ip_pkt.mark_data =3D 0; + com_ip_pkt.offset =3D buf->data_offset; + com_ip_pkt.alloc_len =3D buf->buffer_size; + com_ip_pkt.filled_len =3D buf->data_size; + com_ip_pkt.input_tag =3D buf->index; + com_ip_pkt.packet_buffer =3D buf->device_addr; + return iris_hfi_queue_cmd_write(inst->core, &com_ip_pkt, + com_ip_pkt.shdr.hdr.size); + } else { + uncom_ip_pkt.shdr.hdr.size =3D + sizeof(struct hfi_session_empty_buffer_uncompressed_pkt); + uncom_ip_pkt.shdr.hdr.pkt_type =3D HFI_CMD_SESSION_EMPTY_BUFFER; + uncom_ip_pkt.shdr.session_id =3D inst->session_id; + uncom_ip_pkt.time_stamp_hi =3D upper_32_bits(buf->timestamp); + uncom_ip_pkt.time_stamp_lo =3D lower_32_bits(buf->timestamp); + uncom_ip_pkt.view_id =3D 0; + uncom_ip_pkt.flags =3D buf->flags; + uncom_ip_pkt.mark_target =3D 0; + uncom_ip_pkt.mark_data =3D 0; + uncom_ip_pkt.offset =3D buf->data_offset; + uncom_ip_pkt.alloc_len =3D buf->buffer_size; + uncom_ip_pkt.filled_len =3D buf->data_size; + uncom_ip_pkt.input_tag =3D buf->index; + uncom_ip_pkt.packet_buffer =3D buf->device_addr; + return iris_hfi_queue_cmd_write(inst->core, &uncom_ip_pkt, + uncom_ip_pkt.shdr.hdr.size); + } } =20 static int iris_hfi_gen1_queue_output_buffer(struct iris_inst *inst, struc= t iris_buffer *buf) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_defines.h index 21853921483b90604b69001064550a50bb9629ad..42226ccee3d9b9eb5f793c3be12= 7acd8afad2138 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_defines.h @@ -216,6 +216,23 @@ struct hfi_session_empty_buffer_compressed_pkt { u32 data; }; =20 +struct hfi_session_empty_buffer_uncompressed_pkt { + struct hfi_session_hdr_pkt shdr; + u32 view_id; + u32 time_stamp_hi; + u32 time_stamp_lo; + u32 flags; + u32 mark_target; + u32 mark_data; + u32 alloc_len; + u32 filled_len; + u32 offset; + u32 input_tag; + u32 packet_buffer; + u32 extradata_buffer; + u32 data; +}; + struct hfi_session_fill_buffer_pkt { struct hfi_session_hdr_pkt shdr; u32 stream_id; @@ -461,6 +478,26 @@ struct hfi_msg_session_empty_buffer_done_pkt { u32 data[]; }; =20 +struct hfi_msg_session_fbd_compressed_pkt { + struct hfi_session_hdr_pkt shdr; + u32 time_stamp_hi; + u32 time_stamp_lo; + u32 error_type; + u32 flags; + u32 mark_target; + u32 mark_data; + u32 stats; + u32 offset; + u32 alloc_len; + u32 filled_len; + u32 input_tag; + u32 output_tag; + u32 picture_type; + u32 packet_buffer; + u32 extradata_buffer; + u32 data[]; +}; + struct hfi_msg_session_fbd_uncompressed_plane0_pkt { struct hfi_session_hdr_pkt shdr; u32 stream_id; diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen1_response.c index 82d3e8de7bff0ac53a971b4763ae848ff8c61ff2..a55d214c84048c6a3ac19a041c0= f78f7e58918b8 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c @@ -387,24 +387,43 @@ static void iris_hfi_gen1_session_etb_done(struct iri= s_inst *inst, void *packet) =20 static void iris_hfi_gen1_session_ftb_done(struct iris_inst *inst, void *p= acket) { - struct hfi_msg_session_fbd_uncompressed_plane0_pkt *pkt =3D packet; + struct hfi_msg_session_fbd_uncompressed_plane0_pkt *uncom_pkt =3D packet; + struct hfi_msg_session_fbd_compressed_pkt *com_pkt =3D packet; struct v4l2_m2m_ctx *m2m_ctx =3D inst->m2m_ctx; struct v4l2_m2m_buffer *m2m_buffer, *n; struct hfi_session_flush_pkt flush_pkt; - u32 timestamp_hi =3D pkt->time_stamp_hi; - u32 timestamp_lo =3D pkt->time_stamp_lo; + u32 timestamp_hi; + u32 timestamp_lo; struct iris_core *core =3D inst->core; - u32 filled_len =3D pkt->filled_len; - u32 pic_type =3D pkt->picture_type; - u32 output_tag =3D pkt->output_tag; + u32 filled_len; + u32 pic_type; + u32 output_tag; struct iris_buffer *buf, *iter; struct iris_buffers *buffers; - u32 hfi_flags =3D pkt->flags; - u32 offset =3D pkt->offset; + u32 hfi_flags; + u32 offset; u64 timestamp_us =3D 0; bool found =3D false; u32 flags =3D 0; =20 + if (inst->domain =3D=3D DECODER) { + timestamp_hi =3D uncom_pkt->time_stamp_hi; + timestamp_lo =3D uncom_pkt->time_stamp_lo; + filled_len =3D uncom_pkt->filled_len; + pic_type =3D uncom_pkt->picture_type; + output_tag =3D uncom_pkt->output_tag; + hfi_flags =3D uncom_pkt->flags; + offset =3D uncom_pkt->offset; + } else { + timestamp_hi =3D com_pkt->time_stamp_hi; + timestamp_lo =3D com_pkt->time_stamp_lo; + filled_len =3D com_pkt->filled_len; + pic_type =3D com_pkt->picture_type; + output_tag =3D com_pkt->output_tag; + hfi_flags =3D com_pkt->flags; + offset =3D com_pkt->offset; + } + if ((hfi_flags & HFI_BUFFERFLAG_EOS) && !filled_len) { reinit_completion(&inst->flush_completion); =20 @@ -418,7 +437,8 @@ static void iris_hfi_gen1_session_ftb_done(struct iris_= inst *inst, void *packet) iris_inst_sub_state_change_drain_last(inst); } =20 - if (iris_split_mode_enabled(inst) && pkt->stream_id =3D=3D 0) { + if (iris_split_mode_enabled(inst) && inst->domain =3D=3D DECODER && + uncom_pkt->stream_id =3D=3D 0) { buffers =3D &inst->buffers[BUF_DPB]; if (!buffers) goto error; @@ -459,7 +479,8 @@ static void iris_hfi_gen1_session_ftb_done(struct iris_= inst *inst, void *packet) timestamp_us =3D timestamp_hi; timestamp_us =3D (timestamp_us << 32) | timestamp_lo; } else { - if (pkt->stream_id =3D=3D 1 && !inst->last_buffer_dequeued) { + if (inst->domain =3D=3D DECODER && uncom_pkt->stream_id =3D=3D 1 && + !inst->last_buffer_dequeued) { if (iris_drc_pending(inst) || iris_drain_pending(inst)) { flags |=3D V4L2_BUF_FLAG_LAST; inst->last_buffer_dequeued =3D true; @@ -551,7 +572,7 @@ static const struct iris_hfi_gen1_response_pkt_info pkt= _infos[] =3D { }, { .pkt =3D HFI_MSG_SESSION_FILL_BUFFER, - .pkt_sz =3D sizeof(struct hfi_msg_session_fbd_uncompressed_plane0_pkt), + .pkt_sz =3D sizeof(struct hfi_msg_session_fbd_compressed_pkt), }, { .pkt =3D HFI_MSG_SESSION_FLUSH, diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen2_command.c index 5aae8162ca1c3b969c30e6ea53b1de88f5ad51cc..4ce71a14250832440099e4cf383= 5b4aedfb749e8 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_command.c @@ -1045,13 +1045,19 @@ static int iris_hfi_gen2_session_drain(struct iris_= inst *inst, u32 plane) inst_hfi_gen2->packet->size); } =20 -static u32 iris_hfi_gen2_buf_type_from_driver(enum iris_buffer_type buffer= _type) +static u32 iris_hfi_gen2_buf_type_from_driver(u32 domain, enum iris_buffer= _type buffer_type) { switch (buffer_type) { case BUF_INPUT: - return HFI_BUFFER_BITSTREAM; + if (domain =3D=3D DECODER) + return HFI_BUFFER_BITSTREAM; + else + return HFI_BUFFER_RAW; case BUF_OUTPUT: - return HFI_BUFFER_RAW; + if (domain =3D=3D DECODER) + return HFI_BUFFER_RAW; + else + return HFI_BUFFER_BITSTREAM; case BUF_BIN: return HFI_BUFFER_BIN; case BUF_COMV: @@ -1091,16 +1097,17 @@ static int iris_set_num_comv(struct iris_inst *inst) &num_comv, sizeof(u32)); } =20 -static void iris_hfi_gen2_get_buffer(struct iris_buffer *buffer, struct ir= is_hfi_buffer *buf) +static void iris_hfi_gen2_get_buffer(u32 domain, struct iris_buffer *buffe= r, + struct iris_hfi_buffer *buf) { memset(buf, 0, sizeof(*buf)); - buf->type =3D iris_hfi_gen2_buf_type_from_driver(buffer->type); + buf->type =3D iris_hfi_gen2_buf_type_from_driver(domain, buffer->type); buf->index =3D buffer->index; buf->base_address =3D buffer->device_addr; buf->addr_offset =3D 0; buf->buffer_size =3D buffer->buffer_size; =20 - if (buffer->type =3D=3D BUF_INPUT) + if (domain =3D=3D DECODER && buffer->type =3D=3D BUF_INPUT) buf->buffer_size =3D ALIGN(buffer->buffer_size, 256); buf->data_offset =3D buffer->data_offset; buf->data_size =3D buffer->data_size; @@ -1117,7 +1124,7 @@ static int iris_hfi_gen2_session_queue_buffer(struct = iris_inst *inst, struct iri u32 port; int ret; =20 - iris_hfi_gen2_get_buffer(buffer, &hfi_buffer); + iris_hfi_gen2_get_buffer(inst->domain, buffer, &hfi_buffer); if (buffer->type =3D=3D BUF_COMV) { ret =3D iris_set_num_comv(inst); if (ret) @@ -1144,7 +1151,7 @@ static int iris_hfi_gen2_session_release_buffer(struc= t iris_inst *inst, struct i struct iris_hfi_buffer hfi_buffer; u32 port; =20 - iris_hfi_gen2_get_buffer(buffer, &hfi_buffer); + iris_hfi_gen2_get_buffer(inst->domain, buffer, &hfi_buffer); hfi_buffer.flags |=3D HFI_BUF_HOST_FLAG_RELEASE; port =3D iris_hfi_gen2_get_port_from_buf_type(inst, buffer->type); =20 diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen2_response.c index 6b8e637ac6d82aee8699db59ee2f04de9e715275..2f1f118eae4f6462ab1aa1d1684= 4b34e6e699f1e 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen2_response.c @@ -480,12 +480,22 @@ static int iris_hfi_gen2_handle_session_buffer(struct= iris_inst *inst, if (!iris_hfi_gen2_is_valid_hfi_port(pkt->port, buffer->type)) return 0; =20 - if (buffer->type =3D=3D HFI_BUFFER_BITSTREAM) - return iris_hfi_gen2_handle_input_buffer(inst, buffer); - else if (buffer->type =3D=3D HFI_BUFFER_RAW) - return iris_hfi_gen2_handle_output_buffer(inst, buffer); - else - return iris_hfi_gen2_handle_release_internal_buffer(inst, buffer); + if (inst->domain =3D=3D DECODER) { + if (buffer->type =3D=3D HFI_BUFFER_BITSTREAM) + return iris_hfi_gen2_handle_input_buffer(inst, buffer); + else if (buffer->type =3D=3D HFI_BUFFER_RAW) + return iris_hfi_gen2_handle_output_buffer(inst, buffer); + else + return iris_hfi_gen2_handle_release_internal_buffer(inst, buffer); + } else { + if (buffer->type =3D=3D HFI_BUFFER_RAW) + return iris_hfi_gen2_handle_input_buffer(inst, buffer); + else if (buffer->type =3D=3D HFI_BUFFER_BITSTREAM) + return iris_hfi_gen2_handle_output_buffer(inst, buffer); + else + return iris_hfi_gen2_handle_release_internal_buffer(inst, buffer); + } + return 0; } =20 static int iris_hfi_gen2_handle_session_drain(struct iris_inst *inst, diff --git a/drivers/media/platform/qcom/iris/iris_vb2.c b/drivers/media/pl= atform/qcom/iris/iris_vb2.c index fbf8ebb74193284dc847c54f76f908656b3098c9..139b821f7952feb33b21a7045ae= f9e8a4782aa3c 100644 --- a/drivers/media/platform/qcom/iris/iris_vb2.c +++ b/drivers/media/platform/qcom/iris/iris_vb2.c @@ -327,7 +327,10 @@ void iris_vb2_buf_queue(struct vb2_buffer *vb2) =20 v4l2_m2m_buf_queue(m2m_ctx, vbuf); =20 - ret =3D iris_vdec_qbuf(inst, vbuf); + if (inst->domain =3D=3D DECODER) + ret =3D iris_vdec_qbuf(inst, vbuf); + else + ret =3D iris_venc_qbuf(inst, vbuf); =20 exit: if (ret) { diff --git a/drivers/media/platform/qcom/iris/iris_vdec.c b/drivers/media/p= latform/qcom/iris/iris_vdec.c index f8d10340f7463490311ab242a44957cf2ddcb3bd..ae13c3e1b426bfd81a7b46dc6c3= ff5eb5c4860cb 100644 --- a/drivers/media/platform/qcom/iris/iris_vdec.c +++ b/drivers/media/platform/qcom/iris/iris_vdec.c @@ -377,44 +377,6 @@ int iris_vdec_streamon_output(struct iris_inst *inst) return ret; } =20 -static int -iris_vdec_vb2_buffer_to_driver(struct vb2_buffer *vb2, struct iris_buffer = *buf) -{ - struct vb2_v4l2_buffer *vbuf =3D to_vb2_v4l2_buffer(vb2); - - buf->type =3D iris_v4l2_type_to_driver(vb2->type); - buf->index =3D vb2->index; - buf->fd =3D vb2->planes[0].m.fd; - buf->buffer_size =3D vb2->planes[0].length; - buf->data_offset =3D vb2->planes[0].data_offset; - buf->data_size =3D vb2->planes[0].bytesused - vb2->planes[0].data_offset; - buf->flags =3D vbuf->flags; - buf->timestamp =3D vb2->timestamp; - buf->attr =3D 0; - - return 0; -} - -static void -iris_set_ts_metadata(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf) -{ - u32 mask =3D V4L2_BUF_FLAG_TIMECODE | V4L2_BUF_FLAG_TSTAMP_SRC_MASK; - struct vb2_buffer *vb =3D &vbuf->vb2_buf; - u64 ts_us =3D vb->timestamp; - - if (inst->metadata_idx >=3D ARRAY_SIZE(inst->tss)) - inst->metadata_idx =3D 0; - - do_div(ts_us, NSEC_PER_USEC); - - inst->tss[inst->metadata_idx].flags =3D vbuf->flags & mask; - inst->tss[inst->metadata_idx].tc =3D vbuf->timecode; - inst->tss[inst->metadata_idx].ts_us =3D ts_us; - inst->tss[inst->metadata_idx].ts_ns =3D vb->timestamp; - - inst->metadata_idx++; -} - int iris_vdec_qbuf(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf) { struct iris_buffer *buf =3D to_iris_buffer(vbuf); @@ -422,7 +384,7 @@ int iris_vdec_qbuf(struct iris_inst *inst, struct vb2_v= 4l2_buffer *vbuf) struct vb2_queue *q; int ret; =20 - ret =3D iris_vdec_vb2_buffer_to_driver(vb2, buf); + ret =3D iris_vb2_buffer_to_driver(vb2, buf); if (ret) return ret; =20 diff --git a/drivers/media/platform/qcom/iris/iris_venc.c b/drivers/media/p= latform/qcom/iris/iris_venc.c index 9f9565bfc2060fbd3a9ba36cb00c0595545675dc..3270c0da668e739d4f98f008db7= 80a0eb5d3dca4 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.c +++ b/drivers/media/platform/qcom/iris/iris_venc.c @@ -10,6 +10,7 @@ #include "iris_common.h" #include "iris_ctrls.h" #include "iris_instance.h" +#include "iris_power.h" #include "iris_venc.h" #include "iris_vpu_buffer.h" =20 @@ -493,3 +494,28 @@ int iris_venc_streamon_output(struct iris_inst *inst) =20 return ret; } + +int iris_venc_qbuf(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf) +{ + struct iris_buffer *buf =3D to_iris_buffer(vbuf); + struct vb2_buffer *vb2 =3D &vbuf->vb2_buf; + struct vb2_queue *q; + int ret; + + ret =3D iris_vb2_buffer_to_driver(vb2, buf); + if (ret) + return ret; + + if (buf->type =3D=3D BUF_INPUT) + iris_set_ts_metadata(inst, vbuf); + + q =3D v4l2_m2m_get_vq(inst->m2m_ctx, vb2->type); + if (!vb2_is_streaming(q)) { + buf->attr |=3D BUF_ATTR_DEFERRED; + return 0; + } + + iris_scale_power(inst); + + return iris_queue_buffer(inst, buf); +} diff --git a/drivers/media/platform/qcom/iris/iris_venc.h b/drivers/media/p= latform/qcom/iris/iris_venc.h index 941b5c186e4550e3eb6325d5ae3eeac4fcee4675..bbf3b635288dd6cc39719bdde19= 42918357791aa 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.h +++ b/drivers/media/platform/qcom/iris/iris_venc.h @@ -20,5 +20,6 @@ int iris_venc_g_param(struct iris_inst *inst, struct v4l2= _streamparm *s_parm); int iris_venc_s_param(struct iris_inst *inst, struct v4l2_streamparm *s_pa= rm); int iris_venc_streamon_input(struct iris_inst *inst); int iris_venc_streamon_output(struct iris_inst *inst); +int iris_venc_qbuf(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf); =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/p= latform/qcom/iris/iris_vidc.c index 9f2e76a3704fcf3ff5fd10b29c43a6937b9ffe1f..245a68248a3f0fdda13b993ece4= 5fa4c0a45aff9 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -664,6 +664,14 @@ static const struct v4l2_ioctl_ops iris_v4l2_ioctl_ops= _enc =3D { .vidioc_g_parm =3D iris_g_parm, .vidioc_streamon =3D v4l2_m2m_ioctl_streamon, .vidioc_streamoff =3D v4l2_m2m_ioctl_streamoff, + .vidioc_reqbufs =3D v4l2_m2m_ioctl_reqbufs, + .vidioc_querybuf =3D v4l2_m2m_ioctl_querybuf, + .vidioc_create_bufs =3D v4l2_m2m_ioctl_create_bufs, + .vidioc_prepare_buf =3D v4l2_m2m_ioctl_prepare_buf, + .vidioc_expbuf =3D v4l2_m2m_ioctl_expbuf, + .vidioc_qbuf =3D v4l2_m2m_ioctl_qbuf, + .vidioc_dqbuf =3D v4l2_m2m_ioctl_dqbuf, + .vidioc_remove_bufs =3D v4l2_m2m_ioctl_remove_bufs, }; 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Mon, 25 Aug 2025 07:02:31 GMT Received: from hu-dikshita-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.24; Mon, 25 Aug 2025 00:02:27 -0700 From: Dikshita Agarwal Date: Mon, 25 Aug 2025 12:30:50 +0530 Subject: [PATCH v4 26/26] media: iris: Add support for drain sequence in encoder video device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250825-iris-video-encoder-v4-26-84aa2bc0a46b@quicinc.com> References: <20250825-iris-video-encoder-v4-0-84aa2bc0a46b@quicinc.com> In-Reply-To: <20250825-iris-video-encoder-v4-0-84aa2bc0a46b@quicinc.com> To: Vikash Garodia , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Stefan Schmidt , Vedang Nagar , "Hans Verkuil" , Hans Verkuil CC: , , , Renjiang Han , Wangao Wang , Dikshita Agarwal , Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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This enables proper signaling to the firmware and ensures that all pending frames are processed and flushed before completing the stream. Tested-by: Vikash Garodia # X1E80100 Reviewed-by: Vikash Garodia Tested-by: Neil Armstrong # on SM8550-HDK Tested-by: Neil Armstrong # on SM8650-HDK Signed-off-by: Dikshita Agarwal Tested-by: Bryan O'Donoghue # x1e80100-crd --- .../platform/qcom/iris/iris_hfi_gen1_command.c | 30 ++++++++--- .../platform/qcom/iris/iris_hfi_gen1_response.c | 5 ++ drivers/media/platform/qcom/iris/iris_state.c | 4 +- drivers/media/platform/qcom/iris/iris_venc.c | 58 ++++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_venc.h | 2 + drivers/media/platform/qcom/iris/iris_vidc.c | 35 +++++++++++++ 6 files changed, 125 insertions(+), 9 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c b/dri= vers/media/platform/qcom/iris/iris_hfi_gen1_command.c index d10a23a3d592c2c5eb6c82f67e330957a01baa8a..29cf392ca2566da286ea3e928ce= 4a22c2e970cc8 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_command.c @@ -450,15 +450,31 @@ static int iris_hfi_gen1_session_unset_buffers(struct= iris_inst *inst, struct ir =20 static int iris_hfi_gen1_session_drain(struct iris_inst *inst, u32 plane) { - struct hfi_session_empty_buffer_compressed_pkt ip_pkt =3D {0}; + if (inst->domain =3D=3D DECODER) { + struct hfi_session_empty_buffer_compressed_pkt ip_pkt =3D {0}; + + ip_pkt.shdr.hdr.size =3D sizeof(struct hfi_session_empty_buffer_compress= ed_pkt); + ip_pkt.shdr.hdr.pkt_type =3D HFI_CMD_SESSION_EMPTY_BUFFER; + ip_pkt.shdr.session_id =3D inst->session_id; + ip_pkt.flags =3D HFI_BUFFERFLAG_EOS; + ip_pkt.packet_buffer =3D 0xdeadb000; + + return iris_hfi_queue_cmd_write(inst->core, &ip_pkt, ip_pkt.shdr.hdr.siz= e); + } =20 - ip_pkt.shdr.hdr.size =3D sizeof(struct hfi_session_empty_buffer_compresse= d_pkt); - ip_pkt.shdr.hdr.pkt_type =3D HFI_CMD_SESSION_EMPTY_BUFFER; - ip_pkt.shdr.session_id =3D inst->session_id; - ip_pkt.flags =3D HFI_BUFFERFLAG_EOS; - ip_pkt.packet_buffer =3D 0xdeadb000; + if (inst->domain =3D=3D ENCODER) { + struct hfi_session_empty_buffer_uncompressed_pkt ip_pkt =3D {0}; + + ip_pkt.shdr.hdr.size =3D sizeof(struct hfi_session_empty_buffer_uncompre= ssed_pkt); + ip_pkt.shdr.hdr.pkt_type =3D HFI_CMD_SESSION_EMPTY_BUFFER; + ip_pkt.shdr.session_id =3D inst->session_id; + ip_pkt.flags =3D HFI_BUFFERFLAG_EOS; + ip_pkt.packet_buffer =3D 0xdeadb000; + + return iris_hfi_queue_cmd_write(inst->core, &ip_pkt, ip_pkt.shdr.hdr.siz= e); + } =20 - return iris_hfi_queue_cmd_write(inst->core, &ip_pkt, ip_pkt.shdr.hdr.size= ); + return -EINVAL; } =20 static int diff --git a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c b/dr= ivers/media/platform/qcom/iris/iris_hfi_gen1_response.c index a55d214c84048c6a3ac19a041c0f78f7e58918b8..8e864c239e293e004d21e9c3604= d3e985c15d9bd 100644 --- a/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c +++ b/drivers/media/platform/qcom/iris/iris_hfi_gen1_response.c @@ -485,6 +485,11 @@ static void iris_hfi_gen1_session_ftb_done(struct iris= _inst *inst, void *packet) flags |=3D V4L2_BUF_FLAG_LAST; inst->last_buffer_dequeued =3D true; } + } else if (inst->domain =3D=3D ENCODER) { + if (!inst->last_buffer_dequeued && iris_drain_pending(inst)) { + flags |=3D V4L2_BUF_FLAG_LAST; + inst->last_buffer_dequeued =3D true; + } } } buf->timestamp =3D timestamp_us; diff --git a/drivers/media/platform/qcom/iris/iris_state.c b/drivers/media/= platform/qcom/iris/iris_state.c index d1dc1a863da0b0b1af60974e9ed2ef68ea225cdd..d14472414750dc7edc4834f32a5= 1f2c5adc3762e 100644 --- a/drivers/media/platform/qcom/iris/iris_state.c +++ b/drivers/media/platform/qcom/iris/iris_state.c @@ -263,11 +263,11 @@ bool iris_allow_cmd(struct iris_inst *inst, u32 cmd) struct vb2_queue *src_q =3D v4l2_m2m_get_src_vq(inst->m2m_ctx); struct vb2_queue *dst_q =3D v4l2_m2m_get_dst_vq(inst->m2m_ctx); =20 - if (cmd =3D=3D V4L2_DEC_CMD_START) { + if (cmd =3D=3D V4L2_DEC_CMD_START || cmd =3D=3D V4L2_ENC_CMD_START) { if (vb2_is_streaming(src_q) || vb2_is_streaming(dst_q)) if (iris_drc_pending(inst) || iris_drain_pending(inst)) return true; - } else if (cmd =3D=3D V4L2_DEC_CMD_STOP) { + } else if (cmd =3D=3D V4L2_DEC_CMD_STOP || cmd =3D=3D V4L2_ENC_CMD_STOP) { if (vb2_is_streaming(src_q)) if (inst->sub_state !=3D IRIS_INST_SUB_DRAIN) return true; diff --git a/drivers/media/platform/qcom/iris/iris_venc.c b/drivers/media/p= latform/qcom/iris/iris_venc.c index 3270c0da668e739d4f98f008db780a0eb5d3dca4..099bd5ed4ae0294725860305254= c4cad1ec88d7e 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.c +++ b/drivers/media/platform/qcom/iris/iris_venc.c @@ -519,3 +519,61 @@ int iris_venc_qbuf(struct iris_inst *inst, struct vb2_= v4l2_buffer *vbuf) =20 return iris_queue_buffer(inst, buf); } + +int iris_venc_start_cmd(struct iris_inst *inst) +{ + const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + enum iris_inst_sub_state clear_sub_state =3D 0; + struct vb2_queue *dst_vq; + int ret; + + dst_vq =3D v4l2_m2m_get_dst_vq(inst->m2m_ctx); + + if (inst->sub_state & IRIS_INST_SUB_DRAIN && + inst->sub_state & IRIS_INST_SUB_DRAIN_LAST) { + vb2_clear_last_buffer_dequeued(dst_vq); + clear_sub_state =3D IRIS_INST_SUB_DRAIN | IRIS_INST_SUB_DRAIN_LAST; + if (inst->sub_state & IRIS_INST_SUB_INPUT_PAUSE) { + if (hfi_ops->session_resume_drain) { + ret =3D hfi_ops->session_resume_drain(inst, + V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); + if (ret) + return ret; + } + clear_sub_state |=3D IRIS_INST_SUB_INPUT_PAUSE; + } + if (inst->sub_state & IRIS_INST_SUB_OUTPUT_PAUSE) { + if (hfi_ops->session_resume_drain) { + ret =3D hfi_ops->session_resume_drain(inst, + V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); + if (ret) + return ret; + } + clear_sub_state |=3D IRIS_INST_SUB_OUTPUT_PAUSE; + } + } else { + dev_err(inst->core->dev, "start called before receiving last_flag\n"); + iris_inst_change_state(inst, IRIS_INST_ERROR); + return -EBUSY; + } + + inst->last_buffer_dequeued =3D false; + + return iris_inst_change_sub_state(inst, clear_sub_state, 0); +} + +int iris_venc_stop_cmd(struct iris_inst *inst) +{ + const struct iris_hfi_command_ops *hfi_ops =3D inst->core->hfi_ops; + int ret; + + ret =3D hfi_ops->session_drain(inst, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); + if (ret) + return ret; + + ret =3D iris_inst_change_sub_state(inst, 0, IRIS_INST_SUB_DRAIN); + + iris_scale_power(inst); + + return ret; +} diff --git a/drivers/media/platform/qcom/iris/iris_venc.h b/drivers/media/p= latform/qcom/iris/iris_venc.h index bbf3b635288dd6cc39719bdde1942918357791aa..c4db7433da537578e05d566d53d= 89a22e1901678 100644 --- a/drivers/media/platform/qcom/iris/iris_venc.h +++ b/drivers/media/platform/qcom/iris/iris_venc.h @@ -21,5 +21,7 @@ int iris_venc_s_param(struct iris_inst *inst, struct v4l2= _streamparm *s_parm); int iris_venc_streamon_input(struct iris_inst *inst); int iris_venc_streamon_output(struct iris_inst *inst); int iris_venc_qbuf(struct iris_inst *inst, struct vb2_v4l2_buffer *vbuf); +int iris_venc_start_cmd(struct iris_inst *inst); +int iris_venc_stop_cmd(struct iris_inst *inst); =20 #endif diff --git a/drivers/media/platform/qcom/iris/iris_vidc.c b/drivers/media/p= latform/qcom/iris/iris_vidc.c index 245a68248a3f0fdda13b993ece45fa4c0a45aff9..798c3613e57eac1742633d61c14= 82229dbc32562 100644 --- a/drivers/media/platform/qcom/iris/iris_vidc.c +++ b/drivers/media/platform/qcom/iris/iris_vidc.c @@ -597,6 +597,39 @@ static int iris_dec_cmd(struct file *filp, void *fh, return ret; } =20 +static int iris_enc_cmd(struct file *filp, void *fh, + struct v4l2_encoder_cmd *enc) +{ + struct iris_inst *inst =3D iris_get_inst(filp); + int ret =3D 0; + + mutex_lock(&inst->lock); + + ret =3D v4l2_m2m_ioctl_encoder_cmd(filp, fh, enc); + if (ret) + goto unlock; + + if (inst->state =3D=3D IRIS_INST_DEINIT) + goto unlock; + + if (!iris_allow_cmd(inst, enc->cmd)) { + ret =3D -EBUSY; + goto unlock; + } + + if (enc->cmd =3D=3D V4L2_ENC_CMD_START) + ret =3D iris_venc_start_cmd(inst); + else if (enc->cmd =3D=3D V4L2_ENC_CMD_STOP) + ret =3D iris_venc_stop_cmd(inst); + else + ret =3D -EINVAL; + +unlock: + mutex_unlock(&inst->lock); + + return ret; +} + static struct v4l2_file_operations iris_v4l2_file_ops =3D { .owner =3D THIS_MODULE, .open =3D iris_open, @@ -672,6 +705,8 @@ static const struct v4l2_ioctl_ops iris_v4l2_ioctl_ops_= enc =3D { .vidioc_qbuf =3D v4l2_m2m_ioctl_qbuf, .vidioc_dqbuf =3D v4l2_m2m_ioctl_dqbuf, .vidioc_remove_bufs =3D v4l2_m2m_ioctl_remove_bufs, + .vidioc_try_encoder_cmd =3D v4l2_m2m_ioctl_try_encoder_cmd, + .vidioc_encoder_cmd =3D iris_enc_cmd, }; =20 void iris_init_ops(struct iris_core *core) --=20 2.34.1