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Mon, 25 Aug 2025 02:48:59 -0700 (PDT) From: Bartosz Golaszewski Date: Mon, 25 Aug 2025 11:48:50 +0200 Subject: [PATCH RESEND 09/14] gpio: dwapb: use new generic GPIO chip API Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-gpio-mmio-gpio-conv-v1-9-356b4b1d5110@linaro.org> References: <20250825-gpio-mmio-gpio-conv-v1-0-356b4b1d5110@linaro.org> In-Reply-To: <20250825-gpio-mmio-gpio-conv-v1-0-356b4b1d5110@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Yinbo Zhu , Hoan Tran , Manivannan Sadhasivam , Yang Shen Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-unisoc@lists.infradead.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=13939; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=bJtZHBh+83sX2WnxophXL3lqiaxB1fbZNtH20byx7Cc=; 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Signed-off-by: Bartosz Golaszewski --- drivers/gpio/gpio-dwapb.c | 160 +++++++++++++++++++++++++-----------------= ---- 1 file changed, 86 insertions(+), 74 deletions(-) diff --git a/drivers/gpio/gpio-dwapb.c b/drivers/gpio/gpio-dwapb.c index 43b667b41f5dce4a1a971af4506146e4ffb59b25..0fb781ca9da29545dce23ddbdf3= bd5927c714b4c 100644 --- a/drivers/gpio/gpio-dwapb.c +++ b/drivers/gpio/gpio-dwapb.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -99,7 +100,7 @@ struct dwapb_gpio_port_irqchip { }; =20 struct dwapb_gpio_port { - struct gpio_chip gc; + struct gpio_generic_chip chip; struct dwapb_gpio_port_irqchip *pirq; struct dwapb_gpio *gpio; #ifdef CONFIG_PM_SLEEP @@ -107,8 +108,12 @@ struct dwapb_gpio_port { #endif unsigned int idx; }; -#define to_dwapb_gpio(_gc) \ - (container_of(_gc, struct dwapb_gpio_port, gc)->gpio) + +static inline struct dwapb_gpio *to_dwapb_gpio(struct gpio_chip *gc) +{ + return container_of(to_gpio_generic_chip(gc), + struct dwapb_gpio_port, chip)->gpio; +} =20 struct dwapb_gpio { struct device *dev; @@ -148,19 +153,19 @@ static inline u32 gpio_reg_convert(struct dwapb_gpio = *gpio, unsigned int offset) =20 static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset) { - struct gpio_chip *gc =3D &gpio->ports[0].gc; - void __iomem *reg_base =3D gpio->regs; + struct gpio_generic_chip *chip =3D &gpio->ports[0].chip; + void __iomem *reg_base =3D gpio->regs; =20 - return gc->read_reg(reg_base + gpio_reg_convert(gpio, offset)); + return gpio_generic_read_reg(chip, reg_base + gpio_reg_convert(gpio, offs= et)); } =20 static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offse= t, u32 val) { - struct gpio_chip *gc =3D &gpio->ports[0].gc; - void __iomem *reg_base =3D gpio->regs; + struct gpio_generic_chip *chip =3D &gpio->ports[0].chip; + void __iomem *reg_base =3D gpio->regs; =20 - gc->write_reg(reg_base + gpio_reg_convert(gpio, offset), val); + gpio_generic_write_reg(chip, reg_base + gpio_reg_convert(gpio, offset), v= al); } =20 static struct dwapb_gpio_port *dwapb_offs_to_port(struct dwapb_gpio *gpio,= unsigned int offs) @@ -186,7 +191,7 @@ static void dwapb_toggle_trigger(struct dwapb_gpio *gpi= o, unsigned int offs) =20 if (!port) return; - gc =3D &port->gc; + gc =3D &port->chip.gc; =20 pol =3D dwapb_read(gpio, GPIO_INT_POLARITY); /* Just read the current value right out of the data register */ @@ -201,13 +206,13 @@ static void dwapb_toggle_trigger(struct dwapb_gpio *g= pio, unsigned int offs) =20 static u32 dwapb_do_irq(struct dwapb_gpio *gpio) { - struct gpio_chip *gc =3D &gpio->ports[0].gc; + struct gpio_generic_chip *gen_gc =3D &gpio->ports[0].chip; unsigned long irq_status; irq_hw_number_t hwirq; =20 irq_status =3D dwapb_read(gpio, GPIO_INTSTATUS); for_each_set_bit(hwirq, &irq_status, DWAPB_MAX_GPIOS) { - int gpio_irq =3D irq_find_mapping(gc->irq.domain, hwirq); + int gpio_irq =3D irq_find_mapping(gen_gc->gc.irq.domain, hwirq); u32 irq_type =3D irq_get_trigger_type(gpio_irq); =20 generic_handle_irq(gpio_irq); @@ -237,27 +242,27 @@ static irqreturn_t dwapb_irq_handler_mfd(int irq, voi= d *dev_id) static void dwapb_irq_ack(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct gpio_generic_chip *gen_gc =3D to_gpio_generic_chip(gc); struct dwapb_gpio *gpio =3D to_dwapb_gpio(gc); u32 val =3D BIT(irqd_to_hwirq(d)); - unsigned long flags; =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(gen_gc); + dwapb_write(gpio, GPIO_PORTA_EOI, val); - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); } =20 static void dwapb_irq_mask(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct gpio_generic_chip *gen_gc =3D to_gpio_generic_chip(gc); struct dwapb_gpio *gpio =3D to_dwapb_gpio(gc); irq_hw_number_t hwirq =3D irqd_to_hwirq(d); - unsigned long flags; u32 val; =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); - val =3D dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq); - dwapb_write(gpio, GPIO_INTMASK, val); - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); + scoped_guard(gpio_generic_lock_irqsave, gen_gc) { + val =3D dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq); + dwapb_write(gpio, GPIO_INTMASK, val); + } =20 gpiochip_disable_irq(gc, hwirq); } @@ -265,59 +270,61 @@ static void dwapb_irq_mask(struct irq_data *d) static void dwapb_irq_unmask(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct gpio_generic_chip *gen_gc =3D to_gpio_generic_chip(gc); struct dwapb_gpio *gpio =3D to_dwapb_gpio(gc); irq_hw_number_t hwirq =3D irqd_to_hwirq(d); - unsigned long flags; u32 val; =20 gpiochip_enable_irq(gc, hwirq); =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(gen_gc); + val =3D dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq); dwapb_write(gpio, GPIO_INTMASK, val); - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); } =20 static void dwapb_irq_enable(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct gpio_generic_chip *gen_gc =3D to_gpio_generic_chip(gc); struct dwapb_gpio *gpio =3D to_dwapb_gpio(gc); irq_hw_number_t hwirq =3D irqd_to_hwirq(d); - unsigned long flags; u32 val; =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(gen_gc); + val =3D dwapb_read(gpio, GPIO_INTEN) | BIT(hwirq); dwapb_write(gpio, GPIO_INTEN, val); val =3D dwapb_read(gpio, GPIO_INTMASK) & ~BIT(hwirq); dwapb_write(gpio, GPIO_INTMASK, val); - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); } =20 static void dwapb_irq_disable(struct irq_data *d) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct gpio_generic_chip *gen_gc =3D to_gpio_generic_chip(gc); struct dwapb_gpio *gpio =3D to_dwapb_gpio(gc); irq_hw_number_t hwirq =3D irqd_to_hwirq(d); - unsigned long flags; u32 val; =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(gen_gc); + val =3D dwapb_read(gpio, GPIO_INTMASK) | BIT(hwirq); dwapb_write(gpio, GPIO_INTMASK, val); val =3D dwapb_read(gpio, GPIO_INTEN) & ~BIT(hwirq); dwapb_write(gpio, GPIO_INTEN, val); - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); } =20 static int dwapb_irq_set_type(struct irq_data *d, u32 type) { struct gpio_chip *gc =3D irq_data_get_irq_chip_data(d); + struct gpio_generic_chip *gen_gc =3D to_gpio_generic_chip(gc); struct dwapb_gpio *gpio =3D to_dwapb_gpio(gc); irq_hw_number_t bit =3D irqd_to_hwirq(d); - unsigned long level, polarity, flags; + unsigned long level, polarity; + + guard(gpio_generic_lock_irqsave)(gen_gc); =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); level =3D dwapb_read(gpio, GPIO_INTTYPE_LEVEL); polarity =3D dwapb_read(gpio, GPIO_INT_POLARITY); =20 @@ -352,7 +359,6 @@ static int dwapb_irq_set_type(struct irq_data *d, u32 t= ype) dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level); if (type !=3D IRQ_TYPE_EDGE_BOTH) dwapb_write(gpio, GPIO_INT_POLARITY, polarity); - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); =20 return 0; } @@ -393,11 +399,12 @@ static int dwapb_gpio_set_debounce(struct gpio_chip *= gc, unsigned offset, unsigned debounce) { struct dwapb_gpio_port *port =3D gpiochip_get_data(gc); + struct gpio_generic_chip *gen_gc =3D to_gpio_generic_chip(gc); struct dwapb_gpio *gpio =3D port->gpio; - unsigned long flags, val_deb; + unsigned long val_deb; unsigned long mask =3D BIT(offset); =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(gen_gc); =20 val_deb =3D dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); if (debounce) @@ -406,8 +413,6 @@ static int dwapb_gpio_set_debounce(struct gpio_chip *gc, val_deb &=3D ~mask; dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb); =20 - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); - return 0; } =20 @@ -445,7 +450,7 @@ static void dwapb_configure_irqs(struct dwapb_gpio *gpi= o, struct dwapb_port_property *pp) { struct dwapb_gpio_port_irqchip *pirq; - struct gpio_chip *gc =3D &port->gc; + struct gpio_chip *gc =3D &port->chip.gc; struct gpio_irq_chip *girq; int err; =20 @@ -501,6 +506,7 @@ static int dwapb_gpio_add_port(struct dwapb_gpio *gpio, struct dwapb_port_property *pp, unsigned int offs) { + struct gpio_generic_chip_config config; struct dwapb_gpio_port *port; void __iomem *dat, *set, *dirout; int err; @@ -519,32 +525,39 @@ static int dwapb_gpio_add_port(struct dwapb_gpio *gpi= o, set =3D gpio->regs + GPIO_SWPORTA_DR + pp->idx * GPIO_SWPORT_DR_STRIDE; dirout =3D gpio->regs + GPIO_SWPORTA_DDR + pp->idx * GPIO_SWPORT_DDR_STRI= DE; =20 + config =3D (typeof(config)){ + .dev =3D gpio->dev, + .sz =3D 4, + .dat =3D dat, + .set =3D set, + .dirout =3D dirout, + }; + /* This registers 32 GPIO lines per port */ - err =3D bgpio_init(&port->gc, gpio->dev, 4, dat, set, NULL, dirout, - NULL, 0); + err =3D gpio_generic_chip_init(&port->chip, &config); if (err) { dev_err(gpio->dev, "failed to init gpio chip for port%d\n", port->idx); return err; } =20 - port->gc.fwnode =3D pp->fwnode; - port->gc.ngpio =3D pp->ngpio; - port->gc.base =3D pp->gpio_base; - port->gc.request =3D gpiochip_generic_request; - port->gc.free =3D gpiochip_generic_free; + port->chip.gc.fwnode =3D pp->fwnode; + port->chip.gc.ngpio =3D pp->ngpio; + port->chip.gc.base =3D pp->gpio_base; + port->chip.gc.request =3D gpiochip_generic_request; + port->chip.gc.free =3D gpiochip_generic_free; =20 /* Only port A support debounce */ if (pp->idx =3D=3D 0) - port->gc.set_config =3D dwapb_gpio_set_config; + port->chip.gc.set_config =3D dwapb_gpio_set_config; else - port->gc.set_config =3D gpiochip_generic_config; + port->chip.gc.set_config =3D gpiochip_generic_config; =20 /* Only port A can provide interrupts in all configurations of the IP */ if (pp->idx =3D=3D 0) dwapb_configure_irqs(gpio, port, pp); =20 - err =3D devm_gpiochip_add_data(gpio->dev, &port->gc, port); + err =3D devm_gpiochip_add_data(gpio->dev, &port->chip.gc, port); if (err) { dev_err(gpio->dev, "failed to register gpiochip for port%d\n", port->idx); @@ -750,38 +763,37 @@ static int dwapb_gpio_probe(struct platform_device *p= dev) static int dwapb_gpio_suspend(struct device *dev) { struct dwapb_gpio *gpio =3D dev_get_drvdata(dev); - struct gpio_chip *gc =3D &gpio->ports[0].gc; - unsigned long flags; + struct gpio_generic_chip *gen_gc =3D &gpio->ports[0].chip; int i; =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); - for (i =3D 0; i < gpio->nr_ports; i++) { - unsigned int offset; - unsigned int idx =3D gpio->ports[i].idx; - struct dwapb_context *ctx =3D gpio->ports[i].ctx; + scoped_guard(gpio_generic_lock_irqsave, gen_gc) { + for (i =3D 0; i < gpio->nr_ports; i++) { + unsigned int offset; + unsigned int idx =3D gpio->ports[i].idx; + struct dwapb_context *ctx =3D gpio->ports[i].ctx; =20 - offset =3D GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE; - ctx->dir =3D dwapb_read(gpio, offset); + offset =3D GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_STRIDE; + ctx->dir =3D dwapb_read(gpio, offset); =20 - offset =3D GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE; - ctx->data =3D dwapb_read(gpio, offset); + offset =3D GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_STRIDE; + ctx->data =3D dwapb_read(gpio, offset); =20 - offset =3D GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE; - ctx->ext =3D dwapb_read(gpio, offset); + offset =3D GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_STRIDE; + ctx->ext =3D dwapb_read(gpio, offset); =20 - /* Only port A can provide interrupts */ - if (idx =3D=3D 0) { - ctx->int_mask =3D dwapb_read(gpio, GPIO_INTMASK); - ctx->int_en =3D dwapb_read(gpio, GPIO_INTEN); - ctx->int_pol =3D dwapb_read(gpio, GPIO_INT_POLARITY); - ctx->int_type =3D dwapb_read(gpio, GPIO_INTTYPE_LEVEL); - ctx->int_deb =3D dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); + /* Only port A can provide interrupts */ + if (idx =3D=3D 0) { + ctx->int_mask =3D dwapb_read(gpio, GPIO_INTMASK); + ctx->int_en =3D dwapb_read(gpio, GPIO_INTEN); + ctx->int_pol =3D dwapb_read(gpio, GPIO_INT_POLARITY); + ctx->int_type =3D dwapb_read(gpio, GPIO_INTTYPE_LEVEL); + ctx->int_deb =3D dwapb_read(gpio, GPIO_PORTA_DEBOUNCE); =20 - /* Mask out interrupts */ - dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en); + /* Mask out interrupts */ + dwapb_write(gpio, GPIO_INTMASK, ~ctx->wake_en); + } } } - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); =20 clk_bulk_disable_unprepare(DWAPB_NR_CLOCKS, gpio->clks); =20 @@ -791,8 +803,8 @@ static int dwapb_gpio_suspend(struct device *dev) static int dwapb_gpio_resume(struct device *dev) { struct dwapb_gpio *gpio =3D dev_get_drvdata(dev); - struct gpio_chip *gc =3D &gpio->ports[0].gc; - unsigned long flags; + struct gpio_chip *gc =3D &gpio->ports[0].chip.gc; + struct gpio_generic_chip *gen_gc =3D to_gpio_generic_chip(gc); int i, err; =20 err =3D clk_bulk_prepare_enable(DWAPB_NR_CLOCKS, gpio->clks); @@ -801,7 +813,8 @@ static int dwapb_gpio_resume(struct device *dev) return err; } =20 - raw_spin_lock_irqsave(&gc->bgpio_lock, flags); + guard(gpio_generic_lock_irqsave)(gen_gc); + for (i =3D 0; i < gpio->nr_ports; i++) { unsigned int offset; unsigned int idx =3D gpio->ports[i].idx; @@ -828,7 +841,6 @@ static int dwapb_gpio_resume(struct device *dev) dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff); } } - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); =20 return 0; } --=20 2.48.1