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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-24668864431sm84989705ad.93.2025.08.25.23.03.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Aug 2025 23:03:11 -0700 (PDT) From: Wenbin Yao Date: Mon, 25 Aug 2025 23:01:50 -0700 Subject: [PATCH v3 4/4] phy: qcom: qmp-pcie: Add support for Glymur PCIe Gen5x4 PHY Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-glymur_pcie5-v3-4-5c1d1730c16f@oss.qualcomm.com> References: <20250825-glymur_pcie5-v3-0-5c1d1730c16f@oss.qualcomm.com> In-Reply-To: <20250825-glymur_pcie5-v3-0-5c1d1730c16f@oss.qualcomm.com> To: Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Wenbin Yao , konrad.dybcio@oss.qualcomm.com, qiang.yu@oss.qualcomm.com, Prudhvi Yarlagadda X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756188184; l=2792; i=wenbin.yao@oss.qualcomm.com; s=20250806; h=from:subject:message-id; bh=Nr0WsLxc/VUi4y8+iOUuwvKAT/kAkH+eKp93ndoPpzE=; b=IUeQDJcS0dNEhoUydBJ/BH9E2XHxLFHiVZroalqVWq/AMBSiil/8rq7ghXuNk5bZdyRNohUj3 zH7iwApD2x4CZ+dNfxgFd4NhxSVSBGlfMIl9G/oSS4izoGfAJBLsfiT X-Developer-Key: i=wenbin.yao@oss.qualcomm.com; a=ed25519; pk=nBPq+51QejLSupTaJoOMvgFbXSyRVCJexMZ+bUTG5KU= X-Proofpoint-ORIG-GUID: yBnv7u0xin9-AvBGh8yiAg72XPUx1U-9 X-Proofpoint-GUID: yBnv7u0xin9-AvBGh8yiAg72XPUx1U-9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODI2MDAwMSBTYWx0ZWRfX4eV0N53HA7OU BaRi9LA0tfxiCoOq+1YrC++lLcQA+NMV7hH80Ixz51Nkn1ulPBtv+8PZrKogDOjzFlw1dqhNw2H IrnywG5wQ6NA+cEpiP/LB/HxHYfDC8JMOiQDs7K9N2/ARA1QNrcR/zAOy3hoEY/jtP4fRJn2wym ZgOhCT5qx0iSWWbUJz0vO9LgVOl+BvtKi/Nd6lq3pB/ScuYXpjL3TQ0V4XieB9KzVQFbKV7Nhn2 FDcM09JGOc1KxgY9aMgH3aQ72pcShDtSeoAmyrKeT5xp7f5AiaDxMhFSrxxCPo7Dcrmcsb4jZUD mRhSwyMgm4kU5u/LCGv0bbnRYRrfHTWN4wrXlBygwHKLUTC70J7odWJVji1XxvOJSxy5C/UXeP1 Og4i4lII X-Authority-Analysis: v=2.4 cv=PJUP+eqC c=1 sm=1 tr=0 ts=68ad4e21 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=KvwrgBbZ-pJFRlqJlL4A:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-26_01,2025-08-26_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 impostorscore=0 phishscore=0 priorityscore=1501 spamscore=0 adultscore=0 clxscore=1015 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508260001 From: Prudhvi Yarlagadda Add support for Gen5 x4 PCIe QMP PHY found on Glymur platform. Signed-off-by: Prudhvi Yarlagadda Signed-off-by: Wenbin Yao Acked-by: Manivannan Sadhasivam Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 32 ++++++++++++++++++++++++++++= ++++ 1 file changed, 32 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcom= m/phy-qcom-qmp-pcie.c index 95830dcfdec9b1f68fd55d1cc3c102985cfafcc1..011687e6191e7a496b56cd85a14= 9b10f7f00a749 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -93,6 +93,12 @@ static const unsigned int pciephy_v6_regs_layout[QPHY_LA= YOUT_SIZE] =3D { [QPHY_PCS_POWER_DOWN_CONTROL] =3D QPHY_V6_PCS_POWER_DOWN_CONTROL, }; =20 +static const unsigned int pciephy_v8_50_regs_layout[QPHY_LAYOUT_SIZE] =3D { + [QPHY_START_CTRL] =3D QPHY_V8_50_PCS_START_CONTROL, + [QPHY_PCS_STATUS] =3D QPHY_V8_50_PCS_STATUS1, + [QPHY_PCS_POWER_DOWN_CONTROL] =3D QPHY_V8_50_PCS_POWER_DOWN_CONTROL, +}; + static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] =3D { QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14), QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), @@ -2963,6 +2969,7 @@ struct qmp_pcie_offsets { u16 rx2; u16 txz; u16 rxz; + u16 txrxz; u16 ln_shrd; }; =20 @@ -3229,6 +3236,12 @@ static const struct qmp_pcie_offsets qmp_pcie_offset= s_v6_30 =3D { .ln_shrd =3D 0x8000, }; =20 +static const struct qmp_pcie_offsets qmp_pcie_offsets_v8_50 =3D { + .serdes =3D 0x8000, + .pcs =3D 0x9000, + .txrxz =3D 0xd000, +}; + static const struct qmp_phy_cfg ipq8074_pciephy_cfg =3D { .lanes =3D 1, =20 @@ -4258,6 +4271,22 @@ static const struct qmp_phy_cfg qmp_v6_gen4x4_pcieph= y_cfg =3D { .phy_status =3D PHYSTATUS_4_20, }; =20 +static const struct qmp_phy_cfg glymur_qmp_gen5x4_pciephy_cfg =3D { + .lanes =3D 4, + + .offsets =3D &qmp_pcie_offsets_v8_50, + + .reset_list =3D sdm845_pciephy_reset_l, + .num_resets =3D ARRAY_SIZE(sdm845_pciephy_reset_l), + .vreg_list =3D qmp_phy_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + + .regs =3D pciephy_v8_50_regs_layout, + + .pwrdn_ctrl =3D SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status =3D PHYSTATUS_4_20, +}; + static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_ph= y_cfg_tbls *tbls) { const struct qmp_phy_cfg *cfg =3D qmp->cfg; @@ -5004,6 +5033,9 @@ static int qmp_pcie_probe(struct platform_device *pde= v) =20 static const struct of_device_id qmp_pcie_of_match_table[] =3D { { + .compatible =3D "qcom,glymur-qmp-gen5x4-pcie-phy", + .data =3D &glymur_qmp_gen5x4_pciephy_cfg, + }, { .compatible =3D "qcom,ipq6018-qmp-pcie-phy", .data =3D &ipq6018_pciephy_cfg, }, { --=20 2.34.1