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Sun, 24 Aug 2025 22:51:18 -0700 (PDT) Received: from [127.0.0.1] ([172.191.151.49]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70da72da3fdsm39639156d6.73.2025.08.24.22.51.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Aug 2025 22:51:17 -0700 (PDT) From: Denzeel Oliva Date: Mon, 25 Aug 2025 05:51:15 +0000 Subject: [PATCH v4 1/4] clk: samsung: exynos990: Fix CMU TOP mux/div widths and add fixed-factors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-cmu-top-v4-1-71d783680529@gmail.com> References: <20250825-cmu-top-v4-0-71d783680529@gmail.com> In-Reply-To: <20250825-cmu-top-v4-0-71d783680529@gmail.com> To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Denzeel Oliva X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1756101076; l=6467; i=wachiturroxd150@gmail.com; s=20250825; h=from:subject:message-id; bh=20mWLZEGgEbpDt41ggUQHBXHpARZ9CqTlFdX4+rxceg=; b=Zri0g7KTRqMlS6NXZPNPZ2GsLp22QhlEGJhIAojRC7rJQvKzBzlzXB2Hhzt6LVv14Vxw22iGu Zh1DMhIjqkPBVXfKgGtLVZwq2cp9QQpmGEbBdIjw5tvSITyd+NIoPPq X-Developer-Key: i=wachiturroxd150@gmail.com; a=ed25519; pk=qZrip2idhSTNQABELWG6WKCrg9xOKep//pV9JGKmW5k= Correct mux/div bit widths in CMU TOP (DPU, DSP_BUS, G2D_MSCL, HSI0/1/2). Replace wrong divs with fixed-factor clocks for HSI1/2 PCIe and USBDP debug. Also add OTP rate in ffactor. These align with Exynos990 downstream cmucal and ensure correct parent/rate selection. Signed-off-by: Denzeel Oliva --- drivers/clk/samsung/clk-exynos990.c | 37 +++++++++++++++++++++------------= ---- 1 file changed, 21 insertions(+), 16 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-= exynos990.c index 8d3f193d2..105ba0363 100644 --- a/drivers/clk/samsung/clk-exynos990.c +++ b/drivers/clk/samsung/clk-exynos990.c @@ -759,11 +759,11 @@ static const struct samsung_mux_clock top_mux_clks[] = __initconst =3D { MUX(CLK_MOUT_CMU_DPU_ALT, "mout_cmu_dpu_alt", mout_cmu_dpu_alt_p, CLK_CON_MUX_MUX_CLKCMU_DPU_ALT, 0, 2), MUX(CLK_MOUT_CMU_DSP_BUS, "mout_cmu_dsp_bus", - mout_cmu_dsp_bus_p, CLK_CON_MUX_MUX_CLKCMU_DSP_BUS, 0, 2), + mout_cmu_dsp_bus_p, CLK_CON_MUX_MUX_CLKCMU_DSP_BUS, 0, 3), MUX(CLK_MOUT_CMU_G2D_G2D, "mout_cmu_g2d_g2d", mout_cmu_g2d_g2d_p, CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 2), MUX(CLK_MOUT_CMU_G2D_MSCL, "mout_cmu_g2d_mscl", - mout_cmu_g2d_mscl_p, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 1), + mout_cmu_g2d_mscl_p, CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 2), MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p, CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2), MUX(CLK_MOUT_CMU_HSI0_BUS, "mout_cmu_hsi0_bus", @@ -775,7 +775,7 @@ static const struct samsung_mux_clock top_mux_clks[] __= initconst =3D { 0, 2), MUX(CLK_MOUT_CMU_HSI0_USBDP_DEBUG, "mout_cmu_hsi0_usbdp_debug", mout_cmu_hsi0_usbdp_debug_p, - CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG, 0, 2), + CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDP_DEBUG, 0, 1), MUX(CLK_MOUT_CMU_HSI1_BUS, "mout_cmu_hsi1_bus", mout_cmu_hsi1_bus_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 3), MUX(CLK_MOUT_CMU_HSI1_MMC_CARD, "mout_cmu_hsi1_mmc_card", @@ -788,7 +788,7 @@ static const struct samsung_mux_clock top_mux_clks[] __= initconst =3D { 0, 2), MUX(CLK_MOUT_CMU_HSI1_UFS_EMBD, "mout_cmu_hsi1_ufs_embd", mout_cmu_hsi1_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_HSI1_UFS_EMBD, - 0, 1), + 0, 2), MUX(CLK_MOUT_CMU_HSI2_BUS, "mout_cmu_hsi2_bus", mout_cmu_hsi2_bus_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 1), MUX(CLK_MOUT_CMU_HSI2_PCIE, "mout_cmu_hsi2_pcie", @@ -862,7 +862,7 @@ static const struct samsung_div_clock top_div_clks[] __= initconst =3D { CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1), =20 DIV(CLK_DOUT_CMU_APM_BUS, "dout_cmu_apm_bus", "gout_cmu_apm_bus", - CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3), + CLK_CON_DIV_CLKCMU_APM_BUS, 0, 2), DIV(CLK_DOUT_CMU_AUD_CPU, "dout_cmu_aud_cpu", "gout_cmu_aud_cpu", CLK_CON_DIV_CLKCMU_AUD_CPU, 0, 3), DIV(CLK_DOUT_CMU_BUS0_BUS, "dout_cmu_bus0_bus", "gout_cmu_bus0_bus", @@ -887,9 +887,9 @@ static const struct samsung_div_clock top_div_clks[] __= initconst =3D { CLK_CON_DIV_CLKCMU_CMU_BOOST, 0, 2), DIV(CLK_DOUT_CMU_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus", CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), - DIV(CLK_DOUT_CMU_CPUCL0_DBG_BUS, "dout_cmu_cpucl0_debug", + DIV(CLK_DOUT_CMU_CPUCL0_DBG_BUS, "dout_cmu_cpucl0_dbg_bus", "gout_cmu_cpucl0_dbg_bus", CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS, - 0, 3), + 0, 4), DIV(CLK_DOUT_CMU_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch", "gout_cmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3), DIV(CLK_DOUT_CMU_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch", @@ -924,16 +924,11 @@ static const struct samsung_div_clock top_div_clks[] = __initconst =3D { CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 3), DIV(CLK_DOUT_CMU_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd", "gout_cmu_hsi0_usb31drd", CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 4), - DIV(CLK_DOUT_CMU_HSI0_USBDP_DEBUG, "dout_cmu_hsi0_usbdp_debug", - "gout_cmu_hsi0_usbdp_debug", CLK_CON_DIV_CLKCMU_HSI0_USBDP_DEBUG, - 0, 4), DIV(CLK_DOUT_CMU_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus", CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 3), DIV(CLK_DOUT_CMU_HSI1_MMC_CARD, "dout_cmu_hsi1_mmc_card", "gout_cmu_hsi1_mmc_card", CLK_CON_DIV_CLKCMU_HSI1_MMC_CARD, 0, 9), - DIV(CLK_DOUT_CMU_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie", - CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 7), DIV(CLK_DOUT_CMU_HSI1_UFS_CARD, "dout_cmu_hsi1_ufs_card", "gout_cmu_hsi1_ufs_card", CLK_CON_DIV_CLKCMU_HSI1_UFS_CARD, 0, 3), @@ -942,8 +937,6 @@ static const struct samsung_div_clock top_div_clks[] __= initconst =3D { 0, 3), DIV(CLK_DOUT_CMU_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus", CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4), - DIV(CLK_DOUT_CMU_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie", - CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 7), DIV(CLK_DOUT_CMU_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus", CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4), DIV(CLK_DOUT_CMU_ITP_BUS, "dout_cmu_itp_bus", "gout_cmu_itp_bus", @@ -979,8 +972,18 @@ static const struct samsung_div_clock top_div_clks[] _= _initconst =3D { CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4), DIV(CLK_DOUT_CMU_VRA_BUS, "dout_cmu_vra_bus", "gout_cmu_vra_bus", CLK_CON_DIV_CLKCMU_VRA_BUS, 0, 4), - DIV(CLK_DOUT_CMU_DPU, "dout_cmu_clkcmu_dpu", "gout_cmu_dpu", - CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 4), + DIV(CLK_DOUT_CMU_DPU, "dout_cmu_dpu", "gout_cmu_dpu", + CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 3), +}; + +static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initcon= st =3D { + FFACTOR(CLK_DOUT_CMU_HSI1_PCIE, "dout_cmu_hsi1_pcie", + "gout_cmu_hsi1_pcie", 1, 8, 0), + FFACTOR(CLK_DOUT_CMU_OTP, "dout_cmu_otp", "oscclk", 1, 8, 0), + FFACTOR(CLK_DOUT_CMU_HSI0_USBDP_DEBUG, "dout_cmu_hsi0_usbdp_debug", + "gout_cmu_hsi0_usbdp_debug", 1, 8, 0), + FFACTOR(CLK_DOUT_CMU_HSI2_PCIE, "dout_cmu_hsi2_pcie", + "gout_cmu_hsi2_pcie", 1, 8, 0), }; =20 static const struct samsung_gate_clock top_gate_clks[] __initconst =3D { @@ -1126,6 +1129,8 @@ static const struct samsung_cmu_info top_cmu_info __i= nitconst =3D { .nr_mux_clks =3D ARRAY_SIZE(top_mux_clks), .div_clks =3D top_div_clks, .nr_div_clks =3D ARRAY_SIZE(top_div_clks), + .fixed_factor_clks =3D cmu_top_ffactor, + .nr_fixed_factor_clks =3D ARRAY_SIZE(cmu_top_ffactor), .gate_clks =3D top_gate_clks, .nr_gate_clks =3D ARRAY_SIZE(top_gate_clks), .nr_clk_ids =3D CLKS_NR_TOP, --=20 2.50.1 From nobody Fri Oct 3 20:48:36 2025 Received: from mail-qv1-f53.google.com (mail-qv1-f53.google.com [209.85.219.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5DB30274B35; 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Sun, 24 Aug 2025 22:51:19 -0700 (PDT) Received: from [127.0.0.1] ([172.191.151.49]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70da72da3fdsm39639156d6.73.2025.08.24.22.51.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Aug 2025 22:51:18 -0700 (PDT) From: Denzeel Oliva Date: Mon, 25 Aug 2025 05:51:16 +0000 Subject: [PATCH v4 2/4] dt-bindings: clock: exynos990: Extend clocks IDs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-cmu-top-v4-2-71d783680529@gmail.com> References: <20250825-cmu-top-v4-0-71d783680529@gmail.com> In-Reply-To: <20250825-cmu-top-v4-0-71d783680529@gmail.com> To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Denzeel Oliva X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1756101076; l=810; i=wachiturroxd150@gmail.com; s=20250825; h=from:subject:message-id; bh=AFWxNCwJDRPuUp625KmPRnIz16SzHb+8zKtDFa4qFN0=; b=86l9x9jH4KH7N9/7czWjjlqusOscAoMLCTWzrM9rQcezqMzVH5dh6OLzn+x6z5pWd0ZqngQAY IGmd+ZOsuP3D/Qa0TERWIGlb7opv9J3RSwXziV3+Fb3b9h1QMgteBki X-Developer-Key: i=wachiturroxd150@gmail.com; a=ed25519; pk=qZrip2idhSTNQABELWG6WKCrg9xOKep//pV9JGKmW5k= Add missing clock definitions for DPU and CMUREF. Signed-off-by: Denzeel Oliva Acked-by: Rob Herring (Arm) --- include/dt-bindings/clock/samsung,exynos990.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/dt-bindings/clock/samsung,exynos990.h b/include/dt-bin= dings/clock/samsung,exynos990.h index 6b9df09d2..c5c79e078 100644 --- a/include/dt-bindings/clock/samsung,exynos990.h +++ b/include/dt-bindings/clock/samsung,exynos990.h @@ -208,6 +208,10 @@ #define CLK_GOUT_CMU_SSP_BUS 197 #define CLK_GOUT_CMU_TNR_BUS 198 #define CLK_GOUT_CMU_VRA_BUS 199 +#define CLK_MOUT_CMU_CMUREF 200 +#define CLK_MOUT_CMU_DPU_BUS 201 +#define CLK_MOUT_CMU_CLK_CMUREF 202 +#define CLK_DOUT_CMU_CLK_CMUREF 203 =20 /* CMU_HSI0 */ #define CLK_MOUT_HSI0_BUS_USER 1 --=20 2.50.1 From nobody Fri Oct 3 20:48:36 2025 Received: from mail-qv1-f52.google.com (mail-qv1-f52.google.com [209.85.219.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57CBC27CB04; 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Sun, 24 Aug 2025 22:51:19 -0700 (PDT) Received: from [127.0.0.1] ([172.191.151.49]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70da72da3fdsm39639156d6.73.2025.08.24.22.51.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Aug 2025 22:51:19 -0700 (PDT) From: Denzeel Oliva Date: Mon, 25 Aug 2025 05:51:17 +0000 Subject: [PATCH v4 3/4] clk: samsung: exynos990: update CLK_NR_TOP for new IDs clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-cmu-top-v4-3-71d783680529@gmail.com> References: <20250825-cmu-top-v4-0-71d783680529@gmail.com> In-Reply-To: <20250825-cmu-top-v4-0-71d783680529@gmail.com> To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Denzeel Oliva X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1756101076; l=799; i=wachiturroxd150@gmail.com; s=20250825; h=from:subject:message-id; bh=KshG0umwTRkOxCv1V2lWLWj7+xMZ/xwWZ8K/klaG7Hc=; b=sHj7Cnj2MhG7M0vHjH1Q6Ak9rHV+FWEzfch2nuIl9sDn5a02RL15KFfLARo+Ym+YKHQog7IzG WK7oRg+7rhQDMY3lrhIfJrZRlQupSke11v0Pv4aVbFtoVtcLWijn/Ic X-Developer-Key: i=wachiturroxd150@gmail.com; a=ed25519; pk=qZrip2idhSTNQABELWG6WKCrg9xOKep//pV9JGKmW5k= The new clock IDs have been added and put last, it is necessary to change. Signed-off-by: Denzeel Oliva --- drivers/clk/samsung/clk-exynos990.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-= exynos990.c index 105ba0363..9fcdad7cc 100644 --- a/drivers/clk/samsung/clk-exynos990.c +++ b/drivers/clk/samsung/clk-exynos990.c @@ -17,7 +17,7 @@ #include "clk-pll.h" =20 /* NOTE: Must be equal to the last clock ID increased by one */ -#define CLKS_NR_TOP (CLK_GOUT_CMU_VRA_BUS + 1) +#define CLKS_NR_TOP (CLK_DOUT_CMU_CLK_CMUREF + 1) #define CLKS_NR_HSI0 (CLK_GOUT_HSI0_XIU_D_HSI0_ACLK + 1) #define CLKS_NR_PERIS (CLK_GOUT_PERIS_OTP_CON_TOP_OSCCLK + 1) =20 --=20 2.50.1 From nobody Fri Oct 3 20:48:36 2025 Received: from mail-qv1-f50.google.com (mail-qv1-f50.google.com [209.85.219.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 307A527BF95; Mon, 25 Aug 2025 05:51:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Sun, 24 Aug 2025 22:51:20 -0700 (PDT) Received: from [127.0.0.1] ([172.191.151.49]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-70da72da3fdsm39639156d6.73.2025.08.24.22.51.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Aug 2025 22:51:20 -0700 (PDT) From: Denzeel Oliva Date: Mon, 25 Aug 2025 05:51:18 +0000 Subject: [PATCH v4 4/4] clk: samsung: exynos990: Fix PLL mux regs, add DPU/CMUREF Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-cmu-top-v4-4-71d783680529@gmail.com> References: <20250825-cmu-top-v4-0-71d783680529@gmail.com> In-Reply-To: <20250825-cmu-top-v4-0-71d783680529@gmail.com> To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Denzeel Oliva X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1756101076; l=10122; i=wachiturroxd150@gmail.com; s=20250825; h=from:subject:message-id; bh=Y0ZxxBRl7hBkknwka1s15x2LVpNvmBcxzcvftKRpm/g=; b=liCYjLIFmRRNjhwysuxkUrfhv7gc8+SYJvbDaFtvIffmfcMtJpj0+W+4PxprTsM5hgB+6wcTX lVutLYLS/LnBzlvICefssfgepEpNYljd+bmQryRaqOnO6CaXIsz4HfD X-Developer-Key: i=wachiturroxd150@gmail.com; a=ed25519; pk=qZrip2idhSTNQABELWG6WKCrg9xOKep//pV9JGKmW5k= Switch PLL muxes to PLL_CON0 to correct parent selection and clock rates. Add DPU_BUS and CMUREF mux/div and their register hooks and parents. Signed-off-by: Denzeel Oliva --- drivers/clk/samsung/clk-exynos990.c | 97 ++++++++++++++++++++++++---------= ---- 1 file changed, 63 insertions(+), 34 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-= exynos990.c index 9fcdad7cc..d1135708c 100644 --- a/drivers/clk/samsung/clk-exynos990.c +++ b/drivers/clk/samsung/clk-exynos990.c @@ -45,6 +45,7 @@ #define PLL_CON3_PLL_SHARED3 0x024c #define PLL_CON0_PLL_SHARED4 0x0280 #define PLL_CON3_PLL_SHARED4 0x028c +#define CLK_CON_MUX_CLKCMU_DPU_BUS 0x1000 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1004 #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x1008 #define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x100c @@ -103,6 +104,8 @@ #define CLK_CON_MUX_MUX_CLKCMU_SSP_BUS 0x10e0 #define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10e4 #define CLK_CON_MUX_MUX_CLKCMU_VRA_BUS 0x10e8 +#define CLK_CON_MUX_MUX_CLK_CMU_CMUREF 0x10f0 +#define CLK_CON_MUX_MUX_CMU_CMUREF 0x10f4 #define CLK_CON_DIV_CLKCMU_APM_BUS 0x1800 #define CLK_CON_DIV_CLKCMU_AUD_CPU 0x1804 #define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1808 @@ -162,6 +165,7 @@ #define CLK_CON_DIV_CLKCMU_VRA_BUS 0x18e0 #define CLK_CON_DIV_DIV_CLKCMU_DPU 0x18e8 #define CLK_CON_DIV_DIV_CLKCMU_DPU_ALT 0x18ec +#define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18f0 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x18f4 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18f8 #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x18fc @@ -239,13 +243,21 @@ static const unsigned long top_clk_regs[] __initconst= =3D { PLL_LOCKTIME_PLL_SHARED2, PLL_LOCKTIME_PLL_SHARED3, PLL_LOCKTIME_PLL_SHARED4, + PLL_CON0_PLL_G3D, PLL_CON3_PLL_G3D, + PLL_CON0_PLL_MMC, PLL_CON3_PLL_MMC, + PLL_CON0_PLL_SHARED0, PLL_CON3_PLL_SHARED0, + PLL_CON0_PLL_SHARED1, PLL_CON3_PLL_SHARED1, + PLL_CON0_PLL_SHARED2, PLL_CON3_PLL_SHARED2, + PLL_CON0_PLL_SHARED3, PLL_CON3_PLL_SHARED3, + PLL_CON0_PLL_SHARED4, PLL_CON3_PLL_SHARED4, + CLK_CON_MUX_CLKCMU_DPU_BUS, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, @@ -304,6 +316,8 @@ static const unsigned long top_clk_regs[] __initconst = =3D { CLK_CON_MUX_MUX_CLKCMU_SSP_BUS, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, CLK_CON_MUX_MUX_CLKCMU_VRA_BUS, + CLK_CON_MUX_MUX_CLK_CMU_CMUREF, + CLK_CON_MUX_MUX_CMU_CMUREF, CLK_CON_DIV_CLKCMU_APM_BUS, CLK_CON_DIV_CLKCMU_AUD_CPU, CLK_CON_DIV_CLKCMU_BUS0_BUS, @@ -363,6 +377,7 @@ static const unsigned long top_clk_regs[] __initconst = =3D { CLK_CON_DIV_CLKCMU_VRA_BUS, CLK_CON_DIV_DIV_CLKCMU_DPU, CLK_CON_DIV_DIV_CLKCMU_DPU_ALT, + CLK_CON_DIV_DIV_CLK_CMU_CMUREF, CLK_CON_DIV_PLL_SHARED0_DIV2, CLK_CON_DIV_PLL_SHARED0_DIV3, CLK_CON_DIV_PLL_SHARED0_DIV4, @@ -458,6 +473,8 @@ PNAME(mout_pll_shared3_p) =3D { "oscclk", "fout_shared= 3_pll" }; PNAME(mout_pll_shared4_p) =3D { "oscclk", "fout_shared4_pll" }; PNAME(mout_pll_mmc_p) =3D { "oscclk", "fout_mmc_pll" }; PNAME(mout_pll_g3d_p) =3D { "oscclk", "fout_g3d_pll" }; +PNAME(mout_cmu_dpu_bus_p) =3D { "dout_cmu_dpu", + "dout_cmu_dpu_alt" }; PNAME(mout_cmu_apm_bus_p) =3D { "dout_cmu_shared0_div2", "dout_cmu_shared2_div2" }; PNAME(mout_cmu_aud_cpu_p) =3D { "dout_cmu_shared0_div2", @@ -507,7 +524,7 @@ PNAME(mout_cmu_cpucl0_switch_p) =3D { "fout_shared4_pl= l", "dout_cmu_shared0_div2", "fout_shared2_pll", "dout_cmu_shared0_div4" }; -PNAME(mout_cmu_cpucl1_switch_p) =3D { "fout_shared4_pll", +PNAME(mout_cmu_cpucl1_switch_p) =3D { "fout_shared4_pll", "dout_cmu_shared0_div2", "fout_shared2_pll", "dout_cmu_shared0_div4" }; @@ -577,7 +594,7 @@ PNAME(mout_cmu_hsi1_bus_p) =3D { "dout_cmu_shared0_div= 3", "dout_cmu_shared4_div3", "dout_cmu_shared2_div2", "fout_mmc_pll", "oscclk", "oscclk" }; -PNAME(mout_cmu_hsi1_mmc_card_p) =3D { "oscclk", "fout_shared2_pll", +PNAME(mout_cmu_hsi1_mmc_card_p) =3D { "oscclk", "fout_shared2_pll", "fout_mmc_pll", "dout_cmu_shared0_div4" }; PNAME(mout_cmu_hsi1_pcie_p) =3D { "oscclk", "fout_shared2_pll" }; @@ -672,6 +689,12 @@ PNAME(mout_cmu_vra_bus_p) =3D { "dout_cmu_shared0_div= 3", "dout_cmu_shared4_div2", "dout_cmu_shared0_div4", "dout_cmu_shared4_div3" }; +PNAME(mout_cmu_cmuref_p) =3D { "oscclk", + "dout_cmu_clk_cmuref" }; +PNAME(mout_cmu_clk_cmuref_p) =3D { "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", + "oscclk" }; =20 /* * Register name to clock name mangling strategy used in this file @@ -689,19 +712,21 @@ PNAME(mout_cmu_vra_bus_p) =3D { "dout_cmu_shared0_di= v3", =20 static const struct samsung_mux_clock top_mux_clks[] __initconst =3D { MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p, - PLL_CON3_PLL_SHARED0, 4, 1), + PLL_CON0_PLL_SHARED0, 4, 1), MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p, - PLL_CON3_PLL_SHARED1, 4, 1), + PLL_CON0_PLL_SHARED1, 4, 1), MUX(CLK_MOUT_PLL_SHARED2, "mout_pll_shared2", mout_pll_shared2_p, - PLL_CON3_PLL_SHARED2, 4, 1), + PLL_CON0_PLL_SHARED2, 4, 1), MUX(CLK_MOUT_PLL_SHARED3, "mout_pll_shared3", mout_pll_shared3_p, - PLL_CON3_PLL_SHARED3, 4, 1), + PLL_CON0_PLL_SHARED3, 4, 1), MUX(CLK_MOUT_PLL_SHARED4, "mout_pll_shared4", mout_pll_shared4_p, PLL_CON0_PLL_SHARED4, 4, 1), MUX(CLK_MOUT_PLL_MMC, "mout_pll_mmc", mout_pll_mmc_p, PLL_CON0_PLL_MMC, 4, 1), MUX(CLK_MOUT_PLL_G3D, "mout_pll_g3d", mout_pll_g3d_p, PLL_CON0_PLL_G3D, 4, 1), + MUX(CLK_MOUT_CMU_DPU_BUS, "mout_cmu_dpu_bus", + mout_cmu_dpu_bus_p, CLK_CON_MUX_CLKCMU_DPU_BUS, 0, 1), MUX(CLK_MOUT_CMU_APM_BUS, "mout_cmu_apm_bus", mout_cmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1), MUX(CLK_MOUT_CMU_AUD_CPU, "mout_cmu_aud_cpu", @@ -830,37 +855,13 @@ static const struct samsung_mux_clock top_mux_clks[] = __initconst =3D { mout_cmu_tnr_bus_p, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3), MUX(CLK_MOUT_CMU_VRA_BUS, "mout_cmu_vra_bus", mout_cmu_vra_bus_p, CLK_CON_MUX_MUX_CLKCMU_VRA_BUS, 0, 2), + MUX(CLK_MOUT_CMU_CMUREF, "mout_cmu_cmuref", + mout_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1), + MUX(CLK_MOUT_CMU_CLK_CMUREF, "mout_cmu_clk_cmuref", + mout_cmu_clk_cmuref_p, CLK_CON_MUX_MUX_CLK_CMU_CMUREF, 0, 2), }; =20 static const struct samsung_div_clock top_div_clks[] __initconst =3D { - /* SHARED0 region*/ - DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2", "mout_pll_shared0= ", - CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), - DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3", "mout_pll_shared0= ", - CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), - DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4", "dout_cmu_shared0= _div2", - CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), - - /* SHARED1 region*/ - DIV(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2", "mout_pll_shared1= ", - CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), - DIV(CLK_DOUT_CMU_SHARED1_DIV3, "dout_cmu_shared1_div3", "mout_pll_shared1= ", - CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), - DIV(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4", "dout_cmu_shared1= _div2", - CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), - - /* SHARED2 region */ - DIV(CLK_DOUT_CMU_SHARED2_DIV2, "dout_cmu_shared2_div2", "mout_pll_shared2= ", - CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1), - - /* SHARED4 region*/ - DIV(CLK_DOUT_CMU_SHARED4_DIV2, "dout_cmu_shared4_div2", "mout_pll_shared4= ", - CLK_CON_DIV_PLL_SHARED4_DIV2, 0, 1), - DIV(CLK_DOUT_CMU_SHARED4_DIV3, "dout_cmu_shared4_div3", "mout_pll_shared4= ", - CLK_CON_DIV_PLL_SHARED4_DIV3, 0, 2), - DIV(CLK_DOUT_CMU_SHARED4_DIV4, "dout_cmu_shared4_div4", "mout_pll_shared4= ", - CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1), - DIV(CLK_DOUT_CMU_APM_BUS, "dout_cmu_apm_bus", "gout_cmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 2), DIV(CLK_DOUT_CMU_AUD_CPU, "dout_cmu_aud_cpu", "gout_cmu_aud_cpu", @@ -974,6 +975,34 @@ static const struct samsung_div_clock top_div_clks[] _= _initconst =3D { CLK_CON_DIV_CLKCMU_VRA_BUS, 0, 4), DIV(CLK_DOUT_CMU_DPU, "dout_cmu_dpu", "gout_cmu_dpu", CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 3), + DIV(CLK_DOUT_CMU_DPU_ALT, "dout_cmu_dpu_alt", "gout_cmu_dpu_bus", + CLK_CON_DIV_DIV_CLKCMU_DPU_ALT, 0, 4), + DIV(CLK_DOUT_CMU_CLK_CMUREF, "dout_cmu_clk_cmuref", "mout_cmu_clk_cmuref", + CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0, 2), + /* SHARED0 region*/ + DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2", "mout_pll_shared0= ", + CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), + DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3", "mout_pll_shared0= ", + CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), + DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4", "dout_cmu_shared0= _div2", + CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), + /* SHARED1 region*/ + DIV(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2", "mout_pll_shared1= ", + CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), + DIV(CLK_DOUT_CMU_SHARED1_DIV3, "dout_cmu_shared1_div3", "mout_pll_shared1= ", + CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), + DIV(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4", "dout_cmu_shared1= _div2", + CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), + /* SHARED2 region */ + DIV(CLK_DOUT_CMU_SHARED2_DIV2, "dout_cmu_shared2_div2", "mout_pll_shared2= ", + CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1), + /* SHARED4 region*/ + DIV(CLK_DOUT_CMU_SHARED4_DIV2, "dout_cmu_shared4_div2", "mout_pll_shared4= ", + CLK_CON_DIV_PLL_SHARED4_DIV2, 0, 1), + DIV(CLK_DOUT_CMU_SHARED4_DIV3, "dout_cmu_shared4_div3", "mout_pll_shared4= ", + CLK_CON_DIV_PLL_SHARED4_DIV3, 0, 2), + DIV(CLK_DOUT_CMU_SHARED4_DIV4, "dout_cmu_shared4_div4", "dout_cmu_shared4= _div2", + CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1), }; =20 static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initcon= st =3D { --=20 2.50.1