From nobody Fri Oct 3 21:38:03 2025 Received: from sender4-op-o12.zoho.com (sender4-op-o12.zoho.com [136.143.188.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 11EFC29E11B; Mon, 25 Aug 2025 08:30:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.12 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756110626; cv=pass; b=WMRauBe1qRef8O8vqFKfwtMvjfw3Ieme/uZa6qkfrSumiUtQ3KE5MZvq+cTZv0TC9LCRaG3gXQ154SA9zNE+Jj4FvR4cRZe9FpRiwkp4EbNKDl6bXy55B2ARu2VCJ+vMtsGaz+tKwNSDTC7O6kEtt81I9TK3S7HBiI4NhZQPFrc= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756110626; c=relaxed/simple; bh=AxjCXjo5OFr0eh39M/fGPJILA4LiUvPk7/eG0ZPWUTQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=hU4s2Rcq8R4PlTPwT2S11rakKLqCYxP/j3YtfwyHH5jlvWqvl9y+iwvf8ZTj9Aa01hUL9pbfnvTO7XtDv3z162f+GXH5V1ulXP8LiOBBqRTBgH5Ab5aulLfOGqg5uOuPkk9kxCKMWmH1UUdwxL/pPTqyeK+U9lSEzUht91cpT6c= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b=cPLPo+ug; arc=pass smtp.client-ip=136.143.188.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=nicolas.frattaroli@collabora.com header.b="cPLPo+ug" ARC-Seal: i=1; a=rsa-sha256; t=1756110548; cv=none; d=zohomail.com; s=zohoarc; b=fcoF6iTWhunYRzmFhgB2V3l5FZ9P/Bv+oOvF+IuclMEqjuYKNO3vJ/sLEWEvCGVAAnsfbR4tGjIqBruztA25yFUmJDCcSab4zBGNsB0Sl+mb1GMnjFFQPkIYI4ekgXtLI4bhQffnlBV6S34KGJLeZ2TT57Xr6Dexx3M0N3SGUxE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756110548; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=+ds7UJ/GcM+1QFx5GWEDvr7qiCy8pTo68rCv3gqg+cA=; b=jcVgmokYWSc3/2pFP2AN4L5NRtJj546MoILinFFpiugnyVfJ0uvPNHkFMi3gtM4KRVbDCjEfL+CZz83bciBuK0ik7VjyTjWoh5vtsRX0f3NYVHspwiMLAAO4Q5N/gglpU/SPDX1nnO+5iC8bxmZz2KuwVRAMr2tPsYxe14QvEpw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=nicolas.frattaroli@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1756110548; s=zohomail; d=collabora.com; i=nicolas.frattaroli@collabora.com; h=From:From:Date:Date:Subject:Subject:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-Id:Message-Id:References:In-Reply-To:To:To:Cc:Cc:Reply-To; bh=+ds7UJ/GcM+1QFx5GWEDvr7qiCy8pTo68rCv3gqg+cA=; b=cPLPo+ugJ9OTuZR0YLUSsUMHTndMsIh1nn7r0cp8U3GoZh17B+lYsHNmg1lfhLoV i6RUuPyzRMf8lSBk0TUkt8NGh7loOLdjy4D6F+hmqC4knvMQhv6QyJIPnLNoT4qka/0 /pzdWdzF4llaxjRtAiqg0a2zRs/NiFpg3Ai9dZ8k= Received: by mx.zohomail.com with SMTPS id 1756110545721254.6775577730043; Mon, 25 Aug 2025 01:29:05 -0700 (PDT) From: Nicolas Frattaroli Date: Mon, 25 Aug 2025 10:28:21 +0200 Subject: [PATCH v3 01/20] bitmap: introduce hardware-specific bitfield operations Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250825-byeword-update-v3-1-947b841cdb29@collabora.com> References: <20250825-byeword-update-v3-0-947b841cdb29@collabora.com> In-Reply-To: <20250825-byeword-update-v3-0-947b841cdb29@collabora.com> To: Yury Norov , Rasmus Villemoes , Jaehoon Chung , Ulf Hansson , Heiko Stuebner , Shreeya Patel , Mauro Carvalho Chehab , Sandy Huang , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Vinod Koul , Kishon Vijay Abraham I , Nicolas Frattaroli , Liam Girdwood , Mark Brown , Jaroslav Kysela , Takashi Iwai , Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Shawn Lin , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Chanwoo Choi , MyungJoo Ham , Kyungmin Park , Qin Jian , Michael Turquette , Stephen Boyd , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt Cc: kernel@collabora.com, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-media@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-phy@lists.infradead.org, linux-sound@vger.kernel.org, netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-pci@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, llvm@lists.linux.dev, Nicolas Frattaroli X-Mailer: b4 0.14.2 Hardware of various vendors, but very notably Rockchip, often uses 32-bit registers where the upper 16-bit half of the register is a write-enable mask for the lower half. This type of hardware setup allows for more granular concurrent register write access. Over the years, many drivers have hand-rolled their own version of this macro, usually without any checks, often called something like HIWORD_UPDATE or FIELD_PREP_HIWORD, commonly with slightly different semantics between them. Clearly there is a demand for such a macro, and thus the demand should be satisfied in a common header file. As this is a convention that spans across multiple vendors, and similar conventions may also have cross-vendor adoption, it's best if it lives in a vendor-agnostic header file that can be expanded over time. Add hw_bitfield.h with two macros: FIELD_PREP_WM16, and FIELD_PREP_WM16_CONST. The latter is a version that can be used in initializers, like FIELD_PREP_CONST. Suggested-by: Yury Norov [NVIDIA] Signed-off-by: Nicolas Frattaroli Acked-by: Heiko Stuebner Acked-by: Jakub Kicinski --- MAINTAINERS | 1 + include/linux/hw_bitfield.h | 62 +++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 63 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index d4bddc462c079f85ee35e685527c93dd1620f890..75a266a78a13721372a92b9ae45= b9ae56e301347 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -4281,6 +4281,7 @@ F: include/linux/bits.h F: include/linux/cpumask.h F: include/linux/cpumask_types.h F: include/linux/find.h +F: include/linux/hw_bitfield.h F: include/linux/nodemask.h F: include/linux/nodemask_types.h F: include/uapi/linux/bits.h diff --git a/include/linux/hw_bitfield.h b/include/linux/hw_bitfield.h new file mode 100644 index 0000000000000000000000000000000000000000..df202e167ce487122e4440962ea= cb2e44817ad9f --- /dev/null +++ b/include/linux/hw_bitfield.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2025, Collabora Ltd. + */ + +#ifndef _LINUX_HW_BITFIELD_H +#define _LINUX_HW_BITFIELD_H + +#include +#include +#include + +/** + * FIELD_PREP_WM16() - prepare a bitfield element with a mask in the upper= half + * @_mask: shifted mask defining the field's length and position + * @_val: value to put in the field + * + * FIELD_PREP_WM16() masks and shifts up the value, as well as bitwise ORs= the + * result with the mask shifted up by 16. + * + * This is useful for a common design of hardware registers where the upper + * 16-bit half of a 32-bit register is used as a write-enable mask. In suc= h a + * register, a bit in the lower half is only updated if the corresponding = bit + * in the upper half is high. + */ +#define FIELD_PREP_WM16(_mask, _val) \ + ({ \ + typeof(_val) __val =3D _val; \ + typeof(_mask) __mask =3D _mask; \ + __BF_FIELD_CHECK(__mask, ((u16)0U), __val, \ + "HWORD_UPDATE: "); \ + (((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) | \ + ((__mask) << 16); \ + }) + +/** + * FIELD_PREP_WM16_CONST() - prepare a constant bitfield element with a ma= sk in + * the upper half + * @_mask: shifted mask defining the field's length and position + * @_val: value to put in the field + * + * FIELD_PREP_WM16_CONST() masks and shifts up the value, as well as bitwi= se ORs + * the result with the mask shifted up by 16. + * + * This is useful for a common design of hardware registers where the upper + * 16-bit half of a 32-bit register is used as a write-enable mask. In suc= h a + * register, a bit in the lower half is only updated if the corresponding = bit + * in the upper half is high. + * + * Unlike FIELD_PREP_WM16(), this is a constant expression and can therefo= re + * be used in initializers. Error checking is less comfortable for this + * version. + */ +#define FIELD_PREP_WM16_CONST(_mask, _val) \ + ( \ + FIELD_PREP_CONST(_mask, _val) | \ + (BUILD_BUG_ON_ZERO(const_true((u64)(_mask) > U16_MAX)) + \ + ((_mask) << 16)) \ + ) + + +#endif /* _LINUX_HW_BITFIELD_H */ --=20 2.51.0