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Signed-off-by: Chelsy Ratnawat --- drivers/accel/habanalabs/common/firmware_if.c | 14 +++++++------- drivers/accel/habanalabs/gaudi/gaudi_coresight.c | 9 +++++---- drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c | 9 +++++---- drivers/accel/habanalabs/goya/goya.c | 3 ++- drivers/accel/habanalabs/goya/goya_coresight.c | 9 +++++---- 5 files changed, 24 insertions(+), 20 deletions(-) diff --git a/drivers/accel/habanalabs/common/firmware_if.c b/drivers/accel/= habanalabs/common/firmware_if.c index eeb6b2a80fc7..cef53a3fd839 100644 --- a/drivers/accel/habanalabs/common/firmware_if.c +++ b/drivers/accel/habanalabs/common/firmware_if.c @@ -14,6 +14,7 @@ #include #include #include +#include =20 #include =20 @@ -1705,13 +1706,13 @@ static void hl_fw_preboot_update_state(struct hl_de= vice *hdev) cpu_boot_dev_sts1); =20 dev_dbg(hdev->dev, "Firmware preboot hard-reset is %s\n", - prop->hard_reset_done_by_fw ? "enabled" : "disabled"); + str_enabled_disabled(prop->hard_reset_done_by_fw)); =20 dev_dbg(hdev->dev, "firmware-level security is %s\n", - prop->fw_security_enabled ? "enabled" : "disabled"); + str_enabled_disabled(prop->fw_security_enabled)); =20 dev_dbg(hdev->dev, "GIC controller is %s\n", - prop->gic_interrupts_enable ? "enabled" : "disabled"); + str_enabled_disabled(prop->gic_interrupts_enable)); } =20 static int hl_fw_static_read_preboot_status(struct hl_device *hdev) @@ -2455,7 +2456,7 @@ static void hl_fw_boot_fit_update_state(struct hl_dev= ice *hdev, } =20 dev_dbg(hdev->dev, "Firmware boot CPU hard-reset is %s\n", - prop->hard_reset_done_by_fw ? "enabled" : "disabled"); + str_enabled_disabled(prop->hard_reset_done_by_fw)); } =20 static void hl_fw_dynamic_update_linux_interrupt_if(struct hl_device *hdev) @@ -2647,8 +2648,7 @@ static void hl_fw_linux_update_state(struct hl_device= *hdev, prop->fw_app_cpu_boot_dev_sts0); =20 dev_dbg(hdev->dev, "GIC controller is %s\n", - prop->gic_interrupts_enable ? - "enabled" : "disabled"); + str_enabled_disabled(prop->gic_interrupts_enable)); } =20 if (prop->fw_cpu_boot_dev_sts1_valid) { @@ -2660,7 +2660,7 @@ static void hl_fw_linux_update_state(struct hl_device= *hdev, } =20 dev_dbg(hdev->dev, "Firmware application CPU hard-reset is %s\n", - prop->hard_reset_done_by_fw ? "enabled" : "disabled"); + str_enabled_disabled(prop->hard_reset_done_by_fw)); =20 dev_info(hdev->dev, "Successfully loaded firmware to device\n"); } diff --git a/drivers/accel/habanalabs/gaudi/gaudi_coresight.c b/drivers/acc= el/habanalabs/gaudi/gaudi_coresight.c index 1168fefa33f4..3900a7727f4c 100644 --- a/drivers/accel/habanalabs/gaudi/gaudi_coresight.c +++ b/drivers/accel/habanalabs/gaudi/gaudi_coresight.c @@ -12,6 +12,7 @@ #include "../include/gaudi/gaudi_reg_map.h" =20 #include +#include =20 #define SPMU_SECTION_SIZE MME0_ACC_SPMU_MAX_OFFSET #define SPMU_EVENT_TYPES_OFFSET 0x400 @@ -497,7 +498,7 @@ static int gaudi_config_etf(struct hl_device *hdev, if (rc) { dev_err(hdev->dev, "Failed to %s ETF on timeout, error %d\n", - params->enable ? "enable" : "disable", rc); + str_enable_disable(params->enable), rc); return rc; } =20 @@ -505,7 +506,7 @@ static int gaudi_config_etf(struct hl_device *hdev, if (rc) { dev_err(hdev->dev, "Failed to %s ETF on timeout, error %d\n", - params->enable ? "enable" : "disable", rc); + str_enable_disable(params->enable), rc); return rc; } =20 @@ -601,14 +602,14 @@ static int gaudi_config_etr(struct hl_device *hdev, rc =3D gaudi_coresight_timeout(hdev, mmPSOC_ETR_FFCR, 6, false); if (rc) { dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", - params->enable ? "enable" : "disable", rc); + str_enable_disable(params->enable), rc); return rc; } =20 rc =3D gaudi_coresight_timeout(hdev, mmPSOC_ETR_STS, 2, true); if (rc) { dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", - params->enable ? "enable" : "disable", rc); + str_enable_disable(params->enable), rc); return rc; } =20 diff --git a/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c b/drivers/a= ccel/habanalabs/gaudi2/gaudi2_coresight.c index 2423620ff358..f35a024ad532 100644 --- a/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c +++ b/drivers/accel/habanalabs/gaudi2/gaudi2_coresight.c @@ -6,6 +6,7 @@ */ #include "gaudi2_coresight_regs.h" #include +#include =20 #define GAUDI2_PLDM_CORESIGHT_TIMEOUT_USEC (CORESIGHT_TIMEOUT_USEC * 2000) #define SPMU_MAX_COUNTERS 6 @@ -2106,14 +2107,14 @@ static int gaudi2_config_etf(struct hl_device *hdev= , struct hl_debug_params *par rc =3D gaudi2_coresight_timeout(hdev, base_reg + mmETF_FFCR_OFFSET, 6, fa= lse); if (rc) { dev_err(hdev->dev, "Failed to %s ETF on timeout, error %d\n", - params->enable ? "enable" : "disable", rc); + str_enable_disable(params->enable), rc); return rc; } =20 rc =3D gaudi2_coresight_timeout(hdev, base_reg + mmETF_STS_OFFSET, 2, tru= e); if (rc) { dev_err(hdev->dev, "Failed to %s ETF on timeout, error %d\n", - params->enable ? "enable" : "disable", rc); + str_enable_disable(params->enable), rc); return rc; } =20 @@ -2215,14 +2216,14 @@ static int gaudi2_config_etr(struct hl_device *hdev= , struct hl_ctx *ctx, rc =3D gaudi2_coresight_timeout(hdev, mmPSOC_ETR_FFCR, 6, false); if (rc) { dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", - params->enable ? "enable" : "disable", rc); + str_enable_disable(params->enable), rc); return rc; } =20 rc =3D gaudi2_coresight_timeout(hdev, mmPSOC_ETR_STS, 2, true); if (rc) { dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", - params->enable ? "enable" : "disable", rc); + str_enable_disable(params->enable), rc); return rc; } =20 diff --git a/drivers/accel/habanalabs/goya/goya.c b/drivers/accel/habanalab= s/goya/goya.c index 84768e306269..cca904a21392 100644 --- a/drivers/accel/habanalabs/goya/goya.c +++ b/drivers/accel/habanalabs/goya/goya.c @@ -15,6 +15,7 @@ #include #include #include +#include =20 /* * GOYA security scheme: @@ -820,7 +821,7 @@ int goya_set_frequency(struct hl_device *hdev, enum hl_= pll_frequency freq) return 0; =20 dev_dbg(hdev->dev, "Changing device frequency to %s\n", - freq =3D=3D PLL_HIGH ? "high" : "low"); + str_high_low(freq =3D=3D PLL_HIGH)); =20 goya_set_pll_profile(hdev, freq); =20 diff --git a/drivers/accel/habanalabs/goya/goya_coresight.c b/drivers/accel= /habanalabs/goya/goya_coresight.c index 3827ea4c02f7..f65c9a802444 100644 --- a/drivers/accel/habanalabs/goya/goya_coresight.c +++ b/drivers/accel/habanalabs/goya/goya_coresight.c @@ -11,6 +11,7 @@ #include "../include/goya/asic_reg/goya_masks.h" =20 #include +#include =20 #define GOYA_PLDM_CORESIGHT_TIMEOUT_USEC (CORESIGHT_TIMEOUT_USEC * 100) =20 @@ -330,7 +331,7 @@ static int goya_config_etf(struct hl_device *hdev, if (rc) { dev_err(hdev->dev, "Failed to %s ETF on timeout, error %d\n", - params->enable ? "enable" : "disable", rc); + str_enable_disable(params->enable), rc); return rc; } =20 @@ -338,7 +339,7 @@ static int goya_config_etf(struct hl_device *hdev, if (rc) { dev_err(hdev->dev, "Failed to %s ETF on timeout, error %d\n", - params->enable ? "enable" : "disable", rc); + str_enable_disable(params->enable), rc); return rc; } =20 @@ -405,14 +406,14 @@ static int goya_config_etr(struct hl_device *hdev, rc =3D goya_coresight_timeout(hdev, mmPSOC_ETR_FFCR, 6, false); if (rc) { dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", - params->enable ? "enable" : "disable", rc); + str_enable_disable(params->enable), rc); return rc; } =20 rc =3D goya_coresight_timeout(hdev, mmPSOC_ETR_STS, 2, true); if (rc) { dev_err(hdev->dev, "Failed to %s ETR on timeout, error %d\n", - params->enable ? "enable" : "disable", rc); + str_enable_disable(params->enable), rc); return rc; } =20 --=20 2.47.3