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[46.142.10.197]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45b5757453fsm66470895e9.14.2025.08.24.04.34.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 24 Aug 2025 04:34:38 -0700 (PDT) From: Jonas Jelonek To: Chris Packham , Andi Shyti , Rob Herring , Krzysztof Kozlowski Cc: linux-i2c@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Markus Stockhausen , Sven Eckelmann , Harshal Gohel , Wolfram Sang , Jonas Jelonek Subject: [PATCH v6 12/12] i2c: rtl9300: add support for RTL9310 I2C controller Date: Sun, 24 Aug 2025 11:33:48 +0000 Message-ID: <20250824113348.263475-13-jelonek.jonas@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250824113348.263475-1-jelonek.jonas@gmail.com> References: <20250824113348.263475-1-jelonek.jonas@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the internal I2C controllers of RTL9310 series based SoCs to the driver for RTL9300. Add register definitions, chip-specific functions and compatible strings for known RTL9310-based SoCs RTL9311, RTL9312 and RTL9313. Make use of a new device tree property 'realtek,scl' which needs to be specified in case both or only the second master is used. This is required due how the register layout changed in contrast to RTL9300, which has SCL selection in a global register instead of a master-specific one. Signed-off-by: Jonas Jelonek Tested-by: Sven Eckelmann --- drivers/i2c/busses/i2c-rtl9300.c | 44 ++++++++++++++++++++++++++++++-- 1 file changed, 42 insertions(+), 2 deletions(-) diff --git a/drivers/i2c/busses/i2c-rtl9300.c b/drivers/i2c/busses/i2c-rtl9= 300.c index c67463228604..bfceca24ad7d 100644 --- a/drivers/i2c/busses/i2c-rtl9300.c +++ b/drivers/i2c/busses/i2c-rtl9300.c @@ -60,14 +60,16 @@ struct rtl9300_i2c_drv_data { }; =20 #define RTL9300_I2C_MUX_NCHAN 8 +#define RTL9310_I2C_MUX_NCHAN 12 =20 struct rtl9300_i2c { struct regmap *regmap; struct device *dev; - struct rtl9300_i2c_chan chans[RTL9300_I2C_MUX_NCHAN]; + struct rtl9300_i2c_chan chans[RTL9310_I2C_MUX_NCHAN]; struct regmap_field *fields[F_NUM_FIELDS]; u32 reg_base; u32 data_reg; + u8 scl_num; u8 sda_num; struct mutex lock; }; @@ -98,6 +100,12 @@ struct rtl9300_i2c_xfer { #define RTL9300_I2C_MST_DATA_WORD3 0x14 #define RTL9300_I2C_MST_GLB_CTRL 0x384 =20 +#define RTL9310_I2C_MST_IF_CTRL 0x1004 +#define RTL9310_I2C_MST_IF_SEL 0x1008 +#define RTL9310_I2C_MST_CTRL 0x0 +#define RTL9310_I2C_MST_MEMADDR_CTRL 0x4 +#define RTL9310_I2C_MST_DATA_CTRL 0x8 + static int rtl9300_i2c_reg_addr_set(struct rtl9300_i2c *i2c, u32 reg, u16 = len) { int ret; @@ -114,6 +122,11 @@ static int rtl9300_i2c_select_scl(struct rtl9300_i2c *= i2c, u8 scl) return regmap_field_write(i2c->fields[F_SCL_SEL], 1); } =20 +static int rtl9310_i2c_select_scl(struct rtl9300_i2c *i2c, u8 scl) +{ + return regmap_field_update_bits(i2c->fields[F_SCL_SEL], BIT(scl), BIT(scl= )); +} + static int rtl9300_i2c_config_chan(struct rtl9300_i2c *i2c, struct rtl9300= _i2c_chan *chan) { struct rtl9300_i2c_drv_data *drv_data; @@ -127,7 +140,7 @@ static int rtl9300_i2c_config_chan(struct rtl9300_i2c *= i2c, struct rtl9300_i2c_c return ret; =20 drv_data =3D (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->de= v); - ret =3D drv_data->select_scl(i2c, 0); + ret =3D drv_data->select_scl(i2c, i2c->scl_num); if (ret) return ret; =20 @@ -379,6 +392,10 @@ static int rtl9300_i2c_probe(struct platform_device *p= dev) if (ret) return ret; =20 + ret =3D device_property_read_u8(dev, "realtek,scl", &i2c->scl_num); + if (ret || i2c->scl_num !=3D 1) + i2c->scl_num =3D 0; + platform_set_drvdata(pdev, i2c); =20 drv_data =3D (struct rtl9300_i2c_drv_data *)device_get_match_data(i2c->de= v); @@ -474,12 +491,35 @@ static const struct rtl9300_i2c_drv_data rtl9300_i2c_= drv_data =3D { .max_nchan =3D RTL9300_I2C_MUX_NCHAN, }; =20 +static const struct rtl9300_i2c_drv_data rtl9310_i2c_drv_data =3D { + .field_desc =3D { + [F_SCL_SEL] =3D GLB_REG_FIELD(RTL9310_I2C_MST_IF_SEL, 12, 13), + [F_SDA_SEL] =3D GLB_REG_FIELD(RTL9310_I2C_MST_IF_SEL, 0, 11), + [F_SCL_FREQ] =3D MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 30, 31), + [F_DEV_ADDR] =3D MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 11, 17), + [F_SDA_OUT_SEL] =3D MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 18, 21), + [F_MEM_ADDR_WIDTH] =3D MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 9, 10), + [F_DATA_WIDTH] =3D MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 5, 8), + [F_RD_MODE] =3D MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 4, 4), + [F_RWOP] =3D MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 2, 2), + [F_I2C_FAIL] =3D MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 1, 1), + [F_I2C_TRIG] =3D MST_REG_FIELD(RTL9310_I2C_MST_CTRL, 0, 0), + [F_MEM_ADDR] =3D MST_REG_FIELD(RTL9310_I2C_MST_MEMADDR_CTRL, 0, 23), + }, + .select_scl =3D rtl9310_i2c_select_scl, + .data_reg =3D RTL9310_I2C_MST_DATA_CTRL, + .max_nchan =3D RTL9310_I2C_MUX_NCHAN, +}; =20 static const struct of_device_id i2c_rtl9300_dt_ids[] =3D { { .compatible =3D "realtek,rtl9301-i2c", .data =3D (void *) &rtl9300_i2c_= drv_data }, { .compatible =3D "realtek,rtl9302b-i2c", .data =3D (void *) &rtl9300_i2c= _drv_data }, { .compatible =3D "realtek,rtl9302c-i2c", .data =3D (void *) &rtl9300_i2c= _drv_data }, { .compatible =3D "realtek,rtl9303-i2c", .data =3D (void *) &rtl9300_i2c_= drv_data }, + { .compatible =3D "realtek,rtl9310-i2c", .data =3D (void *) &rtl9310_i2c_= drv_data }, + { .compatible =3D "realtek,rtl9311-i2c", .data =3D (void *) &rtl9310_i2c_= drv_data }, + { .compatible =3D "realtek,rtl9312-i2c", .data =3D (void *) &rtl9310_i2c_= drv_data }, + { .compatible =3D "realtek,rtl9313-i2c", .data =3D (void *) &rtl9310_i2c_= drv_data }, {} }; MODULE_DEVICE_TABLE(of, i2c_rtl9300_dt_ids); --=20 2.48.1