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Sun, 24 Aug 2025 01:40:20 -0700 From: Mark Bloch To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Tariq Toukan , Leon Romanovsky , "Saeed Mahameed" , , , Gal Pressman , Moshe Shemesh , Parav Pandit , Mark Bloch , Shay Drory Subject: [PATCH net 07/11] net/mlx5: Nack sync reset when SFs are present Date: Sun, 24 Aug 2025 11:39:40 +0300 Message-ID: <20250824083944.523858-8-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250824083944.523858-1-mbloch@nvidia.com> References: <20250824083944.523858-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD82:EE_|MW4PR12MB7000:EE_ X-MS-Office365-Filtering-Correlation-Id: 1ed5d553-55a5-40b8-2dbd-08dde2e9e709 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?MvU36WoTOJ7XVkZQaOyU0vCjk0ZZY1VK80NeWukrN2rnO7CFlRGXJu57Yrux?= =?us-ascii?Q?oKCweKR8ZSPyqK5KVkdw538X8l7GOzZ9cO1dgGpYTPwAIWQw/vyXcFsUBF11?= =?us-ascii?Q?JX1PNhkWlrTV3lPaGlx2OnwkEbGgg1hzrTljf2Dfk+vhAjW0jtY1eTL94gI3?= =?us-ascii?Q?qe65tEw4raP7c83Dh6F6soO8otuXnaVXZu9xmVUbj6xmvl2etEMX98bh/cmg?= =?us-ascii?Q?/vPLzShy7weFH0LMx/VXgTUhHjFh8mXJWwJSli36KWr1nHlm4i0xAZQejCwj?= =?us-ascii?Q?aUsRVuDdA0uddsJcFmZ75sgEhL7WJV9M0/3fvdVF+9OsmhHjmrt01MBXOwS9?= =?us-ascii?Q?FeEkeaSK2DSbnB04KPWiljbA8weYQB/xYr+52fFBZSNqVl7Ru9uG9Z0cxWBk?= =?us-ascii?Q?tpYI+XboFsQy9DebPOOE9KeHRpVhasO0HrXye5cgDypVgnvPdC/POH+fnwBJ?= =?us-ascii?Q?GQ6sB/GPShc1/jadU09y2QSUXJ+LCu4E1OS751Q69/TEEy7kPrxS362DrV6C?= =?us-ascii?Q?6yFbqgBcgQ2awua9AvEscEecQwXAw3HDVrqjeVWEeYmbqiI45cfRyUJu8BeY?= =?us-ascii?Q?k51buQecIo83L0uODMnGxZmH/KS4z9YKNM3XWbQJk9Vim5YsOcgT6aEWoeOB?= =?us-ascii?Q?NTHjqjzvdt4/34Af4lbysyseBoJiKfB7slh7L6GQVNN2FKabPMbQe+YMJr48?= =?us-ascii?Q?5gbWvyO2z+xbZ6CEmcPmq79xTAKP+DXAosW4ui3zy+4xRY4QACuKdhJ20nVh?= =?us-ascii?Q?Ula8396tJ3S+SHqs/APMyIdBGlPyTZ6wNoCeRWENsQ2p6Y/JFdEaoCUlQfJH?= =?us-ascii?Q?KeS5gWcT3MGWzQq4MJ5SmFzwaK0hXbLrzHyNm183onziAsFEc0ZFYHBaSADJ?= =?us-ascii?Q?mTUxl6YJqFrpEPN78RLckqrpbHypx8sfqLzXMRSayYo6xHr4OI439u7vu6kq?= =?us-ascii?Q?zvGURm2bkSP8U4TAu+MxxEi5uJ6jHib9QG/4sE41WIrrTz3rvME9mDUZgvaF?= =?us-ascii?Q?4Pr4Ex/5lOTAhmtYQyXz9BmM7SfFUi169/6YZmK1DcdzRl8NLfBWEof/TU+i?= =?us-ascii?Q?Vv1b7Z8siNT9aMibx+emAspWCPZ7QLBs0UL2SMGI8R/ZDg7I7w1NiQBtqcOR?= =?us-ascii?Q?2hLjemOUCVb+WHxfqnjNbOEiffZ5q440vPH3C+EbPXs1PXuPuzkgvHuOYJTi?= =?us-ascii?Q?JUJnXfxmi3uuvAPzNv8Rx+RFsl6B6uqNC/jRmTap4jykO6jtGujUCenG5Xyo?= =?us-ascii?Q?le1Jf7zaJsEzas5Pf7NRW/DkL0w2daj0fiiX8UX05o9R/qDWqD0X5ApCW3s+?= =?us-ascii?Q?4UV1T6OpLU+5376lH8/YSIM6xK2N4oJZEWqRZDy/gs06uI+y2d+0CgVp5TLI?= =?us-ascii?Q?4KtOO9QQHGptFY9ANlsUXtfKTY354ttvYODYXVzuz2ZVkh4gdZT3MK7YH5wr?= =?us-ascii?Q?kNXgRlL+UimItRBoNhDoyVHVqUyJhB6N/LcIaOSiYiTIW6vr2RIgYSHPlcTD?= =?us-ascii?Q?It3y3F0BPfHN09zWEtXwxjssU8ztZp/OhZNT?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Aug 2025 08:40:38.6122 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1ed5d553-55a5-40b8-2dbd-08dde2e9e709 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD82.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7000 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh If PF (Physical Function) has SFs (Sub-Functions), since the SFs are not taking part in the synchronization flow, sync reset can lead to fatal error on the SFs, as the function will be closed unexpectedly from the SF point of view. Add a check to prevent sync reset when there are SFs on a PF device which is not ECPF, as ECPF is teardowned gracefully before reset. Fixes: 92501fa6e421 ("net/mlx5: Ack on sync_reset_request only if PF can do= reset_now") Signed-off-by: Moshe Shemesh Reviewed-by: Parav Pandit Reviewed-by: Tariq Toukan Signed-off-by: Mark Bloch --- drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c | 6 ++++++ drivers/net/ethernet/mellanox/mlx5/core/sf/devlink.c | 10 ++++++++++ drivers/net/ethernet/mellanox/mlx5/core/sf/sf.h | 6 ++++++ 3 files changed, 22 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c b/drivers/n= et/ethernet/mellanox/mlx5/core/fw_reset.c index 38b9b184ae01..22995131824a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c @@ -6,6 +6,7 @@ #include "fw_reset.h" #include "diag/fw_tracer.h" #include "lib/tout.h" +#include "sf/sf.h" =20 enum { MLX5_FW_RESET_FLAGS_RESET_REQUESTED, @@ -428,6 +429,11 @@ static bool mlx5_is_reset_now_capable(struct mlx5_core= _dev *dev, return false; } =20 + if (!mlx5_core_is_ecpf(dev) && !mlx5_sf_table_empty(dev)) { + mlx5_core_warn(dev, "SFs should be removed before reset\n"); + return false; + } + #if IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE) if (reset_method !=3D MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET) { err =3D mlx5_check_hotplug_interrupt(dev, bridge); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sf/devlink.c b/drivers= /net/ethernet/mellanox/mlx5/core/sf/devlink.c index 0864ba625c07..3304f25cc805 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/sf/devlink.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/sf/devlink.c @@ -518,3 +518,13 @@ void mlx5_sf_table_cleanup(struct mlx5_core_dev *dev) WARN_ON(!xa_empty(&table->function_ids)); kfree(table); } + +bool mlx5_sf_table_empty(const struct mlx5_core_dev *dev) +{ + struct mlx5_sf_table *table =3D dev->priv.sf_table; + + if (!table) + return true; + + return xa_empty(&table->function_ids); +} diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sf/sf.h b/drivers/net/= ethernet/mellanox/mlx5/core/sf/sf.h index 860f9ddb7107..89559a37997a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/sf/sf.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/sf/sf.h @@ -17,6 +17,7 @@ void mlx5_sf_hw_table_destroy(struct mlx5_core_dev *dev); =20 int mlx5_sf_table_init(struct mlx5_core_dev *dev); void mlx5_sf_table_cleanup(struct mlx5_core_dev *dev); +bool mlx5_sf_table_empty(const struct mlx5_core_dev *dev); =20 int mlx5_devlink_sf_port_new(struct devlink *devlink, const struct devlink_port_new_attrs *add_attr, @@ -61,6 +62,11 @@ static inline void mlx5_sf_table_cleanup(struct mlx5_cor= e_dev *dev) { } =20 +static inline bool mlx5_sf_table_empty(const struct mlx5_core_dev *dev) +{ + return true; +} + #endif =20 #endif --=20 2.34.1