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Sun, 24 Aug 2025 01:39:51 -0700 From: Mark Bloch To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Tariq Toukan , Leon Romanovsky , "Saeed Mahameed" , , , Gal Pressman , Lama Kayal , Mark Bloch , Yevgeny Kliteynik , Itamar Gozlan Subject: [PATCH net 01/11] net/mlx5: HWS, Fix memory leak in hws_pool_buddy_init error path Date: Sun, 24 Aug 2025 11:39:34 +0300 Message-ID: <20250824083944.523858-2-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250824083944.523858-1-mbloch@nvidia.com> References: <20250824083944.523858-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD82:EE_|IA1PR12MB6628:EE_ X-MS-Office365-Filtering-Correlation-Id: d13a21e7-2eba-4bc3-0d70-08dde2e9d70a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?n3woIPlf7FfBpUQ9Dur6eEFrSHKn3DpIvZOdttpncVA54/UBNxq42Y+8qktL?= =?us-ascii?Q?q9nwrBxwDHZAB7htZl0W9O7MDlLQ8QmsNNiFN5z/Gk9ftHWQcZQcg9d7j0Xr?= =?us-ascii?Q?lCUDMkdp+K1rYBgGIk1XoHXuGWMldswmRFkNnf8ERN3ziA/nv+DaPG38rEc9?= =?us-ascii?Q?br+0edGdfd7W0X3v1hLndcbJaOqVxVzAxPAvYtawgE7oSAnuvOHOJ8c1ECqQ?= =?us-ascii?Q?har0uoqmmJw6KUP8TVKGPIRr91fRQgcBiZE8ORt86JEkyD37HN/wK1AhxRUP?= =?us-ascii?Q?VvaMtEq9Nk/Q1TT0AcqIUZ4lsMpLafgQd9Y+Y6XmiWsdF2WHeivZ+lpKTLYl?= =?us-ascii?Q?kpl8aZ0ZgRz145/JtquK5zTwbbgOZmfKDh8aG07TQJp9DHJOYItgFSyYOQxt?= =?us-ascii?Q?spUibtjBi3AxIaztVMVdTWiuZevExbM8cZbnwq05HMN6UK71AvClmf196DNW?= =?us-ascii?Q?6ov6R6X4jume/Iz4FCLF9KYGfak1/XnpS9Id6k6evnbEgT9ihDHksU6NErwL?= =?us-ascii?Q?ed9mDLCbVSlmwo06QOQBtl2Z20jNwFpAqr5o/26MlZ8lhZH0x8Jf+fFbTrYX?= =?us-ascii?Q?nVhTa/31YKK+kOb19MwwzgPPNms7iINX2Ncl2bGfqO/MVkZ8vhEUMAcEj5dL?= =?us-ascii?Q?Z+3y4k644ePVcovCjms2KwGokMXqm4cwZxxvSJmP6EjSi+WVwuWYC0B/dMJy?= =?us-ascii?Q?z8nIaut3QQWCR8yr9aHZTYb4hueWRsqbk5Kg0fCs6J4o0R4kRJDOK2VZjL/v?= =?us-ascii?Q?CoMfZtk1YpVn71gHXeKzUSqdOsquJ/vLs3ex3BfN9aInGj2SdX4JrLOy0MtI?= =?us-ascii?Q?8ifaxluD5pmRBMLIX3Kfq2INVZWZlzYUjhR9SRWF7pc14gebtR6b3uxR1SW9?= =?us-ascii?Q?5uVvt+QN16T/okc9V2spvzqtIgCUWLIM0MggehQzczPTdYFta6NarchWdgvj?= =?us-ascii?Q?g1O9VzHUbCCscYxFF38S3uGGyXizzHaEY8J/jXooH8H7TCAADOlWvc0S3QhI?= =?us-ascii?Q?ZQw+jIj4FuSXG/BkeyPv8xX0jvAgty/vPVenNTOvKZDQYUhcdW7hUtQa3Gux?= =?us-ascii?Q?M38uk9TIuEzm7ZciaHNnWL5mAKjmfFwPx9Rsp7uxlYtc/ro4/y9uuI+VXgYd?= =?us-ascii?Q?2Jvl65nsr31AWtsc55XeM8spHKsI/WvF2g4LAZoYM/28z4tsBntaEzwnsAfR?= =?us-ascii?Q?tBv+ixA5X8kfwdaeeWRMgVfn7xRwm5yb1sH1Z5QXadVeXCg0s/fwk++X95Nw?= =?us-ascii?Q?NDek84Mp17sItIbvQu0x+4fuzY2dKf9QvEcg6rxv1nmgvefWkgfi9t+DxmuO?= =?us-ascii?Q?XqBu7IuErSWgQgeTzR3jxPvGT+xeXvB/wrozSMAxXaIl7pkBiRRSUIYQCZJV?= =?us-ascii?Q?VFipe8kZiMjcg2R1MtpTkuzck2FqbT+dAZs+xQYkoqZvW+KzRK3wf5kckYrZ?= =?us-ascii?Q?eyYb7Pl+/Dr6uG/Ykim0B7Tlm1yXvecRYh+Awh4SYd6dEvPqt/5IsYVTRDnz?= =?us-ascii?Q?Mh5+VoCAdadvSku0nw+f8+hgDbyoLS6T/8U3?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Aug 2025 08:40:11.7313 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d13a21e7-2eba-4bc3-0d70-08dde2e9d70a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD82.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6628 Content-Type: text/plain; charset="utf-8" From: Lama Kayal In the error path of hws_pool_buddy_init(), the buddy allocator cleanup doesn't free the allocator structure itself, causing a memory leak. Add the missing kfree() to properly release all allocated memory. Fixes: c61afff94373 ("net/mlx5: HWS, added memory management handling") Signed-off-by: Lama Kayal Reviewed-by: Tariq Toukan Signed-off-by: Mark Bloch --- drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pool.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pool.c b/= drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pool.c index 7e37d6e9eb83..7b5071c3df36 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pool.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pool.c @@ -124,6 +124,7 @@ static int hws_pool_buddy_init(struct mlx5hws_pool *poo= l) mlx5hws_err(pool->ctx, "Failed to create resource type: %d size %zu\n", pool->type, pool->alloc_log_sz); mlx5hws_buddy_cleanup(buddy); + kfree(buddy); return -ENOMEM; } =20 --=20 2.34.1 From nobody Fri Oct 3 21:55:31 2025 Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-sn1nam02on2076.outbound.protection.outlook.com [40.107.96.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 57C781DE885; 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Miller" CC: Tariq Toukan , Leon Romanovsky , "Saeed Mahameed" , , , Gal Pressman , Lama Kayal , Mark Bloch , Yevgeny Kliteynik , Erez Shitrit Subject: [PATCH net 02/11] net/mlx5: HWS, Fix memory leak in hws_action_get_shared_stc_nic error flow Date: Sun, 24 Aug 2025 11:39:35 +0300 Message-ID: <20250824083944.523858-3-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250824083944.523858-1-mbloch@nvidia.com> References: <20250824083944.523858-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000144:EE_|LV2PR12MB5773:EE_ X-MS-Office365-Filtering-Correlation-Id: 1ca1dddf-2211-4fd0-b935-08dde2e9daf1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?AGTPh73wfe40+k7fCBSZiCKtT+alPCKIXGClYXqBoQWX8ZQ924rtHH7o6AXJ?= =?us-ascii?Q?tbwGhZbW5bsYL9+2qstpcMKMPu6A2O+puJeJyz15pQ9VQ65U88neAU7dFmNk?= =?us-ascii?Q?nzweQ6SpRZ3YJEnnmDgIvL5PweZjhS1zytlLiGCsvOh936vB5+bexRIENZ+N?= =?us-ascii?Q?SVIMQK9fa0130l8uVLhblexrY8bp5W+hx/sRpqyTo8ZNS1a+K0vNPE5djEe5?= =?us-ascii?Q?tgSjeCbi7yil1WRjP2jHa3hA8xADgEctL84USsjnop325pm3DhG3dnpP+JKE?= =?us-ascii?Q?5qWoyjYpKUZ97ucE/56iaISczk6HxlNxDRITmHyGoBk0LJ7iyR25bZc9b0A2?= =?us-ascii?Q?QbrflB7cfvI39hKoe5tpukQX78k/Ldu2zfNiD+eGTcHKyqROvQzGKHkniwwI?= =?us-ascii?Q?0H2N9YGmzD5nNrNsgWP3mdj+6uepGiuVxJPmHIVnOigfCAVTyHOzkhHzXn0y?= =?us-ascii?Q?U/nHvS2oYibMqv0kr7IA8IjTkUO3UQUOuCZWi/9VLG5pT6EuuV1OQdQhc9Jy?= =?us-ascii?Q?zRhGsYtFc8eWrfc2PoByaGcF0zd7siBZv27xE2gp3RC6AnXs/FhWOtPakcZz?= =?us-ascii?Q?5DCR6w5W7XPy7TcMjjol3TogZKkKCe3CzASaYusOMRm4dxLgrW1yD2KRnh86?= =?us-ascii?Q?A+E1NdjKCUPTfkld36y6EUpsV8c0Ku5AO+GbFjy7bl10x5JVnqBGcjXn4NFh?= =?us-ascii?Q?a1PznvQyNXKpV97b3S76aWKLLTN0Ae0GAr85TNYkqPFuocOOrO3JXcz90/80?= =?us-ascii?Q?vmyMcWFX0BLQtabmvF+IVwzK2zJkRsOkkYlHS6s+m87TfhHG/W7vgwLrZfG5?= =?us-ascii?Q?subDNE72/NPyKe/EVs6oJTjYZI1Z1RcRkVRdVZwKlOgwPkK3jBpI5qWty64q?= =?us-ascii?Q?M/HyQ2SjEp0ZsUmO0RE7hkZfzeZKKVmwyryDOetZPzm1pS/RJfufg+b1jorJ?= =?us-ascii?Q?1Jpnlx05QHEU0BLvlCxtlpv4Rdfa1NcsMZS1TE9yek5Y5OdpxI3cvonZpkGY?= =?us-ascii?Q?+GvwM2WStAUcqXtqOv5eVTjYCCi5ddJi6MnifzFQJjVCSD/OZ99rMPxvYlC1?= =?us-ascii?Q?/jav0ZjbEO0jiJGzAJGuCpiP+Eh2jwpBEGq7brbGm1oe0XzPrPnZ7CFOY0NN?= =?us-ascii?Q?QDBKtHM8VqKELd3q8BAH1Fe2rz9v/UHjJYfCU0V5gw0166qs6bFahN9kp4qj?= =?us-ascii?Q?HXK/qWQTokc3Q9iMc877HJUd9HhM85iPyMR5GHyWPNk8LyUB5DcvmqBodBRF?= =?us-ascii?Q?JC4i6kxaOUCAdsEwipQMz/ghCxbzKR8tfbnN77rvmSs4sAAQvqV+Cp1Mz7qw?= =?us-ascii?Q?fsX7rowe40iSdACfcA9E2eZA1JYnLi1khwMnf4FGvMamlSjpHHzMx00fb1Ns?= =?us-ascii?Q?u2UzzDhSVE1CPGFj78vT8QR3AYeSyKrNg/FwLJLBC0PbI7/odqxJGZDbdoy8?= =?us-ascii?Q?NbVP6UDOtJpjxMSOX1KcAAmb21JiZQzZYjetG6o+WaLGqSHGglVNsa7bOOCK?= =?us-ascii?Q?2vGusEnog7HPrzFaIy3/DzjP00gzqB8UcYyH?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Aug 2025 08:40:18.3528 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1ca1dddf-2211-4fd0-b935-08dde2e9daf1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000144.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5773 Content-Type: text/plain; charset="utf-8" From: Lama Kayal When an invalid stc_type is provided, the function allocates memory for shared_stc but jumps to unlock_and_out without freeing it, causing a memory leak. Fix by jumping to free_shared_stc label instead to ensure proper cleanup. Fixes: 504e536d9010 ("net/mlx5: HWS, added actions handling") Signed-off-by: Lama Kayal Reviewed-by: Tariq Toukan Signed-off-by: Mark Bloch --- drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c = b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c index 396804369b00..6b36a4a7d895 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/action.c @@ -117,7 +117,7 @@ static int hws_action_get_shared_stc_nic(struct mlx5hws= _context *ctx, mlx5hws_err(ctx, "No such stc_type: %d\n", stc_type); pr_warn("HWS: Invalid stc_type: %d\n", stc_type); ret =3D -EINVAL; - goto unlock_and_out; + goto free_shared_stc; } =20 ret =3D mlx5hws_action_alloc_single_stc(ctx, &stc_attr, tbl_type, --=20 2.34.1 From nobody Fri Oct 3 21:55:31 2025 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2055.outbound.protection.outlook.com [40.107.92.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C43425F7A9; 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Miller" CC: Tariq Toukan , Leon Romanovsky , "Saeed Mahameed" , , , Gal Pressman , Lama Kayal , Mark Bloch , Vlad Dogaru , Yevgeny Kliteynik Subject: [PATCH net 03/11] net/mlx5: HWS, Fix uninitialized variables in mlx5hws_pat_calc_nop error flow Date: Sun, 24 Aug 2025 11:39:36 +0300 Message-ID: <20250824083944.523858-4-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250824083944.523858-1-mbloch@nvidia.com> References: <20250824083944.523858-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7D:EE_|MW3PR12MB4361:EE_ X-MS-Office365-Filtering-Correlation-Id: f2cdef3d-1669-49bf-3d67-08dde2e9dd15 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?70uMi6ia7T/98Z2ea6ePCm8rvF/KiK7200ED1mVJEZztlcFncgAZ/Bgd4+Ye?= =?us-ascii?Q?R0U0yw7TY+qFtGYmmz44AuadTbTOe9ckRSxw4kumc2uHHXgrnQgADdQLODEz?= =?us-ascii?Q?stKC4zaE6kMryexCnISM9wrIJVHEv8h+SzDh7KW9U66gQyNPP4pBW9bjXwYA?= =?us-ascii?Q?jSMt0vTsyFhyUIVtmVfgHHM7lHA4KKnomQfMWeMb22sgslZzg+7xRS4vIA0t?= =?us-ascii?Q?nuiGwRx3hgs+68aDy6O0s1SO1ryzedS5G97VHij4ZgyvPQUFJ16fhExnM4hz?= =?us-ascii?Q?uqg7FyZctbh9j5KSuFvmheB2xQFR4BZI+2E3hDhfy2SYGe4jaXkHr7gMkMjn?= =?us-ascii?Q?KHKt+Vse0KbgH9zThCMbOEfn8qcOFvNW39QGQlH4ZQN7qiWt5Khol+g+eVFn?= =?us-ascii?Q?cuh+QaWzttG2UXfNqOX4BiTgdnhH1k0RaVVWbkj+U67uZthcetUWLweOkQho?= =?us-ascii?Q?Pz9QwqS2tv4NN6Fyz0VPH7VfufU8dG7ihqiEBXgCS/AEbOI/bSBsufuA987K?= =?us-ascii?Q?ldlC/wCCJqkt8+sqxqWjUcUMYp158vUxUHogkroiPb/3Skj1P3VWB8YQ76ss?= =?us-ascii?Q?e+P0tkEPZA1OZ3nYoxCRZsQaTg+IcrzOCHvbKrqNA4mMge/2fM9HAy3S3nmL?= =?us-ascii?Q?H3WFy5s/kk0gNP/4XvKIqbNPJ1XtYZ5vVb0Myv+cpGI5/can5HIE/IlcXr/N?= =?us-ascii?Q?tjf2WvB06DepO6r2GX8f4JSzPJ2v9AE80Cz29e89ACmF3jQVAyQwcTIfownR?= =?us-ascii?Q?AFCKgkQ7y3UbY/ngqXEgoe8J+czfXm6igN3ZbImtfGoLUEsgTc7os6nReqI1?= =?us-ascii?Q?GiH6VNTKPMFFW6K8q7zMAlRdfQwT+rR/0sN7VSTo5s7hwZqSDiUVMT4kflAV?= =?us-ascii?Q?zpRimuN4KA7WduxgEEzQ9B6HNbBwIE3uzsO9T0zGUQMBwwpjclQbuLb/i0d5?= =?us-ascii?Q?6cjGnNARVFfw+R7Ik7qOlCiboHzqtJsDBi6+2MmrVYYEiCqhA7y4PBaBrACI?= =?us-ascii?Q?5zYGqsy2hwZKpF/q7kUg3AF0L5kBOXdG/yAjXwbv8AMz1ky7QoYLDBWydn8J?= =?us-ascii?Q?y6v7GPpGih+VgNTbeN/UMo7AGVANfqoEieN3LMYUagweWR4YOMEMvFnzyOeF?= =?us-ascii?Q?7mBw1aPdOHhSfFbCQGMpwZFUGqubaKyP+q04tDdOxTNBt8A1Vi26p+u2rYuY?= =?us-ascii?Q?zJ3s8RJoGM3P3/wFpHBL29LXb8xLzy3hxxhFEH03NR3TvKef82atEzqHxXZo?= =?us-ascii?Q?Eqt9ZMRFFlikPdC0FX/q8EJUYDIWqS7gesEI4JLk8WFNAwx63uL2teqP6KCS?= =?us-ascii?Q?d0UKwy0Xr6RAZ079SZ820Fe4c1RKGPokWAYwYsiwJ6euTsnVIvU1JM4fJjuS?= =?us-ascii?Q?vKz66q/PnwjoyQ97UqLsZ3TeNzE8y2Rilymc4BAUzJBKogTYjFodCo4k/Fj/?= =?us-ascii?Q?2ADA8M9Fd1EJsUlKpeodRt6ERU6H1/W5Eh6tgQPDYJq3pmYVGQINSd92HJwK?= =?us-ascii?Q?A8qWkmaVQXezQrgNngbv651MVCE/6ss2fKuv?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Aug 2025 08:40:21.8918 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f2cdef3d-1669-49bf-3d67-08dde2e9dd15 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4361 Content-Type: text/plain; charset="utf-8" From: Lama Kayal In mlx5hws_pat_calc_nop(), src_field and dst_field are passed to hws_action_modify_get_target_fields() which should set their values. However, if an invalid action type is encountered, these variables remain uninitialized and are later used to update prev_src_field and prev_dst_field. Initialize both variables to INVALID_FIELD to ensure they have defined values in all code paths. Fixes: 01e035fd0380 ("net/mlx5: HWS, handle modify header actions dependenc= y") Signed-off-by: Lama Kayal Reviewed-by: Tariq Toukan Signed-off-by: Mark Bloch --- .../net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c= b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c index 51e4c551e0ef..622fd579f140 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c @@ -527,7 +527,6 @@ int mlx5hws_pat_calc_nop(__be64 *pattern, size_t num_ac= tions, u32 *nop_locations, __be64 *new_pat) { u16 prev_src_field =3D INVALID_FIELD, prev_dst_field =3D INVALID_FIELD; - u16 src_field, dst_field; u8 action_type; bool dependent; size_t i, j; @@ -539,6 +538,9 @@ int mlx5hws_pat_calc_nop(__be64 *pattern, size_t num_ac= tions, return 0; =20 for (i =3D 0, j =3D 0; i < num_actions; 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Miller" CC: Tariq Toukan , Leon Romanovsky , "Saeed Mahameed" , , , Gal Pressman , Lama Kayal , Mark Bloch , Yevgeny Kliteynik , Hamdan Agbariya Subject: [PATCH net 04/11] net/mlx5: HWS, Fix pattern destruction in mlx5hws_pat_get_pattern error path Date: Sun, 24 Aug 2025 11:39:37 +0300 Message-ID: <20250824083944.523858-5-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250824083944.523858-1-mbloch@nvidia.com> References: <20250824083944.523858-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD81:EE_|DS0PR12MB6486:EE_ X-MS-Office365-Filtering-Correlation-Id: 0c8d45fb-0edc-4fd3-e3c0-08dde2e9e20a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?0tTUyHspbYXQeMiJRx5Z1QTrXsarKDQr/rmzaSAr47wQvqgzvWIDdGWEy2YV?= =?us-ascii?Q?8JNVqB13VEyJIRE3GB3sBnjC19daGsDXrgR0l3EwLVuvuHZIUzd4bw/MOP46?= =?us-ascii?Q?9uzX2T4Zygr9qjgDWSWx4V8aBg1h+W3naiNtx22/2o/BHa5hUMkxol7SoQe9?= =?us-ascii?Q?hY+bOT92NVpw++jjDyizuRLDND67GDI1knE07Ya+R58W0hKMdsSGLp91QKbQ?= =?us-ascii?Q?rS7+cgchgFN9M9qHWpIeL/PaCihWAMZPydUdXqxb2L7EnOYfezv3zO1yWXcT?= =?us-ascii?Q?X7ShT4TdKkllVuFv+8bJ1R+G+gQ+hPByd0Iq8JYvOrBmh0c1kkbNTHueUQqk?= =?us-ascii?Q?9Pov9zympBsYLKeQyI2GotB0zd/XVNluzwGrqqC1xuFRo0lIAMPuVbsOGe8v?= =?us-ascii?Q?LR6HBYp7oUmJ9j0sPsl1EwP+nbIlXl/Kg0iFSODdtAEZjEDS5BuJfDYNS8N5?= =?us-ascii?Q?FWtRz9oNc6ZK8J5v7BPyjxwqr1Pn6wnHt0dIx9wDmnlnHnZeHJMHwKtZn+vN?= =?us-ascii?Q?c+/b/Ol9ZecebhGRMfdnqM0c0N1A9P2F8kqpUgiaqGRYh//EVB83FRLeD6Ul?= =?us-ascii?Q?YrzEDKZ+Q8lOojSFP5Jv8BVxReulMEcp+VluAmid+KOrdUQaThfhcwPvkMT9?= =?us-ascii?Q?rQUMh+gTgymd+saDOpBHytS7/yISI32ZbMOLpFD0ssmpHUV7T4LXg4CoxtG2?= =?us-ascii?Q?qo1rqdjAWNCwEPR6vQeuEG4MZMOH4yeurVhzAIRtav2zkFfslopn6UqNc9mw?= =?us-ascii?Q?3iBIrC1/eEkDtTs1hQeyAKWmj7XzMtnUozvEm5CfgnEtH5YGpZJhlHdKsVOu?= =?us-ascii?Q?q3D9NHPDzsPyG8DEtMx0LN/IAfzOFAH2GFSsRACHTrDVvtfRAxlcbrHHKcpH?= =?us-ascii?Q?Mx1bT72ladHbDQMJqzCW3lU6ozNYVKddbtKy26OucsEqi5TSlWrxHYCysUX9?= =?us-ascii?Q?loNUj9cl+MOqMrmXl/kDgjYwbpb8A/hJ1JfJCjrD7yoV6uY7Pc5I4u/h/YR4?= =?us-ascii?Q?5rs7XeYdgknAS7Vy4jdf99cXZxoj3ps7DfGEjjl3KgcY0/pog7jjH9E3ylKJ?= =?us-ascii?Q?6WoMM0dLaqu5MGptgqTOuroTv2XcCi033OOLzmCSyXA5DQI4p3AZ0To5XdHt?= =?us-ascii?Q?Fo2ge2c7qoTxbxXr2/a1wNDJIzXqfy1ZvR4c5c2iTftpCmg2vSohSnOW95Ar?= =?us-ascii?Q?PJya8yrCGr9kGuTvAbZEg+XDd50JtSzsnXJ2LK16h1HMNSjNlZL+jjyoTHca?= =?us-ascii?Q?1bvytRV1iHFoCKFW2uIT0yruhUx5KFN/ZM8qttVjeUZvrsgehCXTgBiFjo9i?= =?us-ascii?Q?Iyxl3kcTqWjqCYY9PweQBkedm5+tD8UtcocvGkaDmhTzFdhJ1T8F4Oh022M3?= =?us-ascii?Q?Do8ZhtGj3uCDJHBozRj/7ZAA4xO/B7HX4HKyStRCvbDtuCuPk+4Q47AURcFK?= =?us-ascii?Q?GevTCkM87QiI9Epn4uiduJfZ0DJGSjrdTtXvv1wn5XwDiK+uG1GHxNdCsl9k?= =?us-ascii?Q?DfTTSZxqUe0Vvui2b9FE4hobrMhnsm4bDoqr?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Aug 2025 08:40:30.2522 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0c8d45fb-0edc-4fd3-e3c0-08dde2e9e20a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD81.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6486 Content-Type: text/plain; charset="utf-8" From: Lama Kayal In mlx5hws_pat_get_pattern(), when mlx5hws_pat_add_pattern_to_cache() fails, the function attempts to clean up the pattern created by mlx5hws_cmd_header_modify_pattern_create(). However, it incorrectly uses *pattern_id which hasn't been set yet, instead of the local ptrn_id variable that contains the actual pattern ID. This results in attempting to destroy a pattern using uninitialized data from the output parameter, rather than the valid pattern ID returned by the firmware. Use ptrn_id instead of *pattern_id in the cleanup path to properly destroy the created pattern. Fixes: aefc15a0fa1c ("net/mlx5: HWS, added modify header pattern and args h= andling") Signed-off-by: Lama Kayal Reviewed-by: Tariq Toukan Signed-off-by: Mark Bloch --- drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c= b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c index 622fd579f140..d56271a9e4f0 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/pat_arg.c @@ -279,7 +279,7 @@ int mlx5hws_pat_get_pattern(struct mlx5hws_context *ctx, return ret; =20 clean_pattern: - mlx5hws_cmd_header_modify_pattern_destroy(ctx->mdev, *pattern_id); + mlx5hws_cmd_header_modify_pattern_destroy(ctx->mdev, ptrn_id); out_unlock: mutex_unlock(&ctx->pattern_cache->lock); return ret; --=20 2.34.1 From nobody Fri Oct 3 21:55:31 2025 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2082.outbound.protection.outlook.com [40.107.94.82]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A79E025C6EC; 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Miller" CC: Tariq Toukan , Leon Romanovsky , "Saeed Mahameed" , , , Gal Pressman , Moshe Shemesh , Akiva Goldberger , Mark Bloch , Jiri Pirko , Jiri Pirko Subject: [PATCH net 05/11] net/mlx5: Reload auxiliary drivers on fw_activate Date: Sun, 24 Aug 2025 11:39:38 +0300 Message-ID: <20250824083944.523858-6-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250824083944.523858-1-mbloch@nvidia.com> References: <20250824083944.523858-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000147:EE_|CH3PR12MB9429:EE_ X-MS-Office365-Filtering-Correlation-Id: e12b351b-6385-44f6-0d15-08dde2e9e614 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?YPffF0IBWuesDjbLTUoZLJzmCvZ/CBEdkfkuuwNlCHH0DF/LY4vSp9YF9yH2?= =?us-ascii?Q?k9YeNG3hKfq64f3i1MgEnjIL3K7jMUh+R0DWaJ6azLwl6Uel4tSm851nKLU0?= =?us-ascii?Q?iIB1JfHnHG9fLDH/iHMl2ImHiopczRDsjkqA4q45XoVtJWfSTEDek81PFXzF?= =?us-ascii?Q?P0043wKMrG6SUIccqemXHmKJGwz0DDYlHT/QJFKcK7HoVv0PiP0U7ikBC0il?= =?us-ascii?Q?/DHIPAYibAF2jGCGseer7Btg/87GYJFqPlsrX1Wd/zb6XvC1qVQamDfiwQPr?= =?us-ascii?Q?n9h8tsoJ8+qRUD3x2AR910fNhenIJ6beew3hmrw4BB9EBwOZdsF3AqozBOsz?= =?us-ascii?Q?8DcqYZ4g0VcSDUa4BbbWxPlKNbmp9ww6ga+yVw1Kx227DupJDRcMHz0gxDcF?= =?us-ascii?Q?CUtyLDA7WaZQRb1wWd6F6kyW42xrnJKeXm0IgDBojhHs7AViTMIAzgVV/86O?= =?us-ascii?Q?/jKzqFWLFcMACk+XXT5qXY/eC8yYK7SYpQEtO1b3EmuJy6RnRxcAGMSXhirN?= =?us-ascii?Q?QTI/7f5eoXgZYK279GbcKqF0vI0uAD4hiuGovnXbdL+wQJC7CGhjoZgT0eyM?= =?us-ascii?Q?84vYlsEQo20M6UCuH4TWCoEujcPRuMQrlzC5iIuO0K2Y7emdKhNeFqUemUSe?= =?us-ascii?Q?fO7tFXq9pYsnPOPxEkzZPT2egBHsD8+AMjcFPGW6TuiTlG2Mr+gfpCGFXajN?= =?us-ascii?Q?gPa24gsqUpxwogIAjrpWJsSlYjxt7kaYaY9oLL7d7UljH3u+F9BLzPN/82Wd?= =?us-ascii?Q?9ulYKb7v5C8Db+k6P/GVOFEtP0aqQ3L4vfXjjOvUBsg2i++Tzk4v/AgUUoIo?= =?us-ascii?Q?gJUw+U3JfzLFbA5Xccog7krrl8+PD/r3Bd9aD2d3CtYEZXN1X3OnxTumdHgO?= =?us-ascii?Q?r9kB7nEAe16MUx0CvsT2B9NzbDI8aMLjujTTJrPiukOXF+R56Ou9xOdtdaPG?= =?us-ascii?Q?JUCnJKiba+2DuBHlvmxSeZKxpmwKIL5PAvsebZCG5a0wbPlYIhbje2hkqmQD?= =?us-ascii?Q?t8C1+sFnAqEhl9WCLNaRVDFEnuIHyWw58KHYIcOscSW78uqw0UhKRh3Nn0xE?= =?us-ascii?Q?isop5K/5TKKX/MNxWAvPNxA8QTkPA44Ukx8UHSB/Xxwk2mZpiqCMx+8bvg4w?= =?us-ascii?Q?X4ZwDHnbWORJPW4zCnHi8GDdEGnTskXifXkNWtRDfoITkyw5AMB1xEWRUwOu?= =?us-ascii?Q?JxQPqFH0rsXMhZ5c/6Qpml7zvcc75L+DbZlIYKlQmljbr5vzofjEZvvMCLwY?= =?us-ascii?Q?3+cnFfl1RCgG88/aJ+ZpUG9hIbLAtOGV0SPVCoONtQ+Mq1CCsiwPCi/t+AK7?= =?us-ascii?Q?deexjmjezTBV7IseTp/wSuu2FKxvaImiaZ8JoK3yGKN5lERh2pQ5eS9Etrmn?= =?us-ascii?Q?76P+PRCvt630cSUt3l41P8K1EWzZj+zyBn5TsbRcBcu01ZhPwIyPznUlMNbA?= =?us-ascii?Q?e+jvY49XfwHFH3GU7t2jwonMuhx9qLjOeLkZa7B4jMU4SPDQq/3pNb27/RS4?= =?us-ascii?Q?guXdyX1QOBCrMj5vep+XBxTFTRUfJ8gyXzPg?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Aug 2025 08:40:37.0349 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e12b351b-6385-44f6-0d15-08dde2e9e614 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000147.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9429 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh The devlink reload fw_activate command performs firmware activation followed by driver reload, while devlink reload driver_reinit triggers only driver reload. However, the driver reload logic differs between the two modes, as on driver_reinit mode mlx5 also reloads auxiliary drivers, while in fw_activate mode the auxiliary drivers are suspended where applicable. Additionally, following the cited commit, if the device has multiple PFs, the behavior during fw_activate may vary between PFs: one PF may suspend auxiliary drivers, while another reloads them. Align devlink dev reload fw_activate behavior with devlink dev reload driver_reinit, to reload all auxiliary drivers. Fixes: 72ed5d5624af ("net/mlx5: Suspend auxiliary devices only in case of P= CI device suspend") Signed-off-by: Moshe Shemesh Reviewed-by: Tariq Toukan Reviewed-by: Akiva Goldberger Signed-off-by: Mark Bloch --- drivers/net/ethernet/mellanox/mlx5/core/devlink.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/devlink.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/devlink.c index 3ffa3fbacd16..26091e7536d3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/devlink.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/devlink.c @@ -160,7 +160,7 @@ static int mlx5_devlink_reload_fw_activate(struct devli= nk *devlink, struct netli if (err) return err; =20 - mlx5_unload_one_devl_locked(dev, true); + mlx5_unload_one_devl_locked(dev, false); err =3D mlx5_health_wait_pci_up(dev); if (err) NL_SET_ERR_MSG_MOD(extack, "FW activate aborted, PCI reads fail after re= set"); --=20 2.34.1 From nobody Fri Oct 3 21:55:31 2025 Received: from NAM10-BN7-obe.outbound.protection.outlook.com (mail-bn7nam10on2082.outbound.protection.outlook.com [40.107.92.82]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7339F25C833; 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Miller" CC: Tariq Toukan , Leon Romanovsky , "Saeed Mahameed" , , , Gal Pressman , Moshe Shemesh , Mark Bloch , Shay Drory Subject: [PATCH net 06/11] net/mlx5: Fix lockdep assertion on sync reset unload event Date: Sun, 24 Aug 2025 11:39:39 +0300 Message-ID: <20250824083944.523858-7-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250824083944.523858-1-mbloch@nvidia.com> References: <20250824083944.523858-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD82:EE_|DM6PR12MB4465:EE_ X-MS-Office365-Filtering-Correlation-Id: c4023243-1c40-4f48-8a23-08dde2e9e5d8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|36860700013|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?NsbFwTE36mpUe+t3VrvGfhvOrWdf3WOE0x4o26snbWrd9K/FlFNrCI2XrXK+?= =?us-ascii?Q?3RLAaAcIOuFyVQntGgbdA5oaylZT5uBOjU1xc2vppy/oT8VYpfY6zhfWfe3R?= =?us-ascii?Q?R0zA6HVOhaS7IO0Kt4+QUs+S+JYb6Msr8XMFu2xn4+D7m/a/VuDzVF51UTzD?= =?us-ascii?Q?xurI4kuUoxkSzKvaFdM5rHLHwxk1nFDyUdOvQU9NVrpRRDHwm2GwU0J1OIZ2?= =?us-ascii?Q?Y6Q2hegiF3VQqKroEnwB4KGOfkXEg304HOpC6SxLvwjq9liX7TOnroaAMOwR?= =?us-ascii?Q?xLn6CRX4NrmHuaQAGbmbQGtUty00/2wkPtnkvBO6cVLK56WZSwZqcVW1o8W/?= =?us-ascii?Q?I1EMsNZrrZVUOkEM6tZD9w+BpJVg+hHi5IgNSg4EUAHngrg5TWyv8RFluyJB?= =?us-ascii?Q?mMh7XTURt080WcfbSADgYzeeN/XZe8ofAmRBjO8CjCfWhk1sYseBbrcAgVf4?= =?us-ascii?Q?3B3pCbf5SVijUQLwyolhw3n9ix8OCGBWIMEe2Yrs2D6yDEMtjs/RSsB2fhFH?= =?us-ascii?Q?YzX0O4Vpa/NEho/gKhyMPDOGkl0uCFBI04UMZTcrM2kbJQakHIzwSOGPuWGI?= =?us-ascii?Q?Mef73SaM/AJ+wFj1tEPrmza3d1qHMAa2YoxRej+gWX9gxP3GoXF4wrqdwpvF?= =?us-ascii?Q?q5H44nOxY+9TLDzwTDjhw97KdEz3hMQQfMjcIsDz6zRylqZUKipvdMLMGAg8?= =?us-ascii?Q?15oHGt3VpZfxLHVxXYe/FFNCmWFa4t2LcEmog/cLPuUXd53Dsvl6ND1+jHCN?= =?us-ascii?Q?spTh1DVaVjROd9BJeIOrptpbPIE3CwNS0T8tIF0MHz7ojIOuzik0uGT9i/Xl?= =?us-ascii?Q?E+tvH/AI8jX+ibLv66HOWckSVjO8LB32sL/s2HAAd5RcCin+naDLV57GxL6o?= =?us-ascii?Q?W2TdA+RcAwoufRiVYBTBwpgAwr39XxNtl26+JNIQtwgnGAAeDNw/HICsJFX4?= =?us-ascii?Q?u41p8/5L7qfrUMhBxF8KyxUdmOTVOWtZeCTn2DFWemP6R9i5V+VvVC4XsECG?= =?us-ascii?Q?+jk7miD7pt/Wjuwr+5Vg3hjr6+5js0sDyqwd4ZFOk0YwLMMBoM1l7Nu4LLES?= =?us-ascii?Q?e2iSdVH+sn07pzZ/b6Y66qNpWCT2/D668MwJkTd9wE8EeqUeJ0aR9ancNjpS?= =?us-ascii?Q?jMYBnlqQg6ICdQL8iXk20B5PdLR1yel+ISNr8WYjp+rPx/4C/BATcox0YOdv?= =?us-ascii?Q?w9+AGk2UxsNRTLG4o3VD9+WnlLbOk0bVpNQLYQboE1RD56oD4rOdvvmAd3gb?= =?us-ascii?Q?e3sFOFkwesQfLSVxW7yz7yihL9j5I/3vDWHoHtYtIs7K0psXCqWuKNogVJ7h?= =?us-ascii?Q?CYrs4xY2K4jAdZBDUPZo5SnX7XFsgNWbgAqprxe9mJm85lXQWOp9yGM8eo04?= =?us-ascii?Q?t6rOgLujRSB4HqC8aETUKRqKx+MBUctrqVQO3o2I1Vc4+dQPjzRoEq67+B5/?= =?us-ascii?Q?2w4ulRaUJmc3znOGt8gPmm1Y1iy/IvFnW3Yw3Z1Rle0i/ub+gF7bVgrU0/PD?= =?us-ascii?Q?N7svvwAmxdgVwXcbsBzDi2AYCmYyPHunLOOY?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(1800799024)(36860700013)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Aug 2025 08:40:36.6496 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c4023243-1c40-4f48-8a23-08dde2e9e5d8 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD82.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4465 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh Fix lockdep assertion triggered during sync reset unload event. When the sync reset flow is initiated using the devlink reload fw_activate option, the PF already holds the devlink lock while handling unload event. In this case, delegate sync reset unload event handling back to the devlink callback process to avoid double-locking and resolve the lockdep warning. Kernel log: WARNING: CPU: 9 PID: 1578 at devl_assert_locked+0x31/0x40 [...] Call Trace: mlx5_unload_one_devl_locked+0x2c/0xc0 [mlx5_core] mlx5_sync_reset_unload_event+0xaf/0x2f0 [mlx5_core] process_one_work+0x222/0x640 worker_thread+0x199/0x350 kthread+0x10b/0x230 ? __pfx_worker_thread+0x10/0x10 ? __pfx_kthread+0x10/0x10 ret_from_fork+0x8e/0x100 ? __pfx_kthread+0x10/0x10 ret_from_fork_asm+0x1a/0x30 Fixes: 7a9770f1bfea ("net/mlx5: Handle sync reset unload event") Signed-off-by: Moshe Shemesh Signed-off-by: Mark Bloch --- .../net/ethernet/mellanox/mlx5/core/devlink.c | 2 +- .../ethernet/mellanox/mlx5/core/fw_reset.c | 120 ++++++++++-------- .../ethernet/mellanox/mlx5/core/fw_reset.h | 1 + 3 files changed, 69 insertions(+), 54 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/devlink.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/devlink.c index 26091e7536d3..2c0e0c16ca90 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/devlink.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/devlink.c @@ -160,7 +160,7 @@ static int mlx5_devlink_reload_fw_activate(struct devli= nk *devlink, struct netli if (err) return err; =20 - mlx5_unload_one_devl_locked(dev, false); + mlx5_sync_reset_unload_flow(dev, true); err =3D mlx5_health_wait_pci_up(dev); if (err) NL_SET_ERR_MSG_MOD(extack, "FW activate aborted, PCI reads fail after re= set"); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c b/drivers/n= et/ethernet/mellanox/mlx5/core/fw_reset.c index 69933addd921..38b9b184ae01 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c @@ -12,7 +12,8 @@ enum { MLX5_FW_RESET_FLAGS_NACK_RESET_REQUEST, MLX5_FW_RESET_FLAGS_PENDING_COMP, MLX5_FW_RESET_FLAGS_DROP_NEW_REQUESTS, - MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED + MLX5_FW_RESET_FLAGS_RELOAD_REQUIRED, + MLX5_FW_RESET_FLAGS_UNLOAD_EVENT, }; =20 struct mlx5_fw_reset { @@ -219,7 +220,7 @@ int mlx5_fw_reset_set_live_patch(struct mlx5_core_dev *= dev) return mlx5_reg_mfrl_set(dev, MLX5_MFRL_REG_RESET_LEVEL0, 0, 0, false); } =20 -static void mlx5_fw_reset_complete_reload(struct mlx5_core_dev *dev, bool = unloaded) +static void mlx5_fw_reset_complete_reload(struct mlx5_core_dev *dev) { struct mlx5_fw_reset *fw_reset =3D dev->priv.fw_reset; struct devlink *devlink =3D priv_to_devlink(dev); @@ -228,8 +229,7 @@ static void mlx5_fw_reset_complete_reload(struct mlx5_c= ore_dev *dev, bool unload if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags)) { complete(&fw_reset->done); } else { - if (!unloaded) - mlx5_unload_one(dev, false); + mlx5_sync_reset_unload_flow(dev, false); if (mlx5_health_wait_pci_up(dev)) mlx5_core_err(dev, "reset reload flow aborted, PCI reads still not work= ing\n"); else @@ -272,7 +272,7 @@ static void mlx5_sync_reset_reload_work(struct work_str= uct *work) =20 mlx5_sync_reset_clear_reset_requested(dev, false); mlx5_enter_error_state(dev, true); - mlx5_fw_reset_complete_reload(dev, false); + mlx5_fw_reset_complete_reload(dev); } =20 #define MLX5_RESET_POLL_INTERVAL (HZ / 10) @@ -586,6 +586,65 @@ static int mlx5_sync_pci_reset(struct mlx5_core_dev *d= ev, u8 reset_method) return err; } =20 +void mlx5_sync_reset_unload_flow(struct mlx5_core_dev *dev, bool locked) +{ + struct mlx5_fw_reset *fw_reset =3D dev->priv.fw_reset; + unsigned long timeout; + int poll_freq =3D 20; + bool reset_action; + u8 rst_state; + int err; + + if (locked) + mlx5_unload_one_devl_locked(dev, false); + else + mlx5_unload_one(dev, false); + + if (!test_bit(MLX5_FW_RESET_FLAGS_UNLOAD_EVENT, &fw_reset->reset_flags)) + return; + + mlx5_set_fw_rst_ack(dev); + mlx5_core_warn(dev, "Sync Reset Unload done, device reset expected\n"); + + reset_action =3D false; + timeout =3D jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, RESET_UNLOAD)); + do { + rst_state =3D mlx5_get_fw_rst_state(dev); + if (rst_state =3D=3D MLX5_FW_RST_STATE_TOGGLE_REQ || + rst_state =3D=3D MLX5_FW_RST_STATE_IDLE) { + reset_action =3D true; + break; + } + if (rst_state =3D=3D MLX5_FW_RST_STATE_DROP_MODE) { + mlx5_core_info(dev, "Sync Reset Drop mode ack\n"); + mlx5_set_fw_rst_ack(dev); + poll_freq =3D 1000; + } + msleep(poll_freq); + } while (!time_after(jiffies, timeout)); + + if (!reset_action) { + mlx5_core_err(dev, "Got timeout waiting for sync reset action, state =3D= %u\n", + rst_state); + fw_reset->ret =3D -ETIMEDOUT; + goto done; + } + + mlx5_core_warn(dev, "Sync Reset, got reset action. rst_state =3D %u\n", + rst_state); + if (rst_state =3D=3D MLX5_FW_RST_STATE_TOGGLE_REQ) { + err =3D mlx5_sync_pci_reset(dev, fw_reset->reset_method); + if (err) { + mlx5_core_warn(dev, "mlx5_sync_pci_reset failed, err %d\n", + err); + fw_reset->ret =3D err; + } + } + +done: + clear_bit(MLX5_FW_RESET_FLAGS_UNLOAD_EVENT, &fw_reset->reset_flags); +} + static void mlx5_sync_reset_now_event(struct work_struct *work) { struct mlx5_fw_reset *fw_reset =3D container_of(work, struct mlx5_fw_rese= t, @@ -613,17 +672,13 @@ static void mlx5_sync_reset_now_event(struct work_str= uct *work) mlx5_enter_error_state(dev, true); done: fw_reset->ret =3D err; - mlx5_fw_reset_complete_reload(dev, false); + mlx5_fw_reset_complete_reload(dev); } =20 static void mlx5_sync_reset_unload_event(struct work_struct *work) { struct mlx5_fw_reset *fw_reset; struct mlx5_core_dev *dev; - unsigned long timeout; - int poll_freq =3D 20; - bool reset_action; - u8 rst_state; int err; =20 fw_reset =3D container_of(work, struct mlx5_fw_reset, reset_unload_work); @@ -632,6 +687,7 @@ static void mlx5_sync_reset_unload_event(struct work_st= ruct *work) if (mlx5_sync_reset_clear_reset_requested(dev, false)) return; =20 + set_bit(MLX5_FW_RESET_FLAGS_UNLOAD_EVENT, &fw_reset->reset_flags); mlx5_core_warn(dev, "Sync Reset Unload. Function is forced down.\n"); =20 err =3D mlx5_cmd_fast_teardown_hca(dev); @@ -640,49 +696,7 @@ static void mlx5_sync_reset_unload_event(struct work_s= truct *work) else mlx5_enter_error_state(dev, true); =20 - if (test_bit(MLX5_FW_RESET_FLAGS_PENDING_COMP, &fw_reset->reset_flags)) - mlx5_unload_one_devl_locked(dev, false); - else - mlx5_unload_one(dev, false); - - mlx5_set_fw_rst_ack(dev); - mlx5_core_warn(dev, "Sync Reset Unload done, device reset expected\n"); - - reset_action =3D false; - timeout =3D jiffies + msecs_to_jiffies(mlx5_tout_ms(dev, RESET_UNLOAD)); - do { - rst_state =3D mlx5_get_fw_rst_state(dev); - if (rst_state =3D=3D MLX5_FW_RST_STATE_TOGGLE_REQ || - rst_state =3D=3D MLX5_FW_RST_STATE_IDLE) { - reset_action =3D true; - break; - } - if (rst_state =3D=3D MLX5_FW_RST_STATE_DROP_MODE) { - mlx5_core_info(dev, "Sync Reset Drop mode ack\n"); - mlx5_set_fw_rst_ack(dev); - poll_freq =3D 1000; - } - msleep(poll_freq); - } while (!time_after(jiffies, timeout)); - - if (!reset_action) { - mlx5_core_err(dev, "Got timeout waiting for sync reset action, state =3D= %u\n", - rst_state); - fw_reset->ret =3D -ETIMEDOUT; - goto done; - } - - mlx5_core_warn(dev, "Sync Reset, got reset action. rst_state =3D %u\n", r= st_state); - if (rst_state =3D=3D MLX5_FW_RST_STATE_TOGGLE_REQ) { - err =3D mlx5_sync_pci_reset(dev, fw_reset->reset_method); - if (err) { - mlx5_core_warn(dev, "mlx5_sync_pci_reset failed, err %d\n", err); - fw_reset->ret =3D err; - } - } - -done: - mlx5_fw_reset_complete_reload(dev, true); + mlx5_fw_reset_complete_reload(dev); } =20 static void mlx5_sync_reset_abort_event(struct work_struct *work) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.h b/drivers/n= et/ethernet/mellanox/mlx5/core/fw_reset.h index ea527d06a85f..d5b28525c960 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.h @@ -12,6 +12,7 @@ int mlx5_fw_reset_set_reset_sync(struct mlx5_core_dev *de= v, u8 reset_type_sel, int mlx5_fw_reset_set_live_patch(struct mlx5_core_dev *dev); =20 int mlx5_fw_reset_wait_reset_done(struct mlx5_core_dev *dev); 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Miller" CC: Tariq Toukan , Leon Romanovsky , "Saeed Mahameed" , , , Gal Pressman , Moshe Shemesh , Parav Pandit , Mark Bloch , Shay Drory Subject: [PATCH net 07/11] net/mlx5: Nack sync reset when SFs are present Date: Sun, 24 Aug 2025 11:39:40 +0300 Message-ID: <20250824083944.523858-8-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250824083944.523858-1-mbloch@nvidia.com> References: <20250824083944.523858-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD82:EE_|MW4PR12MB7000:EE_ X-MS-Office365-Filtering-Correlation-Id: 1ed5d553-55a5-40b8-2dbd-08dde2e9e709 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?MvU36WoTOJ7XVkZQaOyU0vCjk0ZZY1VK80NeWukrN2rnO7CFlRGXJu57Yrux?= =?us-ascii?Q?oKCweKR8ZSPyqK5KVkdw538X8l7GOzZ9cO1dgGpYTPwAIWQw/vyXcFsUBF11?= =?us-ascii?Q?JX1PNhkWlrTV3lPaGlx2OnwkEbGgg1hzrTljf2Dfk+vhAjW0jtY1eTL94gI3?= =?us-ascii?Q?qe65tEw4raP7c83Dh6F6soO8otuXnaVXZu9xmVUbj6xmvl2etEMX98bh/cmg?= =?us-ascii?Q?/vPLzShy7weFH0LMx/VXgTUhHjFh8mXJWwJSli36KWr1nHlm4i0xAZQejCwj?= =?us-ascii?Q?aUsRVuDdA0uddsJcFmZ75sgEhL7WJV9M0/3fvdVF+9OsmhHjmrt01MBXOwS9?= =?us-ascii?Q?FeEkeaSK2DSbnB04KPWiljbA8weYQB/xYr+52fFBZSNqVl7Ru9uG9Z0cxWBk?= =?us-ascii?Q?tpYI+XboFsQy9DebPOOE9KeHRpVhasO0HrXye5cgDypVgnvPdC/POH+fnwBJ?= =?us-ascii?Q?GQ6sB/GPShc1/jadU09y2QSUXJ+LCu4E1OS751Q69/TEEy7kPrxS362DrV6C?= =?us-ascii?Q?6yFbqgBcgQ2awua9AvEscEecQwXAw3HDVrqjeVWEeYmbqiI45cfRyUJu8BeY?= =?us-ascii?Q?k51buQecIo83L0uODMnGxZmH/KS4z9YKNM3XWbQJk9Vim5YsOcgT6aEWoeOB?= =?us-ascii?Q?NTHjqjzvdt4/34Af4lbysyseBoJiKfB7slh7L6GQVNN2FKabPMbQe+YMJr48?= =?us-ascii?Q?5gbWvyO2z+xbZ6CEmcPmq79xTAKP+DXAosW4ui3zy+4xRY4QACuKdhJ20nVh?= =?us-ascii?Q?Ula8396tJ3S+SHqs/APMyIdBGlPyTZ6wNoCeRWENsQ2p6Y/JFdEaoCUlQfJH?= =?us-ascii?Q?KeS5gWcT3MGWzQq4MJ5SmFzwaK0hXbLrzHyNm183onziAsFEc0ZFYHBaSADJ?= =?us-ascii?Q?mTUxl6YJqFrpEPN78RLckqrpbHypx8sfqLzXMRSayYo6xHr4OI439u7vu6kq?= =?us-ascii?Q?zvGURm2bkSP8U4TAu+MxxEi5uJ6jHib9QG/4sE41WIrrTz3rvME9mDUZgvaF?= =?us-ascii?Q?4Pr4Ex/5lOTAhmtYQyXz9BmM7SfFUi169/6YZmK1DcdzRl8NLfBWEof/TU+i?= =?us-ascii?Q?Vv1b7Z8siNT9aMibx+emAspWCPZ7QLBs0UL2SMGI8R/ZDg7I7w1NiQBtqcOR?= =?us-ascii?Q?2hLjemOUCVb+WHxfqnjNbOEiffZ5q440vPH3C+EbPXs1PXuPuzkgvHuOYJTi?= =?us-ascii?Q?JUJnXfxmi3uuvAPzNv8Rx+RFsl6B6uqNC/jRmTap4jykO6jtGujUCenG5Xyo?= =?us-ascii?Q?le1Jf7zaJsEzas5Pf7NRW/DkL0w2daj0fiiX8UX05o9R/qDWqD0X5ApCW3s+?= =?us-ascii?Q?4UV1T6OpLU+5376lH8/YSIM6xK2N4oJZEWqRZDy/gs06uI+y2d+0CgVp5TLI?= =?us-ascii?Q?4KtOO9QQHGptFY9ANlsUXtfKTY354ttvYODYXVzuz2ZVkh4gdZT3MK7YH5wr?= =?us-ascii?Q?kNXgRlL+UimItRBoNhDoyVHVqUyJhB6N/LcIaOSiYiTIW6vr2RIgYSHPlcTD?= =?us-ascii?Q?It3y3F0BPfHN09zWEtXwxjssU8ztZp/OhZNT?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700013)(376014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Aug 2025 08:40:38.6122 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1ed5d553-55a5-40b8-2dbd-08dde2e9e709 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD82.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7000 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh If PF (Physical Function) has SFs (Sub-Functions), since the SFs are not taking part in the synchronization flow, sync reset can lead to fatal error on the SFs, as the function will be closed unexpectedly from the SF point of view. Add a check to prevent sync reset when there are SFs on a PF device which is not ECPF, as ECPF is teardowned gracefully before reset. Fixes: 92501fa6e421 ("net/mlx5: Ack on sync_reset_request only if PF can do= reset_now") Signed-off-by: Moshe Shemesh Reviewed-by: Parav Pandit Reviewed-by: Tariq Toukan Signed-off-by: Mark Bloch --- drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c | 6 ++++++ drivers/net/ethernet/mellanox/mlx5/core/sf/devlink.c | 10 ++++++++++ drivers/net/ethernet/mellanox/mlx5/core/sf/sf.h | 6 ++++++ 3 files changed, 22 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c b/drivers/n= et/ethernet/mellanox/mlx5/core/fw_reset.c index 38b9b184ae01..22995131824a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c @@ -6,6 +6,7 @@ #include "fw_reset.h" #include "diag/fw_tracer.h" #include "lib/tout.h" +#include "sf/sf.h" =20 enum { MLX5_FW_RESET_FLAGS_RESET_REQUESTED, @@ -428,6 +429,11 @@ static bool mlx5_is_reset_now_capable(struct mlx5_core= _dev *dev, return false; } =20 + if (!mlx5_core_is_ecpf(dev) && !mlx5_sf_table_empty(dev)) { + mlx5_core_warn(dev, "SFs should be removed before reset\n"); + return false; + } + #if IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE) if (reset_method !=3D MLX5_MFRL_REG_PCI_RESET_METHOD_HOT_RESET) { err =3D mlx5_check_hotplug_interrupt(dev, bridge); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sf/devlink.c b/drivers= /net/ethernet/mellanox/mlx5/core/sf/devlink.c index 0864ba625c07..3304f25cc805 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/sf/devlink.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/sf/devlink.c @@ -518,3 +518,13 @@ void mlx5_sf_table_cleanup(struct mlx5_core_dev *dev) WARN_ON(!xa_empty(&table->function_ids)); kfree(table); } + +bool mlx5_sf_table_empty(const struct mlx5_core_dev *dev) +{ + struct mlx5_sf_table *table =3D dev->priv.sf_table; + + if (!table) + return true; + + return xa_empty(&table->function_ids); +} diff --git a/drivers/net/ethernet/mellanox/mlx5/core/sf/sf.h b/drivers/net/= ethernet/mellanox/mlx5/core/sf/sf.h index 860f9ddb7107..89559a37997a 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/sf/sf.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/sf/sf.h @@ -17,6 +17,7 @@ void mlx5_sf_hw_table_destroy(struct mlx5_core_dev *dev); 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Miller" CC: Tariq Toukan , Leon Romanovsky , "Saeed Mahameed" , , , Gal Pressman , Moshe Shemesh , Mark Bloch Subject: [PATCH net 08/11] net/mlx5: Prevent flow steering mode changes in switchdev mode Date: Sun, 24 Aug 2025 11:39:41 +0300 Message-ID: <20250824083944.523858-9-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250824083944.523858-1-mbloch@nvidia.com> References: <20250824083944.523858-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7D:EE_|SA5PPFC3F406448:EE_ X-MS-Office365-Filtering-Correlation-Id: c08a82fd-b8f2-4d3a-281b-08dde2e9e9d1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?V4AWfvfevwFs9ASS27a/nUxqKq5PZV23v5FI1JlUlXhodt6PvwIECXa6v6XE?= =?us-ascii?Q?AUc+0d6eg4pgtoEuWmxHokvA5LDiSAFuLW4BjYSvEd1aw4/+A/p5GyW4SRdH?= =?us-ascii?Q?w05MmKF0C70iysVL3arA3EQuZlTzpKUZ95/5Xe2pRmMQDDrc7evlUfG7Df9E?= =?us-ascii?Q?pEXJGN47qKQzanhW7rwVJaklE6qk06nNcwn50m6SFv7EmHKU2yclb5Ns8Yff?= =?us-ascii?Q?YsLrkueHKk4S/ZJRIrv8y2a29n3j69J6ko1Tc4FHDhEWGfzszQboDORS4Ck2?= =?us-ascii?Q?TzdXDE5O780OUvKfsudjCUKYJLzE1xxhZyIEJsGT2eFci3fIpp120i6jzVZl?= =?us-ascii?Q?nbK0Q9rTiKhxRnWv0jQuJOzcUY++SPmMtCMFuheVItzZ8EvewnMSt36JiYRB?= =?us-ascii?Q?nrYElvOvhNjw53qVjarjKp4GGvPJW+IfaLI8kK98Eqtp4SnqDjyk/YkWRDBs?= =?us-ascii?Q?rPhEuhk2TYItQPnCv+GEbVBPcwyZkUgMcLKyOpoS0qbCRDAeKI+ropR+RaG0?= =?us-ascii?Q?dFrz4wFi88FfmDDG/grRcYQ/RhTv7KMqPZYAiMsls65xmEzmmjkIrIE7w3Zk?= =?us-ascii?Q?g/aSam3bjT07frTHXHHSi7kQd2LjTLzAygyKm+uIc0rWhw88bxaiY0kW0L/O?= =?us-ascii?Q?z63pkkAIfAr3xjJWPI+P1r+fNbIIWkeCRTWnaLAoOmzDSYS5BJMMp77IT8i5?= =?us-ascii?Q?DMyYf9Pk4FESepSgHHHGSQNgyr6DzZbAld8qb4eX0kwBnPQ/sJsEDkaB+Wnv?= =?us-ascii?Q?kq/0bFRadShhCYS5TtiaFvV2A7wuH16eTcdswupYx1lLdA5xqTw2ftdy5guK?= =?us-ascii?Q?n9roiAtUAxVzo9fmwiu3UCGItoTJVi2ZQFZCed8xka1oPJkXRIzMXPZCqJHa?= =?us-ascii?Q?sQdBr8YRsrGG00ABO6aXcQMRNVuIOaIuOYquJenMC7YtUsytj/FoM0HCZUrz?= =?us-ascii?Q?PgB2SD5twbnWzlSZVS5mj/4E5j9zyedogMpITr2G56O+O/45KeEpVtNI1VFY?= =?us-ascii?Q?1PTxNmQ7OWQ02lzH2ruiHLkGL0maQpEV4zadsttd/PE9Zg8xQ+3yQ7yLiYTP?= =?us-ascii?Q?iwFSjqIsVo3H4FCJ+0IhcfMj3MK/OngVIWxinvjsV0sma9jnz7C8Ufo/8EFC?= =?us-ascii?Q?ud50XDa7oBf8gJuFeXId74yxzDi7+75WbtiTD/SQwKIJx9SA06m08wR6bmUr?= =?us-ascii?Q?6ihxzYzsbsf8fx5xmtsmwbv1k4agq5ZoOBuvMBNIaSZbdb9oUGC5FuLtEimg?= =?us-ascii?Q?FXhOEX+e2/SyDLau3/7OnZ/Ujx4/OJzl9hN7UNpNJki1KbsfeMs3hX7LCIdQ?= =?us-ascii?Q?pxAAJ/RMt+FUsnQ+Pk9PCmQntZsY8jrCGYDixm9Ja7xCgvMzEKhHrI5laNrT?= =?us-ascii?Q?+mMDExYTmEqHhH3U4cU3sICx+vBGVYGscrS0Hks4mwRLoE9fC0V5JpxKqWt3?= =?us-ascii?Q?ks0RQEP82k2q0Tq/xEVn6Zxh0uMV3nXaOrMPXy4Prvn+zsf0xqWB2h4MHnhS?= =?us-ascii?Q?fK1bUFpGh2UP+IIG1i2oDfj8fA2/nHYSBc0S?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(376014)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Aug 2025 08:40:43.3232 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c08a82fd-b8f2-4d3a-281b-08dde2e9e9d1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7D.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPFC3F406448 Content-Type: text/plain; charset="utf-8" From: Moshe Shemesh Changing flow steering modes is not allowed when eswitch is in switchdev mode. This fix ensures that any steering mode change, including to firmware steering, is correctly blocked while eswitch mode is switchdev. Fixes: e890acd5ff18 ("net/mlx5: Add devlink flow_steering_mode parameter") Signed-off-by: Moshe Shemesh Signed-off-by: Mark Bloch --- drivers/net/ethernet/mellanox/mlx5/core/fs_core.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/fs_core.c index d87392360dbd..cb165085a4c1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/fs_core.c @@ -3734,6 +3734,13 @@ static int mlx5_fs_mode_validate(struct devlink *dev= link, u32 id, char *value =3D val.vstr; u8 eswitch_mode; =20 + eswitch_mode =3D mlx5_eswitch_mode(dev); + if (eswitch_mode =3D=3D MLX5_ESWITCH_OFFLOADS) { + NL_SET_ERR_MSG_FMT_MOD(extack, + "Changing fs mode is not supported when eswitch offloads enable= d."); + return -EOPNOTSUPP; + } + if (!strcmp(value, "dmfs")) return 0; =20 @@ -3759,14 +3766,6 @@ static int mlx5_fs_mode_validate(struct devlink *dev= link, u32 id, return -EINVAL; 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Miller" CC: Tariq Toukan , Leon Romanovsky , "Saeed Mahameed" , , , Gal Pressman , Alexei Lazar , Mark Bloch Subject: [PATCH net 09/11] net/mlx5e: Update and set Xon/Xoff upon MTU set Date: Sun, 24 Aug 2025 11:39:42 +0300 Message-ID: <20250824083944.523858-10-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250824083944.523858-1-mbloch@nvidia.com> References: <20250824083944.523858-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7E:EE_|SA0PR12MB7003:EE_ X-MS-Office365-Filtering-Correlation-Id: e6eeb563-4981-46da-b1ca-08dde2e9eb97 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?kp1+Ep1WDIkGxhx2Amc6BT2d1BVJ+MKrRm3dObACcIW+2nxPwiQVP0h20q07?= =?us-ascii?Q?t+XeGRy2GV5caMcrmUPT7OnIPEzYe3j4CDWCueIxZL2GW3t68f/Zd9o4hDnf?= =?us-ascii?Q?XshGOAZ+wp3EhxGHf6Yu8tJED8YxyYCa7fJF2D00q2gdCzEx6t1AOs12DIGl?= =?us-ascii?Q?q7D0PdNZWqyJTJ0ElZf96utTPEil6hQSUwzvZ4uiDCPK5991cez+j0kvXcq4?= =?us-ascii?Q?kWQNdEogFIX4T2PA/oPZzFvJ0QCVUPySsL1jUWF529bKTI0pElG1kJT/RcXP?= =?us-ascii?Q?j6zfgvie+r2Mc95o7mDiqZXmVwi2q0V5xheLDwlSh3v06V/Nj4rO/rnD9rDI?= =?us-ascii?Q?gkx0qB7Va0vGWvq4f0yh+dhzKx46+xq8pVzv6PQmZ8EDBCTCsTOWR5YzEUac?= =?us-ascii?Q?8gQVAgmJF+kg3g5xlMSgrAgKTfXak2ihS2WEVOm18c1H0jO1FDIV4SjfVzuz?= =?us-ascii?Q?qNt4+i4mfRJ2IFiC8fxotzPYmupkFAWcdV1zm/SR6Pm+F9wFaJlrY0HzY341?= =?us-ascii?Q?0a6ibCL5B8mvzY5aEhSvzydIlTh1W2C/fBlxSrlVGmmKiH6Z0QnER1G/TK6K?= =?us-ascii?Q?Qhr0/U4yrsOuU5Y1BCa9PXvJraknQg2rO6IDtwTCrYd/O95vcRCVH1K9/aWD?= =?us-ascii?Q?2z0TcZU1tlNTA3oYHtpAPnBf5LTcIJy5FerDuRKdNqqmMXc6EnQ0RtqzM/dZ?= =?us-ascii?Q?jXWkVmIJ78lJ0xt6y5J+vm4UdrG45SWmM7mUD6YpkSy3K1+TErCLeJejGMNW?= =?us-ascii?Q?EXC1dTP86r6m7UbOBUVlgqQlMIsmN5iXEjQrMCzkFzVai1Pf2qNE6xjTCjCT?= =?us-ascii?Q?GnSK1sD7eM0c0CZIj8cen+zn2oj6GTPHgugv5IGVunZG3EzmGqZNtcJnbI3+?= =?us-ascii?Q?S54kALuWxqrBLgO60TS2GXSZqvNHzfRbZMHwmL2LcfcMk8dCunStNh5WN1D5?= =?us-ascii?Q?vQWTJcVoMWwoNjs/HW5XNjPLK9lhKQHOHjEz/mMF8MyZ4xzBaNi+1p5fXF1v?= =?us-ascii?Q?wCVscauccGgyK/V9fQ5KGi5VUZDwThRoEkg0qmzAhyk4RDSp9hMYm+QLhGwZ?= =?us-ascii?Q?kiPd5Y7zQxIserFSBqn5DRmTdlvIcNf8u9d3WsUowQtpRCnxt4H3tNGd0zLL?= =?us-ascii?Q?rRTG4xQK60jlGf5LInfzLiQm4Zqgk+eb9H/zCD6WjwmoYlJMJAf1LlTEwZ5D?= =?us-ascii?Q?nxjI/cyXArisZDHmYKN5e2GyXL/Qs0Q+ptX8uPblohW0VX6u4l7Glqg2cN8H?= =?us-ascii?Q?JSS9JjQkk6jYLLkq8HXwFtVJBCL3T8lySiNEa1zWsyUlQekfCQHA1yT/Y4pa?= =?us-ascii?Q?ZQv9ovdi8zuo3a1fjZzkIsnLTizgzD7OFxTWAdM8gbiH9jLWZfqV7eBVjqLP?= =?us-ascii?Q?eIauJQQPgc0R+zwcJjYSMOMaCUKLqKBA0jDo4TAIZ9QPeXpnFL/GCV1iRHbM?= =?us-ascii?Q?ZtuN86WyFfl7tAqgS+/99x9owo727zgBiOSdze2zQ+ovjiVncK77fmvfww/R?= =?us-ascii?Q?DyfAbpLZ2ONI6nuR/N2F2+h/DwrCVFR+Ys95?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(82310400026)(1800799024)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Aug 2025 08:40:46.2683 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e6eeb563-4981-46da-b1ca-08dde2e9eb97 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA0PR12MB7003 Content-Type: text/plain; charset="utf-8" From: Alexei Lazar Xon/Xoff sizes are derived from calculation that include the MTU size. Set Xon/Xoff when MTU is set. If Xon/Xoff fails, set the previous MTU. Fixes: 0696d60853d5 ("net/mlx5e: Receive buffer configuration") Signed-off-by: Alexei Lazar Reviewed-by: Tariq Toukan Signed-off-by: Mark Bloch --- .../mellanox/mlx5/core/en/port_buffer.h | 12 ++++++++++++ .../net/ethernet/mellanox/mlx5/core/en_main.c | 17 ++++++++++++++++- 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/port_buffer.h b/dri= vers/net/ethernet/mellanox/mlx5/core/en/port_buffer.h index f4a19ffbb641..39efa4d98cc3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/port_buffer.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/port_buffer.h @@ -66,11 +66,23 @@ struct mlx5e_port_buffer { struct mlx5e_bufferx_reg buffer[MLX5E_MAX_NETWORK_BUFFER]; }; =20 +#ifdef CONFIG_MLX5_CORE_EN_DCB int mlx5e_port_manual_buffer_config(struct mlx5e_priv *priv, u32 change, unsigned int mtu, struct ieee_pfc *pfc, u32 *buffer_size, u8 *prio2buffer); +#else +static inline int +mlx5e_port_manual_buffer_config(struct mlx5e_priv *priv, + u32 change, unsigned int mtu, + struct ieee_pfc *pfc, + u32 *buffer_size, + u8 *prio2buffer) +{ + return 0; +} +#endif =20 int mlx5e_port_query_buffer(struct mlx5e_priv *priv, struct mlx5e_port_buffer *port_buffer); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 21bb88c5d3dc..15eded36b872 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -49,6 +49,7 @@ #include "en.h" #include "en/dim.h" #include "en/txrx.h" +#include "en/port_buffer.h" #include "en_tc.h" #include "en_rep.h" #include "en_accel/ipsec.h" @@ -3040,9 +3041,11 @@ int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv) struct mlx5e_params *params =3D &priv->channels.params; struct net_device *netdev =3D priv->netdev; struct mlx5_core_dev *mdev =3D priv->mdev; - u16 mtu; + u16 mtu, prev_mtu; int err; =20 + mlx5e_query_mtu(mdev, params, &prev_mtu); + err =3D mlx5e_set_mtu(mdev, params, params->sw_mtu); if (err) return err; @@ -3052,6 +3055,18 @@ int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv) netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n", __func__, mtu, params->sw_mtu); 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Miller" CC: Tariq Toukan , Leon Romanovsky , "Saeed Mahameed" , , , Gal Pressman , Alexei Lazar , Mark Bloch Subject: [PATCH net 10/11] net/mlx5e: Update and set Xon/Xoff upon port speed set Date: Sun, 24 Aug 2025 11:39:43 +0300 Message-ID: <20250824083944.523858-11-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250824083944.523858-1-mbloch@nvidia.com> References: <20250824083944.523858-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000147:EE_|SN7PR12MB7107:EE_ X-MS-Office365-Filtering-Correlation-Id: 3f352d7b-73eb-45f5-550c-08dde2e9ee55 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?v2CZyi7f1NE5ghoV5rhKiXwmpdgQk4yWY0fFiA3H22WsavLfb+fUOIiie69Q?= =?us-ascii?Q?aS+5jL5T4vPalAy6HdeYfuKt7WkL/M2FNyQKIHHlw9UbssM44lR+jofJ2JVO?= =?us-ascii?Q?Oq2OCkV27M8trbJhl/hce2WW+nR4MJjEDwh/U42GdHtydEyq+KUV78dxvexA?= =?us-ascii?Q?KQDXzwQACT6Dm7VHug0qGRCxP24JPWnSCEUHuOgExUBgxlmbonhGQ84xPWfZ?= =?us-ascii?Q?8OILxMpIrZwZHShZ2qSyEmN3L9oiTt45rFgoDqvlYAiWdM0mGMJtPbDwHl1w?= =?us-ascii?Q?l8V0yT4uOQSwm0DhvHUucd8sCpPj1Yz02ZlPwEjemqFdgUHE7GQiaZvBtJhc?= =?us-ascii?Q?2sPkxwxxETmzZilaiKB/MZAanz8xAd7jm4eUHWmOWCEn0vIurJC1g3zvK8wN?= =?us-ascii?Q?WanW6czorwuX3v6jTWSzNUghwRUzWr/VuXaoJfefbsjK3prbRa29bxcrr5xt?= =?us-ascii?Q?es3dKyx6brXRN1Suv34PvMT5MYcx+l1IzkwEQrdUQpKuKhICLn35G9+vr4JA?= =?us-ascii?Q?GzhuEP08KkffzU/fJO2BUJIERUeW2Gcbu/HYEhrFww3ISln1Hf45NKz71kEd?= =?us-ascii?Q?eL3kBkafUQ0oAKBZdyVUGJL+zjzNlSEARxsenHxS66sLWZZ0Qb4QaP6Vp8We?= =?us-ascii?Q?9BIgbq8mDtk/qGAVrGPCXRIv2pFnPjJTl3c+Y6K2x5AoNeUIbSyCMLU//WdM?= =?us-ascii?Q?pS9Ff+Qec2H9VlbYSKv3E5bXD1GnfPMwZTd+gxfLxA1RDndHT1pFuq/MSa73?= =?us-ascii?Q?YFm6zn6JVxAe9WjSYvGfbWTIU3Vfz/d7fxB/FyNFlvn+tObJuh3T2/SjFW/B?= =?us-ascii?Q?PPZTpRgEk14fnrIrbtbzAuwXk8KeIJ1tf6kLVkxd6BgegRxqLDXdGKZ0wRha?= =?us-ascii?Q?8v/3u0b135EqJ8ZDqez6tpmv5pize55eUY3Yqlj8lvSIh1xCE6UhZv4YprSW?= =?us-ascii?Q?aQFtToV0zgrN80+uF5vfskBzSRbutiitbL4htku4dGDl1M9elw9xiDmHgWKi?= =?us-ascii?Q?pLt4zuCajg1vZMs/SL4Jgprnvedbtv4xu6qgStwOZ8en1a2GgO1mBooUGyDJ?= =?us-ascii?Q?dXF+GO7ml6cE+1xBJr3WEoHcAcy8S/v7/+jXRw+bQKqAgxZih4U9jLsBwjGl?= =?us-ascii?Q?J1hAExCq3yr/jsjJf8OXZ30WXKeK3Tc6w9Z7afCBxvrtyXBJYNbhLxSWEiwC?= =?us-ascii?Q?5z2ci6NI8VnREg2BpPobZfKURSOQ43o1I1/4gd8u5GHaHFfGYQCF25n+zn86?= =?us-ascii?Q?kdDpfo8VGiijOJcK69yyjWjMDXr8qZdbO6uHzv5e/EOV3SK8CvaUQTTjf98f?= =?us-ascii?Q?gm1/R+SoI0uicXi+5l+pUD2RHyLgSsG4XjmDCa8b9ZQ0+G0Zpr8h6PQ942/Y?= =?us-ascii?Q?el2Shc/2ISZAFHPsM6YS09AQZc66f4j+n8vKMuwb7JU6Slo0vNUFcByi+LNA?= =?us-ascii?Q?D8gUignfDx9H8E7aQl/xwe6OSiQsW/Oyr3baZx3VJSVSDbSKVfbzwBE2SyxQ?= =?us-ascii?Q?C7VT0Fq7XF8LVZD3zLX4UIpigXmVLpZxnF/P?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Aug 2025 08:40:50.8717 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3f352d7b-73eb-45f5-550c-08dde2e9ee55 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000147.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7107 Content-Type: text/plain; charset="utf-8" From: Alexei Lazar Xon/Xoff sizes are derived from calculations that include the port speed. These settings need to be updated and applied whenever the port speed is changed. The port speed is typically set after the physical link goes down and is negotiated as part of the link-up process between the two connected interfaces. Xon/Xoff parameters being updated at the point where the new negotiated speed is established. Fixes: 0696d60853d5 ("net/mlx5e: Receive buffer configuration") Signed-off-by: Alexei Lazar Reviewed-by: Tariq Toukan Signed-off-by: Mark Bloch --- drivers/net/ethernet/mellanox/mlx5/core/en_main.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/en_main.c index 15eded36b872..e680673ffb72 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_main.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_main.c @@ -139,6 +139,8 @@ void mlx5e_update_carrier(struct mlx5e_priv *priv) if (up) { netdev_info(priv->netdev, "Link up\n"); netif_carrier_on(priv->netdev); + mlx5e_port_manual_buffer_config(priv, 0, priv->netdev->mtu, + NULL, NULL, NULL); } else { netdev_info(priv->netdev, "Link down\n"); netif_carrier_off(priv->netdev); --=20 2.34.1 From nobody Fri Oct 3 21:55:31 2025 Received: from NAM10-MW2-obe.outbound.protection.outlook.com (mail-mw2nam10on2040.outbound.protection.outlook.com [40.107.94.40]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C084525EFB7; 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Miller" CC: Tariq Toukan , Leon Romanovsky , "Saeed Mahameed" , , , Gal Pressman , Alexei Lazar , Dragos Tatulea , Mark Bloch Subject: [PATCH net 11/11] net/mlx5e: Set local Xoff after FW update Date: Sun, 24 Aug 2025 11:39:44 +0300 Message-ID: <20250824083944.523858-12-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250824083944.523858-1-mbloch@nvidia.com> References: <20250824083944.523858-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000144:EE_|CY8PR12MB7315:EE_ X-MS-Office365-Filtering-Correlation-Id: 43242f2c-1504-4896-8231-08dde2e9f0ce X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?e0mppvBkpXVUztTXL4CBtTe1U6xnNPgEJ92RPayBM+7xAB6TqIHh+GWIVbXn?= =?us-ascii?Q?01TZ+MSI07X/echu1TgiBB8x9i8fK7CcsvLZ/8WCJP6ruu5CbTrT36hvA+Qk?= =?us-ascii?Q?53PwysfriKDvKMVZB7Zt47lrqQh4v3ZQn4h30g2py1jEYamefhV44pWSLJ7V?= =?us-ascii?Q?mBi2vbvvnvlcRNe78ax8O9s+lc/f1mEmiBd8XLqPjqMbTQ2rWok7fn5JWP4Y?= =?us-ascii?Q?6rL+rvitUvwAXnnwjs3OE5sJfH1ZJVa8NdrvkkAdUIvdetnTw9BeE5X2ZPdR?= =?us-ascii?Q?3nES8ZhI1ao5eXSbLIUMmMNSu53Q+RVJHK0VJ9DlG6v6BiuffD9Z0tbURQG/?= =?us-ascii?Q?gJHqujxLCbhOpHVYt/y6sXoQxMQ/ffKGAMRYj+KhOWzM02HaNqXmdCJdAmfE?= =?us-ascii?Q?Meqk09ojgHpNIqSUFu0Dnvg7+PnCch98KhZMgdKjcaNoFp/2Z+fJG11tD0LR?= =?us-ascii?Q?UPWD1eOT6bBx5D9YrgRo+nxsOKitNzSue+7J/3xYgdtriAuqQDtsw9IwkWyG?= =?us-ascii?Q?Iw6OeUOVutCebffU8qNxLn5ATpamgVJ8FA7Wu6afVxMes0YrTYYzJInGRHMU?= =?us-ascii?Q?Pc85YVl6Y+WqwQh3kYgR4XSrI3enUxKulQahHLdBHgferX+ejf6adCb1jRBi?= =?us-ascii?Q?Fbza0sOunc9Mo1124JxLADpOLHUDd3UvTvMvfpRmjmpMoYT+gd2DjyEypaBp?= =?us-ascii?Q?kTekmTJNXay6EChfraHEha4/htbBrApEHFIoi0wR6esnnUXewSC3HmAyisCy?= =?us-ascii?Q?5sZ4JcE05CSnGs9tyomaGm2qDYWEBDUg2Pko9IrDqEIF5QCQ1BJ1JHb46AZz?= =?us-ascii?Q?8VBVjyVMxOOOYRFENk5S0EQpjALAAdzhJ+Phbw8jDMe6k3v6LoUxqFiF4I/R?= =?us-ascii?Q?FtyI/75bBAuWMSNuyCm/AVaEwE/BFGjixpUXscLkRW1ITWqSxIJ5mdT4mzsr?= =?us-ascii?Q?6hPTSauZkJnP6s++wkQXpj286or6TFwbiW7lmsIGsfemAvwu+IP4RnQiHTGR?= =?us-ascii?Q?cMNLYMwDSOCuPv7JT00lzAw6H7D5xQXM6uGemBxIytUGqmRQeACkGlDGBWp4?= =?us-ascii?Q?yXsd571cj2ZWLjNfpczLGmQJSQZRkBoP/k2aURWXlNnsEedhUE7cS+2nvBZI?= =?us-ascii?Q?ZxD87GiOA55qZxeKjeimO3GSj8MA9N/brgqB3Ff+rCy11x8BpX58KJjEA45L?= =?us-ascii?Q?F8v2JbeLiUN56fDwuWVazUIT43Dr23WKT8y6xzGCjVl53/A87UPa1rZDpWZx?= =?us-ascii?Q?rMcPF3/JZ2KjpLWkir+CLuaf8cTY9TZH8TbTNcZXfZQjZpa0WmyvrhX0yv/v?= =?us-ascii?Q?fmwWflrGsUxo4U1756m4CKs0k2cPGEg/ZVibC8yDbbLnzuaZLBQd4XFH65Fs?= =?us-ascii?Q?REdNO3eCkQu+XTUohogzMIlNGtpHQz3gOPWsQ5ztvCldjxEGJhtGoTLSJmr+?= =?us-ascii?Q?g8zv55lR0mOvhrkKyzMz1m2I/l/BIDkZqGeggCA0BxQNTNQcCwh0sH9Zf9OI?= =?us-ascii?Q?FMMwrFo868maz+986p1ZsqR6RZtDSOJFyx7C?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700013)(82310400026)(1800799024);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Aug 2025 08:40:55.0245 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 43242f2c-1504-4896-8231-08dde2e9f0ce X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000144.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7315 Content-Type: text/plain; charset="utf-8" From: Alexei Lazar The local Xoff value is being set before the firmware (FW) update. In case of a failure where the FW is not updated with the new value, there is no fallback to the previous value. Update the local Xoff value after the FW has been successfully set. Fixes: 0696d60853d5 ("net/mlx5e: Receive buffer configuration") Signed-off-by: Alexei Lazar Reviewed-by: Tariq Toukan Reviewed-by: Dragos Tatulea Signed-off-by: Mark Bloch --- drivers/net/ethernet/mellanox/mlx5/core/en/port_buffer.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/port_buffer.c b/dri= vers/net/ethernet/mellanox/mlx5/core/en/port_buffer.c index 3efa8bf1d14e..4720523813b9 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/port_buffer.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/port_buffer.c @@ -575,7 +575,6 @@ int mlx5e_port_manual_buffer_config(struct mlx5e_priv *= priv, if (err) return err; } - priv->dcbx.xoff =3D xoff; =20 /* Apply the settings */ if (update_buffer) { @@ -584,6 +583,8 @@ int mlx5e_port_manual_buffer_config(struct mlx5e_priv *= priv, return err; } =20 + priv->dcbx.xoff =3D xoff; + if (update_prio2buffer) err =3D mlx5e_port_set_priority2buffer(priv->mdev, prio2buffer); =20 --=20 2.34.1