From nobody Fri Oct 3 21:42:32 2025 Received: from forward102b.mail.yandex.net (forward102b.mail.yandex.net [178.154.239.149]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97F4F23D7DD; Sun, 24 Aug 2025 20:42:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.154.239.149 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756068156; cv=none; b=J7ytI5wIYV6NnWtbPhZMe+NGop71X95zHHJZ7t01GFWoF7zTAZTohsXi/7ALvcUuNx7GAunBsYmoOBw4jjWMYYab8OdQ1s1Me5RiRb0+vVADDqpAsT9qOt2VIjInczqa+Cx8IkJ6B8DfqGl2nPR42WWPAkvdj2d+KcZRlww90Ws= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756068156; c=relaxed/simple; bh=2rG/G9NBxbqTu6CuJVAkY8SKvl3EGxAO04K3tqLr340=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TQUBHee0Gv0h6oB5M2qgUowG10mzdB1NQoAQaETr1gj1/dugrZgBThkbuTnjtiFgwdJbdZsK7B8Ni1Rz56pbwt/ZSsOcPpPo4pwGqtMmjAddEosKh/kQLZ4eehvJpHWQRa2qZb/JOToPcC/tOjcKmeVO0xvTEw308mb7gYoDsMw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=yandex.ru; spf=pass smtp.mailfrom=yandex.ru; dkim=pass (1024-bit key) header.d=yandex.ru header.i=@yandex.ru header.b=U5jcIcbA; arc=none smtp.client-ip=178.154.239.149 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=yandex.ru Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=yandex.ru Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=yandex.ru header.i=@yandex.ru header.b="U5jcIcbA" Received: from mail-nwsmtp-smtp-production-main-73.sas.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-73.sas.yp-c.yandex.net [IPv6:2a02:6b8:c37:7521:0:640:a008:0]) by forward102b.mail.yandex.net (Yandex) with ESMTPS id 5D404C0006; Sun, 24 Aug 2025 23:42:26 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-73.sas.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id MgdcKKcLCa60-bf40ep3f; Sun, 24 Aug 2025 23:42:26 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=yandex.ru; s=mail; t=1756068146; bh=T7mI96+5ebnUKGoLkkPBcQK3Tj7pFqnEqbDek2swFQA=; h=Cc:In-Reply-To:Message-Id:To:Date:References:From:Subject; b=U5jcIcbAnBwiPUQOENbvgmrFjedx8iZBK4VJkaBKb/YhOLjdW3+zHvuDDdU7eLyu4 E+1YPVcZEfcVk+NyBVoLjymyMw0wbXViZkpIw4M3PQ1wsO8FlPev37woe4YYxKa6eN gduiu2X2ptA8K4vz/PLvypZm7+1pjWVcODAgcOa4= Authentication-Results: mail-nwsmtp-smtp-production-main-73.sas.yp-c.yandex.net; dkim=pass header.i=@yandex.ru From: Nickolay Goppen Date: Sun, 24 Aug 2025 23:42:25 +0300 Subject: [PATCH 3/3] pinctrl: qcom: Add SDM660 LPASS LPI TLMM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250824-sdm660-lpass-lpi-v1-3-003d5cc28234@yandex.ru> References: <20250824-sdm660-lpass-lpi-v1-0-003d5cc28234@yandex.ru> In-Reply-To: <20250824-sdm660-lpass-lpi-v1-0-003d5cc28234@yandex.ru> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Nickolay Goppen , Richard Acayan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756068142; l=8797; i=setotau@yandex.ru; s=20250815; h=from:subject:message-id; bh=yyEQydoIE+MJbMTGAvlVS0a75IXP1UAi2TgmCLS314Q=; b=AsyhebLKXBpyIjE6gAjEbut4/bSkvN7vpr4LWsN8R0LDxPoexqgm9gkSmkEi+4xHFZ52M47e/ IkGrjjSywe+CQPHP549cNFggQSZ9VHkM6+ISGjs1bR4BvpqzwfYefPp X-Developer-Key: i=setotau@yandex.ru; a=ed25519; pk=Og7YO6LfW+M2QfcJfjaUaXc8oOr5zoK8+4AtX5ICr4o= From: Richard Acayan The Snapdragon 660 has a Low-Power Island (LPI) TLMM for configuring pins related to audio. Add the driver for this. Also, this driver uses it's own quirky pin_offset function like downstream driver does [1]. [1] https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/LA.UM.7.2.c27-0= 7400-sdm660.0/drivers/pinctrl/qcom/pinctrl-lpi.c#L107 Co-developed-by: Nickolay Goppen Signed-off-by: Nickolay Goppen Signed-off-by: Richard Acayan --- drivers/pinctrl/qcom/Kconfig | 10 ++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c | 196 ++++++++++++++++++++= ++++ 3 files changed, 207 insertions(+) diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index dd9bbe8f3e11c37418d2143b33c21eeea10d456b..ef42520115f461302098d878cb7= 6c6f25e55b5e4 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -68,6 +68,16 @@ config PINCTRL_SC7280_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SC7280 platfo= rm. =20 +config PINCTRL_SDM660_LPASS_LPI + tristate "Qualcomm Technologies Inc SDM660 LPASS LPI pin controller drive= r" + depends on GPIOLIB + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SDM660 platfo= rm. + config PINCTRL_SM4250_LPASS_LPI tristate "Qualcomm Technologies Inc SM4250 LPASS LPI pin controller drive= r" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 954f5291cc37242baffc021e3c68d850aabd57cd..cea8617ac650ecfc75c2a0c745a= 53d6a1b829842 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_PINCTRL_SC7280_LPASS_LPI) +=3D pinctrl-sc728= 0-lpass-lpi.o obj-$(CONFIG_PINCTRL_SC8180X) +=3D pinctrl-sc8180x.o obj-$(CONFIG_PINCTRL_SC8280XP) +=3D pinctrl-sc8280xp.o obj-$(CONFIG_PINCTRL_SDM660) +=3D pinctrl-sdm660.o +obj-$(CONFIG_PINCTRL_SDM660_LPASS_LPI) +=3D pinctrl-sdm660-lpass-lpi.o obj-$(CONFIG_PINCTRL_SDM670) +=3D pinctrl-sdm670.o obj-$(CONFIG_PINCTRL_SDM845) +=3D pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SDX55) +=3D pinctrl-sdx55.o diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sdm660-lpass-lpi.c new file mode 100644 index 0000000000000000000000000000000000000000..788e1c019b0b7a22360d8c32180= b5abf4d0fc0dc --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * This driver is solely based on the limited information in downstream co= de. + * Any verification with schematics would be greatly appreciated. + * + * Copyright (c) 2023, Richard Acayan. All rights reserved. + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_comp_rx, + LPI_MUX_dmic12, + LPI_MUX_dmic34, + LPI_MUX_mclk0, + LPI_MUX_pdm_2_gpios, + LPI_MUX_pdm_clk, + LPI_MUX_pdm_rx, + LPI_MUX_pdm_sync, + + LPI_MUX_gpio, + LPI_MUX__, +}; + +static const u32 sdm660_lpi_offset[] =3D { + 0x00000000, + 0x00001000, + 0x00002000, + 0x00002010, + 0x00003000, + 0x00003010, + 0x00004000, + 0x00004010, + 0x00005000, + 0x00005010, + 0x00005020, + 0x00005030, + 0x00006000, + 0x00006010, + 0x00007000, + 0x00007010, + 0x00005040, + 0x00005050, + 0x00008000, + 0x00008010, + 0x00008020, + 0x00008030, + 0x00008040, + 0x00008050, + 0x00008060, + 0x00008070, + 0x00009000, + 0x00009010, + 0x0000A000, + 0x0000A010, + 0x0000B000, + 0x0000B010, +}; + +static const struct pinctrl_pin_desc sdm660_lpi_pinctrl_pins[] =3D { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), + PINCTRL_PIN(19, "gpio19"), + PINCTRL_PIN(20, "gpio20"), + PINCTRL_PIN(21, "gpio21"), + PINCTRL_PIN(22, "gpio22"), + PINCTRL_PIN(23, "gpio23"), + PINCTRL_PIN(24, "gpio24"), + PINCTRL_PIN(25, "gpio25"), + PINCTRL_PIN(26, "gpio26"), + PINCTRL_PIN(27, "gpio27"), + PINCTRL_PIN(28, "gpio28"), + PINCTRL_PIN(29, "gpio29"), + PINCTRL_PIN(30, "gpio30"), + PINCTRL_PIN(31, "gpio31"), +}; + +static const char * const comp_rx_groups[] =3D { "gpio22", "gpio24" }; +static const char * const dmic12_groups[] =3D { "gpio26", "gpio28" }; +static const char * const dmic34_groups[] =3D { "gpio27", "gpio29" }; +static const char * const mclk0_groups[] =3D { "gpio18" }; +static const char * const pdm_2_gpios_groups[] =3D { "gpio20" }; +static const char * const pdm_clk_groups[] =3D { "gpio18" }; +static const char * const pdm_rx_groups[] =3D { "gpio21", "gpio23", "gpio2= 5" }; +static const char * const pdm_sync_groups[] =3D { "gpio19" }; + +const struct lpi_pingroup sdm660_lpi_pinctrl_groups[] =3D { + LPI_PINGROUP(0, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(1, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(2, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(3, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(4, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(5, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(6, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(10, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(11, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(14, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(15, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(16, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(17, LPI_NO_SLEW, _, _, _, _), + + /* The function names of the PDM GPIOs are derived from SDM670 */ + LPI_PINGROUP(18, LPI_NO_SLEW, pdm_clk, mclk0, _, _), + LPI_PINGROUP(19, LPI_NO_SLEW, pdm_sync, _, _, _), + LPI_PINGROUP(20, LPI_NO_SLEW, pdm_2_gpios, _, _, _), + LPI_PINGROUP(21, LPI_NO_SLEW, pdm_rx, _, _, _), + LPI_PINGROUP(22, LPI_NO_SLEW, comp_rx, _, _, _), + LPI_PINGROUP(23, LPI_NO_SLEW, pdm_rx, _, _, _), + LPI_PINGROUP(24, LPI_NO_SLEW, comp_rx, _, _, _), + LPI_PINGROUP(25, LPI_NO_SLEW, pdm_rx, _, _, _), + LPI_PINGROUP(26, LPI_NO_SLEW, dmic12, _, _, _), + LPI_PINGROUP(27, LPI_NO_SLEW, dmic34, _, _, _), + LPI_PINGROUP(28, LPI_NO_SLEW, dmic12, _, _, _), + LPI_PINGROUP(29, LPI_NO_SLEW, dmic34, _, _, _), + + LPI_PINGROUP(30, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(31, LPI_NO_SLEW, _, _, _, _), +}; + +const struct lpi_function sdm660_lpi_pinctrl_functions[] =3D { + LPI_FUNCTION(comp_rx), + LPI_FUNCTION(dmic12), + LPI_FUNCTION(dmic34), + LPI_FUNCTION(mclk0), + LPI_FUNCTION(pdm_2_gpios), + LPI_FUNCTION(pdm_clk), + LPI_FUNCTION(pdm_rx), + LPI_FUNCTION(pdm_sync), +}; + +static u32 pin_offset_sdm660(int pin_id) +{ + return sdm660_lpi_offset[pin_id]; +} + +static const struct lpi_pinctrl_variant_data sdm660_lpi_pinctrl_data =3D { + .pins =3D sdm660_lpi_pinctrl_pins, + .npins =3D ARRAY_SIZE(sdm660_lpi_pinctrl_pins), + .groups =3D sdm660_lpi_pinctrl_groups, + .ngroups =3D ARRAY_SIZE(sdm660_lpi_pinctrl_groups), + .functions =3D sdm660_lpi_pinctrl_functions, + .nfunctions =3D ARRAY_SIZE(sdm660_lpi_pinctrl_functions), + .flags =3D LPI_FLAG_SLEW_RATE_SAME_REG, + .pin_offset =3D pin_offset_sdm660, +}; + +static const struct of_device_id sdm660_lpi_pinctrl_of_match[] =3D { + { + .compatible =3D "qcom,sdm660-lpass-lpi-pinctrl", + .data =3D &sdm660_lpi_pinctrl_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, sdm660_lpi_pinctrl_of_match); + +static struct platform_driver sdm660_lpi_pinctrl_driver =3D { + .driver =3D { + .name =3D "qcom-sdm660-lpass-lpi-pinctrl", + .of_match_table =3D sdm660_lpi_pinctrl_of_match, + }, + .probe =3D lpi_pinctrl_probe, + .remove =3D lpi_pinctrl_remove, +}; +module_platform_driver(sdm660_lpi_pinctrl_driver); + +MODULE_AUTHOR("Richard Acayan "); +MODULE_DESCRIPTION("QTI SDM660 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); --=20 2.51.0