From nobody Fri Oct 3 21:04:30 2025 Received: from forward102b.mail.yandex.net (forward102b.mail.yandex.net [178.154.239.149]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 550A3134CF; Sun, 24 Aug 2025 20:42:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.154.239.149 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756068156; cv=none; b=DCjIq8QWvw/Om+E2Qm14pbK/A5ElDfNdSaqitl0aD6521TNWMg0N+bojdU5tma/ZiSAbBFWWCDXb/8V6MuZKTd6N2wTJ6HWpXQOAxfJ8nCd1K5+EnWJui1KvtI8Fd286l/Ll1r/JVrBlNdXxNwNK7Vg4JMoOrWszgZcj+70Hap0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756068156; c=relaxed/simple; bh=hzvm5B4s4jHkIJ54rtQ+EQO71zBfGIsLhAluQCNnkIs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=alIgq3GDadhrk+kOw3UbsxcNGSPS32Xk3zNpPfNiLo+r7OpfYv2kNPRDjdESM24Ahu5DWvT4r9PYjc98OXj+C2lyaDo3OjsoN7GSAEr7v84dYF4xrIgIwLaBH+sIunQPpTzNK901zL9nVWU5oWeEFpdBeHloKXYR+Cbq1FXWbdw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=yandex.ru; spf=pass smtp.mailfrom=yandex.ru; dkim=pass (1024-bit key) header.d=yandex.ru header.i=@yandex.ru header.b=w9FZTfL1; arc=none smtp.client-ip=178.154.239.149 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=yandex.ru Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=yandex.ru Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=yandex.ru header.i=@yandex.ru header.b="w9FZTfL1" Received: from mail-nwsmtp-smtp-production-main-73.sas.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-73.sas.yp-c.yandex.net [IPv6:2a02:6b8:c37:7521:0:640:a008:0]) by forward102b.mail.yandex.net (Yandex) with ESMTPS id 226DFC0012; Sun, 24 Aug 2025 23:42:25 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-73.sas.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id MgdcKKcLCa60-YVU03z1O; Sun, 24 Aug 2025 23:42:24 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=yandex.ru; s=mail; t=1756068144; bh=hKrMSxmIeX1FivJjeZqMU0TBEaGJvNIqVAB+Qbz11bQ=; h=Cc:In-Reply-To:Message-Id:To:Date:References:From:Subject; b=w9FZTfL1vl/dydoETXp8e9DomnV8olwEwQ/0zyT6jP+NQzjMxNe6gGkb5nbPk+w4E Og3VWuXx/FDCvfflVbmHkIsWTJsVHsIKIuAtId0uwLLLkBRERZJLr7wV8Jy+JoA3Fh aZgOU0fK+QCPdoV7ZL7SmAc3Af5bqUoqViUCOlWM= Authentication-Results: mail-nwsmtp-smtp-production-main-73.sas.yp-c.yandex.net; dkim=pass header.i=@yandex.ru From: Nickolay Goppen Date: Sun, 24 Aug 2025 23:42:23 +0300 Subject: [PATCH 1/3] pinctrl: qcom: lpass-lpi: Introduce pin_offset callback Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250824-sdm660-lpass-lpi-v1-1-003d5cc28234@yandex.ru> References: <20250824-sdm660-lpass-lpi-v1-0-003d5cc28234@yandex.ru> In-Reply-To: <20250824-sdm660-lpass-lpi-v1-0-003d5cc28234@yandex.ru> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Nickolay Goppen X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756068142; l=8823; i=setotau@yandex.ru; s=20250815; h=from:subject:message-id; bh=hzvm5B4s4jHkIJ54rtQ+EQO71zBfGIsLhAluQCNnkIs=; b=+NDDXHwB5WX2cy6qWQpud0v4IZg7yUvO2di5Xcjpt7ax/TG5mF4AJdWDqR0M0kQdsJt3yQQYn rEqFoZCou5qDjYko+XsYXQoOC9rtlo8PqpnSlRMk4cUNyt2Ia8heHVU X-Developer-Key: i=setotau@yandex.ru; a=ed25519; pk=Og7YO6LfW+M2QfcJfjaUaXc8oOr5zoK8+4AtX5ICr4o= By default pin_offset is calculated by formula: LPI_TLMM_REG_OFFSET * pin_id. However not all platforms are using this pin_offset formula (e.g. SDM660 LPASS LPI uses a predefined array of offsets [1]), so add a callback to the default pin_offset function to add an ability for some platforms to use their own quirky pin_offset functions and add callbacks to pin_offset_default function for other platforms. [1] https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/LA.UM.7.2.c27-0= 7400-sdm660.0/drivers/pinctrl/qcom/pinctrl-lpi.c#L107 Signed-off-by: Nickolay Goppen --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 13 +++++++++++-- drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 2 ++ drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c | 1 + drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c | 1 + drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c | 1 + drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c | 1 + drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c | 1 + drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c | 1 + drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c | 1 + drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c | 1 + drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c | 1 + 11 files changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qco= m/pinctrl-lpass-lpi.c index 57fefeb603f0e2502fccd14ba3982ae3cb591978..8ba0ebf12d8113cdc501e9fe973= 11ec0764fbef5 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -38,16 +38,25 @@ struct lpi_pinctrl { const struct lpi_pinctrl_variant_data *data; }; =20 +u32 pin_offset_default(int pin_id) +{ + return LPI_TLMM_REG_OFFSET * pin_id; +} + static int lpi_gpio_read(struct lpi_pinctrl *state, unsigned int pin, unsigned int addr) { - return ioread32(state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); + const u32 pin_offset =3D state->data->pin_offset(pin); + + return ioread32(state->tlmm_base + pin_offset + addr); } =20 static int lpi_gpio_write(struct lpi_pinctrl *state, unsigned int pin, unsigned int addr, unsigned int val) { - iowrite32(val, state->tlmm_base + LPI_TLMM_REG_OFFSET * pin + addr); + const u32 pin_offset =3D state->data->pin_offset(pin); + + iowrite32(val, state->tlmm_base + pin_offset + addr); =20 return 0; } diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qco= m/pinctrl-lpass-lpi.h index a9b2f65c1ebe0f8fb5d7814f8ef8b723c617c85b..3a2969ac85410e9fb796ec792d1= 349822257b3a0 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h @@ -85,9 +85,11 @@ struct lpi_pinctrl_variant_data { const struct lpi_function *functions; int nfunctions; unsigned int flags; + u32 (*pin_offset)(int pin_id); }; =20 int lpi_pinctrl_probe(struct platform_device *pdev); void lpi_pinctrl_remove(struct platform_device *pdev); +u32 pin_offset_default(int pin_id); =20 #endif /*__PINCTRL_LPASS_LPI_H__*/ diff --git a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sc7280-lpass-lpi.c index 1161f0a91a002aaa9b1ba2f9ca13e94b2f145ec8..ed0c57fb1ed4770cce4afe7b1f3= ec51aa3d44cf3 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sc7280-lpass-lpi.c @@ -125,6 +125,7 @@ static const struct lpi_pinctrl_variant_data sc7280_lpi= _data =3D { .ngroups =3D ARRAY_SIZE(sc7280_groups), .functions =3D sc7280_functions, .nfunctions =3D ARRAY_SIZE(sc7280_functions), + .pin_offset =3D pin_offset_default, }; =20 static const struct of_device_id lpi_pinctrl_of_match[] =3D { diff --git a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c b/drivers/pi= nctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c index 0e839b6aaaf4bd88f078cf36091faa9c2c885518..40834242a7699352c63ad2ddc82= ca3663a39275f 100644 --- a/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sc8280xp-lpass-lpi.c @@ -162,6 +162,7 @@ static const struct lpi_pinctrl_variant_data sc8280xp_l= pi_data =3D { .ngroups =3D ARRAY_SIZE(sc8280xp_groups), .functions =3D sc8280xp_functions, .nfunctions =3D ARRAY_SIZE(sc8280xp_functions), + .pin_offset =3D pin_offset_default, }; =20 static const struct of_device_id lpi_pinctrl_of_match[] =3D { diff --git a/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm4250-lpass-lpi.c index c0e178be9cfc3ea8578a39d8998033058f40dabf..69074c80744663268fc034019ca= 5523a18ce7f22 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm4250-lpass-lpi.c @@ -213,6 +213,7 @@ static const struct lpi_pinctrl_variant_data sm4250_lpi= _data =3D { .ngroups =3D ARRAY_SIZE(sm4250_groups), .functions =3D sm4250_functions, .nfunctions =3D ARRAY_SIZE(sm4250_functions), + .pin_offset =3D pin_offset_default, }; =20 static const struct of_device_id lpi_pinctrl_of_match[] =3D { diff --git a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm6115-lpass-lpi.c index b7d9186861a2ffa9f3c00a660bde00858fff9462..651e52f4c886821ebb8207af378= 3da87758f1a30 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm6115-lpass-lpi.c @@ -133,6 +133,7 @@ static const struct lpi_pinctrl_variant_data sm6115_lpi= _data =3D { .ngroups =3D ARRAY_SIZE(sm6115_groups), .functions =3D sm6115_functions, .nfunctions =3D ARRAY_SIZE(sm6115_functions), + .pin_offset =3D pin_offset_default, }; =20 static const struct of_device_id lpi_pinctrl_of_match[] =3D { diff --git a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm8250-lpass-lpi.c index 64494a86490e2f5d3e00184622f68097bbcdfff0..a693df05c4fdb40750f449a5881= 7e2371e564dea 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8250-lpass-lpi.c @@ -123,6 +123,7 @@ static const struct lpi_pinctrl_variant_data sm8250_lpi= _data =3D { .ngroups =3D ARRAY_SIZE(sm8250_groups), .functions =3D sm8250_functions, .nfunctions =3D ARRAY_SIZE(sm8250_functions), + .pin_offset =3D pin_offset_default, }; =20 static const struct of_device_id lpi_pinctrl_of_match[] =3D { diff --git a/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm8350-lpass-lpi.c index 7b146b4acfdf42e7dd69f1f022c0041b3e45b174..15d453482d68b8b9ae2d572f753= 8e05f83425a12 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8350-lpass-lpi.c @@ -125,6 +125,7 @@ static const struct lpi_pinctrl_variant_data sm8350_lpi= _data =3D { .ngroups =3D ARRAY_SIZE(sm8350_groups), .functions =3D sm8350_functions, .nfunctions =3D ARRAY_SIZE(sm8350_functions), + .pin_offset =3D pin_offset_default, }; =20 static const struct of_device_id lpi_pinctrl_of_match[] =3D { diff --git a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm8450-lpass-lpi.c index 439f6541622e924a2a77db7a8b15ccb709e7a53d..629a110963d610fe7b9667ea1ab= ab66338711bf1 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8450-lpass-lpi.c @@ -191,6 +191,7 @@ static const struct lpi_pinctrl_variant_data sm8450_lpi= _data =3D { .ngroups =3D ARRAY_SIZE(sm8450_groups), .functions =3D sm8450_functions, .nfunctions =3D ARRAY_SIZE(sm8450_functions), + .pin_offset =3D pin_offset_default, }; =20 static const struct of_device_id lpi_pinctrl_of_match[] =3D { diff --git a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm8550-lpass-lpi.c index 73065919c8c2654670b07372bd2dd5839baf2979..1ebc93a61e965f8c0d293485869= 05cb0e38ae074 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8550-lpass-lpi.c @@ -199,6 +199,7 @@ static const struct lpi_pinctrl_variant_data sm8550_lpi= _data =3D { .ngroups =3D ARRAY_SIZE(sm8550_groups), .functions =3D sm8550_functions, .nfunctions =3D ARRAY_SIZE(sm8550_functions), + .pin_offset =3D pin_offset_default, }; =20 static const struct of_device_id lpi_pinctrl_of_match[] =3D { diff --git a/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sm8650-lpass-lpi.c index f9fcedf5a65d7115e605c54229ba0096b9081636..a6dfeef0f6fa0860f44808a4bb8= e5db57d10d116 100644 --- a/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-sm8650-lpass-lpi.c @@ -206,6 +206,7 @@ static const struct lpi_pinctrl_variant_data sm8650_lpi= _data =3D { .functions =3D sm8650_functions, .nfunctions =3D ARRAY_SIZE(sm8650_functions), .flags =3D LPI_FLAG_SLEW_RATE_SAME_REG, + .pin_offset =3D pin_offset_default, }; =20 static const struct of_device_id lpi_pinctrl_of_match[] =3D { --=20 2.51.0 From nobody Fri Oct 3 21:04:30 2025 Received: from forward204b.mail.yandex.net (forward204b.mail.yandex.net [178.154.239.153]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A84CC1F95C; Sun, 24 Aug 2025 20:50:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.154.239.153 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756068604; cv=none; b=s61wrooIr9Lb8SYsVcIzIzDhinHWGU91UIdj5p6mMvtlPHi5tbUDbIZpc/qRGGeNTuMnoLpFjZGLf3dbta/L+aV2GOSFx2n8MCL4M8z9blylQvKkR7hFlbukiitLXfx64ZTU5BCk9fq3HyTJUJflMKEAVoXle8sZ1dGipilp2hk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756068604; c=relaxed/simple; bh=lw+wkCHuwJi81P9r9kd3s9iM9l26tF2/jGo2tCXg0SE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=WbJ1CBfLXVvUffkmw/KaCWWQljuf9pVnm09f17tX68kepkAiak5sGYEpDnE14qepBtsOy+5RkcZTpoXEnUFF2RMoMrayh/4mHHO3ls88I/R2zSr/kvcdeQCHFmtyLnX3MyZxveMzCzSpkhYj79MnayM42pHhIFGLfKZNhhRmf94= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=yandex.ru; spf=pass smtp.mailfrom=yandex.ru; dkim=pass (1024-bit key) header.d=yandex.ru header.i=@yandex.ru header.b=pZyGAFlH; arc=none smtp.client-ip=178.154.239.153 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=yandex.ru Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=yandex.ru Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=yandex.ru header.i=@yandex.ru header.b="pZyGAFlH" Received: from forward100b.mail.yandex.net (forward100b.mail.yandex.net [IPv6:2a02:6b8:c02:900:1:45:d181:d100]) by forward204b.mail.yandex.net (Yandex) with ESMTPS id 50CB482B50; Sun, 24 Aug 2025 23:42:35 +0300 (MSK) Received: from mail-nwsmtp-smtp-production-main-73.sas.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-73.sas.yp-c.yandex.net [IPv6:2a02:6b8:c37:7521:0:640:a008:0]) by forward100b.mail.yandex.net (Yandex) with ESMTPS id CD97080618; Sun, 24 Aug 2025 23:42:25 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-73.sas.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id MgdcKKcLCa60-Ig04LBeh; Sun, 24 Aug 2025 23:42:25 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=yandex.ru; s=mail; t=1756068145; bh=vJiDsVwE5O5ovqLkchcKAZLTA0N7DfACsKJu+Tw8KmU=; h=Cc:In-Reply-To:Message-Id:To:Date:References:From:Subject; b=pZyGAFlHlMfTbXq7+479HHUWmahlPoPx7QT1p3JLtOtSa2vNiqyGLa5vzLJtEExf2 2AlqWeRxAyc0LkLTGaIf10m9HKEDkryBca4K+V9PKgC1T8VQsMlpnUR8aww46FFj4W zRyw3MNDLDsSqUsaDRZ1fJXOw0gREDQT2OUMz7x0= Authentication-Results: mail-nwsmtp-smtp-production-main-73.sas.yp-c.yandex.net; dkim=pass header.i=@yandex.ru From: Nickolay Goppen Date: Sun, 24 Aug 2025 23:42:24 +0300 Subject: [PATCH 2/3] dt-bindings: pinctrl: qcom: Add SDM660 LPI pinctrl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250824-sdm660-lpass-lpi-v1-2-003d5cc28234@yandex.ru> References: <20250824-sdm660-lpass-lpi-v1-0-003d5cc28234@yandex.ru> In-Reply-To: <20250824-sdm660-lpass-lpi-v1-0-003d5cc28234@yandex.ru> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Nickolay Goppen , Richard Acayan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756068142; l=2866; i=setotau@yandex.ru; s=20250815; h=from:subject:message-id; bh=lw+wkCHuwJi81P9r9kd3s9iM9l26tF2/jGo2tCXg0SE=; b=F7pibNqUfOJePDY6F5m7GczkuEvLs0+A1Xs1LrpODEcu/2APuimP5R1tjqIkIA+HQK/LS7G9N 6SggJcLH1biBs0+h7bhqeL2o66ST5QLia7QuAkDesnn2CdF1d3BRizX X-Developer-Key: i=setotau@yandex.ru; a=ed25519; pk=Og7YO6LfW+M2QfcJfjaUaXc8oOr5zoK8+4AtX5ICr4o= Add bindings for pin controller in SDM660 Low Power Audio SubSystem (LPASS). Co-developed-by: Richard Acayan Signed-off-by: Richard Acayan Signed-off-by: Nickolay Goppen --- .../pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml | 74 ++++++++++++++++++= ++++ 1 file changed, 74 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpass-lp= i-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpas= s-lpi-pinctrl.yaml new file mode 100644 index 0000000000000000000000000000000000000000..6b930a5b914bc79a00dbaead411= 89efc525c2eb2 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpass-lpi-pinct= rl.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.y= aml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM660 SoC LPASS LPI TLMM + +maintainers: + - Nickolay Goppen + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSyst= em + (LPASS) Low Power Island (LPI) of Qualcomm SDM660 SoC. + +properties: + compatible: + const: qcom,sdm660-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sdm660-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sdm660-lpass-state" + additionalProperties: false + +$defs: + qcom-sdm660-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configura= tion. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-9]|2[0-6])$" + + function: + enum: [ gpio, comp_rx, dmic12, dmic34, mclk0, pdm_2_gpios, + pdm_clk, pdm_rx, pdm_sync ] + description: + Specify the alternative function to be configured for the specif= ied + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + lpi_tlmm: pinctrl@15070000 { + compatible =3D "qcom,sdm660-lpass-lpi-pinctrl"; + reg =3D <0x15070000 0x20000>; + gpio-controller; + #gpio-cells =3D <2>; + gpio-ranges =3D <&lpi_tlmm 0 0 32>; + }; --=20 2.51.0 From nobody Fri Oct 3 21:04:30 2025 Received: from forward102b.mail.yandex.net (forward102b.mail.yandex.net [178.154.239.149]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97F4F23D7DD; Sun, 24 Aug 2025 20:42:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=178.154.239.149 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756068156; cv=none; b=J7ytI5wIYV6NnWtbPhZMe+NGop71X95zHHJZ7t01GFWoF7zTAZTohsXi/7ALvcUuNx7GAunBsYmoOBw4jjWMYYab8OdQ1s1Me5RiRb0+vVADDqpAsT9qOt2VIjInczqa+Cx8IkJ6B8DfqGl2nPR42WWPAkvdj2d+KcZRlww90Ws= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756068156; c=relaxed/simple; bh=2rG/G9NBxbqTu6CuJVAkY8SKvl3EGxAO04K3tqLr340=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TQUBHee0Gv0h6oB5M2qgUowG10mzdB1NQoAQaETr1gj1/dugrZgBThkbuTnjtiFgwdJbdZsK7B8Ni1Rz56pbwt/ZSsOcPpPo4pwGqtMmjAddEosKh/kQLZ4eehvJpHWQRa2qZb/JOToPcC/tOjcKmeVO0xvTEw308mb7gYoDsMw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=yandex.ru; spf=pass smtp.mailfrom=yandex.ru; dkim=pass (1024-bit key) header.d=yandex.ru header.i=@yandex.ru header.b=U5jcIcbA; arc=none smtp.client-ip=178.154.239.149 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=yandex.ru Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=yandex.ru Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=yandex.ru header.i=@yandex.ru header.b="U5jcIcbA" Received: from mail-nwsmtp-smtp-production-main-73.sas.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-73.sas.yp-c.yandex.net [IPv6:2a02:6b8:c37:7521:0:640:a008:0]) by forward102b.mail.yandex.net (Yandex) with ESMTPS id 5D404C0006; Sun, 24 Aug 2025 23:42:26 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-73.sas.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id MgdcKKcLCa60-bf40ep3f; Sun, 24 Aug 2025 23:42:26 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=yandex.ru; s=mail; t=1756068146; bh=T7mI96+5ebnUKGoLkkPBcQK3Tj7pFqnEqbDek2swFQA=; h=Cc:In-Reply-To:Message-Id:To:Date:References:From:Subject; b=U5jcIcbAnBwiPUQOENbvgmrFjedx8iZBK4VJkaBKb/YhOLjdW3+zHvuDDdU7eLyu4 E+1YPVcZEfcVk+NyBVoLjymyMw0wbXViZkpIw4M3PQ1wsO8FlPev37woe4YYxKa6eN gduiu2X2ptA8K4vz/PLvypZm7+1pjWVcODAgcOa4= Authentication-Results: mail-nwsmtp-smtp-production-main-73.sas.yp-c.yandex.net; dkim=pass header.i=@yandex.ru From: Nickolay Goppen Date: Sun, 24 Aug 2025 23:42:25 +0300 Subject: [PATCH 3/3] pinctrl: qcom: Add SDM660 LPASS LPI TLMM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250824-sdm660-lpass-lpi-v1-3-003d5cc28234@yandex.ru> References: <20250824-sdm660-lpass-lpi-v1-0-003d5cc28234@yandex.ru> In-Reply-To: <20250824-sdm660-lpass-lpi-v1-0-003d5cc28234@yandex.ru> To: Bjorn Andersson , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, ~postmarketos/upstreaming@lists.sr.ht, Nickolay Goppen , Richard Acayan X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1756068142; l=8797; i=setotau@yandex.ru; s=20250815; h=from:subject:message-id; bh=yyEQydoIE+MJbMTGAvlVS0a75IXP1UAi2TgmCLS314Q=; b=AsyhebLKXBpyIjE6gAjEbut4/bSkvN7vpr4LWsN8R0LDxPoexqgm9gkSmkEi+4xHFZ52M47e/ IkGrjjSywe+CQPHP549cNFggQSZ9VHkM6+ISGjs1bR4BvpqzwfYefPp X-Developer-Key: i=setotau@yandex.ru; a=ed25519; pk=Og7YO6LfW+M2QfcJfjaUaXc8oOr5zoK8+4AtX5ICr4o= From: Richard Acayan The Snapdragon 660 has a Low-Power Island (LPI) TLMM for configuring pins related to audio. Add the driver for this. Also, this driver uses it's own quirky pin_offset function like downstream driver does [1]. [1] https://git.codelinaro.org/clo/la/kernel/msm-4.4/-/blob/LA.UM.7.2.c27-0= 7400-sdm660.0/drivers/pinctrl/qcom/pinctrl-lpi.c#L107 Co-developed-by: Nickolay Goppen Signed-off-by: Nickolay Goppen Signed-off-by: Richard Acayan --- drivers/pinctrl/qcom/Kconfig | 10 ++ drivers/pinctrl/qcom/Makefile | 1 + drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c | 196 ++++++++++++++++++++= ++++ 3 files changed, 207 insertions(+) diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig index dd9bbe8f3e11c37418d2143b33c21eeea10d456b..ef42520115f461302098d878cb7= 6c6f25e55b5e4 100644 --- a/drivers/pinctrl/qcom/Kconfig +++ b/drivers/pinctrl/qcom/Kconfig @@ -68,6 +68,16 @@ config PINCTRL_SC7280_LPASS_LPI Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI (Low Power Island) found on the Qualcomm Technologies Inc SC7280 platfo= rm. =20 +config PINCTRL_SDM660_LPASS_LPI + tristate "Qualcomm Technologies Inc SDM660 LPASS LPI pin controller drive= r" + depends on GPIOLIB + depends on ARM64 || COMPILE_TEST + depends on PINCTRL_LPASS_LPI + help + This is the pinctrl, pinmux, pinconf and gpiolib driver for the + Qualcomm Technologies Inc LPASS (Low Power Audio SubSystem) LPI + (Low Power Island) found on the Qualcomm Technologies Inc SDM660 platfo= rm. + config PINCTRL_SM4250_LPASS_LPI tristate "Qualcomm Technologies Inc SM4250 LPASS LPI pin controller drive= r" depends on ARM64 || COMPILE_TEST diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile index 954f5291cc37242baffc021e3c68d850aabd57cd..cea8617ac650ecfc75c2a0c745a= 53d6a1b829842 100644 --- a/drivers/pinctrl/qcom/Makefile +++ b/drivers/pinctrl/qcom/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_PINCTRL_SC7280_LPASS_LPI) +=3D pinctrl-sc728= 0-lpass-lpi.o obj-$(CONFIG_PINCTRL_SC8180X) +=3D pinctrl-sc8180x.o obj-$(CONFIG_PINCTRL_SC8280XP) +=3D pinctrl-sc8280xp.o obj-$(CONFIG_PINCTRL_SDM660) +=3D pinctrl-sdm660.o +obj-$(CONFIG_PINCTRL_SDM660_LPASS_LPI) +=3D pinctrl-sdm660-lpass-lpi.o obj-$(CONFIG_PINCTRL_SDM670) +=3D pinctrl-sdm670.o obj-$(CONFIG_PINCTRL_SDM845) +=3D pinctrl-sdm845.o obj-$(CONFIG_PINCTRL_SDX55) +=3D pinctrl-sdx55.o diff --git a/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c b/drivers/pinc= trl/qcom/pinctrl-sdm660-lpass-lpi.c new file mode 100644 index 0000000000000000000000000000000000000000..788e1c019b0b7a22360d8c32180= b5abf4d0fc0dc --- /dev/null +++ b/drivers/pinctrl/qcom/pinctrl-sdm660-lpass-lpi.c @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * This driver is solely based on the limited information in downstream co= de. + * Any verification with schematics would be greatly appreciated. + * + * Copyright (c) 2023, Richard Acayan. All rights reserved. + */ + +#include +#include +#include +#include +#include + +#include "pinctrl-lpass-lpi.h" + +enum lpass_lpi_functions { + LPI_MUX_comp_rx, + LPI_MUX_dmic12, + LPI_MUX_dmic34, + LPI_MUX_mclk0, + LPI_MUX_pdm_2_gpios, + LPI_MUX_pdm_clk, + LPI_MUX_pdm_rx, + LPI_MUX_pdm_sync, + + LPI_MUX_gpio, + LPI_MUX__, +}; + +static const u32 sdm660_lpi_offset[] =3D { + 0x00000000, + 0x00001000, + 0x00002000, + 0x00002010, + 0x00003000, + 0x00003010, + 0x00004000, + 0x00004010, + 0x00005000, + 0x00005010, + 0x00005020, + 0x00005030, + 0x00006000, + 0x00006010, + 0x00007000, + 0x00007010, + 0x00005040, + 0x00005050, + 0x00008000, + 0x00008010, + 0x00008020, + 0x00008030, + 0x00008040, + 0x00008050, + 0x00008060, + 0x00008070, + 0x00009000, + 0x00009010, + 0x0000A000, + 0x0000A010, + 0x0000B000, + 0x0000B010, +}; + +static const struct pinctrl_pin_desc sdm660_lpi_pinctrl_pins[] =3D { + PINCTRL_PIN(0, "gpio0"), + PINCTRL_PIN(1, "gpio1"), + PINCTRL_PIN(2, "gpio2"), + PINCTRL_PIN(3, "gpio3"), + PINCTRL_PIN(4, "gpio4"), + PINCTRL_PIN(5, "gpio5"), + PINCTRL_PIN(6, "gpio6"), + PINCTRL_PIN(7, "gpio7"), + PINCTRL_PIN(8, "gpio8"), + PINCTRL_PIN(9, "gpio9"), + PINCTRL_PIN(10, "gpio10"), + PINCTRL_PIN(11, "gpio11"), + PINCTRL_PIN(12, "gpio12"), + PINCTRL_PIN(13, "gpio13"), + PINCTRL_PIN(14, "gpio14"), + PINCTRL_PIN(15, "gpio15"), + PINCTRL_PIN(16, "gpio16"), + PINCTRL_PIN(17, "gpio17"), + PINCTRL_PIN(18, "gpio18"), + PINCTRL_PIN(19, "gpio19"), + PINCTRL_PIN(20, "gpio20"), + PINCTRL_PIN(21, "gpio21"), + PINCTRL_PIN(22, "gpio22"), + PINCTRL_PIN(23, "gpio23"), + PINCTRL_PIN(24, "gpio24"), + PINCTRL_PIN(25, "gpio25"), + PINCTRL_PIN(26, "gpio26"), + PINCTRL_PIN(27, "gpio27"), + PINCTRL_PIN(28, "gpio28"), + PINCTRL_PIN(29, "gpio29"), + PINCTRL_PIN(30, "gpio30"), + PINCTRL_PIN(31, "gpio31"), +}; + +static const char * const comp_rx_groups[] =3D { "gpio22", "gpio24" }; +static const char * const dmic12_groups[] =3D { "gpio26", "gpio28" }; +static const char * const dmic34_groups[] =3D { "gpio27", "gpio29" }; +static const char * const mclk0_groups[] =3D { "gpio18" }; +static const char * const pdm_2_gpios_groups[] =3D { "gpio20" }; +static const char * const pdm_clk_groups[] =3D { "gpio18" }; +static const char * const pdm_rx_groups[] =3D { "gpio21", "gpio23", "gpio2= 5" }; +static const char * const pdm_sync_groups[] =3D { "gpio19" }; + +const struct lpi_pingroup sdm660_lpi_pinctrl_groups[] =3D { + LPI_PINGROUP(0, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(1, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(2, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(3, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(4, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(5, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(6, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(7, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(8, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(9, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(10, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(11, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(12, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(13, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(14, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(15, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(16, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(17, LPI_NO_SLEW, _, _, _, _), + + /* The function names of the PDM GPIOs are derived from SDM670 */ + LPI_PINGROUP(18, LPI_NO_SLEW, pdm_clk, mclk0, _, _), + LPI_PINGROUP(19, LPI_NO_SLEW, pdm_sync, _, _, _), + LPI_PINGROUP(20, LPI_NO_SLEW, pdm_2_gpios, _, _, _), + LPI_PINGROUP(21, LPI_NO_SLEW, pdm_rx, _, _, _), + LPI_PINGROUP(22, LPI_NO_SLEW, comp_rx, _, _, _), + LPI_PINGROUP(23, LPI_NO_SLEW, pdm_rx, _, _, _), + LPI_PINGROUP(24, LPI_NO_SLEW, comp_rx, _, _, _), + LPI_PINGROUP(25, LPI_NO_SLEW, pdm_rx, _, _, _), + LPI_PINGROUP(26, LPI_NO_SLEW, dmic12, _, _, _), + LPI_PINGROUP(27, LPI_NO_SLEW, dmic34, _, _, _), + LPI_PINGROUP(28, LPI_NO_SLEW, dmic12, _, _, _), + LPI_PINGROUP(29, LPI_NO_SLEW, dmic34, _, _, _), + + LPI_PINGROUP(30, LPI_NO_SLEW, _, _, _, _), + LPI_PINGROUP(31, LPI_NO_SLEW, _, _, _, _), +}; + +const struct lpi_function sdm660_lpi_pinctrl_functions[] =3D { + LPI_FUNCTION(comp_rx), + LPI_FUNCTION(dmic12), + LPI_FUNCTION(dmic34), + LPI_FUNCTION(mclk0), + LPI_FUNCTION(pdm_2_gpios), + LPI_FUNCTION(pdm_clk), + LPI_FUNCTION(pdm_rx), + LPI_FUNCTION(pdm_sync), +}; + +static u32 pin_offset_sdm660(int pin_id) +{ + return sdm660_lpi_offset[pin_id]; +} + +static const struct lpi_pinctrl_variant_data sdm660_lpi_pinctrl_data =3D { + .pins =3D sdm660_lpi_pinctrl_pins, + .npins =3D ARRAY_SIZE(sdm660_lpi_pinctrl_pins), + .groups =3D sdm660_lpi_pinctrl_groups, + .ngroups =3D ARRAY_SIZE(sdm660_lpi_pinctrl_groups), + .functions =3D sdm660_lpi_pinctrl_functions, + .nfunctions =3D ARRAY_SIZE(sdm660_lpi_pinctrl_functions), + .flags =3D LPI_FLAG_SLEW_RATE_SAME_REG, + .pin_offset =3D pin_offset_sdm660, +}; + +static const struct of_device_id sdm660_lpi_pinctrl_of_match[] =3D { + { + .compatible =3D "qcom,sdm660-lpass-lpi-pinctrl", + .data =3D &sdm660_lpi_pinctrl_data, + }, + { } +}; +MODULE_DEVICE_TABLE(of, sdm660_lpi_pinctrl_of_match); + +static struct platform_driver sdm660_lpi_pinctrl_driver =3D { + .driver =3D { + .name =3D "qcom-sdm660-lpass-lpi-pinctrl", + .of_match_table =3D sdm660_lpi_pinctrl_of_match, + }, + .probe =3D lpi_pinctrl_probe, + .remove =3D lpi_pinctrl_remove, +}; +module_platform_driver(sdm660_lpi_pinctrl_driver); + +MODULE_AUTHOR("Richard Acayan "); +MODULE_DESCRIPTION("QTI SDM660 LPI GPIO pin control driver"); +MODULE_LICENSE("GPL"); --=20 2.51.0