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Sat, 23 Aug 2025 13:02:30 -0700 From: Sumit Gupta To: , , , , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH v2 7/7] cpufreq: CPPC: add autonomous mode boot parameter support Date: Sun, 24 Aug 2025 01:31:20 +0530 Message-ID: <20250823200121.1320197-8-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250823200121.1320197-1-sumitg@nvidia.com> References: <20250823200121.1320197-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B071:EE_|DS0PR12MB8197:EE_ X-MS-Office365-Filtering-Correlation-Id: 17ca3b96-6d77-4a26-297b-08dde2800b48 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014|7416014|921020; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Aug 2025 20:02:52.7670 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 17ca3b96-6d77-4a26-297b-08dde2800b48 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B071.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8197 Content-Type: text/plain; charset="utf-8" Add kernel boot parameter 'cppc_cpufreq.auto_sel_mode' to enable CPPC autonomous performance selection at system startup. When autonomous mode is enabled, the hardware automatically adjusts CPU performance based on workload demands using Energy Performance Preference (EPP) hints from the OS. This parameter allows to configure the autonomous mode on all CPUs without requiring runtime sysfs manipulation if the 'auto_sel' register is present. When auto_sel_mode=3D1: - All CPUs are configured for autonomous operation during driver init - EPP is set to performance preference (0x0) by default - Min/max performance bounds use defaults - CPU frequency scaling is handled by hardware rather than OS Also ensure that when autonomous mode is active, the set_target callback returns early since hardware controls frequency scaling directly. Signed-off-by: Sumit Gupta Reviewed-by: Randy Dunlap --- .../admin-guide/kernel-parameters.txt | 12 ++ drivers/cpufreq/cppc_cpufreq.c | 171 ++++++++++++++++-- 2 files changed, 168 insertions(+), 15 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentatio= n/admin-guide/kernel-parameters.txt index 86f395f2933b..ea58deb88c36 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -911,6 +911,18 @@ Format: ,,,[,] =20 + cppc_cpufreq.auto_sel_mode=3D + [CPU_FREQ] Autonomous Performance Level Selection. + When Autonomous selection is enabled, then the hardware is + allowed to autonomously select the CPU frequency. + In Autonomous mode, Energy Performance Preference(EPP) + provides input to the hardware to favour performance (0x0) + or energy efficiency (0xff). + Format: + Default: disabled. + 0: force disabled + 1: force enabled + cpuidle.off=3D1 [CPU_IDLE] disable the cpuidle sub-system =20 diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index 5e1bbb5f67b8..bbf654c56ff9 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -27,6 +27,8 @@ #include =20 static struct cpufreq_driver cppc_cpufreq_driver; +/* Autonomous Selection */ +static bool auto_sel_mode; =20 #ifdef CONFIG_ACPI_CPPC_CPUFREQ_FIE static enum { @@ -272,6 +274,14 @@ static int cppc_cpufreq_set_target(struct cpufreq_poli= cy *policy, freqs.old =3D policy->cur; freqs.new =3D target_freq; =20 + /* + * In autonomous mode, hardware handles frequency scaling directly + * based on workload demands and EPP hints, so OS frequency requests + * are not needed. + */ + if (cpu_data->perf_caps.auto_sel) + return ret; + cpufreq_freq_transition_begin(policy, &freqs); ret =3D cppc_set_perf_ctrls(cpu, &cpu_data->perf_ctrls); cpufreq_freq_transition_end(policy, &freqs, ret !=3D 0); @@ -555,6 +565,12 @@ static struct cppc_cpudata *cppc_cpufreq_get_cpu_data(= unsigned int cpu) goto free_mask; } =20 + ret =3D cppc_get_perf_ctrls(cpu, &cpu_data->perf_ctrls); + if (ret) { + pr_debug("Err reading CPU%d perf ctrls: ret:%d\n", cpu, ret); + goto free_mask; + } + return cpu_data; =20 free_mask: @@ -642,6 +658,79 @@ static int cppc_cpufreq_set_max_perf(struct cpufreq_po= licy *policy, u64 val, return (ret =3D=3D -EOPNOTSUPP) ? 0 : ret; } =20 +static int cppc_cpufreq_update_autosel_epp(struct cpufreq_policy *policy, = int auto_sel, u32 epp) +{ + struct cppc_cpudata *cpu_data =3D policy->driver_data; + unsigned int cpu =3D policy->cpu; + int ret; + + pr_debug("cpu%d: curr epp:%u, curr mode:%u, new epp:%u, new mode:%d\n", c= pu, + cpu_data->perf_ctrls.energy_perf, cpu_data->perf_caps.auto_sel, epp, au= to_sel); + + mutex_lock(&cppc_cpufreq_update_autosel_config_lock); + + ret =3D cppc_set_epp(cpu, epp); + if (ret) { + pr_warn("failed to set energy_perf for cpu:%d (%d)\n", cpu, ret); + goto out; + } + cpu_data->perf_ctrls.energy_perf =3D epp; + + ret =3D cppc_set_auto_sel(cpu, auto_sel); + if (ret) { + pr_warn("failed to set auto_sel for cpu:%d (%d)\n", cpu, ret); + return ret; + } + cpu_data->perf_caps.auto_sel =3D auto_sel; + +out: + mutex_unlock(&cppc_cpufreq_update_autosel_config_lock); + return ret; +} + +static int cppc_cpufreq_update_autosel_mperf_ctrls(struct cpufreq_policy *= policy, u32 min_p, + u32 max_p, bool update_reg, bool update_policy) +{ + struct cppc_cpudata *cpu_data =3D policy->driver_data; + unsigned int cpu =3D policy->cpu; + int ret; + + pr_debug("cpu%d: curr max_perf:%u, curr min_perf:%u, new max_perf:%u, new= min_perf:%u\n", + cpu, cpu_data->perf_ctrls.max_perf, cpu_data->perf_ctrls.min_perf, max_= p, min_p); + + ret =3D cppc_cpufreq_set_min_perf(policy, min_p, update_reg, update_polic= y); + if (ret) { + pr_debug("failed to set min_perf for cpu:%d (%d)\n", cpu, ret); + return ret; + } + + ret =3D cppc_cpufreq_set_max_perf(policy, max_p, update_reg, update_polic= y); + if (ret) { + pr_debug("failed to set max_perf for cpu:%d (%d)\n", cpu, ret); + return ret; + } + + return ret; +} + +static int cppc_cpufreq_update_autosel_configs(struct cpufreq_policy *poli= cy, int auto_sel, + u32 epp, u32 min_perf, u32 max_perf, + bool update_reg, bool update_policy) +{ + int ret; + + ret =3D cppc_cpufreq_update_autosel_mperf_ctrls(policy, min_perf, max_per= f, + update_reg, update_policy); + if (ret) + return ret; + + ret =3D cppc_cpufreq_update_autosel_epp(policy, auto_sel, epp); + if (ret) + return ret; + + return 0; +} + static int cppc_cpufreq_cpu_init(struct cpufreq_policy *policy) { unsigned int cpu =3D policy->cpu; @@ -710,11 +799,28 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_polic= y *policy) policy->cur =3D cppc_perf_to_khz(caps, caps->highest_perf); cpu_data->perf_ctrls.desired_perf =3D caps->highest_perf; =20 - ret =3D cppc_set_perf_ctrls(cpu, &cpu_data->perf_ctrls); - if (ret) { - pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n", - caps->highest_perf, cpu, ret); - goto out; + if (cpu_data->perf_caps.auto_sel) { + ret =3D cppc_set_enable(cpu, true); + if (ret) { + pr_err("Failed to enable CPPC on cpu%d (%d)\n", cpu, ret); + goto out; + } + + ret =3D cppc_cpufreq_update_autosel_configs(policy, true, + CPPC_EPP_PERFORMANCE_PREF, + caps->lowest_nonlinear_perf, + caps->nominal_perf, true, false); + if (ret) { + pr_debug("Failed to update autosel configs on CPU%d(%d)\n", cpu, ret); + goto out; + } + } else { + ret =3D cppc_set_perf_ctrls(cpu, &cpu_data->perf_ctrls); + if (ret) { + pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n", + caps->highest_perf, cpu, ret); + goto out; + } } =20 cppc_cpufreq_cpu_fie_init(policy); @@ -736,6 +842,13 @@ static void cppc_cpufreq_cpu_exit(struct cpufreq_polic= y *policy) =20 cpu_data->perf_ctrls.desired_perf =3D caps->lowest_perf; =20 + if (cpu_data->perf_caps.auto_sel) { + ret =3D cppc_cpufreq_update_autosel_epp(policy, false, + CPPC_EPP_ENERGY_EFFICIENCY_PREF); + if (ret) + return; + } + ret =3D cppc_set_perf_ctrls(cpu, &cpu_data->perf_ctrls); if (ret) pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n", @@ -920,17 +1033,10 @@ static ssize_t store_auto_select(struct cpufreq_poli= cy *policy, * On enabling auto_select: set min/max_perf register and update policy. * On disabling auto_select: update only policy. */ - ret =3D cppc_cpufreq_set_min_perf(policy, min_perf, update_reg, true); - if (ret) { - pr_warn("failed to %s update min policy for cpu:%d (%d)\n", - val > 0 ? "set min_perf and" : "", cpu, ret); - return ret; - } - - ret =3D cppc_cpufreq_set_max_perf(policy, max_perf, update_reg, true); + ret =3D cppc_cpufreq_update_autosel_mperf_ctrls(policy, min_perf, max_per= f, update_reg, true); if (ret) { - pr_warn("failed to %s update max policy for cpu:%d (%d)\n", - val > 0 ? "set max_perf and" : "", cpu, ret); + pr_warn("failed to %s update policy for cpu:%d (%d)\n", + val > 0 ? "set min/max_perf and" : "", cpu, ret); return ret; } =20 @@ -1139,13 +1245,44 @@ static struct cpufreq_driver cppc_cpufreq_driver = =3D { .name =3D "cppc_cpufreq", }; =20 +static void cppc_cpufreq_set_epp_autosel_allcpus(bool auto_sel, u64 epp) +{ + int cpu, ret; + + for_each_present_cpu(cpu) { + ret =3D cppc_set_epp(cpu, epp); + if (ret) + pr_debug("failed to set energy_perf for cpu:%d (%d)\n", cpu, ret); + + ret =3D cppc_set_auto_sel(cpu, auto_sel); + if (ret) + pr_debug("failed to set auto_sel for cpu:%d (%d)\n", cpu, ret); + } +} + static int __init cppc_cpufreq_init(void) { + bool auto_sel; int ret; =20 if (!acpi_cpc_valid()) return -ENODEV; =20 + if (auto_sel_mode) { + /* + * Check if autonomous selection is supported by testing CPU 0. + * If supported, enable autonomous mode on all CPUs. + */ + ret =3D cppc_get_auto_sel(0, &auto_sel); + if (!ret) { + pr_info("Enabling autonomous mode on all CPUs\n"); + cppc_cpufreq_set_epp_autosel_allcpus(true, CPPC_EPP_PERFORMANCE_PREF); + } else { + pr_warn("Autonomous selection not supported, disabling auto_sel_mode\n"= ); + auto_sel_mode =3D false; + } + } + cppc_freq_invariance_init(); populate_efficiency_class(); =20 @@ -1160,8 +1297,12 @@ static void __exit cppc_cpufreq_exit(void) { cpufreq_unregister_driver(&cppc_cpufreq_driver); cppc_freq_invariance_exit(); + auto_sel_mode =3D 0; } =20 +module_param(auto_sel_mode, bool, 0000); +MODULE_PARM_DESC(auto_sel_mode, "Enable Autonomous Performance Level Selec= tion"); + module_exit(cppc_cpufreq_exit); MODULE_AUTHOR("Ashwin Chaugule"); MODULE_DESCRIPTION("CPUFreq driver based on the ACPI CPPC v5.0+ spec"); --=20 2.34.1