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Sat, 23 Aug 2025 13:02:13 -0700 From: Sumit Gupta To: , , , , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH v2 5/7] cpufreq: CPPC: update policy min/max when toggling auto_select Date: Sun, 24 Aug 2025 01:31:18 +0530 Message-ID: <20250823200121.1320197-6-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250823200121.1320197-1-sumitg@nvidia.com> References: <20250823200121.1320197-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AE7:EE_|DM4PR12MB6012:EE_ X-MS-Office365-Filtering-Correlation-Id: 2f59c1cf-18ca-4a48-ce35-08dde27fff22 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014|7416014|921020; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?SqgvuSq3gERFF8KxvYuzBcE2u5ZaSamLuQvYcDjt6ckxfrGnLxkmlNHrTavQ?= =?us-ascii?Q?MobkMppvKkIqR7OyKEyQHXocNls+Qz59Cgu8nUGE2vl70K1/fMczanF5VSJl?= =?us-ascii?Q?JEQ3OLvOaOqvyONaxwK9lNGt291sDszj9HzBiovQGnvAh7xfrTZkTPYTEFg8?= =?us-ascii?Q?r+SWBAj0vNwMnLO2cTcT1mm95huOz9/TBcTeTe69s6akII/OmoxxnlPNbUR7?= =?us-ascii?Q?HGd3F60NPCYAy6GeOswED9W/hd8Ynt/J1a9GOu1nPBE2jL8Yj7HAk9GCYz1Z?= =?us-ascii?Q?/Q18fDr74u86imWFKFMuIO6wzfsN8TtEP18Wluc5SKvgnq8TYqEnkdeUhTgI?= =?us-ascii?Q?Fr59pcWCnwQWgyBuzjxayBWakmwYluHoFc4Sdb/VTIuN5uWFzIyuwxWnrRYS?= =?us-ascii?Q?IMkDeAQHfg1x2FtM6E3uMMVnnA9pUTPYOsK1bdM+FYpCYmHG2ZSvGORo4O27?= =?us-ascii?Q?cMaskqzb2gUrVogotZYT2NAa8CSByn7rdCgfBp+oEOQBLOFSIZ1s3ia/ib2l?= =?us-ascii?Q?+JZD2HE35QdOLTpv+X9iG+phwFy3k0uBBa35T0VhaJp2+2RUiq8gNgE1eurW?= =?us-ascii?Q?i2SSLzEGnUmn0T7Z9O15SqCgffQf+8S7TbbPE1VJJ50YfIZdBKDTk3D7E7Hz?= =?us-ascii?Q?9hzyI72bkNjh6eM1IOCgnCcDV5nXsXm35O2+5DftYslFBoqq9mAPfWTmB4zD?= =?us-ascii?Q?CG64AZHo5GaqdVRGXcI+lj5Nlsr8QiJpoHrZujl/QWIa7xzqgcXzon3YaShF?= =?us-ascii?Q?B7GjYENudjV5traWTKpMwFQxkE00Z16zuQcpgCX5m9pck16VOMW4qWQCobES?= =?us-ascii?Q?S/rInENUlPTHenrCW0Hvs3PJsWVNiiRhLrQsG64QeWvnbALFo9bhceq5WDVn?= =?us-ascii?Q?/qXZGXom87iqM7icktIr7vzdb9XC+WXJyvoqt6KWYieJ2gavITPjGBmneO+q?= =?us-ascii?Q?GtIPzjJPUNzsgnFK9VbBeD6Sozn+VoVpbl2RsPU0HSE4rR09hLN924GhjoJq?= =?us-ascii?Q?T6x6BQn94nvJaCDQ/Z2DjXtQ/dEq0/MjjW/a2ZjGy7iH/yEd2oZViCbJDWJn?= =?us-ascii?Q?gazTlV8PNVPSxoUe+l0ca2aBgw8BrRhIGA819N+J/rxSr0v8psVzod1JXfzl?= =?us-ascii?Q?y8D3HpOhU7HRJeRip4ZXudEOyk/KO81Z3Ps6XDRkbxNl8G+qm6mo8VvyOF2W?= =?us-ascii?Q?+4CkL5qJvFywxWnBKi5qy3qURvtEcXa/x4TMyFWS+N0RMF3fZtMfCPS0If5q?= =?us-ascii?Q?KGi+rJM41FTQM7ndGa2JVBU3WZF0pEtjc24NHfd8PcGmI3wWpCO1myD/F1mo?= =?us-ascii?Q?HcZw4jpuIRVW+ZhtL6irju8orL4hfOkebz1YEcui7JUAW4axNEloYXX44azk?= =?us-ascii?Q?Cyg8kMwCw2/lxsUtXJowqVLo4/2CMliKGmobedDE/pWYHYAvk8aImy70Dnqv?= =?us-ascii?Q?71JW16RgnwQLuQKL6DXAd74lpA1pDfWyOQhonYg9+yItWYnFRuz0I4aVmW+0?= =?us-ascii?Q?h3hPFmTryUmxD2yVmCNBXTLG+j4sjKmBZkvkeR77hkFJj00uLqGF1jpthQ?= =?us-ascii?Q?=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(1800799024)(82310400026)(376014)(7416014)(921020);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Aug 2025 20:02:32.4060 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2f59c1cf-18ca-4a48-ce35-08dde27fff22 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6012 Content-Type: text/plain; charset="utf-8" When CPPC autonomous selection (auto_select) is enabled or disabled, the policy min/max frequency limits should be updated appropriately to reflect the new operating mode. Currently, toggling auto_select only changes the hardware register but doesn't update the cpufreq policy constraints, which can lead to inconsistent behavior between the hardware state and the policy limits visible to userspace and other kernel components. When auto_select is enabled, preserve the current min/max performance values to maintain user-configured limits. When disabled, the hardware operates in a default mode where the OS directly controls performance, so update the policy limits accordingly. Signed-off-by: Sumit Gupta --- drivers/cpufreq/cppc_cpufreq.c | 47 ++++++++++++++++++++++++++++++++-- 1 file changed, 45 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index d9aae1ec26e1..5e1bbb5f67b8 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -880,6 +880,10 @@ static ssize_t show_auto_select(struct cpufreq_policy = *policy, char *buf) static ssize_t store_auto_select(struct cpufreq_policy *policy, const char *buf, size_t count) { + struct cppc_cpudata *cpu_data =3D policy->driver_data; + unsigned int cpu =3D policy->cpu; + bool update_reg =3D false; + u32 min_perf, max_perf; bool val; int ret; =20 @@ -887,9 +891,48 @@ static ssize_t store_auto_select(struct cpufreq_policy= *policy, if (ret) return ret; =20 - ret =3D cppc_set_auto_sel(policy->cpu, val); - if (ret) + mutex_lock(&cppc_cpufreq_update_autosel_config_lock); + if (val) { + /* Enabling auto_select: set current user-configured limits */ + min_perf =3D cpu_data->perf_ctrls.min_perf; + max_perf =3D cpu_data->perf_ctrls.max_perf; + update_reg =3D true; + } else { + /* + * Disabling auto_select: set defaults for OS control. + * Use lowest_nonlinear_perf as minimum to avoid very low frequencies + * and nominal_perf as maximum for balanced operation. + */ + min_perf =3D cpu_data->perf_caps.lowest_nonlinear_perf; + max_perf =3D cpu_data->perf_caps.nominal_perf; + } + + ret =3D cppc_set_auto_sel(cpu, val); + if (ret) { + pr_warn("failed to set auto_sel for cpu:%d (%d)\n", cpu, ret); + mutex_unlock(&cppc_cpufreq_update_autosel_config_lock); + return ret; + } + cpu_data->perf_caps.auto_sel =3D val; + mutex_unlock(&cppc_cpufreq_update_autosel_config_lock); + + /* + * On enabling auto_select: set min/max_perf register and update policy. + * On disabling auto_select: update only policy. + */ + ret =3D cppc_cpufreq_set_min_perf(policy, min_perf, update_reg, true); + if (ret) { + pr_warn("failed to %s update min policy for cpu:%d (%d)\n", + val > 0 ? "set min_perf and" : "", cpu, ret); return ret; + } + + ret =3D cppc_cpufreq_set_max_perf(policy, max_perf, update_reg, true); + if (ret) { + pr_warn("failed to %s update max policy for cpu:%d (%d)\n", + val > 0 ? "set max_perf and" : "", cpu, ret); + return ret; + } =20 return count; } --=20 2.34.1