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Sat, 23 Aug 2025 13:01:45 -0700 From: Sumit Gupta To: , , , , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH v2 2/7] ACPI: CPPC: extend APIs to support auto_sel and epp Date: Sun, 24 Aug 2025 01:31:15 +0530 Message-ID: <20250823200121.1320197-3-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250823200121.1320197-1-sumitg@nvidia.com> References: <20250823200121.1320197-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AE5:EE_|SA1PR12MB7296:EE_ X-MS-Office365-Filtering-Correlation-Id: c6ea3f9b-e727-4a09-0542-08dde27fecfc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|36860700013|82310400026|921020; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Aug 2025 20:02:01.9579 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c6ea3f9b-e727-4a09-0542-08dde27fecfc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE5.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7296 Content-Type: text/plain; charset="utf-8" Add read of auto_sel in cppc_get_perf_caps(). Add write of auto_sel and epp in cppc_set_epp_and_autosel(). Signed-off-by: Sumit Gupta --- drivers/acpi/cppc_acpi.c | 32 +++++++++++++++++++++++++++----- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 24baaa298af3..fbcfbe4bcbf0 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1344,8 +1344,8 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf_c= aps *perf_caps) struct cpc_desc *cpc_desc =3D per_cpu(cpc_desc_ptr, cpunum); struct cpc_register_resource *highest_reg, *lowest_reg, *lowest_non_linear_reg, *nominal_reg, *guaranteed_reg, - *low_freq_reg =3D NULL, *nom_freq_reg =3D NULL; - u64 high, low, guaranteed, nom, min_nonlinear, low_f =3D 0, nom_f =3D 0; + *low_freq_reg =3D NULL, *nom_freq_reg =3D NULL, *auto_sel_reg =3D NULL; + u64 high, low, guaranteed, nom, min_nonlinear, low_f =3D 0, nom_f =3D 0, = auto_sel =3D 0; int pcc_ss_id =3D per_cpu(cpu_pcc_subspace_idx, cpunum); struct cppc_pcc_data *pcc_ss_data =3D NULL; int ret =3D 0, regs_in_pcc =3D 0; @@ -1362,11 +1362,12 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf= _caps *perf_caps) low_freq_reg =3D &cpc_desc->cpc_regs[LOWEST_FREQ]; nom_freq_reg =3D &cpc_desc->cpc_regs[NOMINAL_FREQ]; guaranteed_reg =3D &cpc_desc->cpc_regs[GUARANTEED_PERF]; + auto_sel_reg =3D &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; =20 /* Are any of the regs PCC ?*/ if (CPC_IN_PCC(highest_reg) || CPC_IN_PCC(lowest_reg) || CPC_IN_PCC(lowest_non_linear_reg) || CPC_IN_PCC(nominal_reg) || - CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg)) { + CPC_IN_PCC(low_freq_reg) || CPC_IN_PCC(nom_freq_reg) || CPC_IN_PCC(auto_= sel_reg)) { if (pcc_ss_id < 0) { pr_debug("Invalid pcc_ss_id\n"); return -ENODEV; @@ -1414,6 +1415,9 @@ int cppc_get_perf_caps(int cpunum, struct cppc_perf_c= aps *perf_caps) perf_caps->lowest_freq =3D low_f; perf_caps->nominal_freq =3D nom_f; =20 + if (CPC_SUPPORTED(auto_sel_reg)) + cpc_read(cpunum, auto_sel_reg, &auto_sel); + perf_caps->auto_sel =3D (bool)auto_sel; =20 out_err: if (regs_in_pcc) @@ -1555,6 +1559,8 @@ int cppc_set_epp_and_autosel(int cpu, struct cppc_per= f_ctrls *perf_ctrls, bool e struct cpc_register_resource *auto_sel_reg; struct cpc_desc *cpc_desc =3D per_cpu(cpc_desc_ptr, cpu); struct cppc_pcc_data *pcc_ss_data =3D NULL; + bool autosel_support_in_ffh_or_sysmem; + bool epp_support_in_ffh_or_sysmem; int ret; =20 if (!cpc_desc) { @@ -1565,6 +1571,11 @@ int cppc_set_epp_and_autosel(int cpu, struct cppc_pe= rf_ctrls *perf_ctrls, bool e auto_sel_reg =3D &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; epp_set_reg =3D &cpc_desc->cpc_regs[ENERGY_PERF]; =20 + epp_support_in_ffh_or_sysmem =3D CPC_SUPPORTED(epp_set_reg) && + (CPC_IN_FFH(epp_set_reg) || CPC_IN_SYSTEM_MEMORY(epp_set_reg)); + autosel_support_in_ffh_or_sysmem =3D CPC_SUPPORTED(auto_sel_reg) && + (CPC_IN_FFH(auto_sel_reg) || CPC_IN_SYSTEM_MEMORY(auto_sel_reg)); + if (CPC_IN_PCC(epp_set_reg) || CPC_IN_PCC(auto_sel_reg)) { if (pcc_ss_id < 0) { pr_debug("Invalid pcc_ss_id for CPU:%d\n", cpu); @@ -1590,8 +1601,19 @@ int cppc_set_epp_and_autosel(int cpu, struct cppc_pe= rf_ctrls *perf_ctrls, bool e ret =3D send_pcc_cmd(pcc_ss_id, CMD_WRITE); up_write(&pcc_ss_data->pcc_lock); } else if (osc_cpc_flexible_adr_space_confirmed && - CPC_SUPPORTED(epp_set_reg) && CPC_IN_FFH(epp_set_reg)) { - ret =3D cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf); + epp_support_in_ffh_or_sysmem && autosel_support_in_ffh_or_sysmem) { + ret =3D cpc_write(cpu, auto_sel_reg, enable); + if (ret) { + pr_debug("Failed to write auto_sel=3D%d for CPU:%d\n", enable, cpu); + return ret; + } + + ret =3D cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf); + if (ret) { + pr_debug("Failed to write energy_perf=3D%u for CPU:%d\n", + perf_ctrls->energy_perf, cpu); + return ret; + } } else { ret =3D -ENOTSUPP; pr_debug("_CPC in PCC and _CPC in FFH are not supported\n"); --=20 2.34.1