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Sat, 23 Aug 2025 13:01:32 -0700 From: Sumit Gupta To: , , , , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH v2 1/7] ACPI: CPPC: add perf control read API and clarify naming Date: Sun, 24 Aug 2025 01:31:14 +0530 Message-ID: <20250823200121.1320197-2-sumitg@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250823200121.1320197-1-sumitg@nvidia.com> References: <20250823200121.1320197-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00003AE9:EE_|MW6PR12MB8758:EE_ X-MS-Office365-Filtering-Correlation-Id: b1c37024-0c51-4ae0-788a-08dde27fe756 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|376014|7416014|921020; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Aug 2025 20:01:52.2671 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b1c37024-0c51-4ae0-788a-08dde27fe756 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003AE9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8758 Content-Type: text/plain; charset="utf-8" Add cppc_get_perf_ctrls() to read performance control register values. Rename existing APIs for clarity as: - To distinguish between: - Feedback counters (fb_ctrs): Read-only performance monitoring data. - Performance controls (perf_ctrls): Read-write config registers. - cppc_set_epp_perf() updates both EPP and Autonomous Selection. API's renamed: - cppc_set_perf() to cppc_set_perf_ctrls(). - cppc_get_perf_ctrs() to cppc_get_perf_fb_ctrs(). - cppc_get_perf_ctrs_sample() to cppc_get_perf_fb_ctrs_sample(). - cppc_set_epp_perf() to cppc_set_epp_and_autosel(). Remove redundant energy_perf field from 'struct cppc_perf_caps' since the same information is available in 'struct cppc_perf_ctrls' which is actively used. All existing callers are updated to maintain compatibility. Signed-off-by: Sumit Gupta --- drivers/acpi/cppc_acpi.c | 95 +++++++++++++++++++++++++++++----- drivers/cpufreq/amd-pstate.c | 2 +- drivers/cpufreq/cppc_cpufreq.c | 26 +++++----- include/acpi/cppc_acpi.h | 18 ++++--- 4 files changed, 106 insertions(+), 35 deletions(-) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 6b649031808f..24baaa298af3 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -58,7 +58,7 @@ struct cppc_pcc_data { /* * Lock to provide controlled access to the PCC channel. * - * For performance critical usecases(currently cppc_set_perf) + * For performance critical usecases(currently cppc_set_perf_ctrls) * We need to take read_lock and check if channel belongs to OSPM * before reading or writing to PCC subspace * We need to take write_lock before transferring the channel @@ -182,8 +182,8 @@ show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, guar= anteed_perf); show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, lowest_freq); show_cppc_data(cppc_get_perf_caps, cppc_perf_caps, nominal_freq); =20 -show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, reference_perf); -show_cppc_data(cppc_get_perf_ctrs, cppc_perf_fb_ctrs, wraparound_time); +show_cppc_data(cppc_get_perf_fb_ctrs, cppc_perf_fb_ctrs, reference_perf); +show_cppc_data(cppc_get_perf_fb_ctrs, cppc_perf_fb_ctrs, wraparound_time); =20 /* Check for valid access_width, otherwise, fallback to using bit_width */ #define GET_BIT_WIDTH(reg) ((reg)->access_width ? (8 << ((reg)->access_wid= th - 1)) : (reg)->bit_width) @@ -202,7 +202,7 @@ static ssize_t show_feedback_ctrs(struct kobject *kobj, struct cppc_perf_fb_ctrs fb_ctrs =3D {0}; int ret; =20 - ret =3D cppc_get_perf_ctrs(cpc_ptr->cpu_id, &fb_ctrs); + ret =3D cppc_get_perf_fb_ctrs(cpc_ptr->cpu_id, &fb_ctrs); if (ret) return ret; =20 @@ -1427,7 +1427,7 @@ EXPORT_SYMBOL_GPL(cppc_get_perf_caps); * * CPPC has flexibility about how CPU performance counters are accessed. * One of the choices is PCC regions, which can have a high access latency= . This - * routine allows callers of cppc_get_perf_ctrs() to know this ahead of ti= me. + * routine allows callers of cppc_get_perf_fb_ctrs() to know this ahead of= time. * * Return: true if any of the counters are in PCC regions, false otherwise */ @@ -1465,13 +1465,13 @@ bool cppc_perf_ctrs_in_pcc(void) EXPORT_SYMBOL_GPL(cppc_perf_ctrs_in_pcc); =20 /** - * cppc_get_perf_ctrs - Read a CPU's performance feedback counters. + * cppc_get_perf_fb_ctrs - Read a CPU's performance feedback counters. * @cpunum: CPU from which to read counters. * @perf_fb_ctrs: ptr to cppc_perf_fb_ctrs. See cppc_acpi.h * * Return: 0 for success with perf_fb_ctrs populated else -ERRNO. */ -int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) +int cppc_get_perf_fb_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ct= rs) { struct cpc_desc *cpc_desc =3D per_cpu(cpc_desc_ptr, cpunum); struct cpc_register_resource *delivered_reg, *reference_reg, @@ -1542,13 +1542,13 @@ int cppc_get_perf_ctrs(int cpunum, struct cppc_perf= _fb_ctrs *perf_fb_ctrs) up_write(&pcc_ss_data->pcc_lock); return ret; } -EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); +EXPORT_SYMBOL_GPL(cppc_get_perf_fb_ctrs); =20 /* * Set Energy Performance Preference Register value through * Performance Controls Interface */ -int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, bool en= able) +int cppc_set_epp_and_autosel(int cpu, struct cppc_perf_ctrls *perf_ctrls, = bool enable) { int pcc_ss_id =3D per_cpu(cpu_pcc_subspace_idx, cpu); struct cpc_register_resource *epp_set_reg; @@ -1599,7 +1599,7 @@ int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls= *perf_ctrls, bool enable) =20 return ret; } -EXPORT_SYMBOL_GPL(cppc_set_epp_perf); +EXPORT_SYMBOL_GPL(cppc_set_epp_and_autosel); =20 /** * cppc_set_epp() - Write the EPP register. @@ -1731,15 +1731,82 @@ int cppc_set_enable(int cpu, bool enable) return cppc_set_reg_val(cpu, ENABLE, enable); } EXPORT_SYMBOL_GPL(cppc_set_enable); +/** + * cppc_get_perf_ctrls - Get a CPU's performance controls. + * @cpu: CPU for which to get performance controls. + * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h + * + * Return: 0 for success with perf_ctrls, -ERRNO otherwise. + */ +int cppc_get_perf_ctrls(int cpu, struct cppc_perf_ctrls *perf_ctrls) +{ + struct cpc_desc *cpc_desc =3D per_cpu(cpc_desc_ptr, cpu); + struct cpc_register_resource *desired_perf_reg, *min_perf_reg, *max_perf_= reg, + *energy_perf_reg; + u64 max, min, desired_perf, energy_perf; + int pcc_ss_id =3D per_cpu(cpu_pcc_subspace_idx, cpu); + struct cppc_pcc_data *pcc_ss_data =3D NULL; + int ret =3D 0, regs_in_pcc =3D 0; + + if (!cpc_desc) { + pr_debug("No CPC descriptor for CPU:%d\n", cpu); + return -ENODEV; + } + + desired_perf_reg =3D &cpc_desc->cpc_regs[DESIRED_PERF]; + min_perf_reg =3D &cpc_desc->cpc_regs[MIN_PERF]; + max_perf_reg =3D &cpc_desc->cpc_regs[MAX_PERF]; + energy_perf_reg =3D &cpc_desc->cpc_regs[ENERGY_PERF]; + + /* Are any of the regs PCC ?*/ + if (CPC_IN_PCC(desired_perf_reg) || CPC_IN_PCC(min_perf_reg) || + CPC_IN_PCC(max_perf_reg) || CPC_IN_PCC(energy_perf_reg)) { + if (pcc_ss_id < 0) { + pr_debug("Invalid pcc_ss_id\n"); + return -ENODEV; + } + pcc_ss_data =3D pcc_data[pcc_ss_id]; + regs_in_pcc =3D 1; + down_write(&pcc_ss_data->pcc_lock); + /* Ring doorbell once to update PCC subspace */ + if (send_pcc_cmd(pcc_ss_id, CMD_READ) < 0) { + ret =3D -EIO; + goto out_err; + } + } + + /* Read optional elements if present */ + if (CPC_SUPPORTED(max_perf_reg)) + cpc_read(cpu, max_perf_reg, &max); + perf_ctrls->max_perf =3D max; + + if (CPC_SUPPORTED(min_perf_reg)) + cpc_read(cpu, min_perf_reg, &min); + perf_ctrls->min_perf =3D min; + + if (CPC_SUPPORTED(desired_perf_reg)) + cpc_read(cpu, desired_perf_reg, &desired_perf); + perf_ctrls->desired_perf =3D desired_perf; + + if (CPC_SUPPORTED(energy_perf_reg)) + cpc_read(cpu, energy_perf_reg, &energy_perf); + perf_ctrls->energy_perf =3D energy_perf; + +out_err: + if (regs_in_pcc) + up_write(&pcc_ss_data->pcc_lock); + return ret; +} +EXPORT_SYMBOL_GPL(cppc_get_perf_ctrls); =20 /** - * cppc_set_perf - Set a CPU's performance controls. + * cppc_set_perf_ctrls - Set a CPU's performance controls. * @cpu: CPU for which to set performance controls. * @perf_ctrls: ptr to cppc_perf_ctrls. See cppc_acpi.h * * Return: 0 for success, -ERRNO otherwise. */ -int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) +int cppc_set_perf_ctrls(int cpu, struct cppc_perf_ctrls *perf_ctrls) { struct cpc_desc *cpc_desc =3D per_cpu(cpc_desc_ptr, cpu); struct cpc_register_resource *desired_reg, *min_perf_reg, *max_perf_reg; @@ -1803,7 +1870,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *pe= rf_ctrls) /* * This is Phase-II where we transfer the ownership of PCC to Platform * - * Short Summary: Basically if we think of a group of cppc_set_perf + * Short Summary: Basically if we think of a group of cppc_set_perf_ctrls * requests that happened in short overlapping interval. The last CPU to * come out of Phase-I will enter Phase-II and ring the doorbell. * @@ -1862,7 +1929,7 @@ int cppc_set_perf(int cpu, struct cppc_perf_ctrls *pe= rf_ctrls) } return ret; } -EXPORT_SYMBOL_GPL(cppc_set_perf); +EXPORT_SYMBOL_GPL(cppc_set_perf_ctrls); =20 /** * cppc_get_transition_latency - returns frequency transition latency in ns diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index bbc27ef9edf7..b98539d1a6aa 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -355,7 +355,7 @@ static int shmem_set_epp(struct cpufreq_policy *policy,= u8 epp) return 0; =20 perf_ctrls.energy_perf =3D epp; - ret =3D cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1); + ret =3D cppc_set_epp_and_autosel(cpudata->cpu, &perf_ctrls, 1); if (ret) { pr_debug("failed to set energy perf value (%d)\n", ret); return ret; diff --git a/drivers/cpufreq/cppc_cpufreq.c b/drivers/cpufreq/cppc_cpufreq.c index ecbeb12f46e6..e4666836306d 100644 --- a/drivers/cpufreq/cppc_cpufreq.c +++ b/drivers/cpufreq/cppc_cpufreq.c @@ -81,7 +81,7 @@ static void cppc_scale_freq_workfn(struct kthread_work *w= ork) cppc_fi =3D container_of(work, struct cppc_freq_invariance, work); cpu_data =3D cppc_fi->cpu_data; =20 - if (cppc_get_perf_ctrs(cppc_fi->cpu, &fb_ctrs)) { + if (cppc_get_perf_fb_ctrs(cppc_fi->cpu, &fb_ctrs)) { pr_warn("%s: failed to read perf counters\n", __func__); return; } @@ -115,7 +115,7 @@ static void cppc_scale_freq_tick(void) struct cppc_freq_invariance *cppc_fi =3D &per_cpu(cppc_freq_inv, smp_proc= essor_id()); =20 /* - * cppc_get_perf_ctrs() can potentially sleep, call that from the right + * cppc_get_perf_fb_ctrs() can potentially sleep, call that from the right * context. */ irq_work_queue(&cppc_fi->irq_work); @@ -141,7 +141,7 @@ static void cppc_cpufreq_cpu_fie_init(struct cpufreq_po= licy *policy) kthread_init_work(&cppc_fi->work, cppc_scale_freq_workfn); init_irq_work(&cppc_fi->irq_work, cppc_irq_work); =20 - ret =3D cppc_get_perf_ctrs(cpu, &cppc_fi->prev_perf_fb_ctrs); + ret =3D cppc_get_perf_fb_ctrs(cpu, &cppc_fi->prev_perf_fb_ctrs); if (ret) { pr_warn("%s: failed to read perf counters for cpu:%d: %d\n", __func__, cpu, ret); @@ -271,7 +271,7 @@ static int cppc_cpufreq_set_target(struct cpufreq_polic= y *policy, freqs.new =3D target_freq; =20 cpufreq_freq_transition_begin(policy, &freqs); - ret =3D cppc_set_perf(cpu, &cpu_data->perf_ctrls); + ret =3D cppc_set_perf_ctrls(cpu, &cpu_data->perf_ctrls); cpufreq_freq_transition_end(policy, &freqs, ret !=3D 0); =20 if (ret) @@ -291,7 +291,7 @@ static unsigned int cppc_cpufreq_fast_switch(struct cpu= freq_policy *policy, =20 desired_perf =3D cppc_khz_to_perf(&cpu_data->perf_caps, target_freq); cpu_data->perf_ctrls.desired_perf =3D desired_perf; - ret =3D cppc_set_perf(cpu, &cpu_data->perf_ctrls); + ret =3D cppc_set_perf_ctrls(cpu, &cpu_data->perf_ctrls); =20 if (ret) { pr_debug("Failed to set target on CPU:%d. ret:%d\n", @@ -640,7 +640,7 @@ static int cppc_cpufreq_cpu_init(struct cpufreq_policy = *policy) policy->cur =3D cppc_perf_to_khz(caps, caps->highest_perf); cpu_data->perf_ctrls.desired_perf =3D caps->highest_perf; =20 - ret =3D cppc_set_perf(cpu, &cpu_data->perf_ctrls); + ret =3D cppc_set_perf_ctrls(cpu, &cpu_data->perf_ctrls); if (ret) { pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n", caps->highest_perf, cpu, ret); @@ -666,7 +666,7 @@ static void cppc_cpufreq_cpu_exit(struct cpufreq_policy= *policy) =20 cpu_data->perf_ctrls.desired_perf =3D caps->lowest_perf; =20 - ret =3D cppc_set_perf(cpu, &cpu_data->perf_ctrls); + ret =3D cppc_set_perf_ctrls(cpu, &cpu_data->perf_ctrls); if (ret) pr_debug("Err setting perf value:%d on CPU:%d. ret:%d\n", caps->lowest_perf, cpu, ret); @@ -705,19 +705,19 @@ static int cppc_perf_from_fbctrs(struct cppc_perf_fb_= ctrs *fb_ctrs_t0, return (reference_perf * delta_delivered) / delta_reference; } =20 -static int cppc_get_perf_ctrs_sample(int cpu, - struct cppc_perf_fb_ctrs *fb_ctrs_t0, - struct cppc_perf_fb_ctrs *fb_ctrs_t1) +static int cppc_get_perf_fb_ctrs_sample(int cpu, + struct cppc_perf_fb_ctrs *fb_ctrs_t0, + struct cppc_perf_fb_ctrs *fb_ctrs_t1) { int ret; =20 - ret =3D cppc_get_perf_ctrs(cpu, fb_ctrs_t0); + ret =3D cppc_get_perf_fb_ctrs(cpu, fb_ctrs_t0); if (ret) return ret; =20 udelay(2); /* 2usec delay between sampling */ =20 - return cppc_get_perf_ctrs(cpu, fb_ctrs_t1); + return cppc_get_perf_fb_ctrs(cpu, fb_ctrs_t1); } =20 static unsigned int cppc_cpufreq_get_rate(unsigned int cpu) @@ -735,7 +735,7 @@ static unsigned int cppc_cpufreq_get_rate(unsigned int = cpu) =20 cpufreq_cpu_put(policy); =20 - ret =3D cppc_get_perf_ctrs_sample(cpu, &fb_ctrs_t0, &fb_ctrs_t1); + ret =3D cppc_get_perf_fb_ctrs_sample(cpu, &fb_ctrs_t0, &fb_ctrs_t1); if (ret) { if (ret =3D=3D -EFAULT) /* Any of the associated CPPC regs is 0. */ diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index 20f3d62e7a16..2f2dbeeced65 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -119,7 +119,6 @@ struct cppc_perf_caps { u32 lowest_nonlinear_perf; u32 lowest_freq; u32 nominal_freq; - u32 energy_perf; bool auto_sel; }; =20 @@ -150,8 +149,9 @@ struct cppc_cpudata { extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf); extern int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf); extern int cppc_get_highest_perf(int cpunum, u64 *highest_perf); -extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_c= trs); -extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); +extern int cppc_get_perf_fb_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_f= b_ctrs); +extern int cppc_get_perf_ctrls(int cpu, struct cppc_perf_ctrls *perf_ctrls= ); +extern int cppc_set_perf_ctrls(int cpu, struct cppc_perf_ctrls *perf_ctrls= ); extern int cppc_set_enable(int cpu, bool enable); extern int cppc_get_perf_caps(int cpu, struct cppc_perf_caps *caps); extern bool cppc_perf_ctrs_in_pcc(void); @@ -166,7 +166,7 @@ extern bool cpc_supported_by_cpu(void); extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val); extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val); extern int cppc_get_epp_perf(int cpunum, u64 *epp_perf); -extern int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls, = bool enable); +extern int cppc_set_epp_and_autosel(int cpu, struct cppc_perf_ctrls *perf_= ctrls, bool enable); extern int cppc_set_epp(int cpu, u64 epp_val); extern int cppc_get_auto_act_window(int cpu, u64 *auto_act_window); extern int cppc_set_auto_act_window(int cpu, u64 auto_act_window); @@ -188,11 +188,15 @@ static inline int cppc_get_highest_perf(int cpunum, u= 64 *highest_perf) { return -EOPNOTSUPP; } -static inline int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *pe= rf_fb_ctrs) +static inline int cppc_get_perf_fb_ctrs(int cpu, struct cppc_perf_fb_ctrs = *perf_fb_ctrs) +{ + return -EOPNOTSUPP; +} +static inline int cppc_get_perf_ctrls(int cpu, struct cppc_perf_ctrls *per= f_ctrls) { return -EOPNOTSUPP; } -static inline int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrl= s) +static inline int cppc_set_perf_ctrls(int cpu, struct cppc_perf_ctrls *per= f_ctrls) { return -EOPNOTSUPP; } @@ -232,7 +236,7 @@ static inline int cpc_write_ffh(int cpunum, struct cpc_= reg *reg, u64 val) { return -EOPNOTSUPP; } -static inline int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_= ctrls, bool enable) +static inline int cppc_set_epp_and_autosel(int cpu, struct cppc_perf_ctrls= *perf_ctrls, bool enable) { return -EOPNOTSUPP; } --=20 2.34.1