From nobody Fri Oct 3 23:13:21 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 954742EBDFD; Sat, 23 Aug 2025 16:09:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755965395; cv=none; b=WbM6lh1anBWmXENQvCfs56MIIzyOFe3EndEHmLEKBMMecnqZFwGFoWyLDxKKGyFdu4F8x4VZ1pn26z1fGbmyQYtl6vYLCps6Q4b2AJMzDhmwj+y8G1OrC4xU6EEEyZmjDabPnzRjDlEHgsHBSHsRWDesYKSpP78MAxwlivHreb8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755965395; c=relaxed/simple; bh=e4pFmNtb144n0LaTAeN8GEaLs7wHs40/fTicEW8jzJ4=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=d7R0dhM3SFuiEFVAgDc979Xh5gVM8+0emXaY+jIP26Cq9VKK9KOeWEm71p4nhPWc/dP19+gNF23orveRWBJEdFL6nkRNbXf7+k5RPHlL77mFKiB+JJhnnPh8do/kRrXT+xPOEn0jT0X7Z7B9ZexK012yKxgykYNFBumjAVCPaHU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=VWSe4x0y; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="VWSe4x0y" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57NG9nuf935874; Sat, 23 Aug 2025 11:09:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1755965389; bh=jeHZj0+GD6nZS2XaHswPXodXKw27MWco7dfvktxz7k8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=VWSe4x0y/qBsPqjGz2FmplewW3vsDyupV36fQzVz72reAqH95C2GcykIhb9HkoPu6 McZV53eF+mBTSvaHZXjVlMlm3EdBeyL/HJbmNcA7gwaksg+UAxlivLXZMx1vquy0iw 2EDsDs8CkX6jvyBlZr7QZoam2pMOzOgCAqbOsKN0= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57NG9mcj239285 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Sat, 23 Aug 2025 11:09:48 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Sat, 23 Aug 2025 11:09:48 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Sat, 23 Aug 2025 11:09:48 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57NG9ExM1274978; Sat, 23 Aug 2025 11:09:44 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , Subject: [PATCH v2 06/33] arm64: dts: ti: k3-am62: Enable remote processors at board level Date: Sat, 23 Aug 2025 21:38:34 +0530 Message-ID: <20250823160901.2177841-7-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250823160901.2177841-1-b-padhi@ti.com> References: <20250823160901.2177841-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Remote Processors defined in top-level AM62x SoC dtsi files are incomplete without the memory carveouts and mailbox assignments which are only known at board integration level. Therefore, disable the remote processors at SoC level and enable them at board level where above information is available. Signed-off-by: Beleswar Padhi Reviewed-by: Wadim Egorov Tested-by: Wadim Egorov --- v2: Changelog: 1. Re-ordered patch from [PATCH 21/33] to [PATCH v2 06/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-22-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/b= oot/dts/ti/k3-am62-phycore-som.dtsi index 10e6b5c08619..dcd22ff487ec 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -407,4 +407,5 @@ &wkup_r5fss0_core0 { mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/d= ts/ti/k3-am62-wakeup.dtsi index 6549b7efa656..75aed3a88284 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -128,6 +128,7 @@ wkup_r5fss0_core0: r5f@78000000 { ti,sci =3D <&dmsc>; ti,sci-dev-id =3D <121>; ti,sci-proc-ids =3D <0x01 0xff>; + status =3D "disabled"; }; }; =20 diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am62x-sk-common.dtsi index 13e1d36123d5..840772060cb1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -506,6 +506,7 @@ &wkup_r5fss0_core0 { mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; }; =20 &usbss0 { --=20 2.34.1