From nobody Fri Oct 3 23:12:14 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E6E12F6189; Sat, 23 Aug 2025 16:11:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755965516; cv=none; b=R9qpzuvGS1rs8bNisH7189sqozx2utDFXuseiB8wN28P1j5Evhnwy3p8ExKTolC5jpvLlV9XIDqow88O82QwmfizA1QEMcVv2qt48ysN/NFr0v1vZ/iVxcdAP55OVGjwJoj2jz6PSuTQ26I8ejkUS/kjvgxXI/4ZKU26Mgm7grk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755965516; c=relaxed/simple; bh=Ko01Z4hSRpBLagSuYER8H5RHDiqZsEid50HZwffdP+c=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=tzXhAaHr3Ga46G8uRO4KJvg61kAMhPgXpvmJdc7YVkpN/+80ewMURi64Ufhm8l3Hmk4iq4Jwcxx6LpAKpQsLx4PAXnkRfvPd8lfcL3xjhhs5xvAFdlB4hjq0AdMN88Xt1MhB+Er05IhcNJ15TpVooRoCS77W0sKzdJkeEA6/Nso= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=oxESDF3v; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="oxESDF3v" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57NGBo2H468668; Sat, 23 Aug 2025 11:11:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1755965510; bh=krlVJxioMsDrJW2XlkwyB0bBUJJkPx1oQj9XKMu+vrQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=oxESDF3vCfszk+9xgHKlmWh/m54kTI5SPeRbuCfAvgYRzFuWavTLA4h5hwVRJZGRm 3BC3Z42nebPvRxMpd9gK0YD+ujcn/m/pnTUbNxyzq6PF9LwKMZAt87YxMWENTA6kVc xK97gu9194aFs3Yd4ar4oGIB1JXc2JsKAoP4O6V4= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57NGBoTp3736591 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Sat, 23 Aug 2025 11:11:50 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Sat, 23 Aug 2025 11:11:49 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Sat, 23 Aug 2025 11:11:49 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57NG9Exn1274978; Sat, 23 Aug 2025 11:11:46 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , Subject: [PATCH v2 33/33] arm64: dts: ti: k3-am65-ti-ipc-firmware: Refactor IPC cfg into new dtsi Date: Sat, 23 Aug 2025 21:39:01 +0530 Message-ID: <20250823160901.2177841-34-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250823160901.2177841-1-b-padhi@ti.com> References: <20250823160901.2177841-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The TI K3 AM65 SoCs have multiple programmable remote processors like R5Fs. The TI SDKs for AM65 SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi --- v2: Changelog: 1. Re-ordered patch from [PATCH 32/33] to [PATCH v2 33/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-33-b-padhi@ti.com/ .../boot/dts/ti/k3-am65-iot2050-common.dtsi | 62 ++---------------- .../boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi | 64 +++++++++++++++++++ .../arm64/boot/dts/ti/k3-am654-base-board.dts | 58 +---------------- 3 files changed, 72 insertions(+), 112 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm6= 4/boot/dts/ti/k3-am65-iot2050-common.dtsi index 6cd499ea53e7..19eb4a32e18d 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -59,24 +59,6 @@ mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { no-map; }; =20 - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0 0xa1000000 0 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0 0xa1100000 0 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a2000000 { - reg =3D <0x00 0xa2000000 0x00 0x00200000>; - alignment =3D <0x1000>; - no-map; - }; - /* To reserve the power-on(PON) reason for watchdog reset */ wdt_reset_memory_region: wdt-memory@a2200000 { reg =3D <0x00 0xa2200000 0x00 0x1000>; @@ -582,44 +564,6 @@ &pcie1_rc { reset-gpios =3D <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - interrupts =3D <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-tx =3D <1 0 0>; - ti,mbox-rx =3D <0 0 0>; - }; -}; - -&mailbox0_cluster1 { - status =3D "okay"; - interrupts =3D <432>; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-tx =3D <1 0 0>; - ti,mbox-rx =3D <0 0 0>; - }; -}; - -&mcu_r5fss0 { - status =3D "okay"; -}; - -&mcu_r5fss0_core0 { - memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - status =3D "okay"; -}; - -&mcu_r5fss0_core1 { - memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; - mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; - status =3D "okay"; -}; - &mcu_rti1 { memory-region =3D <&wdt_reset_memory_region>; }; @@ -692,3 +636,9 @@ &mcu_r5fss0 { /* lock-step mode not supported on iot2050 boards */ ti,cluster-mode =3D <0>; }; + +#include "k3-am65-ti-ipc-firmware.dtsi" + +&rtos_ipc_memory_region { + reg =3D <0x00 0xa2000000 0x00 0x00200000>; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi b/arch/arm= 64/boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..514ec4c03056 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on AM65 SoCs + * + * Copyright (C) 2016-2025 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +&reserved_memory { + mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0xa1000000 0 0x100000>; + no-map; + }; + + mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0xa1100000 0 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a2000000 { + reg =3D <0x00 0xa2000000 0x00 0x00100000>; + alignment =3D <0x1000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status =3D "okay"; + interrupts =3D <436>; + + mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { + ti,mbox-tx =3D <1 0 0>; + ti,mbox-rx =3D <0 0 0>; + }; +}; + +&mailbox0_cluster1 { + status =3D "okay"; + interrupts =3D <432>; + + mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { + ti,mbox-tx =3D <1 0 0>; + ti,mbox-rx =3D <0 0 0>; + }; +}; + +&mcu_r5fss0 { + status =3D "okay"; +}; + +&mcu_r5fss0_core0 { + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; + status =3D "okay"; +}; + +&mcu_r5fss0_core1 { + memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, + <&mcu_r5fss0_core1_memory_region>; + mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/bo= ot/dts/ti/k3-am654-base-board.dts index e532ea0a22b2..adb7b8e6d52e 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -61,24 +61,6 @@ mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { reg =3D <0 0xa0100000 0 0xf00000>; no-map; }; - - mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0 0xa1000000 0 0x100000>; - no-map; - }; - - mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0 0xa1100000 0 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a2000000 { - reg =3D <0x00 0xa2000000 0x00 0x00100000>; - alignment =3D <0x1000>; - no-map; - }; }; =20 gpio-keys { @@ -521,44 +503,6 @@ &serdes1 { status =3D "disabled"; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - interrupts =3D <436>; - - mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { - ti,mbox-tx =3D <1 0 0>; - ti,mbox-rx =3D <0 0 0>; - }; -}; - -&mailbox0_cluster1 { - status =3D "okay"; - interrupts =3D <432>; - - mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { - ti,mbox-tx =3D <1 0 0>; - ti,mbox-rx =3D <0 0 0>; - }; -}; - -&mcu_r5fss0 { - status =3D "okay"; -}; - -&mcu_r5fss0_core0 { - memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, - <&mcu_r5fss0_core0_memory_region>; - mboxes =3D <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; - status =3D "okay"; -}; - -&mcu_r5fss0_core1 { - memory-region =3D <&mcu_r5fss0_core1_dma_memory_region>, - <&mcu_r5fss0_core1_memory_region>; - mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>; - status =3D "okay"; -}; - &ospi0 { status =3D "okay"; pinctrl-names =3D "default"; @@ -653,3 +597,5 @@ &dss { &wkup_gpio0 { bootph-all; }; + +#include "k3-am65-ti-ipc-firmware.dtsi" --=20 2.34.1