From nobody Fri Oct 3 23:12:14 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 990792F616F; Sat, 23 Aug 2025 16:11:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755965513; cv=none; b=YN3xEgzIRCnPcOdg402cpU8GlBSdzKTTBpirQ9Eap390tM0H046jcg4jId1ksOZ8bQCRoTrrVg1wtGUOhwJwABJQuAkxY2qBT7u5ZARIyArqzLdvBV/VzWpuXvx3py+bOKm9qHcc13GIKkhOqrDWF6S3CxbWpL78kGt/zn2SUhQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755965513; c=relaxed/simple; bh=i0iWbH4K7PoiPJHsArD5WOpcZyAykt0fjrlgt3HWjLU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=V3prSvS32mTz2VJGV/jb+rBzUR66goMnn0DYImpTDlj1/xJa6owXTcrcUpwA7+FvIiCUlBXFtiQ99viJZqEb0xyxXf6pgRLYzh6/s1lVzpUwjZdlSXrIULaxXMWVtgeRwegRo/yaZ+Il5xrBWbTKyssAVnZneTnICI6rLm3s+kk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=scorjsCg; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="scorjsCg" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57NGBkr8468664; Sat, 23 Aug 2025 11:11:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1755965506; bh=oTRsBFpXgN8clLSqGp/gG9c2LE/U8LLIC5nV7OvCyGw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=scorjsCgwFJXAKoqJ/RaSfaHTFF1AWWsv6rpGoQaepaRjtLdVc6pGr/TyZ02ACuxL fPVIPtdTDIMMvxT8QktK/rm8ucFrSsCpHxua4gZEL6u6P/w+puANtGqRDgWUqVqfQ9 dy+vzt6vrfUpUQfwDYctnMy1QzfsrqHzDhodqqyo= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57NGBkjM240185 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Sat, 23 Aug 2025 11:11:46 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Sat, 23 Aug 2025 11:11:45 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Sat, 23 Aug 2025 11:11:45 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57NG9Exm1274978; Sat, 23 Aug 2025 11:11:41 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , Subject: [PATCH v2 32/33] arm64: dts: ti: k3-am64-ti-ipc-firmware: Refactor IPC cfg into new dtsi Date: Sat, 23 Aug 2025 21:39:00 +0530 Message-ID: <20250823160901.2177841-33-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250823160901.2177841-1-b-padhi@ti.com> References: <20250823160901.2177841-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The TI K3 AM64 SoCs have multiple programmable remote processors like R5F, M4F etc. The TI SDKs for AM64 SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi Reviewed-by: Wadim Egorov # phycore-am64x Tested-by: Wadim Egorov # phycore-am64x --- v2: Changelog: 1. Re-ordered patch from [PATCH 30/33] to [PATCH v2 32/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-31-b-padhi@ti.com/ .../boot/dts/ti/k3-am64-phycore-som.dtsi | 160 +---------------- .../boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi | 162 ++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am642-evm.dts | 156 +---------------- arch/arm64/boot/dts/ti/k3-am642-sk.dts | 156 +---------------- arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi | 156 +---------------- .../arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi | 156 +---------------- 6 files changed, 172 insertions(+), 774 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/b= oot/dts/ti/k3-am64-phycore-som.dtsi index 1efd547b2ba6..af0fed6124e2 100644 --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi @@ -52,60 +52,6 @@ main_r5fss0_core0_memory_region: r5f-memory@a0100000 { reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a2100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a3100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: m4f-memory@a4100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a5000000 { - reg =3D <0x00 0xa5000000 0x00 0x00800000>; - alignment =3D <0x1000>; - no-map; - }; }; =20 leds { @@ -238,67 +184,6 @@ &cpsw_port1 { status =3D "okay"; }; =20 -&mailbox0_cluster2 { - status =3D "okay"; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx =3D <2 0 2>; - ti,mbox-tx =3D <3 0 2>; - }; -}; - -&mailbox0_cluster4 { - status =3D "okay"; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx =3D <2 0 2>; - ti,mbox-tx =3D <3 0 2>; - }; -}; - -&mailbox0_cluster6 { - status =3D "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; -}; - -/* main_timer8 is used by r5f0-0 */ -&main_timer8 { - status =3D "reserved"; -}; - -/* main_timer9 is used by r5f0-1 */ -&main_timer9 { - status =3D "reserved"; -}; - -/* main_timer10 is used by r5f1-0 */ -&main_timer10 { - status =3D "reserved"; -}; - -/* main_timer11 is used by r5f1-1 */ -&main_timer11 { - status =3D "reserved"; -}; - -&main_r5fss0 { - status =3D "okay"; -}; - &main_i2c0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_i2c0_pins_default>; @@ -373,49 +258,6 @@ &main_pktdma { bootph-all; }; =20 -&main_r5fss0 { - status =3D "okay"; -}; - -&main_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; - memory-region =3D <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss0_core1 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; - memory-region =3D <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1 { - status =3D "okay"; -}; - -&main_r5fss1_core0 { - mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; - memory-region =3D <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1_core1 { - mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; - memory-region =3D <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; - status =3D "okay"; -}; - -&mcu_m4fss { - mboxes =3D <&mailbox0_cluster6 &mbox_m4_0>; - memory-region =3D <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status =3D "okay"; -}; - &ospi0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&ospi0_pins_default>; @@ -451,3 +293,5 @@ adc { ti,adc-channels =3D <0 1 2 3 4 5 6 7>; }; }; + +#include "k3-am64-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi b/arch/arm= 64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..847495f76831 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am64-ti-ipc-firmware.dtsi @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on AM64 SoCs + * + * Copyright (C) 2024-2025 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +&reserved_memory { + main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1000000 0x00 0x100000>; + no-map; + }; + + main_r5fss0_core1_memory_region: r5f-memory@a1100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa1100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core0_memory_region: r5f-memory@a2100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa2100000 0x00 0xf00000>; + no-map; + }; + + main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3000000 0x00 0x100000>; + no-map; + }; + + main_r5fss1_core1_memory_region: r5f-memory@a3100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa3100000 0x00 0xf00000>; + no-map; + }; + + mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: m4f-memory@a4100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a5000000 { + reg =3D <0x00 0xa5000000 0x00 0x00800000>; + alignment =3D <0x1000>; + no-map; + }; +}; + +&mailbox0_cluster2 { + status =3D "okay"; + + mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { + ti,mbox-rx =3D <0 0 2>; + ti,mbox-tx =3D <1 0 2>; + }; + + mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { + ti,mbox-rx =3D <2 0 2>; + ti,mbox-tx =3D <3 0 2>; + }; +}; + +&mailbox0_cluster4 { + status =3D "okay"; + + mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { + ti,mbox-rx =3D <0 0 2>; + ti,mbox-tx =3D <1 0 2>; + }; + + mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { + ti,mbox-rx =3D <2 0 2>; + ti,mbox-tx =3D <3 0 2>; + }; +}; + +&mailbox0_cluster6 { + status =3D "okay"; + + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx =3D <0 0 2>; + ti,mbox-tx =3D <1 0 2>; + }; +}; + +/* main_timer8 is used by r5f0-0 */ +&main_timer8 { + status =3D "reserved"; +}; + +/* main_timer9 is used by r5f0-1 */ +&main_timer9 { + status =3D "reserved"; +}; + +/* main_timer10 is used by r5f1-0 */ +&main_timer10 { + status =3D "reserved"; +}; + +/* main_timer11 is used by r5f1-1 */ +&main_timer11 { + status =3D "reserved"; +}; + +&main_r5fss0 { + status =3D "okay"; +}; + +&main_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; + memory-region =3D <&main_r5fss0_core0_dma_memory_region>, + <&main_r5fss0_core0_memory_region>; + status =3D "okay"; +}; + +&main_r5fss0_core1 { + mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; + memory-region =3D <&main_r5fss0_core1_dma_memory_region>, + <&main_r5fss0_core1_memory_region>; + status =3D "okay"; +}; + +&main_r5fss1 { + status =3D "okay"; +}; + +&main_r5fss1_core0 { + mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; + memory-region =3D <&main_r5fss1_core0_dma_memory_region>, + <&main_r5fss1_core0_memory_region>; + status =3D "okay"; +}; + +&main_r5fss1_core1 { + mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; + memory-region =3D <&main_r5fss1_core1_dma_memory_region>, + <&main_r5fss1_core1_memory_region>; + status =3D "okay"; +}; + +&mcu_m4fss { + mboxes =3D <&mailbox0_cluster6 &mbox_m4_0>; + memory-region =3D <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/= ti/k3-am642-evm.dts index 7640c5efe9b8..05b7cdd25a8c 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -64,60 +64,6 @@ main_r5fss0_core0_memory_region: r5f-memory@a0100000 { reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a2100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a3100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: m4f-memory@a4100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a5000000 { - reg =3D <0x00 0xa5000000 0x00 0x00800000>; - alignment =3D <0x1000>; - no-map; - }; }; =20 evm_12v0: regulator-0 { @@ -727,106 +673,6 @@ partition@3fc0000 { }; }; =20 -&mailbox0_cluster2 { - status =3D "okay"; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx =3D <2 0 2>; - ti,mbox-tx =3D <3 0 2>; - }; -}; - -&mailbox0_cluster4 { - status =3D "okay"; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx =3D <2 0 2>; - ti,mbox-tx =3D <3 0 2>; - }; -}; - -&mailbox0_cluster6 { - status =3D "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; -}; - -&main_r5fss0 { - status =3D "okay"; -}; - -&main_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; - memory-region =3D <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss0_core1 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; - memory-region =3D <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1 { - status =3D "okay"; -}; - -&main_r5fss1_core0 { - mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; - memory-region =3D <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1_core1 { - mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; - memory-region =3D <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; - status =3D "okay"; -}; - -&mcu_m4fss { - mboxes =3D <&mailbox0_cluster6 &mbox_m4_0>; - memory-region =3D <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status =3D "okay"; -}; - -/* main_timer8 is used by r5f0-0 */ -&main_timer8 { - status =3D "reserved"; -}; - -/* main_timer9 is used by r5f0-1 */ -&main_timer9 { - status =3D "reserved"; -}; - -/* main_timer10 is used by r5f1-0 */ -&main_timer10 { - status =3D "reserved"; -}; - -/* main_timer11 is used by r5f1-1 */ -&main_timer11 { - status =3D "reserved"; -}; - &serdes_ln_ctrl { idle-states =3D ; }; @@ -890,3 +736,5 @@ &icssg1_iep0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&icssg1_iep0_pins_default>; }; + +#include "k3-am64-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/t= i/k3-am642-sk.dts index fb8bd66f2f94..cc1569a6519b 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -62,60 +62,6 @@ main_r5fss0_core0_memory_region: r5f-memory@a0100000 { reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a2100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a3100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: m4f-memory@a4100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a5000000 { - reg =3D <0x00 0xa5000000 0x00 0x00800000>; - alignment =3D <0x1000>; - no-map; - }; }; =20 vusb_main: regulator-0 { @@ -642,106 +588,6 @@ partition@3fc0000 { }; }; =20 -&mailbox0_cluster2 { - status =3D "okay"; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx =3D <2 0 2>; - ti,mbox-tx =3D <3 0 2>; - }; -}; - -&mailbox0_cluster4 { - status =3D "okay"; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx =3D <2 0 2>; - ti,mbox-tx =3D <3 0 2>; - }; -}; - -&mailbox0_cluster6 { - status =3D "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; -}; - -&main_r5fss0 { - status =3D "okay"; -}; - -&main_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; - memory-region =3D <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss0_core1 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; - memory-region =3D <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1 { - status =3D "okay"; -}; - -&main_r5fss1_core0 { - mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; - memory-region =3D <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1_core1 { - mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; - memory-region =3D <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; - status =3D "okay"; -}; - -&mcu_m4fss { - mboxes =3D <&mailbox0_cluster6 &mbox_m4_0>; - memory-region =3D <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status =3D "okay"; -}; - -/* main_timer8 is used by r5f0-0 */ -&main_timer8 { - status =3D "reserved"; -}; - -/* main_timer9 is used by r5f0-1 */ -&main_timer9 { - status =3D "reserved"; -}; - -/* main_timer10 is used by r5f1-0 */ -&main_timer10 { - status =3D "reserved"; -}; - -/* main_timer11 is used by r5f1-1 */ -&main_timer11 { - status =3D "reserved"; -}; - &ecap0 { status =3D "okay"; /* PWM is available on Pin 1 of header J3 */ @@ -755,3 +601,5 @@ &eqep0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_eqep0_pins_default>; }; + +#include "k3-am64-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi b/arch/arm64/boot/= dts/ti/k3-am642-sr-som.dtsi index 8cb61f831734..ce23362b88c3 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi @@ -126,60 +126,6 @@ main_r5fss0_core0_memory_region: r5f-memory@a0100000 { reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a2100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a3100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: m4f-memory@a4100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a5000000 { - reg =3D <0x00 0xa5000000 0x00 0x00800000>; - alignment =3D <0x1000>; - no-map; - }; }; =20 vdd_mmc0: regulator-vdd-mmc0 { @@ -281,63 +227,6 @@ ethernet_phy2: ethernet-phy@f { }; }; =20 -&mailbox0_cluster2 { - status =3D "okay"; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx =3D <2 0 2>; - ti,mbox-tx =3D <3 0 2>; - }; -}; - -&mailbox0_cluster4 { - status =3D "okay"; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx =3D <2 0 2>; - ti,mbox-tx =3D <3 0 2>; - }; -}; - -&mailbox0_cluster6 { - status =3D "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; -}; - -/* main_timer8 is used by r5f0-0 */ -&main_timer8 { - status =3D "reserved"; -}; - -/* main_timer9 is used by r5f0-1 */ -&main_timer9 { - status =3D "reserved"; -}; - -/* main_timer10 is used by r5f1-0 */ -&main_timer10 { - status =3D "reserved"; -}; - -/* main_timer11 is used by r5f1-1 */ -&main_timer11 { - status =3D "reserved"; -}; - &main_i2c0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_i2c0_default_pins>; @@ -535,49 +424,6 @@ AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* USB0_DRVVBUS.USB= 0_DRVVBUS */ }; }; =20 -&main_r5fss0 { - status =3D "okay"; -}; - -&main_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; - memory-region =3D <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss0_core1 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; - memory-region =3D <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1 { - status =3D "okay"; -}; - -&main_r5fss1_core0 { - mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; - memory-region =3D <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1_core1 { - mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; - memory-region =3D <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; - status =3D "okay"; -}; - -&mcu_m4fss { - mboxes =3D <&mailbox0_cluster6 &mbox_m4_0>; - memory-region =3D <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status =3D "okay"; -}; - /* SoC default UART console */ &main_uart0 { pinctrl-names =3D "default"; @@ -656,3 +502,5 @@ &usbss0 { ti,vbus-divider; ti,usb2-only; }; + +#include "k3-am64-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am642-tqma64xxl.dtsi index 860b79aa5ef5..e752fc8b0a88 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-tqma64xxl.dtsi @@ -42,60 +42,6 @@ main_r5fss0_core0_memory_region: r5f-memory@a0100000 { reg =3D <0x00 0xa0100000 0x00 0xf00000>; no-map; }; - - main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1000000 0x00 0x100000>; - no-map; - }; - - main_r5fss0_core1_memory_region: r5f-memory@a1100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa1100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core0_memory_region: r5f-memory@a2100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa2100000 0x00 0xf00000>; - no-map; - }; - - main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3000000 0x00 0x100000>; - no-map; - }; - - main_r5fss1_core1_memory_region: r5f-memory@a3100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa3100000 0x00 0xf00000>; - no-map; - }; - - mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4000000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: m4f-memory@a4100000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0xa4100000 0x00 0xf00000>; - no-map; - }; - - rtos_ipc_memory_region: ipc-memories@a5000000 { - reg =3D <0x00 0xa5000000 0x00 0x00800000>; - alignment =3D <0x1000>; - no-map; - }; }; =20 reg_1v8: regulator-1v8 { @@ -142,106 +88,6 @@ eeprom1: eeprom@54 { }; }; =20 -&mailbox0_cluster2 { - status =3D "okay"; - - mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; - - mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { - ti,mbox-rx =3D <2 0 2>; - ti,mbox-tx =3D <3 0 2>; - }; -}; - -&mailbox0_cluster4 { - status =3D "okay"; - - mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; - - mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { - ti,mbox-rx =3D <2 0 2>; - ti,mbox-tx =3D <3 0 2>; - }; -}; - -&mailbox0_cluster6 { - status =3D "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx =3D <0 0 2>; - ti,mbox-tx =3D <1 0 2>; - }; -}; - -/* main_timer8 is used by r5f0-0 */ -&main_timer8 { - status =3D "reserved"; -}; - -/* main_timer9 is used by r5f0-1 */ -&main_timer9 { - status =3D "reserved"; -}; - -/* main_timer10 is used by r5f1-0 */ -&main_timer10 { - status =3D "reserved"; -}; - -/* main_timer11 is used by r5f1-1 */ -&main_timer11 { - status =3D "reserved"; -}; - -&main_r5fss0 { - status =3D "okay"; -}; - -&main_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; - memory-region =3D <&main_r5fss0_core0_dma_memory_region>, - <&main_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss0_core1 { - mboxes =3D <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; - memory-region =3D <&main_r5fss0_core1_dma_memory_region>, - <&main_r5fss0_core1_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1 { - status =3D "okay"; -}; - -&main_r5fss1_core0 { - mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; - memory-region =3D <&main_r5fss1_core0_dma_memory_region>, - <&main_r5fss1_core0_memory_region>; - status =3D "okay"; -}; - -&main_r5fss1_core1 { - mboxes =3D <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; - memory-region =3D <&main_r5fss1_core1_dma_memory_region>, - <&main_r5fss1_core1_memory_region>; - status =3D "okay"; -}; - -&mcu_m4fss { - mboxes =3D <&mailbox0_cluster6 &mbox_m4_0>; - memory-region =3D <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status =3D "okay"; -}; - &ospi0 { status =3D "okay"; pinctrl-names =3D "default"; @@ -315,3 +161,5 @@ AM64X_IOPAD(0x0008, PIN_INPUT, 0) >; }; }; + +#include "k3-am64-ti-ipc-firmware.dtsi" --=20 2.34.1