From nobody Fri Oct 3 23:12:14 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2C9A62F548C; Sat, 23 Aug 2025 16:11:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755965507; cv=none; b=RutTJ3snFYvEW0d7tkw1fq7ad3X2kX0np//fdaKP+u1gFCxbT95dIVwy3YbmEmq+5a3gchXrLKdawEffDlcmOHsaduF9XMqFL3s8wSv5sbk3Bi89oPPJhv5Azs6Jn7X9/xZlTFxjLhf0d0vryys2W1UdNpXLnvhVR69ZGEtkuxo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755965507; c=relaxed/simple; bh=B0NBLKlbaed91vWSMrwNG5bzgdqz0h1doVj+zPMaLoY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=uLwOvoJKA5ch2/WJZ0hhp8/UQSpFbCzzR0IAcrpmKrfUvrf8wz7ktmaNCc2cwdI+FUBt8yJDiJ+eQ9B9qv1QbLPek2j9eEP7dOUTID5tT2Yd00bl6ByU356a+DEy4/jpZR8xoye3vC3KRaHTYcwYTEqxjvju2QfdCK3z6Tuaw8s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=TYPyMv7t; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="TYPyMv7t" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57NGBbrS468648; Sat, 23 Aug 2025 11:11:37 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1755965497; bh=kXJu0WetrPlj/J4+7bljAvgxaY+MT+ADGIh8qMvSXMw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=TYPyMv7tTTxhW4W7dmyH8ZInDB2FgzH4dPpbMm52JEl2zQCVxWP6EKYySgPVBt9EN ldRgESW6PcjU9Gj8CF7Z0gN2b0dKwIucFw7UmvwEAOtR5xgnvmbXMsRTU9I6nowHAi XL7cqb4PKnxKmC//dxf8m8J6kC8VUQyTnJutAbyk= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57NGBbTN3512604 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Sat, 23 Aug 2025 11:11:37 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Sat, 23 Aug 2025 11:11:37 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Sat, 23 Aug 2025 11:11:37 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57NG9Exk1274978; Sat, 23 Aug 2025 11:11:33 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , Subject: [PATCH v2 30/33] arm64: dts: ti: k3-am62-ti-ipc-firmware: Refactor IPC cfg into new dtsi Date: Sat, 23 Aug 2025 21:38:58 +0530 Message-ID: <20250823160901.2177841-31-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250823160901.2177841-1-b-padhi@ti.com> References: <20250823160901.2177841-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The TI K3 AM62 SoCs have multiple programmable remote processors like R5F, M4F etc. The TI SDKs for AM62 SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi Reviewed-by: Wadim Egorov # phycore-am62x Tested-by: Wadim Egorov # phycore-am62x --- v2: Changelog: 1. Re-ordered patch from [PATCH 22/33] to [PATCH v2 30/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-23-b-padhi@ti.com/ .../boot/dts/ti/k3-am62-phycore-som.dtsi | 44 +--------------- .../boot/dts/ti/k3-am62-pocketbeagle2.dts | 46 +--------------- .../boot/dts/ti/k3-am62-ti-ipc-firmware.dtsi | 52 +++++++++++++++++++ arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 34 +----------- .../arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 46 +--------------- 5 files changed, 59 insertions(+), 163 deletions(-) create mode 100644 arch/arm64/boot/dts/ti/k3-am62-ti-ipc-firmware.dtsi diff --git a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi b/arch/arm64/b= oot/dts/ti/k3-am62-phycore-som.dtsi index dcd22ff487ec..34b2e8d6bf80 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-phycore-som.dtsi @@ -52,18 +52,6 @@ rtos_ipc_memory_region: ipc-memories@9c800000 { no-map; }; =20 - mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9cb00000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: m4f-memory@9cc00000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9cc00000 0x00 0xe00000>; - no-map; - }; - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9da00000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9da00000 0x00 0x100000>; @@ -245,20 +233,6 @@ cpsw3g_phy1: ethernet-phy@1 { }; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - &main_pktdma { bootph-all; }; @@ -364,13 +338,6 @@ i2c_som_rtc: rtc@52 { }; }; =20 -&mcu_m4fss { - mboxes =3D <&mailbox0_cluster0 &mbox_m4_0>; - memory-region =3D <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status =3D "okay"; -}; - &ospi0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&ospi0_pins_default>; @@ -399,13 +366,4 @@ &sdhci0 { status =3D "okay"; }; =20 -&wkup_r5fss0 { - status =3D "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; - memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status =3D "okay"; -}; +#include "k3-am62-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts b/arch/arm64/= boot/dts/ti/k3-am62-pocketbeagle2.dts index 729901b2ca10..e634abe9e8e6 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts @@ -54,18 +54,6 @@ linux,cma { linux,cma-default; }; =20 - mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9cb00000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: m4f-memory@9cc00000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9cc00000 0x00 0xe00000>; - no-map; - }; - secure_tfa_ddr: tfa@9e780000 { reg =3D <0x00 0x9e780000 0x00 0x80000>; alignment =3D <0x1000>; @@ -298,20 +286,6 @@ &epwm2 { pinctrl-0 =3D <&epwm2_pins_default>; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - &main_uart0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_uart0_pins_default>; @@ -362,24 +336,6 @@ &main_i2c2 { status =3D "okay"; }; =20 -&mcu_m4fss { - mboxes =3D <&mailbox0_cluster0 &mbox_m4_0>; - memory-region =3D <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status =3D "okay"; -}; - -&wkup_r5fss0 { - status =3D "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; - memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - &mcu_pmx0 { wkup_uart0_pins_default: wkup-uart0-default-pins { pinctrl-single,pins =3D < @@ -543,3 +499,5 @@ ldo4_reg: ldo4 { }; }; }; + +#include "k3-am62-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62-ti-ipc-firmware.dtsi b/arch/arm= 64/boot/dts/ti/k3-am62-ti-ipc-firmware.dtsi new file mode 100644 index 000000000000..9376ae91a17f --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am62-ti-ipc-firmware.dtsi @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * Device Tree Source for enabling IPC using TI SDK firmware on AM62 SoCs + * + * Copyright (C) 2021-2025 Texas Instruments Incorporated - https://www.ti= .com/ + */ + +&reserved_memory { + mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9cb00000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: m4f-memory@9cc00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9cc00000 0x00 0xe00000>; + no-map; + }; +}; + +&mailbox0_cluster0 { + status =3D "okay"; + + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; +}; + +&mcu_m4fss { + mboxes =3D <&mailbox0_cluster0 &mbox_m4_0>; + memory-region =3D <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status =3D "okay"; +}; + +&wkup_r5fss0 { + status =3D "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; + memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/d= ts/ti/k3-am62-verdin.dtsi index fa2c1dc738d6..fd83dbc9f37b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -1334,38 +1334,6 @@ &main_i2c3 { status =3D "disabled"; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mcu_m4fss { - mboxes =3D <&mailbox0_cluster0 &mbox_m4_0>; - memory-region =3D <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status =3D "okay"; -}; - -&wkup_r5fss0 { - status =3D "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; - memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - /* Verdin CAN_1 */ &main_mcan0 { pinctrl-names =3D "default"; @@ -1549,3 +1517,5 @@ &wkup_uart0 { pinctrl-0 =3D <&pinctrl_wkup_uart0>; status =3D "disabled"; }; + +#include "k3-am62-ti-ipc-firmware.dtsi" diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am62x-sk-common.dtsi index 03b8e246d8c2..ec2685144558 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -58,18 +58,6 @@ linux,cma { linux,cma-default; }; =20 - mcu_m4fss_dma_memory_region: m4f-dma-memory@9cb00000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9cb00000 0x00 0x100000>; - no-map; - }; - - mcu_m4fss_memory_region: m4f-memory@9cc00000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9cc00000 0x00 0xe00000>; - no-map; - }; - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9da00000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9da00000 0x00 0x100000>; @@ -477,38 +465,6 @@ cpsw3g_phy0: ethernet-phy@0 { }; }; =20 -&mailbox0_cluster0 { - status =3D "okay"; - - mbox_m4_0: mbox-m4-0 { - ti,mbox-rx =3D <0 0 0>; - ti,mbox-tx =3D <1 0 0>; - }; - - mbox_r5_0: mbox-r5-0 { - ti,mbox-rx =3D <2 0 0>; - ti,mbox-tx =3D <3 0 0>; - }; -}; - -&mcu_m4fss { - mboxes =3D <&mailbox0_cluster0 &mbox_m4_0>; - memory-region =3D <&mcu_m4fss_dma_memory_region>, - <&mcu_m4fss_memory_region>; - status =3D "okay"; -}; - -&wkup_r5fss0 { - status =3D "okay"; -}; - -&wkup_r5fss0_core0 { - mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; - memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, - <&wkup_r5fss0_core0_memory_region>; - status =3D "okay"; -}; - &usbss0 { bootph-all; status =3D "okay"; @@ -601,3 +557,5 @@ &epwm1 { pinctrl-0 =3D <&main_epwm1_pins_default>; status =3D "okay"; }; + +#include "k3-am62-ti-ipc-firmware.dtsi" --=20 2.34.1