From nobody Fri Oct 3 23:13:19 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 144262F3622; Sat, 23 Aug 2025 16:11:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755965465; cv=none; b=Tc0OoJOpELdrWdrfwQwyJ+faj+BZeTv3SKzxPolVPDkjhKiHBwVjcbHB4rf5qBrNI/kpJVEhWMv78l598w/jf5JSNB6gGIy8AmZcoYokAmv2I2DBgxDAm0B8iOllE3ol3XIE2YTY6iq286kaCWqB6QMXzdgqLzENJVYIqRKIULs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755965465; c=relaxed/simple; bh=tdjNrBim+bb1N+8vvP7+Y2CQrYd9nak8tR1d7fHPHME=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TQruH8uJCTuQcsXVA/WcqYBzfNk88VH9zgafXfpvMl9Oa/iNpj2cX5dVnqD+oziNwpPYWdmeHLS2AjuJTYvE44Ob4h87pEonCs1XMKt8yUIByZYEU7Kjee9i80NsSqKXzn8IhTX3D8nZB/DRcPvtWpNHH8HDBAJQQdz6VxfsZV8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=eKOFKPSh; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="eKOFKPSh" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57NGAxYE936213; Sat, 23 Aug 2025 11:10:59 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1755965459; bh=4wubkPIHlAQCtCqH8MG9zg1z8L3GCg/PH1flaUEKCdg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=eKOFKPShQ1HGRm6XS9hh6MJmq5LwgUbbIA1KeAccom/fLsZUgZrg24Dn6K9dl7Tbt vcYRCZU5yF0D8tbvA43+9RpM86xKhGJqfDwnVKHyv0REgeiMhS4z92XCKR7OLFovNH ckWIXymwbyQtU3zRh2VcOVXsUQgu7PxSon8tLGtE= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57NGAxDp239768 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Sat, 23 Aug 2025 11:10:59 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Sat, 23 Aug 2025 11:10:58 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Sat, 23 Aug 2025 11:10:58 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57NG9Exb1274978; Sat, 23 Aug 2025 11:10:54 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , Subject: [PATCH v2 21/33] Revert "arm64: dts: ti: k3-j721e-beagleboneai64: Fix reversed C6x carveout locations" Date: Sat, 23 Aug 2025 21:38:49 +0530 Message-ID: <20250823160901.2177841-22-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250823160901.2177841-1-b-padhi@ti.com> References: <20250823160901.2177841-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" This reverts commit 1a314099b7559690fe23cdf3300dfff6e830ecb1. The C6x carveouts are reversed intentionally. This is due to the requirement to keep the DMA memory region as non-cached, however the minimum granular cache region for C6x is 16MB. So, C66x_0 marks the entire C66x_1 16MB memory carveouts as non-cached, and uses the DMA memory region of C66x_1 as its own, and vice-versa. This was also called out in the original commit which introduced these reversed carveouts: "The minimum granularity on the Cache settings on C66x DSP cores is 16MB, so the DMA memory regions are chosen such that they are in separate 16MB regions for each DSP, while reserving a total of 16 MB for each DSP and not changing the overall DSP remoteproc carveouts." Fixes: 1a314099b755 ("arm64: dts: ti: k3-j721e-beagleboneai64: Fix reversed= C6x carveout locations") Signed-off-by: Beleswar Padhi --- v2: Changelog: 1. Re-ordered patch from [PATCH 04/33] to [PATCH v2 21/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-5-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm6= 4/boot/dts/ti/k3-j721e-beagleboneai64.dts index 2ff4cdf1300f..f82966072605 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -123,7 +123,8 @@ main_r5fss1_core1_memory_region: r5f-memory@a5100000 { no-map; }; =20 - c66_0_dma_memory_region: c66-dma-memory@a6000000 { + /* Carveout locations are flipped due to caching */ + c66_1_dma_memory_region: c66-dma-memory@a6000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa6000000 0x00 0x100000>; no-map; @@ -135,7 +136,8 @@ c66_0_memory_region: c66-memory@a6100000 { no-map; }; =20 - c66_1_dma_memory_region: c66-dma-memory@a7000000 { + /* Carveout locations are flipped due to caching */ + c66_0_dma_memory_region: c66-dma-memory@a7000000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0xa7000000 0x00 0x100000>; no-map; --=20 2.34.1