From nobody Fri Oct 3 23:13:18 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 762622EBDE0; Sat, 23 Aug 2025 16:10:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755965453; cv=none; b=YYTt/NuVZYHdflPEp5nTibcXY3Om3wCG0gVfVxQ8vAoy6LBfoP/2pRGu93TTdejiLG8mGXUXgcfOoystvQSq+XFU1K3hv1nnsuuCm/wAk+1avdTJhuivENsKCpNGH2OT14W+a4JWAlWpCY58GlDvqTm9ymUkNW2fpKwkO2RTFI8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755965453; c=relaxed/simple; bh=WcNXw27khYpIWwcP+UcgWcf5uCiEYv3Tk3eUwigGFZw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qi2Ha0fQ5+kwLsFio8fvDCv/6xjTiwZse9BcKKxIXIWoBM/dZ9zWV5sxLZDCcbGayGgY9ObFGYfiXqu/SExXPsbh0tLGGGWkzJ5PZNVGqzsfbxGMTAfLk0wp37mnblOxqGMiFe9roGkd4BuMY3tva2wlbBixjGy83eQdaON4fSs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=NHQspiQW; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="NHQspiQW" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57NGAdcw936150; Sat, 23 Aug 2025 11:10:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1755965439; bh=mQ7/yKmZKo+9zIosa8qFv0soRl7736HFVYfLvsReZLw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=NHQspiQWc/D1X6tIJcEnYtkZanjAJpoLLbOayjUycLrfk2lIoVARmozDIc3KxHq3l xpHpendq/segUv7eCiZzs+qob4qqr4D/aD5Qyk+c2+PXIA6pcOZkY5LkVWuKbmB3VU kJxlm/syRsL6YspJS/ZU8bxTFXG9rB+rlFOc6TYA= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57NGAdGH3512177 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Sat, 23 Aug 2025 11:10:39 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Sat, 23 Aug 2025 11:10:39 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Sat, 23 Aug 2025 11:10:39 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57NG9ExX1274978; Sat, 23 Aug 2025 11:10:34 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , Josua Mayer , Logan Bristol , Matthias Schiffer Subject: [PATCH v2 17/33] arm64: dts: ti: k3-am642-sr-som: Add missing cfg for TI IPC Firmware Date: Sat, 23 Aug 2025 21:38:45 +0530 Message-ID: <20250823160901.2177841-18-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250823160901.2177841-1-b-padhi@ti.com> References: <20250823160901.2177841-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Currently, only R5F remote processors are enabled for k3-am642-sr SoMs, whereas the M4F in MCU domain is disabled. Enable the M4F remote processor at board level by reserving memory carveouts and assigning mailboxes. While at it, reserve the MAIN domain timers that are used by R5F remote processors for ticks to avoid rproc crashes. This config aligns with other AM64 boards and can be refactored out later. Signed-off-by: Beleswar Padhi --- Cc: Josua Mayer Cc: Logan Bristol Cc: Matthias Schiffer Requesting for review/test of this patch. v2: Changelog: 1. Re-ordered patch from [PATCH 27/33] to [PATCH v2 17/33]. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-28-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi | 54 +++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi b/arch/arm64/boot/= dts/ti/k3-am642-sr-som.dtsi index 81adae0a8e55..8cb61f831734 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642-sr-som.dtsi @@ -162,6 +162,24 @@ main_r5fss1_core1_memory_region: r5f-memory@a3100000 { reg =3D <0x00 0xa3100000 0x00 0xf00000>; no-map; }; + + mcu_m4fss_dma_memory_region: m4f-dma-memory@a4000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4000000 0x00 0x100000>; + no-map; + }; + + mcu_m4fss_memory_region: m4f-memory@a4100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa4100000 0x00 0xf00000>; + no-map; + }; + + rtos_ipc_memory_region: ipc-memories@a5000000 { + reg =3D <0x00 0xa5000000 0x00 0x00800000>; + alignment =3D <0x1000>; + no-map; + }; }; =20 vdd_mmc0: regulator-vdd-mmc0 { @@ -291,6 +309,35 @@ mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { }; }; =20 +&mailbox0_cluster6 { + status =3D "okay"; + + mbox_m4_0: mbox-m4-0 { + ti,mbox-rx =3D <0 0 2>; + ti,mbox-tx =3D <1 0 2>; + }; +}; + +/* main_timer8 is used by r5f0-0 */ +&main_timer8 { + status =3D "reserved"; +}; + +/* main_timer9 is used by r5f0-1 */ +&main_timer9 { + status =3D "reserved"; +}; + +/* main_timer10 is used by r5f1-0 */ +&main_timer10 { + status =3D "reserved"; +}; + +/* main_timer11 is used by r5f1-1 */ +&main_timer11 { + status =3D "reserved"; +}; + &main_i2c0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_i2c0_default_pins>; @@ -524,6 +571,13 @@ &main_r5fss1_core1 { status =3D "okay"; }; =20 +&mcu_m4fss { + mboxes =3D <&mailbox0_cluster6 &mbox_m4_0>; + memory-region =3D <&mcu_m4fss_dma_memory_region>, + <&mcu_m4fss_memory_region>; + status =3D "okay"; +}; + /* SoC default UART console */ &main_uart0 { pinctrl-names =3D "default"; --=20 2.34.1