From nobody Fri Oct 3 23:13:19 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 415BD2EA73C; Sat, 23 Aug 2025 16:10:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755965434; cv=none; b=CUdH2apW2zfViPLyLECUR4EgiIf/y5maafaZ0sFlNv9Gbjn3AWFTGDyz5PiJjpa/ordea70gDHIsyr4Nl9WavnYdoKYAg8NJFpDNWHaoHSiR0ovE+HjbtbvU4urW/7hspEKRexf0YvoJKd/Tfh3ke9q0kMzWMjvFtcxs3GlhCfg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755965434; c=relaxed/simple; bh=q9Uxzw21Dunh0okhg+dgt7lPb9tCeG0dHDlzkZzGaSg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=I/zA7LFBy9sdPZRWei9lYrMqlwLvfCFpk2l4ecoZo0nkhqjJ+/kURY/BELmhzvf5+gGJO7VmZie8y7wlZ/typQdFOKNzuPpplkFv/CnVsEhyg2mEJzPQM0XR4CFA7Tbh1o5u3KEWSSF9xtJ69sSkAIiLVVYlflPIYxB+V3zG6Z4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=G3jL19FD; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="G3jL19FD" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57NGAOCU936114; Sat, 23 Aug 2025 11:10:24 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1755965424; bh=BcF6J0GWnLXcPKr5uilhSVH66vVRhVPuGRPj75oeUnw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=G3jL19FDKIPowOT0KaX0YnxbbAYWaJTx893r26UXCSxIK1WiHpKPfwbfI1VJEcL5v 3czgV02RwgE/Zem0F2CjXiaSY+pUc9ZARX+j7wxMqKxsaoYCiyk365T8tA731bYnDn exsY9YL14SR9v2OmsNDEIoEstno4Bh5HqZOcuAsc= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57NGAOBj3736111 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Sat, 23 Aug 2025 11:10:24 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Sat, 23 Aug 2025 11:10:24 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Sat, 23 Aug 2025 11:10:24 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57NG9ExU1274978; Sat, 23 Aug 2025 11:10:19 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , , Hiago De Franco , Francesco Dolcini , Emanuele Ghidoli , Parth Pancholi , Jo_o Paulo Gon_alves Subject: [PATCH v2 14/33] arm64: dts: ti: k3-am62p-verdin: Add missing cfg for TI IPC Firmware Date: Sat, 23 Aug 2025 21:38:42 +0530 Message-ID: <20250823160901.2177841-15-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250823160901.2177841-1-b-padhi@ti.com> References: <20250823160901.2177841-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" The wkup_r5fss0_core0_memory_region is used to store the text/data sections of the Device Manager (DM) firmware itself and is necessary for platform boot. Whereas the wkup_r5fss0_core0_dma_memory_region is used for allocating the Virtio buffers needed for IPC with the DM core which could be optional. The labels were incorrectly used in the k3-am62p-verdin.dtsi file. Correct the firmware memory region label. Currently, only mailbox node is enabled with FIFO assignment. However, there are no users of the enabled mailboxes. Add the missing carveouts for WKUP and MCU R5F remote processors, and enable those by associating to the above carveout and mailboxes. This config aligns with other AM62P boards and can be refactored out later. Signed-off-by: Beleswar Padhi Tested-by: Hiago De Franco # Verdin AM62P --- Cc: Francesco Dolcini Cc: Emanuele Ghidoli Cc: Parth Pancholi Cc: Jo_o Paulo Gon_alves Cc: Hiago De Franco Requesting for a review/test. v2: Changelog: 1. Re-ordered patch from [PATCH 16/33] to [PATCH v2 14/33]. 2. Added T/B tag. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-17-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi | 42 ++++++++++++++++++++- 1 file changed, 41 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi b/arch/arm64/boot/= dts/ti/k3-am62p-verdin.dtsi index 6a04b370d149..0687debf3bbb 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-verdin.dtsi @@ -162,7 +162,25 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000= { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c800000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 { compatible =3D "shared-dma-pool"; reg =3D <0x00 0x9c900000 0x00 0x01e00000>; no-map; @@ -848,6 +866,28 @@ mbox_mcu_r5_0: mbox-mcu-r5-0 { }; }; =20 +&wkup_r5fss0 { + status =3D "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; + memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; + status =3D "okay"; +}; + +&mcu_r5fss0 { + status =3D "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; + status =3D "okay"; +}; + &main0_alert { temperature =3D <95000>; }; --=20 2.34.1