From nobody Fri Oct 3 23:13:20 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D8742EE261; Sat, 23 Aug 2025 16:10:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755965414; cv=none; b=eYMb+6SRrpI6DVcw3uZ6jvqt5vG9XL7FcAAphhZO1zVvHFlAtMorE6+IwIZo6ivGkqK/CTM5/qgUtn3413nDEPiqDMTSBqw3Q0YtJy2o0OiYtGKRlpd1WfZezHOCTdgqgSvhHTiZ/28NPNz5kNc8i0neS83y47NDCGlKfRL2d6Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755965414; c=relaxed/simple; bh=vpHJVcDtxuF+2R9XsGUxp1RHhVmiN2/xqdXZcmXG5eI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=VVL3EwoQB+tfrC8XXTvapU31qjiADnkxL0KK9mUzLV2QDaQDlW0W9xPhj+wXzvWWP9JcqZ962OmsZ8NkdsuuGyTlMwEOJ/8+wWtgfm8EoSmHj2lng/3yPf0yfD5ajiTuGsuf+UtLViD/B15I0IJK7nrGMpKDI00THQCxe4RcoM4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=ThlS8+hF; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="ThlS8+hF" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57NGA6d6936098; Sat, 23 Aug 2025 11:10:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1755965406; bh=nDhNGWCfUb6kTBX0OWO/GZroqWRHbRI1+M8dxVQcqAo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ThlS8+hFLJ6eCq/vYYsRC8f4sfgz1wvO4kMMDaSIYxNUTBKI48Fkn4W2NZfCeosdU dillBcZe4A3BmUhc7KUUWetIE8ddsW7k0vaOwvOh9nbP5BbMkT9Tf1NyxaTs41s579 T9dkEG92HI9lzDwB6bkugpIquqV8GqGoMBtI3PYU= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57NGA6hT4080120 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Sat, 23 Aug 2025 11:10:06 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Sat, 23 Aug 2025 11:10:05 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Sat, 23 Aug 2025 11:10:05 -0500 Received: from uda0510294.dhcp.ti.com (uda0510294.dhcp.ti.com [172.24.234.212]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57NG9ExQ1274978; Sat, 23 Aug 2025 11:10:01 -0500 From: Beleswar Padhi To: , , , , , CC: , , , , , , , Subject: [PATCH v2 10/33] arm64: dts: ti: k3-am62: Enable Mailbox nodes at the board level Date: Sat, 23 Aug 2025 21:38:38 +0530 Message-ID: <20250823160901.2177841-11-b-padhi@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250823160901.2177841-1-b-padhi@ti.com> References: <20250823160901.2177841-1-b-padhi@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Mailbox nodes defined in the top-level AM62x SoC dtsi files are incomplete and may not be functional unless they are extended with a chosen interrupt and connection to a remote processor. As the remote processors depend on memory nodes which are only known at the board integration level, these nodes should only be enabled when provided with the above information. Disable the Mailbox nodes in the dtsi files and only enable the ones that are actually used on a given board. Signed-off-by: Beleswar Padhi --- v2: Changelog: 1. Re-ordered patch from [PATCH 20/33] to [PATCH v2 10/33]. 2. Added new-line before sub-nodes in mailboxes. Link to v1: https://lore.kernel.org/all/20250814223839.3256046-21-b-padhi@ti.com/ arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 1 + arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts | 2 ++ arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi | 2 ++ 3 files changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am62-main.dtsi index 029380dc1a35..40fb3c9e674c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -808,6 +808,7 @@ mailbox0_cluster0: mailbox@29000000 { #mbox-cells =3D <1>; ti,mbox-num-users =3D <4>; ti,mbox-num-fifos =3D <16>; + status =3D "disabled"; }; =20 ecap0: pwm@23100000 { diff --git a/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts b/arch/arm64/= boot/dts/ti/k3-am62-pocketbeagle2.dts index 2e4cf65ee323..2eee5f638e0f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-pocketbeagle2.dts @@ -293,6 +293,8 @@ &epwm2 { }; =20 &mailbox0_cluster0 { + status =3D "okay"; + mbox_m4_0: mbox-m4-0 { ti,mbox-rx =3D <0 0 0>; ti,mbox-tx =3D <1 0 0>; diff --git a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi b/arch/arm64/boot/d= ts/ti/k3-am62-verdin.dtsi index bc2289d74774..bbf2d630b305 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-verdin.dtsi @@ -1317,6 +1317,8 @@ &main_i2c3 { }; =20 &mailbox0_cluster0 { + status =3D "okay"; + mbox_m4_0: mbox-m4-0 { ti,mbox-rx =3D <0 0 0>; ti,mbox-tx =3D <1 0 0>; --=20 2.34.1