From nobody Fri Oct 3 21:52:23 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 28B3E1E5B95; Sat, 23 Aug 2025 15:57:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755964654; cv=none; b=HYZnWZdHiuv5KarkWmCWSA7wRVaI2IqM/UzVJNqwwppW9BCG4+XZxG1vCctEkEkNT2A5EqM3V/ioUgyza0+r84feTlqD+K1pBp7+eqyUXBSTb9YzgRbFCxEOM17J8reSPdraRxGtTlpDpkGcLA+PlHVYqqF6DaVjRY3DwXE22+s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755964654; c=relaxed/simple; bh=E48rlK5pCrVw6V8uNmmSVbPCOsKOLgsmZrs0oelkBrQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KM6hMbpNdZ+zNC4SdHl9H9vDlg3Bu0EEcFld7lvcGFvsGVnBtKaXefMxRIeWUDk9LI9uuu/1bvWqIp9tQ4U1ABHpEuoDrc9qVSL0pSgDVAKbw0enZBbLJTjV3wEehRBOQnfkfov+RDZS3YF9MxgqHzWzrTqSlfWkv6VSiIUT3VU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=e+Ji7du8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="e+Ji7du8" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 32563C4CEF4; Sat, 23 Aug 2025 15:57:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755964653; bh=E48rlK5pCrVw6V8uNmmSVbPCOsKOLgsmZrs0oelkBrQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=e+Ji7du8ydO9/dwQfjyld222hzFjdhjYrIvtRdRNvFPZFHGdxsk5LcRWCE49ic4Vg ObIuK1wHAB2PClhbQreZrtNPQn8788uz5RmBzfuNfPzDoNvQDhAUS8xu/20ZQqdx6A HyOihXrEniYo1JgARPz0OPRETDZWTWAnMsA1BvnyzpWoJ2PIROsU6YtCuWSxEu5cct NPsp0xgLNluknacqGbr88rDYSE/nnaBHwvAOQw1BmyJvnyei6J0sKr1gbpSkxGgyz0 wnvU+2m6s+GOwsU/+KStUvm8RwOTi26kyHuxaBdOtSYjhcmtf7GAPPozK8X/H5qGdO +mdCQiDgDoJyA== From: Jisheng Zhang To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robin Murphy Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 01/14] dmaengine: dma350: Fix CH_CTRL_USESRCTRIGIN definition Date: Sat, 23 Aug 2025 23:39:56 +0800 Message-ID: <20250823154009.25992-2-jszhang@kernel.org> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250823154009.25992-1-jszhang@kernel.org> References: <20250823154009.25992-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Per the arm-dma350 TRM, The CH_CTRL_USESRCTRIGIN is BIT(25). Signed-off-by: Jisheng Zhang Reviewed-by: Robin Murphy --- drivers/dma/arm-dma350.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c index 9efe2ca7d5ec..bf3962f00650 100644 --- a/drivers/dma/arm-dma350.c +++ b/drivers/dma/arm-dma350.c @@ -58,7 +58,7 @@ =20 #define CH_CTRL 0x0c #define CH_CTRL_USEDESTRIGIN BIT(26) -#define CH_CTRL_USESRCTRIGIN BIT(26) +#define CH_CTRL_USESRCTRIGIN BIT(25) #define CH_CTRL_DONETYPE GENMASK(23, 21) #define CH_CTRL_REGRELOADTYPE GENMASK(20, 18) #define CH_CTRL_XTYPE GENMASK(11, 9) --=20 2.50.0 From nobody Fri Oct 3 21:52:23 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B09F92E9746; Sat, 23 Aug 2025 15:57:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755964657; cv=none; b=ersHHJl6FDwumu1wem9t4/3BJuTQ8/gZwFosat3mMF/jn6qgXbAnLWzuW9qlMwTXFRdoLuQK5bhEgUI5yWHkJ3prbkY5slkzOM6pwg8OKN1imp1xIWcoakm/vwSv3wPGK/NHbDox6bZbRhIEP0nUwYXu8tF92xukZxuR4XITbcM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755964657; c=relaxed/simple; bh=Zfl9ZZXjm6An0uUR0To5lSMsxmxg8ZEzVzG4zWVYhDw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SzQu0J+JxKWSQH7V17AACcd7NaHBKQBAHYfEmDwMZimZOjLvEA/3Vzd/hgrlmaT4hxf/aI5GJNyrRTPJtRja6pgn0zkFoCSP6zz08X2q51xBlS5//ArKVM2FzBPw8kQ28L3VUzKl8BZ2Ycm1ZToOfLdJdGDIC+BLbZjy/8ZH5Uw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lM3k5ucP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lM3k5ucP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2ECF9C4CEE7; Sat, 23 Aug 2025 15:57:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755964657; bh=Zfl9ZZXjm6An0uUR0To5lSMsxmxg8ZEzVzG4zWVYhDw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lM3k5ucPnOzynMqVL3YGtLdH/EtayFQWggN/8VKlg7jvTAQjjDDRraeV8LOy3ow2z xJglU4cN2L2IcIghFU0HELbyhflNHTLBwCGZ/gkeAq/QB2k9awwyPXD3DIsy8pCytK nKlqJohWqQogPlzegr1N2WFlwtocnGe7PXs/rQdT+JvBKbdWiGTsW9fdRzPHKSRVYI 6+GdsIX2C6iTaaudAcJJCzscYaIGdtHLI3xhsn9uSyEzcobHs0Z01UuSfYzW8CjYUT SCRk80MzKIB7bGJr4/ZO5ljfZdg7YZzqp6XryYX31YTpGSIZYT4/OPZ8X97r2cvWDx wH8hDxX5Yuv6A== From: Jisheng Zhang To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robin Murphy Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 02/14] dmaengine: dma350: Add missing dch->coherent setting Date: Sat, 23 Aug 2025 23:39:57 +0800 Message-ID: <20250823154009.25992-3-jszhang@kernel.org> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250823154009.25992-1-jszhang@kernel.org> References: <20250823154009.25992-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The dch->coherent setting is missing. Signed-off-by: Jisheng Zhang Reviewed-by: Robin Murphy --- drivers/dma/arm-dma350.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c index bf3962f00650..24cbadc5f076 100644 --- a/drivers/dma/arm-dma350.c +++ b/drivers/dma/arm-dma350.c @@ -587,6 +587,7 @@ static int d350_probe(struct platform_device *pdev) for (int i =3D 0; i < nchan; i++) { struct d350_chan *dch =3D &dmac->channels[i]; =20 + dch->coherent =3D coherent; dch->base =3D base + DMACH(i); writel_relaxed(CH_CMD_CLEAR, dch->base + CH_CMD); =20 --=20 2.50.0 From nobody Fri Oct 3 21:52:23 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E20DD2E9746; Sat, 23 Aug 2025 15:57:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755964661; cv=none; b=JKbOsi5UhbVEl9Lp+JOTtb4XaMFiSxFCnEyw9tSeEl8vrXFH5hTCh92lUcyXBvUGK/JiBmpEdYXzkLUQhNODlZZfduV/zaD0HRY1BEI0MLdpzSQ+ORE9Bb9VjsDZI11ik2mTg20YZPj7NQOu5xq5Lrki4Z1tmAUlxBKnll5I38M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755964661; c=relaxed/simple; bh=mPhmqWPTnMNFn5FnYjezuTC9hDdu0Dic6CcLiRxG/2E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OTVL87oUKrrdi86h3fz/MqObqqPxSqnta8Lsec0v5jXXdmaWr4m40f+6vNSoqjLOO+oshNcT/y3aFe2bbf1VwCHO8TUl5peBpt5H5ITwLE/bYiSVQhIEJilaDEdSrFC0oBFbb1QXlYLwVwJwk/TXjLItRPwep8u3rwpZY/padHs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=uM67uI7C; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uM67uI7C" Received: by smtp.kernel.org (Postfix) with ESMTPSA id ED3F4C4CEE7; Sat, 23 Aug 2025 15:57:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755964660; bh=mPhmqWPTnMNFn5FnYjezuTC9hDdu0Dic6CcLiRxG/2E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uM67uI7CWhJwXbQZuvDsd7Pqr81tTyu7iVzUKwEZICsl8wP4HK5TmAVnm7uV0CroP iAMEVvK7AyoGJn6vCCtyhjoVyXTm9nfRTP8hdR1zYhLKXSgXGSrSpPMQ6s1nUiCgFo P6KHQx3/oaqFCaSjTnBq/MFZUG+MF+fWQcKZ9uNbuyLfQbOt9Oo457b0JN2peKe/IB 3vZAivVjQDRsQR3Kjc+YGcarG316pP99Q9lP7nI5gdtuik1o+yqCi6Z+NPbyuO/qJD RX325lh7j7TfSkj0WLrBA//SZW9T0n0bDr2ZfoW69D9Q1GgIx0IodlvDAUt4XS4JE6 5P7uV1E10pQIg== From: Jisheng Zhang To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robin Murphy Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 03/14] dmaengine: dma350: Check vchan_next_desc() return value Date: Sat, 23 Aug 2025 23:39:58 +0800 Message-ID: <20250823154009.25992-4-jszhang@kernel.org> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250823154009.25992-1-jszhang@kernel.org> References: <20250823154009.25992-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" vchan_next_desc() may return NULL, check its return value. Signed-off-by: Jisheng Zhang --- drivers/dma/arm-dma350.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c index 24cbadc5f076..96350d15ed85 100644 --- a/drivers/dma/arm-dma350.c +++ b/drivers/dma/arm-dma350.c @@ -399,11 +399,14 @@ static enum dma_status d350_tx_status(struct dma_chan= *chan, dma_cookie_t cookie static void d350_start_next(struct d350_chan *dch) { u32 hdr, *reg; + struct virt_dma_desc *vd; =20 - dch->desc =3D to_d350_desc(vchan_next_desc(&dch->vc)); - if (!dch->desc) + vd =3D vchan_next_desc(&dch->vc); + if (!vd) return; =20 + dch->desc =3D to_d350_desc(vd); + list_del(&dch->desc->vd.node); dch->status =3D DMA_IN_PROGRESS; dch->cookie =3D dch->desc->vd.tx.cookie; --=20 2.50.0 From nobody Fri Oct 3 21:52:23 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4D3C2C21E5; Sat, 23 Aug 2025 15:57:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755964664; cv=none; b=mpd+dnXERovzDC4bSE+6wsr3QjX3UbmBJPpBhlvm4XEdn9MjZdPdEcFMp/Q63NtYidtTW4ogi53hav5Et5lR1DfwLuUxan+oN67vgfBjJi1dzPlgTzKd0NvTe5l6sgC5P3UPn5KVeC4u/QSf0dKukeu8NRSH+PlZ1RTloQTBwQk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755964664; c=relaxed/simple; bh=36rUEQ/nyOji+fp5dS6bVayQxIrp+bVWGLzl//eyA4w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gfPknkSaeCQvaeP5RgSCpSDttwX0alBivOfLinqz6VN+qrvtvihBHyw8ci6gtQ6ltgzQKndaS2aRGSKFl3P80jU5rCsKg/9tYXYt1iKRq4CWgP9clly/8wjj++SaUkh9qsz4nqfCf7gfJ7q3vH7wrlLkqfeAwdCEtc0C381i49A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=P57F5fo0; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="P57F5fo0" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4CBA9C116B1; Sat, 23 Aug 2025 15:57:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755964663; bh=36rUEQ/nyOji+fp5dS6bVayQxIrp+bVWGLzl//eyA4w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=P57F5fo0GhLEE06FSqPzmciqCyucHWjCLkal9nX7/kDyGhjbaW5xM/QAmUmmfULJx WufekpRvXthRkhgHHcYgMWgFTLunzBjmJq9/CKP8aSOPcjwy3M7HJgi40AgUERhv8b ilKq9JIR8C0lpHadn+0omYKy/Wn243gANPuQO+lq1gqy0u9EKMYB4vsygF4er96VDT 6Ud3x4BzabV+R6EWH1i9ZLpZtOcO9TaFC99KvAec7Wuz/UEuhabxDKkn7VW5y4B8pq XQ68+BKnzjkldGrv+qXbHAIe9hKh606ZVqE7jmnVbgyhSbjSDMiHQaG9splpYN0Icl EdpMd4Ht7OZDg== From: Jisheng Zhang To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robin Murphy Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 04/14] dmaengine: dma350: Check dma_cookie_status() ret code and txstate Date: Sat, 23 Aug 2025 23:39:59 +0800 Message-ID: <20250823154009.25992-5-jszhang@kernel.org> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250823154009.25992-1-jszhang@kernel.org> References: <20250823154009.25992-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If dma_cookie_status() returns DMA_COMPLETE, we can return immediately. From another side, the txstate is an optional parameter used to get a struct with auxilary transfer status information. When not provided the call to device_tx_status() should return the status of the dma cookie. Return the status of dma cookie when the txstate optional parameter is not provided. Signed-off-by: Jisheng Zhang --- drivers/dma/arm-dma350.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c index 96350d15ed85..17af9bb2a18f 100644 --- a/drivers/dma/arm-dma350.c +++ b/drivers/dma/arm-dma350.c @@ -377,6 +377,8 @@ static enum dma_status d350_tx_status(struct dma_chan *= chan, dma_cookie_t cookie u32 residue =3D 0; =20 status =3D dma_cookie_status(chan, cookie, state); + if (status =3D=3D DMA_COMPLETE || !state) + return status; =20 spin_lock_irqsave(&dch->vc.lock, flags); if (cookie =3D=3D dch->cookie) { --=20 2.50.0 From nobody Fri Oct 3 21:52:23 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 135872EA473; Sat, 23 Aug 2025 15:57:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755964666; cv=none; b=UnGHz1Nc3fU85rbDNIZVXxcSE66OOX2vhVtcrJquByKlML0mylYSGu7pmxl0M1AgEN3Fbsrp70LHNTRRwnlW0FaJNCf71jIQZLvk/0Sv3Tl9j907K3ahcG5/dJ9/kamkt83vxfQTr4o+BYQOunsAS+Yq0UZIe8850LHniL753tE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755964666; c=relaxed/simple; bh=KWbtZGmR1vxk04Y7G5CXe1Skc7vZRzVxtl2PKtoxGyY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=B7jFLWWd9ZwgUah94tmKPktwT3/q2dAGwVSCaouWIzhnzl2F9B11X1a946XQbsOGIv0zx+7rBRKutCluZgJOTvduWJMiujIGVYd+Wb8KRq5AwwIWaFgmsh7YXPn46rXV3+QE2Mc+psBTZ8jPDUvVt8iNH1JPy91A6Tag9789iIo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PLx3ZixC; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PLx3ZixC" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D4589C4CEF4; Sat, 23 Aug 2025 15:57:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755964665; bh=KWbtZGmR1vxk04Y7G5CXe1Skc7vZRzVxtl2PKtoxGyY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PLx3ZixC5rCj5/eVezg1t0UYlvV5cDEBwQ3KALN4OfBsNOpaiYgUkPhVFwcCYXMn4 C0/N2wRGJktQVl3BUuI/i03IoCiElCoxfvGSMUKoD4aPJl+iaTNhDe2GF0voPK55JM DYyEf/xDjGw7N77PITP7rTNS9KF4L31OAJwJivt/DFibuiqgHGDXqO3F2TRrqbcvF/ w6Iv6lWo1mVn1zT5wiy7KxbkCGL7u3KCnBY+FoeC4kny2DmlePZhafN3iwMuUKTPeH FXx51RwVPNE/EOzHdMz70t2+jYa3fGz7dcLdZ/wfkq289ZKrzf2nS++gzHqiA0lFRG 58hmAKxwT+WaA== From: Jisheng Zhang To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robin Murphy Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 05/14] dmaengine: dma350: Register the DMA controller to DT DMA helpers Date: Sat, 23 Aug 2025 23:40:00 +0800 Message-ID: <20250823154009.25992-6-jszhang@kernel.org> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250823154009.25992-1-jszhang@kernel.org> References: <20250823154009.25992-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Register the DMA controller to DT DMA helpers so that we convert a DT phandle to a dma_chan structure. Signed-off-by: Jisheng Zhang --- drivers/dma/arm-dma350.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c index 17af9bb2a18f..6a9f81f941b0 100644 --- a/drivers/dma/arm-dma350.c +++ b/drivers/dma/arm-dma350.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include =20 @@ -635,7 +636,7 @@ static int d350_probe(struct platform_device *pdev) if (ret) return dev_err_probe(dev, ret, "Failed to register DMA device\n"); =20 - return 0; + return of_dma_controller_register(dev->of_node, of_dma_xlate_by_chan_id, = &dmac->dma); } =20 static void d350_remove(struct platform_device *pdev) @@ -643,6 +644,7 @@ static void d350_remove(struct platform_device *pdev) struct d350 *dmac =3D platform_get_drvdata(pdev); =20 dma_async_device_unregister(&dmac->dma); + of_dma_controller_free(pdev->dev.of_node); } =20 static const struct of_device_id d350_of_match[] __maybe_unused =3D { --=20 2.50.0 From nobody Fri Oct 3 21:52:23 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5276B2E92CF; Sat, 23 Aug 2025 15:57:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755964669; cv=none; b=pC6Rgu6LdnysxPM7TQyJAdepCeeuJtr1iWdmu8njf04csnZPOqtvjneDI8sqiIidhNZ3KMVNDFVV5D9vns2YTe1WfE4zI1TymtOpCJJDrRicU/xy2xGyi0KM/XeCChp9X0CSnmil12Phrfg0byKEa/HAlMDX1z94ylWzPZSUs2o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755964669; c=relaxed/simple; bh=s7oD37zLo4PNqPj/0q6kfWR1oTy0TLuV58NqZ0ga9Qc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JWMD4zJPONv3kJCl3fHepkLAA7DyUj8NAeKkcpeq9wWg5HgDUYB+SYP3PNokQ/zdMH09UNnp+hRzuUoxRKwOUeSUacU626q6VPwXKNfyBrbodkY+66GElibOvfygSBF1tj2Iu6GfZvv+QH8sBwznLS22jYLqgFPbecAnxiBShSg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Bhvde1O2; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Bhvde1O2" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C842FC4CEF4; Sat, 23 Aug 2025 15:57:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755964668; bh=s7oD37zLo4PNqPj/0q6kfWR1oTy0TLuV58NqZ0ga9Qc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Bhvde1O2ygcrGguXmvnmR07UkPAS0Jvm3rZz84Is0xnvwI6mvKjfBDnIPWH697qQ2 8jPg4ZpiZ9tQVhZZNAJKf47REOJoPYA7zFwUGoeRdPHHPDpg474Fn1fosF4QLqqdTx lWLtYrfHzjBKgvfx6ZUENfB/Hgm5L7ROOtQ5i1TLh+pMjF69hYS937v2u68xPHWdnP izlL1nucTRV7hYyMuRj+dL7tE8YUSQ70Vrc/9kqXuBloZxNaKb+x0fG5MLdHRPCIAS n9M6fV+OrJaNkDvwq2C3oIxC8se9pgBXiB3NAJZ1pbsVaBWHtVvCDnKQFgwqj50V+r 0UMzEBhIYa+JA== From: Jisheng Zhang To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robin Murphy Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 06/14] dmaengine: dma350: Use dmaenginem_async_device_register Date: Sat, 23 Aug 2025 23:40:01 +0800 Message-ID: <20250823154009.25992-7-jszhang@kernel.org> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250823154009.25992-1-jszhang@kernel.org> References: <20250823154009.25992-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use managed API dmaenginem_async_device_register() to simplify code path. Signed-off-by: Jisheng Zhang --- drivers/dma/arm-dma350.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c index 6a9f81f941b0..36c8bfa67d70 100644 --- a/drivers/dma/arm-dma350.c +++ b/drivers/dma/arm-dma350.c @@ -632,7 +632,7 @@ static int d350_probe(struct platform_device *pdev) =20 platform_set_drvdata(pdev, dmac); =20 - ret =3D dma_async_device_register(&dmac->dma); + ret =3D dmaenginem_async_device_register(&dmac->dma); if (ret) return dev_err_probe(dev, ret, "Failed to register DMA device\n"); =20 @@ -641,9 +641,6 @@ static int d350_probe(struct platform_device *pdev) =20 static void d350_remove(struct platform_device *pdev) { - struct d350 *dmac =3D platform_get_drvdata(pdev); - - dma_async_device_unregister(&dmac->dma); of_dma_controller_free(pdev->dev.of_node); } =20 --=20 2.50.0 From nobody Fri Oct 3 21:52:23 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69B262E7BAC; Sat, 23 Aug 2025 15:57:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755964672; cv=none; b=Gfd1Cs2LwMPUXTclfBkWwsiAFVvMG1q7esIiwIYvWrM7xJ0jjl9L4xy/zo1SmR7wfEp7+r5PAbD0rN6VsqiLUhxdUfP+Na9FacwR8u1lIx+3s9iEx1IMJRGomf6oFLn9AS/YwQQkfEbnUmJC+941ss/Y/Yp9/0oA6wuvUJWNu68= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755964672; c=relaxed/simple; bh=9tnT3V8EMcpHOzCuSJMK/RG61d+XRxnJ3mZs8oaJHDE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eCOBSY+Z+DFsXySkB/TfsWVOebpqrs1OGrtQ1kr65gdevavB4fg9ybshUgYzVLLca53hSO1IBr+lirusVijbSd5UmUmoqKXO61Fz/q2d7l0HzWMorqiu3h3Nf6EVSABk8k4Qw1oJZFB5ZrnAkarD5nTT+kv4TjBoy61YTWjXk2Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=rOFxm+c/; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="rOFxm+c/" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5BF90C113CF; Sat, 23 Aug 2025 15:57:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755964671; bh=9tnT3V8EMcpHOzCuSJMK/RG61d+XRxnJ3mZs8oaJHDE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rOFxm+c/6i/liATaMDBVIBhL8IELGHv+jqCsZrmJCA/HM6ZxX4WbHJpHmk1GGyGVQ Q0PVlJrL8W6rJcZheVVzDIknqphzQk5DxZKT34WKt0D2QeTR1+Rw/1czG7+owmLqUg DT4NtwEr7iVsqHu6KIsk1rPIPAX3I7udvfEUtOx642H2HUYvEeFZm65hgEVoqQUnqI rHBzq3wOrwaQeQ+UH4IGl5sAGS+yabcOVWkiOHod0Cos7+915Q9FaqjWvaz9MwvyK3 7+KDRBC8o9Lno72xbpmVR6uCAOA6FSev48qUu3YVQJQBw4P4X+SnRO8Dg+etHyA9hO QbJLXNVP85+qw== From: Jisheng Zhang To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robin Murphy Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 07/14] dmaengine: dma350: Remove redundant err msg if platform_get_irq() fails Date: Sat, 23 Aug 2025 23:40:02 +0800 Message-ID: <20250823154009.25992-8-jszhang@kernel.org> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250823154009.25992-1-jszhang@kernel.org> References: <20250823154009.25992-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The platform_get_irq() prints an error message if finding the IRQ fails. Signed-off-by: Jisheng Zhang --- drivers/dma/arm-dma350.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c index 36c8bfa67d70..6a6d1c2a3ee6 100644 --- a/drivers/dma/arm-dma350.c +++ b/drivers/dma/arm-dma350.c @@ -604,8 +604,7 @@ static int d350_probe(struct platform_device *pdev) } dch->irq =3D platform_get_irq(pdev, i); if (dch->irq < 0) - return dev_err_probe(dev, dch->irq, - "Failed to get IRQ for channel %d\n", i); + return dch->irq; =20 dch->has_wrap =3D FIELD_GET(CH_CFG_HAS_WRAP, reg); dch->has_trig =3D FIELD_GET(CH_CFG_HAS_TRIGIN, reg) & --=20 2.50.0 From nobody Fri Oct 3 21:52:23 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56F5C2EBB8C; Sat, 23 Aug 2025 15:57:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755964675; cv=none; b=FEToVoB7CwsVbcAWEpNfU6ytPk7eNm/0dK+dV39+Be58Z2ezArfvnQhhuJDybx6nRmKNLhQhW9OHimkwQTExCaiyuQ35nfrz4CPlWsyL5fgXsrD7USX9xlAS4i2yoBpacNscEHX1XHcaV+MQWK93u5AkdOmCe66qLB6DPBOegJA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755964675; c=relaxed/simple; bh=i5iq1Jzx4wxKCJVdwU1cFzHZFmOjbUhc2dS2K/G9ffs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YrNRk2aai6j93PlA+4SJJWStodjxr+tApYGifQkvi1Q+XfHLazgCuQ+yrkOo2yXzZ/8O9k3KwNjE4cVC3p8PrZkCanX1TEw7FeqAw9vlRX1yAZ4FTKNCua0MoaIy/nwVyOwN2DoeTV8sRy/93ApJr83bd/pgoREDQiBOe0grGI8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Fa5LXq6S; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Fa5LXq6S" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B96E7C116C6; Sat, 23 Aug 2025 15:57:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755964675; bh=i5iq1Jzx4wxKCJVdwU1cFzHZFmOjbUhc2dS2K/G9ffs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Fa5LXq6Sdvf5zLpWKdoPenQXRZfWjoFmAk5KBn9AFYPjeZ8xN+4EvQvQ7Bq8aZuPA 9EgVKXW4jqRvAnsJvjUU8RLR0aWNly1q+2BDXmv2aIjxy3S6YK/JA+t6Z2xKNvfUN+ ++dTrVp9duEkjstuQM3twS7uagEnaPmwZ3w1jJKUDP4EmcDtgZbNo79Xi5Uih+pyZ5 XrHHLdDKChDA3ItPzGQOsagxQfgfjmRuNd+9qBz8vRIPA72XwNhT/K0UUV3MIbACuB NmHps0cH2QWqfHGK7fdEKteFX4hzTmQoyMm8LzNEuouYAx8y3I0BXkMpPs9agfErbo xyAYaFaeGTTLg== From: Jisheng Zhang To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robin Murphy Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 08/14] dt-bindings: dma: dma350: Document interrupt-names Date: Sat, 23 Aug 2025 23:40:03 +0800 Message-ID: <20250823154009.25992-9-jszhang@kernel.org> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250823154009.25992-1-jszhang@kernel.org> References: <20250823154009.25992-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, the dma350 driver assumes all channels are available to linux, this may not be true on some platforms, so it's possible no irq(s) for the unavailable channel(s). What's more, the available channels may not be continuous. To handle this case, we'd better get the irq of each channel by name. Signed-off-by: Jisheng Zhang --- Documentation/devicetree/bindings/dma/arm,dma-350.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/arm,dma-350.yaml b/Docum= entation/devicetree/bindings/dma/arm,dma-350.yaml index 429f682f15d8..94752516e51a 100644 --- a/Documentation/devicetree/bindings/dma/arm,dma-350.yaml +++ b/Documentation/devicetree/bindings/dma/arm,dma-350.yaml @@ -32,6 +32,10 @@ properties: - description: Channel 6 interrupt - description: Channel 7 interrupt =20 + interrupt-names: + minItems: 1 + maxItems: 8 + "#dma-cells": const: 1 description: The cell is the trigger input number @@ -40,5 +44,6 @@ required: - compatible - reg - interrupts + - interrupt-names =20 unevaluatedProperties: false --=20 2.50.0 From nobody Fri Oct 3 21:52:23 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E08AB2EBBBE; Sat, 23 Aug 2025 15:57:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755964678; cv=none; b=WeaLRJB9JVUbRX6Hask25J1CpBnJxW4EkYd6n3kH+KXh5RIBZB9E2B7CqSS061IfQKhmaMyiIYBPZ1DcGFgNhDqJlxQcshfQHr4Hvf7QOWJOkv/9H6EOiG/95dDdw8/fmakvHG5SLe6821d097Oz+fgLQISE6b/qI7xkfF86BcM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755964678; c=relaxed/simple; bh=pVQUvqJRO5H4sWHsAkGOHbGYc59txE4I2DP6q9gpHjo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qfBga8hEpWgvgCAhUCgdKWT1gj7ueFhzovjo3sjrQtBmebQTGKyT2ylFnyC/X03aVq+Gxz4OVjXRexgBCUqZRdf7MgWNI1Kq0UONTZ9eUg+hF+5nM1MOKwvRd680+lug7AAImh/bcO9UOS/dgQQjkf7na1TAuL9Ron2HmuVb/CU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KAgudiOB; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KAgudiOB" Received: by smtp.kernel.org (Postfix) with ESMTPSA id AD23BC116B1; Sat, 23 Aug 2025 15:57:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755964677; bh=pVQUvqJRO5H4sWHsAkGOHbGYc59txE4I2DP6q9gpHjo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KAgudiOBs/ydEz7Y58Rut0JazrdH1up7gt3gCUfUXKuw+UnVYsonvPtJg3vchhnM7 kOfA9WWGjieQlf68ZZs7oj6+fL9R9SZOVUssw6YaLnKJrMgiy1D6wRHzp53xyUUk7g r3bbW89sWFMnv7ct8puViNlM/ZeSTPlkS0BHydhJCZPtUo2JuE+kbO0GCXNDZ3ieds jFXzWZSFHnJ+YP72rg4kENj7myFu8IkVw91IiTW0OVtXpKp9l4PWy2EULSjoy7bZXu 7evyz9/jIoOtmeEcqcbkMNNbuUD5LJAeic3whvG1tiGEQ/Ju93efldoTWG0sEygFl8 cDEGXocRB0zXQ== From: Jisheng Zhang To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robin Murphy Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 09/14] dmaengine: dma350: Support dma-channel-mask Date: Sat, 23 Aug 2025 23:40:04 +0800 Message-ID: <20250823154009.25992-10-jszhang@kernel.org> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250823154009.25992-1-jszhang@kernel.org> References: <20250823154009.25992-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Not all channels are available to kernel, we need to support dma-channel-mask. Signed-off-by: Jisheng Zhang --- drivers/dma/arm-dma350.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c index 6a6d1c2a3ee6..72067518799e 100644 --- a/drivers/dma/arm-dma350.c +++ b/drivers/dma/arm-dma350.c @@ -534,7 +534,7 @@ static int d350_probe(struct platform_device *pdev) struct device *dev =3D &pdev->dev; struct d350 *dmac; void __iomem *base; - u32 reg; + u32 reg, dma_chan_mask; int ret, nchan, dw, aw, r, p; bool coherent, memset; =20 @@ -563,6 +563,15 @@ static int d350_probe(struct platform_device *pdev) =20 dmac->nchan =3D nchan; =20 + /* Enable all channels by default */ + dma_chan_mask =3D nchan - 1; + + ret =3D of_property_read_u32(dev->of_node, "dma-channel-mask", &dma_chan_= mask); + if (ret < 0 && (ret !=3D -EINVAL)) { + dev_err(&pdev->dev, "dma-channel-mask is not complete.\n"); + return ret; + } + reg =3D readl_relaxed(base + DMAINFO + DMA_BUILDCFG1); dmac->nreq =3D FIELD_GET(DMA_CFG_NUM_TRIGGER_IN, reg); =20 @@ -592,6 +601,11 @@ static int d350_probe(struct platform_device *pdev) memset =3D true; for (int i =3D 0; i < nchan; i++) { struct d350_chan *dch =3D &dmac->channels[i]; + char ch_irqname[8]; + + /* skip for reserved channels */ + if (!test_bit(i, (unsigned long *)&dma_chan_mask)) + continue; =20 dch->coherent =3D coherent; dch->base =3D base + DMACH(i); @@ -602,7 +616,9 @@ static int d350_probe(struct platform_device *pdev) dev_warn(dev, "No command link support on channel %d\n", i); continue; } - dch->irq =3D platform_get_irq(pdev, i); + + snprintf(ch_irqname, sizeof(ch_irqname), "ch%d", i); + dch->irq =3D platform_get_irq_byname(pdev, ch_irqname); if (dch->irq < 0) return dch->irq; =20 --=20 2.50.0 From nobody Fri Oct 3 21:52:23 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6255D2E888B; Sat, 23 Aug 2025 15:58:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755964681; cv=none; b=E24sm36YvfamarzEvWhAhgUqI5tCVu2UxcO9bsIBG1+X/L0UzVd8P9uYoAdkNgP0WBVjJgbDUtp0wd6w7FXGyRdGJDC1jiN58pNMmTMFRKaq7BUoZPZjL7zoDbYlVJ10tf61+Tcml62lXBG7xnt30aZ6EGsyqNbuGv4NNNQyofA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755964681; c=relaxed/simple; bh=eRF0y8k9gBqSWRmWw3RnFEXQjPJyHVaqp9mzsJmVrLg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=C4yWlV8azvbimhkfdRpAqatHcsDyzh/hIp/gtJ7JnGlEol6rIbjUZPjbFAdObhV+oXdJmo13vYobHYLrNvPla09U519bvu3LVjyf48MU/hC5NfonmFNuTChnfikZl0V/WffJx6ZIUyEDBBi1I0TH/yfr/Ls82d7OqhbmOrWAD14= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CeF86+0y; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CeF86+0y" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 437F9C116B1; Sat, 23 Aug 2025 15:57:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755964681; bh=eRF0y8k9gBqSWRmWw3RnFEXQjPJyHVaqp9mzsJmVrLg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CeF86+0yhUk+/N7XRTd+EFTcLdsIqcBniToNywamiSlQP1uXKp/0hQsEkvclMka1D tdhju8kL5Kn202gKepoh9ZWI3HUVsWs1saxwlFc/YNJrO+5v3xBxqk9jOKcN0fbyUc nNp438NTCjsObF4kh/pTJrkRNQ7ucIiMyBmrcID1SjD/IcLkrwaPzjw4Sx7P4sLtT8 2HWroMI6+Ub+zSjinWZ5ATbQplQDvP9/Kae1D21yKpj4em7gbjqdK+O/YzrKTnT8YL gRKJOOp3m2B/oS+ryY1i2JaLSssdNYhnSVoKtIe4PDjz+989OkmCRnjQKr4NV7yRK2 2dJuTypWkffRA== From: Jisheng Zhang To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robin Murphy Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 10/14] dmaengine: dma350: Alloc command[] from dma pool Date: Sat, 23 Aug 2025 23:40:05 +0800 Message-ID: <20250823154009.25992-11-jszhang@kernel.org> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250823154009.25992-1-jszhang@kernel.org> References: <20250823154009.25992-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, the command[] is allocated with kzalloc(), but dma350 may be used on dma-non-coherent platforms, to prepare the support of peripheral and scatter-gather chaining on both dma-coherent and dma-non-coherent platforms, let's alloc them from dma pool. Signed-off-by: Jisheng Zhang --- drivers/dma/arm-dma350.c | 143 +++++++++++++++++++++++++++++++-------- 1 file changed, 113 insertions(+), 30 deletions(-) diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c index 72067518799e..3d26a1f020df 100644 --- a/drivers/dma/arm-dma350.c +++ b/drivers/dma/arm-dma350.c @@ -4,6 +4,7 @@ =20 #include #include +#include #include #include #include @@ -143,6 +144,7 @@ #define LINK_LINKADDR BIT(30) #define LINK_LINKADDRHI BIT(31) =20 +#define D350_MAX_CMDS 16 =20 enum ch_ctrl_donetype { CH_CTRL_DONETYPE_NONE =3D 0, @@ -169,18 +171,25 @@ enum ch_cfg_memattr { MEMATTR_WB =3D 0xff }; =20 -struct d350_desc { - struct virt_dma_desc vd; - u32 command[16]; +struct d350_sg { + u32 *command; + dma_addr_t phys; u16 xsize; u16 xsizehi; u8 tsz; }; =20 +struct d350_desc { + struct virt_dma_desc vd; + u32 sglen; + struct d350_sg sg[] __counted_by(sglen); +}; + struct d350_chan { struct virt_dma_chan vc; struct d350_desc *desc; void __iomem *base; + struct dma_pool *cmd_pool; int irq; enum dma_status status; dma_cookie_t cookie; @@ -210,7 +219,14 @@ static inline struct d350_desc *to_d350_desc(struct vi= rt_dma_desc *vd) =20 static void d350_desc_free(struct virt_dma_desc *vd) { - kfree(to_d350_desc(vd)); + struct d350_chan *dch =3D to_d350_chan(vd->tx.chan); + struct d350_desc *desc =3D to_d350_desc(vd); + int i; + + for (i =3D 0; i < desc->sglen; i++) + dma_pool_free(dch->cmd_pool, desc->sg[i].command, desc->sg[i].phys); + + kfree(desc); } =20 static struct dma_async_tx_descriptor *d350_prep_memcpy(struct dma_chan *c= han, @@ -218,22 +234,32 @@ static struct dma_async_tx_descriptor *d350_prep_memc= py(struct dma_chan *chan, { struct d350_chan *dch =3D to_d350_chan(chan); struct d350_desc *desc; + struct d350_sg *sg; + dma_addr_t phys; u32 *cmd; =20 - desc =3D kzalloc(sizeof(*desc), GFP_NOWAIT); + desc =3D kzalloc(struct_size(desc, sg, 1), GFP_NOWAIT); if (!desc) return NULL; =20 - desc->tsz =3D __ffs(len | dest | src | (1 << dch->tsz)); - desc->xsize =3D lower_16_bits(len >> desc->tsz); - desc->xsizehi =3D upper_16_bits(len >> desc->tsz); + sg =3D &desc->sg[0]; + sg->command =3D dma_pool_zalloc(dch->cmd_pool, GFP_NOWAIT, &phys); + if (unlikely(!sg->command)) { + kfree(desc); + return NULL; + } + sg->phys =3D phys; + + sg->tsz =3D __ffs(len | dest | src | (1 << dch->tsz)); + sg->xsize =3D lower_16_bits(len >> sg->tsz); + sg->xsizehi =3D upper_16_bits(len >> sg->tsz); =20 - cmd =3D desc->command; + cmd =3D sg->command; cmd[0] =3D LINK_CTRL | LINK_SRCADDR | LINK_SRCADDRHI | LINK_DESADDR | LINK_DESADDRHI | LINK_XSIZE | LINK_XSIZEHI | LINK_SRCTRANSCFG | LINK_DESTRANSCFG | LINK_XADDRINC | LINK_LINKADDR; =20 - cmd[1] =3D FIELD_PREP(CH_CTRL_TRANSIZE, desc->tsz) | + cmd[1] =3D FIELD_PREP(CH_CTRL_TRANSIZE, sg->tsz) | FIELD_PREP(CH_CTRL_XTYPE, CH_CTRL_XTYPE_CONTINUE) | FIELD_PREP(CH_CTRL_DONETYPE, CH_CTRL_DONETYPE_CMD); =20 @@ -241,13 +267,15 @@ static struct dma_async_tx_descriptor *d350_prep_memc= py(struct dma_chan *chan, cmd[3] =3D upper_32_bits(src); cmd[4] =3D lower_32_bits(dest); cmd[5] =3D upper_32_bits(dest); - cmd[6] =3D FIELD_PREP(CH_XY_SRC, desc->xsize) | FIELD_PREP(CH_XY_DES, des= c->xsize); - cmd[7] =3D FIELD_PREP(CH_XY_SRC, desc->xsizehi) | FIELD_PREP(CH_XY_DES, d= esc->xsizehi); + cmd[6] =3D FIELD_PREP(CH_XY_SRC, sg->xsize) | FIELD_PREP(CH_XY_DES, sg->x= size); + cmd[7] =3D FIELD_PREP(CH_XY_SRC, sg->xsizehi) | FIELD_PREP(CH_XY_DES, sg-= >xsizehi); cmd[8] =3D dch->coherent ? TRANSCFG_WB : TRANSCFG_NC; cmd[9] =3D dch->coherent ? TRANSCFG_WB : TRANSCFG_NC; cmd[10] =3D FIELD_PREP(CH_XY_SRC, 1) | FIELD_PREP(CH_XY_DES, 1); cmd[11] =3D 0; =20 + mb(); + return vchan_tx_prep(&dch->vc, &desc->vd, flags); } =20 @@ -256,34 +284,46 @@ static struct dma_async_tx_descriptor *d350_prep_mems= et(struct dma_chan *chan, { struct d350_chan *dch =3D to_d350_chan(chan); struct d350_desc *desc; + struct d350_sg *sg; + dma_addr_t phys; u32 *cmd; =20 - desc =3D kzalloc(sizeof(*desc), GFP_NOWAIT); + desc =3D kzalloc(struct_size(desc, sg, 1), GFP_NOWAIT); if (!desc) return NULL; =20 - desc->tsz =3D __ffs(len | dest | (1 << dch->tsz)); - desc->xsize =3D lower_16_bits(len >> desc->tsz); - desc->xsizehi =3D upper_16_bits(len >> desc->tsz); + sg =3D &desc->sg[0]; + sg->command =3D dma_pool_zalloc(dch->cmd_pool, GFP_NOWAIT, &phys); + if (unlikely(!sg->command)) { + kfree(desc); + return NULL; + } + sg->phys =3D phys; + + sg->tsz =3D __ffs(len | dest | (1 << dch->tsz)); + sg->xsize =3D lower_16_bits(len >> sg->tsz); + sg->xsizehi =3D upper_16_bits(len >> sg->tsz); =20 - cmd =3D desc->command; + cmd =3D sg->command; cmd[0] =3D LINK_CTRL | LINK_DESADDR | LINK_DESADDRHI | LINK_XSIZE | LINK_XSIZEHI | LINK_DESTRANSCFG | LINK_XADDRINC | LINK_FILLVAL | LINK_LINKADDR; =20 - cmd[1] =3D FIELD_PREP(CH_CTRL_TRANSIZE, desc->tsz) | + cmd[1] =3D FIELD_PREP(CH_CTRL_TRANSIZE, sg->tsz) | FIELD_PREP(CH_CTRL_XTYPE, CH_CTRL_XTYPE_FILL) | FIELD_PREP(CH_CTRL_DONETYPE, CH_CTRL_DONETYPE_CMD); =20 cmd[2] =3D lower_32_bits(dest); cmd[3] =3D upper_32_bits(dest); - cmd[4] =3D FIELD_PREP(CH_XY_DES, desc->xsize); - cmd[5] =3D FIELD_PREP(CH_XY_DES, desc->xsizehi); + cmd[4] =3D FIELD_PREP(CH_XY_DES, sg->xsize); + cmd[5] =3D FIELD_PREP(CH_XY_DES, sg->xsizehi); cmd[6] =3D dch->coherent ? TRANSCFG_WB : TRANSCFG_NC; cmd[7] =3D FIELD_PREP(CH_XY_DES, 1); cmd[8] =3D (u8)value * 0x01010101; cmd[9] =3D 0; =20 + mb(); + return vchan_tx_prep(&dch->vc, &desc->vd, flags); } =20 @@ -319,8 +359,9 @@ static int d350_resume(struct dma_chan *chan) =20 static u32 d350_get_residue(struct d350_chan *dch) { - u32 res, xsize, xsizehi, hi_new; - int retries =3D 3; /* 1st time unlucky, 2nd improbable, 3rd just broken */ + u32 res, xsize, xsizehi, linkaddr, linkaddrhi, hi_new; + int i, sgcur, retries =3D 3; /* 1st time unlucky, 2nd improbable, 3rd jus= t broken */ + struct d350_desc *desc =3D dch->desc; =20 hi_new =3D readl_relaxed(dch->base + CH_XSIZEHI); do { @@ -329,10 +370,26 @@ static u32 d350_get_residue(struct d350_chan *dch) hi_new =3D readl_relaxed(dch->base + CH_XSIZEHI); } while (xsizehi !=3D hi_new && --retries); =20 + hi_new =3D readl_relaxed(dch->base + CH_LINKADDRHI); + do { + linkaddrhi =3D hi_new; + linkaddr =3D readl_relaxed(dch->base + CH_LINKADDR); + hi_new =3D readl_relaxed(dch->base + CH_LINKADDRHI); + } while (linkaddrhi !=3D hi_new && --retries); + + for (i =3D 0; i < desc->sglen; i++) { + if (desc->sg[i].phys =3D=3D (((u64)linkaddrhi << 32) | (linkaddr & ~CH_L= INKADDR_EN))) + sgcur =3D i; + } + res =3D FIELD_GET(CH_XY_DES, xsize); res |=3D FIELD_GET(CH_XY_DES, xsizehi) << 16; + res <<=3D desc->sg[sgcur].tsz; + + for (i =3D sgcur + 1; i < desc->sglen; i++) + res +=3D (((u32)desc->sg[i].xsizehi << 16 | desc->sg[i].xsize) << desc->= sg[i].tsz); =20 - return res << dch->desc->tsz; + return res; } =20 static int d350_terminate_all(struct dma_chan *chan) @@ -365,7 +422,13 @@ static void d350_synchronize(struct dma_chan *chan) =20 static u32 d350_desc_bytes(struct d350_desc *desc) { - return ((u32)desc->xsizehi << 16 | desc->xsize) << desc->tsz; + int i; + u32 bytes =3D 0; + + for (i =3D 0; i < desc->sglen; i++) + bytes +=3D (((u32)desc->sg[i].xsizehi << 16 | desc->sg[i].xsize) << desc= ->sg[i].tsz); + + return bytes; } =20 static enum dma_status d350_tx_status(struct dma_chan *chan, dma_cookie_t = cookie, @@ -415,8 +478,8 @@ static void d350_start_next(struct d350_chan *dch) dch->cookie =3D dch->desc->vd.tx.cookie; dch->residue =3D d350_desc_bytes(dch->desc); =20 - hdr =3D dch->desc->command[0]; - reg =3D &dch->desc->command[1]; + hdr =3D dch->desc->sg[0].command[0]; + reg =3D &dch->desc->sg[0].command[1]; =20 if (hdr & LINK_INTREN) writel_relaxed(*reg++, dch->base + CH_INTREN); @@ -512,11 +575,29 @@ static irqreturn_t d350_irq(int irq, void *data) static int d350_alloc_chan_resources(struct dma_chan *chan) { struct d350_chan *dch =3D to_d350_chan(chan); - int ret =3D request_irq(dch->irq, d350_irq, IRQF_SHARED, - dev_name(&dch->vc.chan.dev->device), dch); - if (!ret) - writel_relaxed(CH_INTREN_DONE | CH_INTREN_ERR, dch->base + CH_INTREN); + int ret; + + dch->cmd_pool =3D dma_pool_create(dma_chan_name(chan), + chan->device->dev, + D350_MAX_CMDS * sizeof(u32), + sizeof(u32), 0); + if (!dch->cmd_pool) { + dev_err(chan->device->dev, "No memory for cmd pool\n"); + return -ENOMEM; + } + + ret =3D request_irq(dch->irq, d350_irq, 0, + dev_name(&dch->vc.chan.dev->device), dch); + if (ret < 0) + goto err_irq; + + writel_relaxed(CH_INTREN_DONE | CH_INTREN_ERR, dch->base + CH_INTREN); + + return 0; =20 +err_irq: + dma_pool_destroy(dch->cmd_pool); + dch->cmd_pool =3D NULL; return ret; } =20 @@ -527,6 +608,8 @@ static void d350_free_chan_resources(struct dma_chan *c= han) writel_relaxed(0, dch->base + CH_INTREN); free_irq(dch->irq, dch); vchan_free_chan_resources(&dch->vc); + dma_pool_destroy(dch->cmd_pool); + dch->cmd_pool =3D NULL; } =20 static int d350_probe(struct platform_device *pdev) --=20 2.50.0 From nobody Fri Oct 3 21:52:23 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A71D2EBDFD; Sat, 23 Aug 2025 15:58:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755964684; 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a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755964684; bh=N5iYBEau1mtI9QojhfZLi4171xb9nHXTmzGExxeg6+o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mSk5doxNwSpotdmbzFRyIrXY/6SaYpA8gBMY5agnBIWyXPukIbQulhTDtw6/HtXzW FdNNUe3m9vMetTzjW/C+fZ8X9DBHS9GHiQHVZMY9nHJfS4PM3BxmfejP4IbL5VlW5v c8Uf8L4UPvc7JHUmyOSUKq35sQjCBBM+d9mpfYw498XyW/XV+1U+78oWbiskyzhnVc Adu2VOqrcvyT+RQTQ17SeAT6+gFSXGa2pbSnSykqqXSqdzGQn0iI6j2ZjdbBhI+bfY tXtprE3NNduRmpYgkxfUkZ+0k+4DXOAsv5cEUeCz6V1IfSbVGg62RLfwyoLdIPQuqI OX4Xl1Q6ZtS6A== From: Jisheng Zhang To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robin Murphy Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 11/14] dmaengine: dma350: Support device_prep_slave_sg Date: Sat, 23 Aug 2025 23:40:06 +0800 Message-ID: <20250823154009.25992-12-jszhang@kernel.org> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250823154009.25992-1-jszhang@kernel.org> References: <20250823154009.25992-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add device_prep_slave_sg() callback function so that DMA_MEM_TO_DEV and DMA_DEV_TO_MEM operations in single mode can be supported. Signed-off-by: Jisheng Zhang --- drivers/dma/arm-dma350.c | 180 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 174 insertions(+), 6 deletions(-) diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c index 3d26a1f020df..a285778264b9 100644 --- a/drivers/dma/arm-dma350.c +++ b/drivers/dma/arm-dma350.c @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0 // Copyright (C) 2024-2025 Arm Limited +// Copyright (C) 2025 Synaptics Incorporated // Arm DMA-350 driver =20 #include @@ -98,7 +99,23 @@ =20 #define CH_FILLVAL 0x38 #define CH_SRCTRIGINCFG 0x4c +#define CH_SRCTRIGINMODE GENMASK(11, 10) +#define CH_SRCTRIG_CMD 0 +#define CH_SRCTRIG_DMA_FC 2 +#define CH_SRCTRIG_PERIF_FC 3 +#define CH_SRCTRIGINTYPE GENMASK(9, 8) +#define CH_SRCTRIG_SW_REQ 0 +#define CH_SRCTRIG_HW_REQ 2 +#define CH_SRCTRIG_INTERN_REQ 3 #define CH_DESTRIGINCFG 0x50 +#define CH_DESTRIGINMODE GENMASK(11, 10) +#define CH_DESTRIG_CMD 0 +#define CH_DESTRIG_DMA_FC 2 +#define CH_DESTRIG_PERIF_FC 3 +#define CH_DESTRIGINTYPE GENMASK(9, 8) +#define CH_DESTRIG_SW_REQ 0 +#define CH_DESTRIG_HW_REQ 2 +#define CH_DESTRIG_INTERN_REQ 3 #define CH_LINKATTR 0x70 #define CH_LINK_SHAREATTR GENMASK(9, 8) #define CH_LINK_MEMATTR GENMASK(7, 0) @@ -190,11 +207,13 @@ struct d350_chan { struct d350_desc *desc; void __iomem *base; struct dma_pool *cmd_pool; + struct dma_slave_config config; int irq; enum dma_status status; dma_cookie_t cookie; u32 residue; u8 tsz; + u8 ch; bool has_trig; bool has_wrap; bool coherent; @@ -327,6 +346,144 @@ static struct dma_async_tx_descriptor *d350_prep_mems= et(struct dma_chan *chan, return vchan_tx_prep(&dch->vc, &desc->vd, flags); } =20 +static struct dma_async_tx_descriptor * +d350_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, + unsigned int sg_len, enum dma_transfer_direction dir, + unsigned long flags, void *context) +{ + struct d350_chan *dch =3D to_d350_chan(chan); + dma_addr_t src, dst, phys; + struct d350_desc *desc; + struct scatterlist *sg; + u32 len, trig, *cmd, *la_cmd, tsz; + struct d350_sg *dsg; + int i, j; + + if (unlikely(!is_slave_direction(dir) || !sg_len)) + return NULL; + + desc =3D kzalloc(struct_size(desc, sg, sg_len), GFP_NOWAIT); + if (!desc) + return NULL; + + desc->sglen =3D sg_len; + + if (dir =3D=3D DMA_MEM_TO_DEV) + tsz =3D __ffs(dch->config.dst_addr_width | (1 << dch->tsz)); + else + tsz =3D __ffs(dch->config.src_addr_width | (1 << dch->tsz)); + + for_each_sg(sgl, sg, sg_len, i) { + desc->sg[i].command =3D dma_pool_zalloc(dch->cmd_pool, GFP_NOWAIT, &phys= ); + if (unlikely(!desc->sg[i].command)) + goto err_cmd_alloc; + + desc->sg[i].phys =3D phys; + dsg =3D &desc->sg[i]; + len =3D sg_dma_len(sg); + + if (dir =3D=3D DMA_MEM_TO_DEV) { + src =3D sg_dma_address(sg); + dst =3D dch->config.dst_addr; + trig =3D CH_CTRL_USEDESTRIGIN; + } else { + src =3D dch->config.src_addr; + dst =3D sg_dma_address(sg); + trig =3D CH_CTRL_USESRCTRIGIN; + } + dsg->tsz =3D tsz; + dsg->xsize =3D lower_16_bits(len >> dsg->tsz); + dsg->xsizehi =3D upper_16_bits(len >> dsg->tsz); + + cmd =3D dsg->command; + if (!i) { + cmd[0] =3D LINK_CTRL | LINK_SRCADDR | LINK_SRCADDRHI | LINK_DESADDR | + LINK_DESADDRHI | LINK_XSIZE | LINK_XSIZEHI | LINK_SRCTRANSCFG | + LINK_DESTRANSCFG | LINK_XADDRINC | LINK_LINKADDR; + + cmd[1] =3D FIELD_PREP(CH_CTRL_TRANSIZE, dsg->tsz) | trig | + FIELD_PREP(CH_CTRL_XTYPE, CH_CTRL_XTYPE_CONTINUE); + + cmd[2] =3D lower_32_bits(src); + cmd[3] =3D upper_32_bits(src); + cmd[4] =3D lower_32_bits(dst); + cmd[5] =3D upper_32_bits(dst); + cmd[6] =3D FIELD_PREP(CH_XY_SRC, dsg->xsize) | + FIELD_PREP(CH_XY_DES, dsg->xsize); + cmd[7] =3D FIELD_PREP(CH_XY_SRC, dsg->xsizehi) | + FIELD_PREP(CH_XY_DES, dsg->xsizehi); + if (dir =3D=3D DMA_MEM_TO_DEV) { + cmd[0] |=3D LINK_DESTRIGINCFG; + cmd[8] =3D dch->coherent ? TRANSCFG_WB : TRANSCFG_NC; + cmd[9] =3D TRANSCFG_DEVICE; + cmd[10] =3D FIELD_PREP(CH_XY_SRC, 1); + cmd[11] =3D FIELD_PREP(CH_DESTRIGINMODE, CH_DESTRIG_DMA_FC) | + FIELD_PREP(CH_DESTRIGINTYPE, CH_DESTRIG_HW_REQ); + } else { + cmd[0] |=3D LINK_SRCTRIGINCFG; + cmd[8] =3D TRANSCFG_DEVICE; + cmd[9] =3D dch->coherent ? TRANSCFG_WB : TRANSCFG_NC; + cmd[10] =3D FIELD_PREP(CH_XY_DES, 1); + cmd[11] =3D FIELD_PREP(CH_SRCTRIGINMODE, CH_SRCTRIG_DMA_FC) | + FIELD_PREP(CH_SRCTRIGINTYPE, CH_SRCTRIG_HW_REQ); + } + la_cmd =3D &cmd[12]; + } else { + *la_cmd =3D phys | CH_LINKADDR_EN; + if (i =3D=3D sg_len - 1) { + cmd[0] =3D LINK_CTRL | LINK_SRCADDR | LINK_SRCADDRHI | LINK_DESADDR | + LINK_DESADDRHI | LINK_XSIZE | LINK_XSIZEHI | LINK_LINKADDR; + cmd[1] =3D FIELD_PREP(CH_CTRL_TRANSIZE, dsg->tsz) | trig | + FIELD_PREP(CH_CTRL_XTYPE, CH_CTRL_XTYPE_CONTINUE); + cmd[2] =3D lower_32_bits(src); + cmd[3] =3D upper_32_bits(src); + cmd[4] =3D lower_32_bits(dst); + cmd[5] =3D upper_32_bits(dst); + cmd[6] =3D FIELD_PREP(CH_XY_SRC, dsg->xsize) | + FIELD_PREP(CH_XY_DES, dsg->xsize); + cmd[7] =3D FIELD_PREP(CH_XY_SRC, dsg->xsizehi) | + FIELD_PREP(CH_XY_DES, dsg->xsizehi); + la_cmd =3D &cmd[8]; + } else { + cmd[0] =3D LINK_SRCADDR | LINK_SRCADDRHI | LINK_DESADDR | + LINK_DESADDRHI | LINK_XSIZE | LINK_XSIZEHI | LINK_LINKADDR; + cmd[1] =3D lower_32_bits(src); + cmd[2] =3D upper_32_bits(src); + cmd[3] =3D lower_32_bits(dst); + cmd[4] =3D upper_32_bits(dst); + cmd[5] =3D FIELD_PREP(CH_XY_SRC, dsg->xsize) | + FIELD_PREP(CH_XY_DES, dsg->xsize); + cmd[6] =3D FIELD_PREP(CH_XY_SRC, dsg->xsizehi) | + FIELD_PREP(CH_XY_DES, dsg->xsizehi); + la_cmd =3D &cmd[7]; + } + } + } + + /* the last command */ + *la_cmd =3D 0; + desc->sg[sg_len - 1].command[1] |=3D FIELD_PREP(CH_CTRL_DONETYPE, CH_CTRL= _DONETYPE_CMD); + + mb(); + + return vchan_tx_prep(&dch->vc, &desc->vd, flags); + +err_cmd_alloc: + for (j =3D 0; j < i; j++) + dma_pool_free(dch->cmd_pool, desc->sg[j].command, desc->sg[j].phys); + kfree(desc); + return NULL; +} + +static int d350_slave_config(struct dma_chan *chan, struct dma_slave_confi= g *config) +{ + struct d350_chan *dch =3D to_d350_chan(chan); + + memcpy(&dch->config, config, sizeof(*config)); + + return 0; +} + static int d350_pause(struct dma_chan *chan) { struct d350_chan *dch =3D to_d350_chan(chan); @@ -558,8 +715,9 @@ static irqreturn_t d350_irq(int irq, void *data) writel_relaxed(ch_status, dch->base + CH_STATUS); =20 spin_lock(&dch->vc.lock); - vchan_cookie_complete(vd); if (ch_status & CH_STAT_INTR_DONE) { + vchan_cookie_complete(vd); + dch->desc =3D NULL; dch->status =3D DMA_COMPLETE; dch->residue =3D 0; d350_start_next(dch); @@ -617,7 +775,7 @@ static int d350_probe(struct platform_device *pdev) struct device *dev =3D &pdev->dev; struct d350 *dmac; void __iomem *base; - u32 reg, dma_chan_mask; + u32 reg, dma_chan_mask, trig_bits =3D 0; int ret, nchan, dw, aw, r, p; bool coherent, memset; =20 @@ -637,13 +795,11 @@ static int d350_probe(struct platform_device *pdev) dw =3D 1 << FIELD_GET(DMA_CFG_DATA_WIDTH, reg); aw =3D FIELD_GET(DMA_CFG_ADDR_WIDTH, reg) + 1; =20 - dma_set_mask_and_coherent(dev, DMA_BIT_MASK(aw)); - coherent =3D device_get_dma_attr(dev) =3D=3D DEV_DMA_COHERENT; - dmac =3D devm_kzalloc(dev, struct_size(dmac, channels, nchan), GFP_KERNEL= ); if (!dmac) return -ENOMEM; =20 + dmac->dma.dev =3D dev; dmac->nchan =3D nchan; =20 /* Enable all channels by default */ @@ -655,12 +811,14 @@ static int d350_probe(struct platform_device *pdev) return ret; } =20 + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(aw)); + coherent =3D device_get_dma_attr(dev) =3D=3D DEV_DMA_COHERENT; + reg =3D readl_relaxed(base + DMAINFO + DMA_BUILDCFG1); dmac->nreq =3D FIELD_GET(DMA_CFG_NUM_TRIGGER_IN, reg); =20 dev_dbg(dev, "DMA-350 r%dp%d with %d channels, %d requests\n", r, p, dmac= ->nchan, dmac->nreq); =20 - dmac->dma.dev =3D dev; for (int i =3D min(dw, 16); i > 0; i /=3D 2) { dmac->dma.src_addr_widths |=3D BIT(i); dmac->dma.dst_addr_widths |=3D BIT(i); @@ -692,6 +850,7 @@ static int d350_probe(struct platform_device *pdev) =20 dch->coherent =3D coherent; dch->base =3D base + DMACH(i); + dch->ch =3D i; writel_relaxed(CH_CMD_CLEAR, dch->base + CH_CMD); =20 reg =3D readl_relaxed(dch->base + CH_BUILDCFG1); @@ -711,6 +870,7 @@ static int d350_probe(struct platform_device *pdev) =20 /* Fill is a special case of Wrap */ memset &=3D dch->has_wrap; + trig_bits |=3D dch->has_trig << dch->ch; =20 reg =3D readl_relaxed(dch->base + CH_BUILDCFG0); dch->tsz =3D FIELD_GET(CH_CFG_DATA_WIDTH, reg); @@ -723,6 +883,13 @@ static int d350_probe(struct platform_device *pdev) vchan_init(&dch->vc, &dmac->dma); } =20 + if (trig_bits) { + dmac->dma.directions |=3D (BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV)); + dma_cap_set(DMA_SLAVE, dmac->dma.cap_mask); + dmac->dma.device_config =3D d350_slave_config; + dmac->dma.device_prep_slave_sg =3D d350_prep_slave_sg; + } + if (memset) { dma_cap_set(DMA_MEMSET, dmac->dma.cap_mask); dmac->dma.device_prep_dma_memset =3D d350_prep_memset; @@ -759,5 +926,6 @@ static struct platform_driver d350_driver =3D { module_platform_driver(d350_driver); =20 MODULE_AUTHOR("Robin Murphy "); +MODULE_AUTHOR("Jisheng Zhang "); MODULE_DESCRIPTION("Arm DMA-350 driver"); MODULE_LICENSE("GPL v2"); --=20 2.50.0 From nobody Fri Oct 3 21:52:23 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E0A22E9ED3; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NS8g/RI3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 00324C4CEE7; Sat, 23 Aug 2025 15:58:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755964687; bh=HrsbhSkWMp6y8bCJ4SusuQXu2u6vriVvJmqCSwtzL1I=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NS8g/RI3qlFLDpSb5AXMXrIdsjq9mri2FbmcIuFzwj9eKnPtynIS6tcc2kxVGOAOW MOAQXoNID1/JwFOxUPXQU655Fn3TL/gVXL2vnIWcjH2cGDhoaJEmQ0dNSI227UEE+U 41wFMfjtYsHQFB9SPejrMyCdX4lHO0NPD3iiE7mZROtcxL7fqgjT01w22Vb2f3De5E qu8TSUwXuMw8GhiQFtOEE7ReWTZtvBM9QYAizc3NNczWsUeKMK5VjTCXaXpO3o3245 OKTzwEA69Zw3erkVkpzYCVAWowev1Ev7pMZLpOuMB2hqv/Kz0PZnXWQAUiKY1qsHVO tGVpVcoD+d/Kw== From: Jisheng Zhang To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robin Murphy Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 12/14] dmaengine: dma350: Support device_prep_dma_cyclic Date: Sat, 23 Aug 2025 23:40:07 +0800 Message-ID: <20250823154009.25992-13-jszhang@kernel.org> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250823154009.25992-1-jszhang@kernel.org> References: <20250823154009.25992-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for device_prep_dma_cyclic() callback function to benefit DMA cyclic client, for example ALSA. Signed-off-by: Jisheng Zhang --- drivers/dma/arm-dma350.c | 118 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 113 insertions(+), 5 deletions(-) diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c index a285778264b9..5abb965c6687 100644 --- a/drivers/dma/arm-dma350.c +++ b/drivers/dma/arm-dma350.c @@ -212,8 +212,10 @@ struct d350_chan { enum dma_status status; dma_cookie_t cookie; u32 residue; + u32 periods; u8 tsz; u8 ch; + bool cyclic; bool has_trig; bool has_wrap; bool coherent; @@ -475,6 +477,105 @@ d350_prep_slave_sg(struct dma_chan *chan, struct scat= terlist *sgl, return NULL; } =20 +static struct dma_async_tx_descriptor * +d350_prep_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, + size_t buf_len, size_t period_len, enum dma_transfer_direction dir, + unsigned long flags) +{ + struct d350_chan *dch =3D to_d350_chan(chan); + u32 periods, trig, *cmd, tsz; + dma_addr_t src, dst, phys; + struct d350_desc *desc; + struct d350_sg *dsg; + int i, j; + + if (unlikely(!is_slave_direction(dir) || !buf_len || !period_len)) + return NULL; + + periods =3D buf_len / period_len; + + desc =3D kzalloc(struct_size(desc, sg, periods), GFP_NOWAIT); + if (!desc) + return NULL; + + dch->cyclic =3D true; + desc->sglen =3D periods; + + if (dir =3D=3D DMA_MEM_TO_DEV) + tsz =3D __ffs(dch->config.dst_addr_width | (1 << dch->tsz)); + else + tsz =3D __ffs(dch->config.src_addr_width | (1 << dch->tsz)); + + for (i =3D 0; i < periods; i++) { + desc->sg[i].command =3D dma_pool_zalloc(dch->cmd_pool, GFP_NOWAIT, &phys= ); + if (unlikely(!desc->sg[i].command)) + goto err_cmd_alloc; + + desc->sg[i].phys =3D phys; + dsg =3D &desc->sg[i]; + + if (dir =3D=3D DMA_MEM_TO_DEV) { + src =3D buf_addr + i * period_len; + dst =3D dch->config.dst_addr; + trig =3D CH_CTRL_USEDESTRIGIN; + } else { + src =3D dch->config.src_addr; + dst =3D buf_addr + i * period_len; + trig =3D CH_CTRL_USESRCTRIGIN; + } + dsg->tsz =3D tsz; + dsg->xsize =3D lower_16_bits(period_len >> dsg->tsz); + dsg->xsizehi =3D upper_16_bits(period_len >> dsg->tsz); + + cmd =3D dsg->command; + cmd[0] =3D LINK_CTRL | LINK_SRCADDR | LINK_SRCADDRHI | LINK_DESADDR | + LINK_DESADDRHI | LINK_XSIZE | LINK_XSIZEHI | LINK_SRCTRANSCFG | + LINK_DESTRANSCFG | LINK_XADDRINC | LINK_LINKADDR; + + cmd[1] =3D FIELD_PREP(CH_CTRL_TRANSIZE, dsg->tsz) | + FIELD_PREP(CH_CTRL_XTYPE, CH_CTRL_XTYPE_CONTINUE) | + FIELD_PREP(CH_CTRL_DONETYPE, CH_CTRL_DONETYPE_CMD) | trig; + + cmd[2] =3D lower_32_bits(src); + cmd[3] =3D upper_32_bits(src); + cmd[4] =3D lower_32_bits(dst); + cmd[5] =3D upper_32_bits(dst); + cmd[6] =3D FIELD_PREP(CH_XY_SRC, dsg->xsize) | FIELD_PREP(CH_XY_DES, dsg= ->xsize); + cmd[7] =3D FIELD_PREP(CH_XY_SRC, dsg->xsizehi) | FIELD_PREP(CH_XY_DES, d= sg->xsizehi); + if (dir =3D=3D DMA_MEM_TO_DEV) { + cmd[0] |=3D LINK_DESTRIGINCFG; + cmd[8] =3D dch->coherent ? TRANSCFG_WB : TRANSCFG_NC; + cmd[9] =3D TRANSCFG_DEVICE; + cmd[10] =3D FIELD_PREP(CH_XY_SRC, 1); + cmd[11] =3D FIELD_PREP(CH_DESTRIGINMODE, CH_DESTRIG_DMA_FC) | + FIELD_PREP(CH_DESTRIGINTYPE, CH_DESTRIG_HW_REQ); + } else { + cmd[0] |=3D LINK_SRCTRIGINCFG; + cmd[8] =3D TRANSCFG_DEVICE; + cmd[9] =3D dch->coherent ? TRANSCFG_WB : TRANSCFG_NC; + cmd[10] =3D FIELD_PREP(CH_XY_DES, 1); + cmd[11] =3D FIELD_PREP(CH_SRCTRIGINMODE, CH_SRCTRIG_DMA_FC) | + FIELD_PREP(CH_SRCTRIGINTYPE, CH_SRCTRIG_HW_REQ); + } + + if (i) + desc->sg[i - 1].command[12] =3D phys | CH_LINKADDR_EN; + } + + /* cyclic list */ + desc->sg[periods - 1].command[12] =3D desc->sg[0].phys | CH_LINKADDR_EN; + + mb(); + + return vchan_tx_prep(&dch->vc, &desc->vd, flags); + +err_cmd_alloc: + for (j =3D 0; j < i; j++) + dma_pool_free(dch->cmd_pool, desc->sg[j].command, desc->sg[j].phys); + kfree(desc); + return NULL; +} + static int d350_slave_config(struct dma_chan *chan, struct dma_slave_confi= g *config) { struct d350_chan *dch =3D to_d350_chan(chan); @@ -565,6 +666,7 @@ static int d350_terminate_all(struct dma_chan *chan) } vchan_get_all_descriptors(&dch->vc, &list); list_splice_tail(&list, &dch->vc.desc_terminated); + dch->cyclic =3D false; spin_unlock_irqrestore(&dch->vc.lock, flags); =20 return 0; @@ -716,11 +818,15 @@ static irqreturn_t d350_irq(int irq, void *data) =20 spin_lock(&dch->vc.lock); if (ch_status & CH_STAT_INTR_DONE) { - vchan_cookie_complete(vd); - dch->desc =3D NULL; - dch->status =3D DMA_COMPLETE; - dch->residue =3D 0; - d350_start_next(dch); + if (dch->cyclic) { + vchan_cyclic_callback(vd); + } else { + vchan_cookie_complete(vd); + dch->desc =3D NULL; + dch->status =3D DMA_COMPLETE; + dch->residue =3D 0; + d350_start_next(dch); + } } else { dch->status =3D DMA_ERROR; dch->residue =3D vd->tx_result.residue; @@ -886,8 +992,10 @@ static int d350_probe(struct platform_device *pdev) if (trig_bits) { dmac->dma.directions |=3D (BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV)); dma_cap_set(DMA_SLAVE, dmac->dma.cap_mask); + dma_cap_set(DMA_CYCLIC, dmac->dma.cap_mask); dmac->dma.device_config =3D d350_slave_config; dmac->dma.device_prep_slave_sg =3D d350_prep_slave_sg; + dmac->dma.device_prep_dma_cyclic =3D d350_prep_cyclic; } =20 if (memset) { --=20 2.50.0 From nobody Fri Oct 3 21:52:23 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 423522ED174; Sat, 23 Aug 2025 15:58:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755964690; cv=none; b=u9Tdvb4lVsuKIOV8WNACf4j3TU1iicXkxNO1TO2xQtOTD15yFMsT4x2UkMdOxOOkh30xHZPClvYAy4jdy8UMc2y0aAs+CkcMsJa1ttmN6os0DXrLUkdQ46WIhwQnQ7qpbEyJNFij1MAcfbSMDLSnf4ClBaq5wePUyTqJB5C3ZbM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755964690; c=relaxed/simple; bh=cowF/ZJoltkSCoRh1kuPJeC/P6BXvPb4vKx2M+p/Qgo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XO/3phD5jBmvi9yOUlb1T0cXfLIikp0PPO4r2yYwAD4hCjnqIkp3QzqRtbQen6j50h7T1SHLfGYcVrNinkYwxYY8tn4JUt2tx2Q4zNhrSxBvReORj8SgY0HYte17nFxjBHGeKAw1SMER/QJAwLA6K8h8xJpIuHEhH9rAm6HcJZk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ncOwNiWH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ncOwNiWH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8845AC113CF; Sat, 23 Aug 2025 15:58:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755964690; bh=cowF/ZJoltkSCoRh1kuPJeC/P6BXvPb4vKx2M+p/Qgo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ncOwNiWHrg0uqXBHtqGU2zpI4ptLy+6dHbnRxhBhadiKRfQKlPvQErpYLuBIFi6HE pg1gEutx0p5TDSGh/f4H3G42H8Gg+c1MoenTjJlqkNC+Q1ghCax+8dOBOGjErZ7xs0 sCaaDQ6Bgt3NnISicdp1K6qih8a6Jt60DgOnShrP6N8oNi6MxkI2FIQ8kHM7Vb/vOH LdLBoSqxkFTSsju+K4cmjR6VyiEcxdB9qgfwGWH3xsGZMLT/NLclvQRNPFPXrNFflR KUS96xTbDsi4NZWCa5pefrQv8hG0h0LSmjD2+Wcd2Tc1Nsy3EpKOyMkfR3QmpaBJho yo57AuLjsB96w== From: Jisheng Zhang To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robin Murphy Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 13/14] dt-bindings: dma: dma350: Support ARM DMA-250 Date: Sat, 23 Aug 2025 23:40:08 +0800 Message-ID: <20250823154009.25992-14-jszhang@kernel.org> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250823154009.25992-1-jszhang@kernel.org> References: <20250823154009.25992-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Compared with ARM DMA-350, DMA-250 is a simplified version, they share many common parts, but they do have difference. The difference will be handled in next driver patch, while let's add DMA-250 compatible string to dt-binding now. Signed-off-by: Jisheng Zhang --- Documentation/devicetree/bindings/dma/arm,dma-350.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/arm,dma-350.yaml b/Docum= entation/devicetree/bindings/dma/arm,dma-350.yaml index 94752516e51a..d49736b7de5e 100644 --- a/Documentation/devicetree/bindings/dma/arm,dma-350.yaml +++ b/Documentation/devicetree/bindings/dma/arm,dma-350.yaml @@ -15,6 +15,7 @@ allOf: properties: compatible: const: arm,dma-350 + const: arm,dma-250 =20 reg: items: --=20 2.50.0 From nobody Fri Oct 3 21:52:23 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7DA7B2EE286; Sat, 23 Aug 2025 15:58:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755964693; cv=none; b=o2lFr/ONgPlWB3nfY1Vfj6mRUQGznt5y+39bZqlHZstLN3lXegdMmNshw3KmN8rBtbwnUEuXl3YTRAlIlGYTGD6KJyFycDKOWQaH5Gf7neICs4OupNsvyli+fbTU5a/5AICERqs5nWxfrVXKLxTvWNIWRm95wqJhupt273hWqg8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755964693; c=relaxed/simple; bh=qolTBlBw2PozsN1Fup62X3yppfz8OpcDwdfJ1vDz0f8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GFCQ+V/0x+BvCGYJ7Ckw91w2OwcjmTrx58KHttuyzAHyM6yHfBtibPQNpM4CI6mod6scuGT1zeMhSJs4llMAriaNzRjPVBV7naxtO0ZHDoBWIc8LSEInp7NSx8aAOjg08CXbmSoSnY/V2Pu/hi44SytdLScCNnzaQ5dWGF373C4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WryLcYN9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WryLcYN9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7D700C4CEE7; Sat, 23 Aug 2025 15:58:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755964693; bh=qolTBlBw2PozsN1Fup62X3yppfz8OpcDwdfJ1vDz0f8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WryLcYN9gb5NscqUUE608gxgzI6JFjz2ED7ziimYFhHNAwa26FvmC96TQwqInOJtO klQJv/49Svzx+B12Br464PBTyqRpqu+s08Y8/CpIKU0qBL+wNw/jdD0BfVLKOxeE/d s2Bz2ys+3zQj5TQFsImNpmULzM+mpfuUKNLIKA1Dzl49T1MUE/qBBDuaxvLSq3H4TW D2HSHRfE4jgPKdnvoYIBspufIIffzaQ4POtx8cld/1Cj/PrAbOxQIh1AZ3og6kvubx kg0TLOPYSPiNi3rFhvdXzSJv4yYw7Hb4q7G7QF0t/85C3erBbKNm0+iaOhfbwY25EP 6mSVhzvNjcBjA== From: Jisheng Zhang To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Robin Murphy Cc: dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 14/14] dmaengine: dma350: Support ARM DMA-250 Date: Sat, 23 Aug 2025 23:40:09 +0800 Message-ID: <20250823154009.25992-15-jszhang@kernel.org> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250823154009.25992-1-jszhang@kernel.org> References: <20250823154009.25992-1-jszhang@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Compared with ARM DMA-350, DMA-250 is a simplified version. They share many common parts, but they do have difference. Add DMA-250 support by handling their difference by using different device_prep_slave_sg, device_prep_dma_cyclic and device_prep_dma_memcpy. DMA-250 doesn't support device_prep_dma_memset. Signed-off-by: Jisheng Zhang --- drivers/dma/arm-dma350.c | 444 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 424 insertions(+), 20 deletions(-) diff --git a/drivers/dma/arm-dma350.c b/drivers/dma/arm-dma350.c index 5abb965c6687..0ee807424b7e 100644 --- a/drivers/dma/arm-dma350.c +++ b/drivers/dma/arm-dma350.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 // Copyright (C) 2024-2025 Arm Limited // Copyright (C) 2025 Synaptics Incorporated -// Arm DMA-350 driver +// Arm DMA-350/DMA-250 driver =20 #include #include @@ -16,6 +16,10 @@ #include "dmaengine.h" #include "virt-dma.h" =20 +#define DMANSECCTRL 0x0200 + +#define NSEC_CNTXBASE 0x10 + #define DMAINFO 0x0f00 =20 #define DMA_BUILDCFG0 0xb0 @@ -26,12 +30,16 @@ #define DMA_BUILDCFG1 0xb4 #define DMA_CFG_NUM_TRIGGER_IN GENMASK(8, 0) =20 +#define DMA_BUILDCFG2 0xb8 +#define DMA_CFG_HAS_TZ BIT(8) + #define IIDR 0xc8 #define IIDR_PRODUCTID GENMASK(31, 20) #define IIDR_VARIANT GENMASK(19, 16) #define IIDR_REVISION GENMASK(15, 12) #define IIDR_IMPLEMENTER GENMASK(11, 0) =20 +#define PRODUCTID_DMA250 0x250 #define PRODUCTID_DMA350 0x3a0 #define IMPLEMENTER_ARM 0x43b =20 @@ -140,6 +148,7 @@ #define CH_CFG_HAS_TRIGSEL BIT(7) #define CH_CFG_HAS_TRIGIN BIT(5) #define CH_CFG_HAS_WRAP BIT(1) +#define CH_CFG_HAS_XSIZEHI BIT(0) =20 =20 #define LINK_REGCLEAR BIT(0) @@ -218,6 +227,7 @@ struct d350_chan { bool cyclic; bool has_trig; bool has_wrap; + bool has_xsizehi; bool coherent; }; =20 @@ -225,6 +235,10 @@ struct d350 { struct dma_device dma; int nchan; int nreq; + bool is_d250; + dma_addr_t cntx_mem_paddr; + void *cntx_mem; + u32 cntx_mem_size; struct d350_chan channels[] __counted_by(nchan); }; =20 @@ -238,6 +252,11 @@ static inline struct d350_desc *to_d350_desc(struct vi= rt_dma_desc *vd) return container_of(vd, struct d350_desc, vd); } =20 +static inline struct d350 *to_d350(struct dma_device *dd) +{ + return container_of(dd, struct d350, dma); +} + static void d350_desc_free(struct virt_dma_desc *vd) { struct d350_chan *dch =3D to_d350_chan(vd->tx.chan); @@ -585,6 +604,337 @@ static int d350_slave_config(struct dma_chan *chan, s= truct dma_slave_config *con return 0; } =20 +static struct dma_async_tx_descriptor *d250_prep_memcpy(struct dma_chan *c= han, + dma_addr_t dest, dma_addr_t src, size_t len, unsigned long flags) +{ + struct d350_chan *dch =3D to_d350_chan(chan); + struct d350_desc *desc; + u32 *cmd, *la_cmd, tsz; + int sglen, i; + struct d350_sg *sg; + size_t xfer_len, step_max; + dma_addr_t phys; + + tsz =3D __ffs(len | dest | src | (1 << dch->tsz)); + step_max =3D ((1UL << 16) - 1) << tsz; + sglen =3D DIV_ROUND_UP(len, step_max); + + desc =3D kzalloc(struct_size(desc, sg, sglen), GFP_NOWAIT); + if (!desc) + return NULL; + + desc->sglen =3D sglen; + sglen =3D 0; + while (len) { + sg =3D &desc->sg[sglen]; + xfer_len =3D (len > step_max) ? step_max : len; + sg->tsz =3D __ffs(xfer_len | dest | src | (1 << dch->tsz)); + sg->xsize =3D lower_16_bits(xfer_len >> sg->tsz); + + sg->command =3D dma_pool_zalloc(dch->cmd_pool, GFP_NOWAIT, &phys); + if (unlikely(!sg->command)) + goto err_cmd_alloc; + sg->phys =3D phys; + + cmd =3D sg->command; + if (!sglen) { + cmd[0] =3D LINK_CTRL | LINK_SRCADDR | LINK_DESADDR | + LINK_XSIZE | LINK_SRCTRANSCFG | + LINK_DESTRANSCFG | LINK_XADDRINC | LINK_LINKADDR; + + cmd[1] =3D FIELD_PREP(CH_CTRL_TRANSIZE, sg->tsz) | + FIELD_PREP(CH_CTRL_XTYPE, CH_CTRL_XTYPE_CONTINUE); + + cmd[2] =3D lower_32_bits(src); + cmd[3] =3D lower_32_bits(dest); + cmd[4] =3D FIELD_PREP(CH_XY_SRC, sg->xsize) | + FIELD_PREP(CH_XY_DES, sg->xsize); + cmd[5] =3D dch->coherent ? TRANSCFG_WB : TRANSCFG_NC; + cmd[6] =3D dch->coherent ? TRANSCFG_WB : TRANSCFG_NC; + cmd[7] =3D FIELD_PREP(CH_XY_SRC, 1) | FIELD_PREP(CH_XY_DES, 1); + la_cmd =3D &cmd[8]; + } else { + *la_cmd =3D phys | CH_LINKADDR_EN; + if (len <=3D step_max) { + cmd[0] =3D LINK_CTRL | LINK_XSIZE | LINK_LINKADDR; + cmd[1] =3D FIELD_PREP(CH_CTRL_TRANSIZE, sg->tsz) | + FIELD_PREP(CH_CTRL_XTYPE, CH_CTRL_XTYPE_CONTINUE); + cmd[2] =3D FIELD_PREP(CH_XY_SRC, sg->xsize) | + FIELD_PREP(CH_XY_DES, sg->xsize); + la_cmd =3D &cmd[3]; + } else { + cmd[0] =3D LINK_XSIZE | LINK_LINKADDR; + cmd[1] =3D FIELD_PREP(CH_XY_SRC, sg->xsize) | + FIELD_PREP(CH_XY_DES, sg->xsize); + la_cmd =3D &cmd[2]; + } + } + + len -=3D xfer_len; + src +=3D xfer_len; + dest +=3D xfer_len; + sglen++; + } + + /* the last cmdlink */ + *la_cmd =3D 0; + desc->sg[sglen - 1].command[1] |=3D FIELD_PREP(CH_CTRL_DONETYPE, CH_CTRL_= DONETYPE_CMD); + + mb(); + + return vchan_tx_prep(&dch->vc, &desc->vd, flags); + +err_cmd_alloc: + for (i =3D 0; i < sglen; i++) + dma_pool_free(dch->cmd_pool, desc->sg[i].command, desc->sg[i].phys); + kfree(desc); + return NULL; +} + +static struct dma_async_tx_descriptor * +d250_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl, + unsigned int sg_len, enum dma_transfer_direction dir, + unsigned long flags, void *context) +{ + struct d350_chan *dch =3D to_d350_chan(chan); + dma_addr_t src, dst, phys, mem_addr; + size_t xfer_len, step_max; + u32 len, trig, *cmd, *la_cmd, tsz; + struct d350_desc *desc; + struct scatterlist *sg; + struct d350_sg *dsg; + int i, sglen =3D 0; + + if (unlikely(!is_slave_direction(dir) || !sg_len)) + return NULL; + + if (dir =3D=3D DMA_MEM_TO_DEV) + tsz =3D __ffs(dch->config.dst_addr_width | (1 << dch->tsz)); + else + tsz =3D __ffs(dch->config.src_addr_width | (1 << dch->tsz)); + step_max =3D ((1UL << 16) - 1) << tsz; + + for_each_sg(sgl, sg, sg_len, i) + sglen +=3D DIV_ROUND_UP(sg_dma_len(sg), step_max); + + desc =3D kzalloc(struct_size(desc, sg, sglen), GFP_NOWAIT); + if (!desc) + return NULL; + + desc->sglen =3D sglen; + + sglen =3D 0; + for_each_sg(sgl, sg, sg_len, i) { + len =3D sg_dma_len(sg); + mem_addr =3D sg_dma_address(sg); + + do { + desc->sg[sglen].command =3D dma_pool_zalloc(dch->cmd_pool, GFP_NOWAIT, = &phys); + if (unlikely(!desc->sg[sglen].command)) + goto err_cmd_alloc; + + xfer_len =3D (len > step_max) ? step_max : len; + desc->sg[sglen].phys =3D phys; + dsg =3D &desc->sg[sglen]; + + if (dir =3D=3D DMA_MEM_TO_DEV) { + src =3D mem_addr; + dst =3D dch->config.dst_addr; + trig =3D CH_CTRL_USEDESTRIGIN; + } else { + src =3D dch->config.src_addr; + dst =3D mem_addr; + trig =3D CH_CTRL_USESRCTRIGIN; + } + dsg->tsz =3D tsz; + dsg->xsize =3D lower_16_bits(xfer_len >> dsg->tsz); + + cmd =3D dsg->command; + if (!sglen) { + cmd[0] =3D LINK_CTRL | LINK_SRCADDR | LINK_DESADDR | + LINK_XSIZE | LINK_SRCTRANSCFG | + LINK_DESTRANSCFG | LINK_XADDRINC | LINK_LINKADDR; + + cmd[1] =3D FIELD_PREP(CH_CTRL_TRANSIZE, dsg->tsz) | trig | + FIELD_PREP(CH_CTRL_XTYPE, CH_CTRL_XTYPE_CONTINUE); + + cmd[2] =3D lower_32_bits(src); + cmd[3] =3D lower_32_bits(dst); + cmd[4] =3D FIELD_PREP(CH_XY_SRC, dsg->xsize) | + FIELD_PREP(CH_XY_DES, dsg->xsize); + if (dir =3D=3D DMA_MEM_TO_DEV) { + cmd[0] |=3D LINK_DESTRIGINCFG; + cmd[5] =3D dch->coherent ? TRANSCFG_WB : TRANSCFG_NC; + cmd[6] =3D TRANSCFG_DEVICE; + cmd[7] =3D FIELD_PREP(CH_XY_SRC, 1); + cmd[8] =3D FIELD_PREP(CH_DESTRIGINMODE, CH_DESTRIG_DMA_FC) | + FIELD_PREP(CH_DESTRIGINTYPE, CH_DESTRIG_HW_REQ); + } else { + cmd[0] |=3D LINK_SRCTRIGINCFG; + cmd[5] =3D TRANSCFG_DEVICE; + cmd[6] =3D dch->coherent ? TRANSCFG_WB : TRANSCFG_NC; + cmd[7] =3D FIELD_PREP(CH_XY_DES, 1); + cmd[8] =3D FIELD_PREP(CH_SRCTRIGINMODE, CH_SRCTRIG_DMA_FC) | + FIELD_PREP(CH_SRCTRIGINTYPE, CH_SRCTRIG_HW_REQ); + } + la_cmd =3D &cmd[9]; + } else { + *la_cmd =3D phys | CH_LINKADDR_EN; + if (sglen =3D=3D desc->sglen - 1) { + cmd[0] =3D LINK_CTRL | LINK_SRCADDR | LINK_DESADDR | + LINK_XSIZE | LINK_LINKADDR; + cmd[1] =3D FIELD_PREP(CH_CTRL_TRANSIZE, dsg->tsz) | trig | + FIELD_PREP(CH_CTRL_XTYPE, CH_CTRL_XTYPE_CONTINUE); + cmd[2] =3D lower_32_bits(src); + cmd[3] =3D lower_32_bits(dst); + cmd[4] =3D FIELD_PREP(CH_XY_SRC, dsg->xsize) | + FIELD_PREP(CH_XY_DES, dsg->xsize); + la_cmd =3D &cmd[5]; + } else { + cmd[0] =3D LINK_SRCADDR | LINK_DESADDR | + LINK_XSIZE | LINK_LINKADDR; + cmd[1] =3D lower_32_bits(src); + cmd[2] =3D lower_32_bits(dst); + cmd[3] =3D FIELD_PREP(CH_XY_SRC, dsg->xsize) | + FIELD_PREP(CH_XY_DES, dsg->xsize); + la_cmd =3D &cmd[4]; + } + } + + len -=3D xfer_len; + mem_addr +=3D xfer_len; + sglen++; + } while (len); + } + + /* the last command */ + *la_cmd =3D 0; + desc->sg[sglen - 1].command[1] |=3D FIELD_PREP(CH_CTRL_DONETYPE, CH_CTRL_= DONETYPE_CMD); + + mb(); + + return vchan_tx_prep(&dch->vc, &desc->vd, flags); + +err_cmd_alloc: + for (i =3D 0; i < sglen; i++) + dma_pool_free(dch->cmd_pool, desc->sg[i].command, desc->sg[i].phys); + kfree(desc); + return NULL; +} + +static struct dma_async_tx_descriptor * +d250_prep_cyclic(struct dma_chan *chan, dma_addr_t buf_addr, + size_t buf_len, size_t period_len, enum dma_transfer_direction dir, + unsigned long flags) +{ + struct d350_chan *dch =3D to_d350_chan(chan); + u32 len, periods, trig, *cmd, tsz; + dma_addr_t src, dst, phys, mem_addr; + size_t xfer_len, step_max; + struct d350_desc *desc; + struct scatterlist *sg; + struct d350_sg *dsg; + int sglen, i; + + if (unlikely(!is_slave_direction(dir) || !buf_len || !period_len)) + return NULL; + + if (dir =3D=3D DMA_MEM_TO_DEV) + tsz =3D __ffs(dch->config.dst_addr_width | (1 << dch->tsz)); + else + tsz =3D __ffs(dch->config.src_addr_width | (1 << dch->tsz)); + step_max =3D ((1UL << 16) - 1) << tsz; + + periods =3D buf_len / period_len; + sglen =3D DIV_ROUND_UP(sg_dma_len(sg), step_max) * periods; + + desc =3D kzalloc(struct_size(desc, sg, sglen), GFP_NOWAIT); + if (!desc) + return NULL; + + dch->cyclic =3D true; + dch->periods =3D periods; + desc->sglen =3D sglen; + + sglen =3D 0; + for (i =3D 0; i < periods; i++) { + len =3D period_len; + mem_addr =3D buf_addr + i * period_len; + do { + desc->sg[sglen].command =3D dma_pool_zalloc(dch->cmd_pool, GFP_NOWAIT, = &phys); + if (unlikely(!desc->sg[sglen].command)) + goto err_cmd_alloc; + + xfer_len =3D (len > step_max) ? step_max : len; + desc->sg[sglen].phys =3D phys; + dsg =3D &desc->sg[sglen]; + + if (dir =3D=3D DMA_MEM_TO_DEV) { + src =3D mem_addr; + dst =3D dch->config.dst_addr; + trig =3D CH_CTRL_USEDESTRIGIN; + } else { + src =3D dch->config.src_addr; + dst =3D mem_addr; + trig =3D CH_CTRL_USESRCTRIGIN; + } + dsg->tsz =3D tsz; + dsg->xsize =3D lower_16_bits(xfer_len >> dsg->tsz); + + cmd =3D dsg->command; + cmd[0] =3D LINK_CTRL | LINK_SRCADDR | LINK_DESADDR | + LINK_XSIZE | LINK_SRCTRANSCFG | + LINK_DESTRANSCFG | LINK_XADDRINC | LINK_LINKADDR; + + cmd[1] =3D FIELD_PREP(CH_CTRL_TRANSIZE, dsg->tsz) | + FIELD_PREP(CH_CTRL_XTYPE, CH_CTRL_XTYPE_CONTINUE) | + FIELD_PREP(CH_CTRL_DONETYPE, CH_CTRL_DONETYPE_CMD) | trig; + + cmd[2] =3D lower_32_bits(src); + cmd[3] =3D lower_32_bits(dst); + cmd[4] =3D FIELD_PREP(CH_XY_SRC, dsg->xsize) | + FIELD_PREP(CH_XY_DES, dsg->xsize); + if (dir =3D=3D DMA_MEM_TO_DEV) { + cmd[0] |=3D LINK_DESTRIGINCFG; + cmd[5] =3D dch->coherent ? TRANSCFG_WB : TRANSCFG_NC; + cmd[6] =3D TRANSCFG_DEVICE; + cmd[7] =3D FIELD_PREP(CH_XY_SRC, 1); + cmd[8] =3D FIELD_PREP(CH_DESTRIGINMODE, CH_DESTRIG_DMA_FC) | + FIELD_PREP(CH_DESTRIGINTYPE, CH_DESTRIG_HW_REQ); + } else { + cmd[0] |=3D LINK_SRCTRIGINCFG; + cmd[5] =3D TRANSCFG_DEVICE; + cmd[6] =3D dch->coherent ? TRANSCFG_WB : TRANSCFG_NC; + cmd[7] =3D FIELD_PREP(CH_XY_DES, 1); + cmd[8] =3D FIELD_PREP(CH_SRCTRIGINMODE, CH_SRCTRIG_DMA_FC) | + FIELD_PREP(CH_SRCTRIGINTYPE, CH_SRCTRIG_HW_REQ); + } + + if (sglen) + desc->sg[sglen - 1].command[9] =3D phys | CH_LINKADDR_EN; + + len -=3D xfer_len; + mem_addr +=3D xfer_len; + sglen++; + } while (len); + desc->sg[sglen - 1].command[1] |=3D FIELD_PREP(CH_CTRL_DONETYPE, + CH_CTRL_DONETYPE_CMD); + } + + /* cyclic list */ + desc->sg[sglen - 1].command[9] =3D desc->sg[0].phys | CH_LINKADDR_EN; + + mb(); + + return vchan_tx_prep(&dch->vc, &desc->vd, flags); + +err_cmd_alloc: + for (i =3D 0; i < sglen; i++) + dma_pool_free(dch->cmd_pool, desc->sg[i].command, desc->sg[i].phys); + kfree(desc); + return NULL; +} + static int d350_pause(struct dma_chan *chan) { struct d350_chan *dch =3D to_d350_chan(chan); @@ -620,20 +970,31 @@ static u32 d350_get_residue(struct d350_chan *dch) u32 res, xsize, xsizehi, linkaddr, linkaddrhi, hi_new; int i, sgcur, retries =3D 3; /* 1st time unlucky, 2nd improbable, 3rd jus= t broken */ struct d350_desc *desc =3D dch->desc; + struct d350 *dmac =3D to_d350(dch->vc.chan.device); =20 - hi_new =3D readl_relaxed(dch->base + CH_XSIZEHI); - do { - xsizehi =3D hi_new; - xsize =3D readl_relaxed(dch->base + CH_XSIZE); + if (dch->has_xsizehi) { hi_new =3D readl_relaxed(dch->base + CH_XSIZEHI); - } while (xsizehi !=3D hi_new && --retries); + do { + xsizehi =3D hi_new; + xsize =3D readl_relaxed(dch->base + CH_XSIZE); + hi_new =3D readl_relaxed(dch->base + CH_XSIZEHI); + } while (xsizehi !=3D hi_new && --retries); + } else { + xsize =3D readl_relaxed(dch->base + CH_XSIZE); + xsizehi =3D 0; + } =20 - hi_new =3D readl_relaxed(dch->base + CH_LINKADDRHI); - do { - linkaddrhi =3D hi_new; - linkaddr =3D readl_relaxed(dch->base + CH_LINKADDR); + if (!dmac->is_d250) { hi_new =3D readl_relaxed(dch->base + CH_LINKADDRHI); - } while (linkaddrhi !=3D hi_new && --retries); + do { + linkaddrhi =3D hi_new; + linkaddr =3D readl_relaxed(dch->base + CH_LINKADDR); + hi_new =3D readl_relaxed(dch->base + CH_LINKADDRHI); + } while (linkaddrhi !=3D hi_new && --retries); + } else { + linkaddr =3D readl_relaxed(dch->base + CH_LINKADDR); + linkaddrhi =3D 0; + } =20 for (i =3D 0; i < desc->sglen; i++) { if (desc->sg[i].phys =3D=3D (((u64)linkaddrhi << 32) | (linkaddr & ~CH_L= INKADDR_EN))) @@ -876,6 +1237,14 @@ static void d350_free_chan_resources(struct dma_chan = *chan) dch->cmd_pool =3D NULL; } =20 +static void d250_cntx_mem_release(void *ptr) +{ + struct d350 *dmac =3D ptr; + struct device *dev =3D dmac->dma.dev; + + dma_free_coherent(dev, dmac->cntx_mem_size, dmac->cntx_mem, dmac->cntx_me= m_paddr); +} + static int d350_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -893,8 +1262,9 @@ static int d350_probe(struct platform_device *pdev) r =3D FIELD_GET(IIDR_VARIANT, reg); p =3D FIELD_GET(IIDR_REVISION, reg); if (FIELD_GET(IIDR_IMPLEMENTER, reg) !=3D IMPLEMENTER_ARM || - FIELD_GET(IIDR_PRODUCTID, reg) !=3D PRODUCTID_DMA350) - return dev_err_probe(dev, -ENODEV, "Not a DMA-350!"); + ((FIELD_GET(IIDR_PRODUCTID, reg) !=3D PRODUCTID_DMA350) && + FIELD_GET(IIDR_PRODUCTID, reg) !=3D PRODUCTID_DMA250)) + return dev_err_probe(dev, -ENODEV, "Not a DMA-350/DMA-250!"); =20 reg =3D readl_relaxed(base + DMAINFO + DMA_BUILDCFG0); nchan =3D FIELD_GET(DMA_CFG_NUM_CHANNELS, reg) + 1; @@ -917,13 +1287,38 @@ static int d350_probe(struct platform_device *pdev) return ret; } =20 + if (device_is_compatible(dev, "arm,dma-250")) { + u32 cfg2; + int secext_present; + + dmac->is_d250 =3D true; + + cfg2 =3D readl_relaxed(base + DMAINFO + DMA_BUILDCFG2); + secext_present =3D (cfg2 & DMA_CFG_HAS_TZ) ? 1 : 0; + dmac->cntx_mem_size =3D nchan * 64 * (1 + secext_present); + dmac->cntx_mem =3D dma_alloc_coherent(dev, dmac->cntx_mem_size, + &dmac->cntx_mem_paddr, + GFP_KERNEL); + if (!dmac->cntx_mem) + return dev_err_probe(dev, -ENOMEM, "Failed to alloc context memory\n"); + + ret =3D devm_add_action_or_reset(dev, d250_cntx_mem_release, dmac); + if (ret) { + dma_free_coherent(dev, dmac->cntx_mem_size, + dmac->cntx_mem, dmac->cntx_mem_paddr); + return ret; + } + writel_relaxed(dmac->cntx_mem_paddr, base + DMANSECCTRL + NSEC_CNTXBASE); + } + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(aw)); coherent =3D device_get_dma_attr(dev) =3D=3D DEV_DMA_COHERENT; =20 reg =3D readl_relaxed(base + DMAINFO + DMA_BUILDCFG1); dmac->nreq =3D FIELD_GET(DMA_CFG_NUM_TRIGGER_IN, reg); =20 - dev_dbg(dev, "DMA-350 r%dp%d with %d channels, %d requests\n", r, p, dmac= ->nchan, dmac->nreq); + dev_info(dev, "%s r%dp%d with %d channels, %d requests\n", + dmac->is_d250 ? "DMA-250" : "DMA-350", r, p, dmac->nchan, dmac->nreq); =20 for (int i =3D min(dw, 16); i > 0; i /=3D 2) { dmac->dma.src_addr_widths |=3D BIT(i); @@ -935,7 +1330,10 @@ static int d350_probe(struct platform_device *pdev) dmac->dma.device_alloc_chan_resources =3D d350_alloc_chan_resources; dmac->dma.device_free_chan_resources =3D d350_free_chan_resources; dma_cap_set(DMA_MEMCPY, dmac->dma.cap_mask); - dmac->dma.device_prep_dma_memcpy =3D d350_prep_memcpy; + if (dmac->is_d250) + dmac->dma.device_prep_dma_memcpy =3D d250_prep_memcpy; + else + dmac->dma.device_prep_dma_memcpy =3D d350_prep_memcpy; dmac->dma.device_pause =3D d350_pause; dmac->dma.device_resume =3D d350_resume; dmac->dma.device_terminate_all =3D d350_terminate_all; @@ -971,8 +1369,8 @@ static int d350_probe(struct platform_device *pdev) return dch->irq; =20 dch->has_wrap =3D FIELD_GET(CH_CFG_HAS_WRAP, reg); - dch->has_trig =3D FIELD_GET(CH_CFG_HAS_TRIGIN, reg) & - FIELD_GET(CH_CFG_HAS_TRIGSEL, reg); + dch->has_xsizehi =3D FIELD_GET(CH_CFG_HAS_XSIZEHI, reg); + dch->has_trig =3D FIELD_GET(CH_CFG_HAS_TRIGIN, reg); =20 /* Fill is a special case of Wrap */ memset &=3D dch->has_wrap; @@ -994,8 +1392,13 @@ static int d350_probe(struct platform_device *pdev) dma_cap_set(DMA_SLAVE, dmac->dma.cap_mask); dma_cap_set(DMA_CYCLIC, dmac->dma.cap_mask); dmac->dma.device_config =3D d350_slave_config; - dmac->dma.device_prep_slave_sg =3D d350_prep_slave_sg; - dmac->dma.device_prep_dma_cyclic =3D d350_prep_cyclic; + if (dmac->is_d250) { + dmac->dma.device_prep_slave_sg =3D d250_prep_slave_sg; + dmac->dma.device_prep_dma_cyclic =3D d250_prep_cyclic; + } else { + dmac->dma.device_prep_slave_sg =3D d350_prep_slave_sg; + dmac->dma.device_prep_dma_cyclic =3D d350_prep_cyclic; + } } =20 if (memset) { @@ -1019,6 +1422,7 @@ static void d350_remove(struct platform_device *pdev) =20 static const struct of_device_id d350_of_match[] __maybe_unused =3D { { .compatible =3D "arm,dma-350" }, + { .compatible =3D "arm,dma-250" }, {} }; MODULE_DEVICE_TABLE(of, d350_of_match); @@ -1035,5 +1439,5 @@ module_platform_driver(d350_driver); =20 MODULE_AUTHOR("Robin Murphy "); MODULE_AUTHOR("Jisheng Zhang "); -MODULE_DESCRIPTION("Arm DMA-350 driver"); +MODULE_DESCRIPTION("Arm DMA-350/DMA-250 driver"); MODULE_LICENSE("GPL v2"); --=20 2.50.0