From nobody Fri Oct 3 21:52:25 2025 Received: from freeshell.de (freeshell.de [116.202.128.144]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 79293C2D1; Sat, 23 Aug 2025 08:59:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.202.128.144 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755939560; cv=none; b=YpOZRqx+ypeZIgHRuXWISKzER4PZ1x9MRquYHSg6WBEaGSshZ364MHd5XoKAfPXoSxHJgwFJun7tF+/5rfrfFGcRp9lCcXnjGrgVKyIceUJDPMPP6lvxGCjXmvhO0z+TMZAmFHPz/jdAAkXqghrmPcu6C0yGE9RWRZYkcgjJSGY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755939560; c=relaxed/simple; bh=aOaYSya72f+RYbJWzyAh/1KzNEgTYHyHYCWVDZvSmrI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=inW2z7cF796SJ9NUMH8/B1vycPF/aHlCPAVIfmc+0WbaM/nK7xONXsiPh1WLcXSbiuGzXHj2+bWFOkzQTu3ZggTesjUxBUKF3eniOObULflMcIoj1PCFY8ijXDRMoGzjPSPjJ401rRNYnxpUBJ8oCUWOpaz2hC8ob9PFFaHATww= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=freeshell.de; spf=pass smtp.mailfrom=freeshell.de; arc=none smtp.client-ip=116.202.128.144 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=freeshell.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=freeshell.de Received: from hay.lan (unknown [IPv6:2605:59c0:2078:cf00:6ecf:39ff:fe00:8375]) (Authenticated sender: e) by freeshell.de (Postfix) with ESMTPSA id EBDB4B4E001F; Sat, 23 Aug 2025 10:59:12 +0200 (CEST) From: E Shattow To: Krzysztof Kozlowski , Rob Herring , Conor Dooley , E Shattow Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hal Feng , Minda Chen Subject: [PATCH v3 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC Date: Sat, 23 Aug 2025 01:58:00 -0700 Message-ID: <20250823085818.203263-2-e@freeshell.de> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250823085818.203263-1-e@freeshell.de> References: <20250823085818.203263-1-e@freeshell.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Describe JH7110 SoC DDR external memory interface. Signed-off-by: E Shattow --- .../starfive,jh7110-dmc.yaml | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/st= arfive,jh7110-dmc.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/starfive,= jh7110-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/star= five,jh7110-dmc.yaml new file mode 100644 index 000000000000..d65313b33a3e --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-= dmc.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/starfive,jh7110-dmc.= yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 DMC + +maintainers: + - E Shattow + +description: + JH7110 DDR external memory interface LPDDR4/DDR4/DDR3/LPDDR3 32-bit at + 2133Mbps (up to 2800Mbps). + +properties: + compatible: + items: + - const: starfive,jh7110-dmc + + reg: + items: + - description: controller registers + - description: phy registers + + clocks: + maxItems: 1 + + clock-names: + items: + - const: pll + + resets: + items: + - description: axi + - description: osc + - description: apb + + reset-names: + items: + - const: axi + - const: osc + - const: apb + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include + #include + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + memory-controller@15700000 { + compatible =3D "starfive,jh7110-dmc"; + reg =3D <0x0 0x15700000 0x0 0x10000>, + <0x0 0x13000000 0x0 0x10000>; + clocks =3D <&syscrg JH7110_PLLCLK_PLL1_OUT>; + clock-names =3D "pll"; + resets =3D <&syscrg JH7110_SYSRST_DDR_AXI>, + <&syscrg JH7110_SYSRST_DDR_OSC>, + <&syscrg JH7110_SYSRST_DDR_APB>; + reset-names =3D "axi", "osc", "apb"; + }; + }; --=20 2.50.0 From nobody Fri Oct 3 21:52:25 2025 Received: from freeshell.de (freeshell.de [116.202.128.144]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C426223C51D; Sat, 23 Aug 2025 08:59:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.202.128.144 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755939564; cv=none; b=HbCB4/BiE4SxB+ElWopIZRf05LmHmB57Trgi+Ecz+QwLZrkIEdk3wp4GWhuBqK207hzUxqVb7G3JaZe9Odbk9rOT6wZST3wr4DlnvZqnXDzyAzRwPo8LB6hRwYTctLrpzO2uzWoVcSoR2ra22+h1GQ1A/f/nRrcNtsyGfyIkqwY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755939564; c=relaxed/simple; bh=V0gZbguz6xs9WFtpOVv8iGW574l1xkCUBM2m+4GVyBQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YKrL15cntOwV1vCzTOBaI+k+JoueVizLXvDaENEwoBfzFfrr8Ro1SHZfnvL4uqdgJbRrBNcHFFFnzdr5rpwq5HS3G4/aVT/x9ruEcDcgwUOsSf+brADvLcvZ7UaaENOyhosU/hSte1Dnxqp1SPYXh3zIpioJudTG0f3SXJHVQKI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=freeshell.de; spf=pass smtp.mailfrom=freeshell.de; arc=none smtp.client-ip=116.202.128.144 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=freeshell.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=freeshell.de Received: from hay.lan (unknown [IPv6:2605:59c0:2078:cf00:6ecf:39ff:fe00:8375]) (Authenticated sender: e) by freeshell.de (Postfix) with ESMTPSA id 6A05EB4E0023; Sat, 23 Aug 2025 10:59:18 +0200 (CEST) From: E Shattow To: Emil Renner Berthing , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hal Feng , Minda Chen , E Shattow , linux-riscv@lists.infradead.org Subject: [PATCH v3 2/3] riscv: dts: starfive: jh7110: add DMC memory controller Date: Sat, 23 Aug 2025 01:58:01 -0700 Message-ID: <20250823085818.203263-3-e@freeshell.de> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250823085818.203263-1-e@freeshell.de> References: <20250823085818.203263-1-e@freeshell.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add JH7110 SoC DDR external memory controller. Signed-off-by: E Shattow --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts= /starfive/jh7110.dtsi index 0ba74ef04679..f3876660c07f 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -931,6 +931,18 @@ watchdog@13070000 { <&syscrg JH7110_SYSRST_WDT_CORE>; }; =20 + memory-controller@15700000 { + compatible =3D "starfive,jh7110-dmc"; + reg =3D <0x0 0x15700000 0x0 0x10000>, + <0x0 0x13000000 0x0 0x10000>; + clocks =3D <&syscrg JH7110_PLLCLK_PLL1_OUT>; + clock-names =3D "pll"; + resets =3D <&syscrg JH7110_SYSRST_DDR_AXI>, + <&syscrg JH7110_SYSRST_DDR_OSC>, + <&syscrg JH7110_SYSRST_DDR_APB>; + reset-names =3D "axi", "osc", "apb"; + }; + crypto: crypto@16000000 { compatible =3D "starfive,jh7110-crypto"; reg =3D <0x0 0x16000000 0x0 0x4000>; --=20 2.50.0 From nobody Fri Oct 3 21:52:25 2025 Received: from freeshell.de (freeshell.de [116.202.128.144]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39B2923ABAA; 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dmarc=pass (p=none dis=none) header.from=freeshell.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=freeshell.de Received: from hay.lan (unknown [IPv6:2605:59c0:2078:cf00:6ecf:39ff:fe00:8375]) (Authenticated sender: e) by freeshell.de (Postfix) with ESMTPSA id 6CCDBB4E0039; Sat, 23 Aug 2025 10:59:25 +0200 (CEST) From: E Shattow To: Emil Renner Berthing , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hal Feng , Minda Chen , E Shattow , linux-riscv@lists.infradead.org Subject: [PATCH v3 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader Date: Sat, 23 Aug 2025 01:58:02 -0700 Message-ID: <20250823085818.203263-4-e@freeshell.de> X-Mailer: git-send-email 2.50.0 In-Reply-To: <20250823085818.203263-1-e@freeshell.de> References: <20250823085818.203263-1-e@freeshell.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add bootph-pre-ram hinting to jh7110.dtsi: - CPU interrupt controller(s) - gmac1_rgmii_rxin fixed-clock (dependency of syscrg) - gmac1_rmii_refin fixed-clock (dependency of syscrg) - oscillator - core local interrupt timer - syscrg clock-controller - pllclk clock-controller (dependency of syscrg) - DDR memory controller Signed-off-by: E Shattow --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts= /starfive/jh7110.dtsi index f3876660c07f..6e56e9d20bb0 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -35,6 +35,7 @@ S7_0: cpu@0 { =20 cpu0_intc: interrupt-controller { compatible =3D "riscv,cpu-intc"; + bootph-pre-ram; interrupt-controller; #interrupt-cells =3D <1>; }; @@ -68,6 +69,7 @@ U74_1: cpu@1 { =20 cpu1_intc: interrupt-controller { compatible =3D "riscv,cpu-intc"; + bootph-pre-ram; interrupt-controller; #interrupt-cells =3D <1>; }; @@ -101,6 +103,7 @@ U74_2: cpu@2 { =20 cpu2_intc: interrupt-controller { compatible =3D "riscv,cpu-intc"; + bootph-pre-ram; interrupt-controller; #interrupt-cells =3D <1>; }; @@ -134,6 +137,7 @@ U74_3: cpu@3 { =20 cpu3_intc: interrupt-controller { compatible =3D "riscv,cpu-intc"; + bootph-pre-ram; interrupt-controller; #interrupt-cells =3D <1>; }; @@ -167,6 +171,7 @@ U74_4: cpu@4 { =20 cpu4_intc: interrupt-controller { compatible =3D "riscv,cpu-intc"; + bootph-pre-ram; interrupt-controller; #interrupt-cells =3D <1>; }; @@ -273,12 +278,14 @@ gmac0_rmii_refin: gmac0-rmii-refin-clock { =20 gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock { compatible =3D "fixed-clock"; + bootph-pre-ram; clock-output-names =3D "gmac1_rgmii_rxin"; #clock-cells =3D <0>; }; =20 gmac1_rmii_refin: gmac1-rmii-refin-clock { compatible =3D "fixed-clock"; + bootph-pre-ram; clock-output-names =3D "gmac1_rmii_refin"; #clock-cells =3D <0>; }; @@ -321,6 +328,7 @@ mclk_ext: mclk-ext-clock { =20 osc: oscillator { compatible =3D "fixed-clock"; + bootph-pre-ram; clock-output-names =3D "osc"; #clock-cells =3D <0>; }; @@ -354,6 +362,7 @@ soc { clint: timer@2000000 { compatible =3D "starfive,jh7110-clint", "sifive,clint0"; reg =3D <0x0 0x2000000 0x0 0x10000>; + bootph-pre-ram; interrupts-extended =3D <&cpu0_intc 3>, <&cpu0_intc 7>, <&cpu1_intc 3>, <&cpu1_intc 7>, <&cpu2_intc 3>, <&cpu2_intc 7>, @@ -880,6 +889,7 @@ qspi: spi@13010000 { syscrg: clock-controller@13020000 { compatible =3D "starfive,jh7110-syscrg"; reg =3D <0x0 0x13020000 0x0 0x10000>; + bootph-pre-ram; clocks =3D <&osc>, <&gmac1_rmii_refin>, <&gmac1_rgmii_rxin>, <&i2stx_bclk_ext>, <&i2stx_lrck_ext>, @@ -904,6 +914,7 @@ sys_syscon: syscon@13030000 { =20 pllclk: clock-controller { compatible =3D "starfive,jh7110-pll"; + bootph-pre-ram; clocks =3D <&osc>; #clock-cells =3D <1>; }; @@ -935,6 +946,7 @@ memory-controller@15700000 { compatible =3D "starfive,jh7110-dmc"; reg =3D <0x0 0x15700000 0x0 0x10000>, <0x0 0x13000000 0x0 0x10000>; + bootph-pre-ram; clocks =3D <&syscrg JH7110_PLLCLK_PLL1_OUT>; clock-names =3D "pll"; resets =3D <&syscrg JH7110_SYSRST_DDR_AXI>, --=20 2.50.0