From nobody Fri Oct 3 23:02:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39FEC2327A3; Fri, 22 Aug 2025 13:15:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755868550; cv=none; b=a+y/mn3YlWIjoiYLPYF/WPlhWqXvjHwJuyVOXKCYK+nPASof8XgHOz83uN9VgVnkJydbei1tzp3P/pEXG/5JAEA2dDAmEu/Iwne6biONh/ESbLGwQBKoOD0ZuHddsl4Tv8MIrCocja0Mlw5nghNYEQvajwNXtwRFRQpWR7c3btE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755868550; c=relaxed/simple; bh=5edwIv2wGdGR2+Ign0FEjaM0t9DIY3ags+xEJ31/G64=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=QSMOQKdAmOiY1gCGS87c3zB6iI17/8x7Ct0ltAFqNpGuNLifO/ZI5LU19Y0V8VmPBs6vewppb374CGgq33556/+QIoCSYNfVwMpYWyAMViUIkToY4oKntFPjN9cs1wL9cVhAYGYvkJGT0e7j2lhgtJiOuNUR1I6gluWAEfb7sak= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=omhht5mX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="omhht5mX" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 77463C113CF; Fri, 22 Aug 2025 13:15:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755868549; bh=5edwIv2wGdGR2+Ign0FEjaM0t9DIY3ags+xEJ31/G64=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=omhht5mX9/geLecs1wdPpTwfso24JHFSn8NH5Y1RsNLTEZFrvoinVWsb8XaAgyz/K VoGZGIEocDVi6Ef9vWx8XM9V2jr0V9wc3jJji0ycuUDe3VtnLdFvUaQgLsWuiRCJlk CPsQBnBgzcIQykxQoH5G/L8Vf5HUJbbFFektpSxEAjlnVYoyGl8NIWQAD3fCWt4K3+ 5Yd+PX9CAQvIuPvJaYC6rDYED1vTCR7+HiW0932tWT/vaaPFiejqFRHs4UnaNozCsk I+4Z5DljalRxr4tBLCT9vB9FCpjlArZjexNMT3sJVNucuJsTmvOU78T1mx/JKbVq+q ubkxprkrhmuJg== From: Michael Walle To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Walle , Jean Delvare , Guenter Roeck , Lee Jones , Srinivas Kandagatla , Wim Van Sebroeck Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH v1 1/7] dt-bindings: arm: ti: Add bindings for Kontron SMARC-sAM67 module Date: Fri, 22 Aug 2025 15:15:25 +0200 Message-Id: <20250822131531.1366437-2-mwalle@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250822131531.1366437-1-mwalle@kernel.org> References: <20250822131531.1366437-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add devicetree bindings for the AM67 based Kontron SMARC-sAM67 module. Signed-off-by: Michael Walle Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/ti/k3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentati= on/devicetree/bindings/arm/ti/k3.yaml index e80c653fa438..af41f1541850 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -181,6 +181,7 @@ properties: items: - enum: - beagle,am67a-beagley-ai + - kontron,sa67 # Kontron SMARC-sAM67 board - ti,j722s-evm - const: ti,j722s =20 --=20 2.39.5 From nobody Fri Oct 3 23:02:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DEB5D2FE585; Fri, 22 Aug 2025 13:15:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755868555; cv=none; b=fLuMf2gUest9gDzkZPHfxFHRouMQwO7iASI36RsRnbffZHvoDVY/mQwbOA1Gd3ZImXmU5rz9itSGM+bhLnMAGEfn6R/zgBGG1jaYw995FukrPo7QU+hQ/mIchjMmjVXI4vB9LbEfy5FDAAEvNdYxoNGaZB2+yEd/8diT20F6aPc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755868555; c=relaxed/simple; bh=t0S8VoLjEG5TZjjggFVPP43JdfXO/Pppd/IA/GIc10g=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=s/15v5VQQtLomOQwW3elTek1GSZy1xYk9gImAdfw8+YtBi9FKxnnvLRcd6vVJZPuJQssiwvceq5F0cIaExc5KiQEoZgdvRKJgk10RPuByyp24nsQwxAAJGF6cYxBTlEY7ikhzyK3B1W6Wug85UZEeCEuUFXUDeCai5Ee8cbnGRA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=B0x3Cq6d; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="B0x3Cq6d" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2D30DC113D0; Fri, 22 Aug 2025 13:15:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755868553; bh=t0S8VoLjEG5TZjjggFVPP43JdfXO/Pppd/IA/GIc10g=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B0x3Cq6dz1yCCPcx33e6Dr106jKGWLypvcT9jzL6hw55CDS0+YsHnc3ZNIlTXa76p WncZNqibOD9REKi4e7TKxFweIySV4CviPiIyTX7ICc+VdTSM7dK98IqEr+CfkdzhVc HLuqV83rXdMY8vX4Pk5RtxNJcfaxEylezdwxh46w86wrrNIbvVLF7TNurbAReC9wjH rZII6F4g9IoqSwUJAJVJSdabdwYJIia/j1qlGFVq3Npb+I8uK8zSDEzADgSB0b0foE rtvjoq23Cs++wVsbq1hGeCBxYAvfWHXMUeJlFJeVXCoBf6Yzvoxnog9zG6xf+EUfaA zMbrek0qXH0Mg== From: Michael Walle To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Walle , Jean Delvare , Guenter Roeck , Lee Jones , Srinivas Kandagatla , Wim Van Sebroeck Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH v1 2/7] dt-bindings: mfd: sl28cpld: add sa67mcu compatible Date: Fri, 22 Aug 2025 15:15:26 +0200 Message-Id: <20250822131531.1366437-3-mwalle@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250822131531.1366437-1-mwalle@kernel.org> References: <20250822131531.1366437-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Kontron SMARC-sAM67 module features an on-board house keeping uC. It's designed to be compatible with the older on-board CPLD used on the SMARC-sAL28 board. To be prepared for any board specific quirks, add a specific compatible. Signed-off-by: Michael Walle Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/mfd/kontron,sl28cpld.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/kontron,sl28cpld.yaml b/= Documentation/devicetree/bindings/mfd/kontron,sl28cpld.yaml index 37207a97e06c..400f56d6a231 100644 --- a/Documentation/devicetree/bindings/mfd/kontron,sl28cpld.yaml +++ b/Documentation/devicetree/bindings/mfd/kontron,sl28cpld.yaml @@ -16,7 +16,12 @@ description: | =20 properties: compatible: - const: kontron,sl28cpld + oneOf: + - items: + - enum: + - kontron,sa67mcu + - const: kontron,sl28cpld + - const: kontron,sl28cpld =20 reg: description: --=20 2.39.5 From nobody Fri Oct 3 23:02:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 332493009C7; Fri, 22 Aug 2025 13:15:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755868557; cv=none; b=rz54h4YFX6WyY4pcuGbHLODVTs9UChrocg2Q8f9X2UDJnBd+GIvnWQ4hgCTHz70ZO+m3I1oihxbvORqDsjW600L4og6ZFakj3V1AqO5FLwegPN/piu88DCVLy6ODzqFZCIJvrP0DfFYNXKq95VlQlsJkMIVRXq5qOUKw23yIgOE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755868557; c=relaxed/simple; bh=a3svFGmTilPFyxqTFgQXgDbt5tuJn8Vyfor/nk7LNPs=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=tMra585sDN+86QasvFl1kmnfVgMdYwV7VoPx0BSY4s8oLx+msVGCTz7Ckw5brOzZ4VmJJ+e6ucP4yn02itJe40+SPIlDaApTgp8xNPjmpm/9CNI93eVgHD/4tc61CWjec3YYRbmCCaJtuTLeS14pSoNLdp2T5CXlZzxXbAv4eA0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DEswPeto; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DEswPeto" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D2B21C4CEED; Fri, 22 Aug 2025 13:15:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755868557; bh=a3svFGmTilPFyxqTFgQXgDbt5tuJn8Vyfor/nk7LNPs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DEswPetoMT+t+QtbFxdvKm4nu0MVOpO5GAX8QMrJzVTerQo1EKssqCEhP5nHLsjP5 gOl6gTaKwvCpXygwVnsDsgCzSuRDmA4SRPs5TJBAWf8zyzbm6Iol4uu5S/1tKjrbRZ DAey6z5BXnef7LsVIsHUog0HGQIqJVDPSwoq5kZsT7k8jabKt++nDPV7J9uyL63HNs bS6o8FY7uFP4QjNiU6cNEgGxwCt9xRVT6sd7eLFD9KqKoyiacYQ2TUmWakzWRbkLEN uc5zBHAhWDEbIbcl3sIq6u2OuL1Z5M/abqjBHQt20KhOVu0/exAp0Zh9fjlB6qTcrJ +xLQg55rGQI9w== From: Michael Walle To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Walle , Jean Delvare , Guenter Roeck , Lee Jones , Srinivas Kandagatla , Wim Van Sebroeck Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH v1 3/7] dt-bindings: hwmon: sl28cpld: add sa67mcu compatible Date: Fri, 22 Aug 2025 15:15:27 +0200 Message-Id: <20250822131531.1366437-4-mwalle@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250822131531.1366437-1-mwalle@kernel.org> References: <20250822131531.1366437-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Kontron SMARC-sAM67 module features an on-board house keeping uC. It is designed to be compatible with the older sl28cpld implementation, but has different sensors, like voltage and temperature monitoring. Add a new compatible for that board. Signed-off-by: Michael Walle Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon= .yaml b/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml index 010333cb25c0..0275803e843c 100644 --- a/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml +++ b/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml @@ -17,6 +17,7 @@ properties: compatible: enum: - kontron,sl28cpld-fan + - kontron,sa67mcu-hwmon =20 reg: maxItems: 1 --=20 2.39.5 From nobody Fri Oct 3 23:02:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37F702FE58C; Fri, 22 Aug 2025 13:16:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755868561; cv=none; b=ZdJ7BNPaGzFaL/mrvdP0J1cESbR674TyAaYJUrkOGiS+Zwi53F1g41UHL5KVdMI3iAJyNcpshz5LCaw7DM7BzvIsZAo9nAAehVLKtFKmlapphh51FbNb5f9e9jN8FQRgt8S1CTgDwhXi4GrZTXlP5s19MSFhYVsoI9vPXqXW8K8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755868561; c=relaxed/simple; bh=pI+PMnpowITNEY4uEFepulTLvkZKfkdPFKnomSd53g4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ednHbVNRdDTTU0mm3+ZDHCaiTVPeH0HxoMvT4SAFMy3W9LzRjEOYr6X5N+mmekKXdriflnoW80M+kjAvkQoU709NZTQry8P1eM5zdktxKzgw5frmIDNl98xOl2V0fd+afNSWLt+meL+u8/4/uDg/jHrAuAknL0h9Ib464DhP/8A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tDgv7D7I; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tDgv7D7I" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 81802C4CEED; Fri, 22 Aug 2025 13:15:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755868560; bh=pI+PMnpowITNEY4uEFepulTLvkZKfkdPFKnomSd53g4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=tDgv7D7I3ypU/cZ863v2Z3/VmVIsgxI7gXlZtLqRkqo+9NC2Z1GtKAhWkm+eX/FgM SH/cDX0ltWG8Gkj3QdFK4n9X3+oVET/rlA5Ab790Yfe9ZDAVrxO0AmFxbBBrLXSRRc NIjv/XK0qLeDBvmgaMkoMlrhm5WuKqOCVnJl2dHW9V6W4KbgRqI4w6UJqtug3LCOzF HT4LvvLKFKoSHkaCoJhnhFiRb237R44HESMNhaNDkeBtlz3qBU3VjPRm56EPTfgOH4 bx2KZOd/nJGEk022CJ51QmQ0H8GwhEt2LQu3OpvyGan2X0yLu1xnBzaH4/aRHmL5NL Pl6/lusyR6AEw== From: Michael Walle To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Walle , Jean Delvare , Guenter Roeck , Lee Jones , Srinivas Kandagatla , Wim Van Sebroeck Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH v1 4/7] dt-bindings: watchdog: add SMARC-sAM67 support Date: Fri, 22 Aug 2025 15:15:28 +0200 Message-Id: <20250822131531.1366437-5-mwalle@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250822131531.1366437-1-mwalle@kernel.org> References: <20250822131531.1366437-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The SMARC-sAM67 board has an on-board uC which has the same register interface as the older CPLD implementation on the SMARC-sAL28 board. Although the MCU emulates the same behavior, be prepared for any quirks and add a board specific compatible. Signed-off-by: Michael Walle Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wd= t.yaml b/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.ya= ml index 179272f74de5..b5b624e85468 100644 --- a/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml @@ -18,7 +18,12 @@ allOf: =20 properties: compatible: - const: kontron,sl28cpld-wdt + oneOf: + - items: + - enum: + - kontron,sa67mcu-wdt + - const: kontron,sl28cpld-wdt + - const: kontron,sl28cpld-wdt =20 reg: maxItems: 1 --=20 2.39.5 From nobody Fri Oct 3 23:02:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A68192FF146; Fri, 22 Aug 2025 13:16:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755868564; cv=none; b=f5u+9mEDjT7DZZ1WbAHAJ0gYEW17D2DuCA9ZST49SQph0Z/c5QKGaMXHZKZ3germ2mvn15bznY5yRPwXVWrGCOT+/R0hK7aPgQ76px2ZZbHJa4t/BUiz0u+Xc03zT9PFlwFH+VDijBLaCuKhOM7noxZM50OKIcOdXdueU0+Zg3U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755868564; c=relaxed/simple; bh=vkUXrJvuvl2RSVFcKK7WtTrWq1T1uZYDD4RoHq5N1YE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UmMf8xYaDRHVFfbCEHkwqxkV86QiuduTleQWN+rF6p+UoyrVQRHQTOWEr3s9+BTznLAXP66ldtMxfP2xFzGt+PavULsH3olDevDXC6GLDHm6N1EdZfgDALYrSKcGNs7hbBmXbvy04SDoSig3CbWm0PbyXemEljfclFcM0l4pzjk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=uWJc1YJy; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uWJc1YJy" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3180CC113CF; Fri, 22 Aug 2025 13:16:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755868564; bh=vkUXrJvuvl2RSVFcKK7WtTrWq1T1uZYDD4RoHq5N1YE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uWJc1YJyV++CB6Cz/TtTfrUhPVxNTPhUIHwKHIqqqCwqoq0Cu+NCpZsQ06uzxwpGH t2pK4FO3dSoxR4bl64qP37S02+9W225g3zCubi6+4UdJ+O1ugoerN/JFbTWktR8/eT C0kztRChb0sF/vXxVT/H8KJUci/gCH8hs1LSuneCrtZv97s0C+FYdkYi9tbUD3tPRW 0G80+gjtUZr8vZl1t9WCCbOSgdal6n8CySlIGa+lFkf4nf0gPyWED6+qelg9uhFz1U 90iZ2ZAagMmitsmil+aMfeGIYWkBe3zDcd0dlX8hIqwBzz96PWvZ+IGVKXQIe+5GwV +WF68Rx8T4eAg== From: Michael Walle To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Walle , Jean Delvare , Guenter Roeck , Lee Jones , Srinivas Kandagatla , Wim Van Sebroeck Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH v1 5/7] dt-bindings: nvmem: sl28cpld: add sa67mcu compatible Date: Fri, 22 Aug 2025 15:15:29 +0200 Message-Id: <20250822131531.1366437-6-mwalle@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250822131531.1366437-1-mwalle@kernel.org> References: <20250822131531.1366437-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Kontron SMARC-sAM67 has the same nvmem layout as the SMARC-sAL28. To To be prepared for any board specific quirks, add a specific compatible. Signed-off-by: Michael Walle Acked-by: Krzysztof Kozlowski --- .../bindings/nvmem/layouts/kontron,sl28-vpd.yaml | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/nvmem/layouts/kontron,sl28-v= pd.yaml b/Documentation/devicetree/bindings/nvmem/layouts/kontron,sl28-vpd.= yaml index c713e23819f1..afd1919c6b1c 100644 --- a/Documentation/devicetree/bindings/nvmem/layouts/kontron,sl28-vpd.yaml +++ b/Documentation/devicetree/bindings/nvmem/layouts/kontron,sl28-vpd.yaml @@ -19,7 +19,12 @@ select: false =20 properties: compatible: - const: kontron,sl28-vpd + oneOf: + - items: + - enum: + - kontron,sa67-vpd + - const: kontron,sl28-vpd + - const: kontron,sl28-vpd =20 serial-number: type: object --=20 2.39.5 From nobody Fri Oct 3 23:02:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9D44A2FFDCA; Fri, 22 Aug 2025 13:16:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755868568; cv=none; b=Db3MALt1CxzV93Uz/J/HMJ8z6coqXeH+6bvE31j325x0CQp44I3u3lIMXUMnjGakqYUAlrwt3cgw9M5BikIi5vDTouRcBUlyWFln48n/nHYBRJRzE7BEQU4R9GqfUTNGSqiJYOmyLX9lM08DpphPpQTdp9Y4A/ehSQIWunbibWQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755868568; c=relaxed/simple; bh=Z4N7E/ATatKbH4cDH2pW0yLzLs+JwnGudzv9sEzmXkk=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=JpIBUDIZ/dAhgA1ERVMMU+fhwEU1yIMYqi4Y3XuR2BBNbc4k5HrwUpM4+Yzn+ex2r1UI3sQfTCadAwnTr2HauCQYmaJReTDYzYbMjTQluQ01g6+7Lclv/cI2k3gLnwpNMNMNY41PYnCmi3DO6+7L1fLAGNjnRk8d6oMvUKA+xoQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=u9qqJqF8; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="u9qqJqF8" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DE105C113D0; Fri, 22 Aug 2025 13:16:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755868568; bh=Z4N7E/ATatKbH4cDH2pW0yLzLs+JwnGudzv9sEzmXkk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=u9qqJqF8cxZ+yFm28exnxYClwNlCvshsNwzS1xiCidbwyZoVkRRzZvSevHaF8YOmh sR6bx5S/N7uXWz6G3HjIIXI7Qi7zE3vUhQ9vHZVcXurFBb6vn8YE9ZzEy6yiiuCnQp AthcgRTahTHUS2Pw5Nav8zyJ+BqRmZ70gMbpc4CAjjF2CLHE0jlJasdqlowrU+PNun X51QbgWaT1DGE5MKOvcjqA3WvhBPeOddaAcreT6vVjdLhHYIBcgP8dJbE2uxeIxe7u Xf3dVMnlHlbO6uvKILUzZv3oC34639BIeey/PhcKuhGj0HoOmnb7kP2c6H0AQW+1NU HycDVuyq1jDNw== From: Michael Walle To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Walle , Jean Delvare , Guenter Roeck , Lee Jones , Srinivas Kandagatla , Wim Van Sebroeck Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH v1 6/7] hwmon: sl28cpld: add SMARC-sAM67 support Date: Fri, 22 Aug 2025 15:15:30 +0200 Message-Id: <20250822131531.1366437-7-mwalle@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250822131531.1366437-1-mwalle@kernel.org> References: <20250822131531.1366437-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The on-board uC on the SMARC-sAM67 board is compatible with the older CPLD implementation on the SMARC-sAL28 board, but has different sensors, namely two voltage sensors and one temperature sensor. Add support for it. Signed-off-by: Michael Walle --- drivers/hwmon/sl28cpld-hwmon.c | 76 ++++++++++++++++++++++++++++++++-- 1 file changed, 73 insertions(+), 3 deletions(-) diff --git a/drivers/hwmon/sl28cpld-hwmon.c b/drivers/hwmon/sl28cpld-hwmon.c index 454cc844fb9d..670308d9b72f 100644 --- a/drivers/hwmon/sl28cpld-hwmon.c +++ b/drivers/hwmon/sl28cpld-hwmon.c @@ -18,6 +18,9 @@ #define FAN_SCALE_X8 BIT(7) #define FAN_VALUE_MASK GENMASK(6, 0) =20 +#define SA67MCU_VOLTAGE(n) (0x00 + ((n) * 2)) +#define SA67MCU_TEMP(n) (0x04 + ((n) * 2)) + struct sl28cpld_hwmon { struct regmap *regmap; u32 offset; @@ -75,8 +78,71 @@ static const struct hwmon_chip_info sl28cpld_hwmon_chip_= info =3D { .info =3D sl28cpld_hwmon_info, }; =20 +static int sa67mcu_hwmon_read(struct device *dev, + enum hwmon_sensor_types type, u32 attr, + int channel, long *input) +{ + struct sl28cpld_hwmon *hwmon =3D dev_get_drvdata(dev); + unsigned int offset; + u8 reg[2]; + int ret; + + switch (type) { + case hwmon_in: + switch (attr) { + case hwmon_in_input: + offset =3D hwmon->offset + SA67MCU_VOLTAGE(channel); + break; + default: + return -EOPNOTSUPP; + } + break; + case hwmon_temp: + switch (attr) { + case hwmon_temp_input: + offset =3D hwmon->offset + SA67MCU_TEMP(channel); + break; + default: + return -EOPNOTSUPP; + } + break; + default: + return -EOPNOTSUPP; + } + + /* Reading the low byte will capture the value */ + ret =3D regmap_bulk_read(hwmon->regmap, offset, reg, ARRAY_SIZE(reg)); + if (ret) + return ret; + + *input =3D reg[1] << 8 | reg[0]; + + /* Temperatures are s16 and in 0.1degC steps. */ + if (type =3D=3D hwmon_temp) + *input =3D sign_extend32(*input, 15) * 100; + + return 0; +} + +static const struct hwmon_channel_info * const sa67mcu_hwmon_info[] =3D { + HWMON_CHANNEL_INFO(in, HWMON_I_INPUT, HWMON_I_INPUT), + HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT), + NULL +}; + +static const struct hwmon_ops sa67mcu_hwmon_ops =3D { + .visible =3D 0444, + .read =3D sa67mcu_hwmon_read, +}; + +static const struct hwmon_chip_info sa67mcu_hwmon_chip_info =3D { + .ops =3D &sa67mcu_hwmon_ops, + .info =3D sa67mcu_hwmon_info, +}; + static int sl28cpld_hwmon_probe(struct platform_device *pdev) { + const struct hwmon_chip_info *chip_info; struct sl28cpld_hwmon *hwmon; struct device *hwmon_dev; int ret; @@ -84,6 +150,10 @@ static int sl28cpld_hwmon_probe(struct platform_device = *pdev) if (!pdev->dev.parent) return -ENODEV; =20 + chip_info =3D device_get_match_data(&pdev->dev); + if (!chip_info) + return -EINVAL; + hwmon =3D devm_kzalloc(&pdev->dev, sizeof(*hwmon), GFP_KERNEL); if (!hwmon) return -ENOMEM; @@ -97,8 +167,7 @@ static int sl28cpld_hwmon_probe(struct platform_device *= pdev) return -EINVAL; =20 hwmon_dev =3D devm_hwmon_device_register_with_info(&pdev->dev, - "sl28cpld_hwmon", hwmon, - &sl28cpld_hwmon_chip_info, NULL); + "sl28cpld_hwmon", hwmon, chip_info, NULL); if (IS_ERR(hwmon_dev)) dev_err(&pdev->dev, "failed to register as hwmon device"); =20 @@ -106,7 +175,8 @@ static int sl28cpld_hwmon_probe(struct platform_device = *pdev) } =20 static const struct of_device_id sl28cpld_hwmon_of_match[] =3D { - { .compatible =3D "kontron,sl28cpld-fan" }, + { .compatible =3D "kontron,sl28cpld-fan", .data =3D &sl28cpld_hwmon_chip_= info }, + { .compatible =3D "kontron,sa67mcu-hwmon", .data =3D &sa67mcu_hwmon_chip_= info }, {} }; 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smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ssEmfiqJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ssEmfiqJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 88901C4CEED; Fri, 22 Aug 2025 13:16:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755868571; bh=JR24Cc5rWgKEKqiEaGWBr5oYXNkRaEkAhtPXkdWCoqc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ssEmfiqJy/wK5Nf9LrJc5/yU4VpKaqxWtPNoiokuW6nYZs9T67jrs/cey5wgxu3D8 t9XRQESdqp7eKSIwLMvRcMDnYZ+tLr/AYGFQ39Z3aI4zalI8kHAr+HT3VoN2Dchb7Y qnMnvKG5zPGjiPUkYPMDsTTK193bGmQCP4wp8A+6AzzqCq5Akh+/A6O/WEGyScb9SQ +MUbJ0nvloNKm48tTHNh/8KwoNh+lAuD5Ns/f805BE+PX5w5U8A7jG89CHcdWJmXCH XS2kx14F5HFIlA7C+oF0Yjw37chScIBxdQHU5mSGlpAR1cuJGRtiTRSFZ2l6ivO/FW 5Xx2V7B9WdcmA== From: Michael Walle To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Walle , Jean Delvare , Guenter Roeck , Lee Jones , Srinivas Kandagatla , Wim Van Sebroeck Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hwmon@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH v1 7/7] arm64: dts: ti: Add support for Kontron SMARC-sAM67 Date: Fri, 22 Aug 2025 15:15:31 +0200 Message-Id: <20250822131531.1366437-8-mwalle@kernel.org> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250822131531.1366437-1-mwalle@kernel.org> References: <20250822131531.1366437-1-mwalle@kernel.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Kontron SMARC-sAM67 is a SMARC module which features a TI AM67 SoC. It supports the following features: * Quad-core AM67A94 with 1.4GHz * 8 GiB RAM * 64 GiB eMMC * 4 MiB SPI flash for failsafe booting * 4x UART * 1x USB 2.0 * 1x USB 3.2 (or 4x USB3.2 with onboard USB 3.2 hub) * 1x RTC * 2x GBE * 1x QSPI (with 2 chip selects) * 1x SPI (with 2 chip selects) * 7x I2C * 4x CSI (*) * 2x LVDS (or one dual-link LVDS) * 1x DSI (*) * 1x DP (*) * onboard microcontroller for boot control, failsafe booting and external watchdog (*) not yet supported by the kernel There is a base device tree and overlays which will add optional features. At the moment there is one full featured variant of that board whose device tree is generated during build by merging all the device tree overlays. Signed-off-by: Michael Walle --- arch/arm64/boot/dts/ti/Makefile | 6 + .../dts/ti/k3-am67a-kontron-sa67-base.dts | 1092 +++++++++++++++++ .../dts/ti/k3-am67a-kontron-sa67-gbe1.dtso | 19 + .../ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso | 24 + 4 files changed, 1141 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso create mode 100644 arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263= .dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makef= ile index aad9177930e6..7047d3421783 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -133,7 +133,13 @@ dtb-$(CONFIG_ARCH_K3) +=3D k3-j721s2-evm.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j721s2-evm-pcie1-ep.dtbo =20 # Boards with J722s SoC +k3-am67a-kontron-sa67-dtbs :=3D k3-am67a-kontron-sa67-base.dtb \ + k3-am67a-kontron-sa67-rtc-rv8263.dtbo k3-am67a-kontron-sa67-gbe1.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-am67a-beagley-ai.dtb +dtb-$(CONFIG_ARCH_K3) +=3D k3-am67a-kontron-sa67.dtb +dtb-$(CONFIG_ARCH_K3) +=3D k3-am67a-kontron-sa67-base.dtb +dtb-$(CONFIG_ARCH_K3) +=3D k3-am67a-kontron-sa67-gbe1.dtbo +dtb-$(CONFIG_ARCH_K3) +=3D k3-am67a-kontron-sa67-rtc-rv8263.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j722s-evm.dtb dtb-$(CONFIG_ARCH_K3) +=3D k3-j722s-evm-csi2-quad-rpi-cam-imx219.dtbo dtb-$(CONFIG_ARCH_K3) +=3D k3-j722s-evm-csi2-quad-tevi-ov5640.dtbo diff --git a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts b/arch/a= rm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts new file mode 100644 index 000000000000..961d8661ec97 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-base.dts @@ -0,0 +1,1092 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Kontron SMARC-sAM67 module + * + * Copyright (c) 2025 Kontron Europe GmbH + */ + +/dts-v1/; + +#include +#include +#include +#include "k3-j722s.dtsi" +#include "k3-serdes.h" + +/ { + compatible =3D "kontron,sa67", "ti,j722s"; + model =3D "Kontron SMARC-sAM67"; + + aliases { + serial0 =3D &mcu_uart0; + serial1 =3D &main_uart0; + serial2 =3D &main_uart5; + serial3 =3D &wkup_uart0; + mmc0 =3D &sdhci0; + mmc1 =3D &sdhci1; + rtc0 =3D &wkup_rtc0; + }; + + lcd0_backlight: backlight-1 { + compatible =3D "pwm-backlight"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&lcd0_backlight_pins_default>; + pwms =3D <&epwm1 0 50000 0>; + brightness-levels =3D <0 32 64 96 128 160 192 224 255>; + default-brightness-level =3D <8>; + enable-gpios =3D <&main_gpio0 29 GPIO_ACTIVE_HIGH>; + status =3D "disabled"; + }; + + lcd1_backlight: backlight-2 { + compatible =3D "pwm-backlight"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&lcd1_backlight_pins_default>; + pwms =3D <&epwm1 1 50000 0>; + brightness-levels =3D <0 32 64 96 128 160 192 224 255>; + default-brightness-level =3D <8>; + enable-gpios =3D <&main_gpio1 18 GPIO_ACTIVE_HIGH>; + status =3D "disabled"; + }; + + chosen { + stdout-path =3D "serial1:115200n8"; + }; + + connector-1 { + compatible =3D "gpio-usb-b-connector", "usb-b-connector"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb0_connector_pins_default>; + type =3D "micro"; + id-gpios =3D <&main_gpio0 34 GPIO_ACTIVE_HIGH>; + vbus-supply =3D <&vcc_usb0_vbus>; + + port { + usb0_connector: endpoint { + remote-endpoint =3D <&usb0_hc>; + }; + }; + + }; + + memory@80000000 { + /* Filled in by bootloader */ + reg =3D <0x00000000 0x00000000 0x00000000 0x00000000>, + <0x00000000 0x00000000 0x00000000 0x00000000>; + device_type =3D "memory"; + bootph-pre-ram; + }; + + reserved_memory: reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + linux,cma { + compatible =3D "shared-dma-pool"; + reusable; + size =3D <0x10000000>; + alignment =3D <0x2000>; + linux,cma-default; + }; + + secure_tfa_ddr: tfa@9e780000 { + reg =3D <0x00 0x9e780000 0x00 0x80000>; + no-map; + }; + + secure_ddr: optee@9e800000 { + reg =3D <0x00 0x9e800000 0x00 0x01800000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@a0100000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0xa0100000 0x00 0xf00000>; + no-map; + }; + }; + + vin_5p0: regulator-1 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_3V0_5V25_IN"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vcc_3p3_s5: regulator-2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_3V3_S5"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vin_5p0>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vcc_1p8_s5: regulator-3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_1V8_S5"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vin_5p0>; + regulator-always-on; + regulator-boot-on; + bootph-all; + }; + + vcc_3p3_s0: regulator-4 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_3V3_S0"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc_3p3_s5>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpios =3D <&tps652g1 1 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vcc_3p3_sd_s0: regulator-5 { + compatible =3D "regulator-fixed"; + regulator-name =3D "SDIO_PWR_EN"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc_3p3_sd_s0_pins_default>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-boot-on; + enable-active-high; + gpios =3D <&main_gpio0 7 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vcc_3p3_sd_vio_s0: regulator-6 { + compatible =3D "regulator-gpio"; + regulator-name =3D "V_3V3_1V8_SD_S0"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc_3p3_sd_vio_s0_pins_default>; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc_3p3_s0>; + regulator-boot-on; + enable-gpios =3D <&main_gpio0 7 GPIO_ACTIVE_HIGH>; + gpios =3D <&main_gpio0 8 GPIO_ACTIVE_HIGH>; + states =3D <3300000 0x0>, + <1800000 0x1>; + bootph-all; + }; + + vcc_3p3_cam_s0: regulator-7 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_3V3_CAM_S0"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc_3p3_cam_s0_pins_default>; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc_3p3_s5>; + enable-active-high; + interrupts-extended =3D <&main_gpio1 30 IRQ_TYPE_EDGE_FALLING>; + bootph-all; + }; + + vcc_1p1_s0: regulator-8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_1V1_S0"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + vin-supply =3D <&vcc_1p1_s3>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + /* shared with V_0V75_0V85_CORE_S0 */ + gpios =3D <&tps652g1 4 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vcc_0p85_vcore_s0: regulator-9 { + compatible =3D "regulator-fixed"; + regulator-name =3D "V_0V75_0V85_CORE_S0"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + vin-supply =3D <&vin_5p0>; + regulator-always-on; + regulator-boot-on; + enable-active-high; + gpios =3D <&tps652g1 4 GPIO_ACTIVE_HIGH>; + bootph-all; + }; + + vcc_lcd0_panel: regulator-10 { + compatible =3D "regulator-fixed"; + regulator-name =3D "LCD0_VDD_EN"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc_lcd0_panel_pins_default>; + enable-active-high; + gpios =3D <&main_gpio0 30 GPIO_ACTIVE_HIGH>; + }; + + vcc_lcd1_panel: regulator-11 { + compatible =3D "regulator-fixed"; + regulator-name =3D "LCD1_VDD_EN"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc_lcd1_panel_pins_default>; + enable-active-high; + gpios =3D <&main_gpio1 19 GPIO_ACTIVE_HIGH>; + }; + + vcc_usb0_vbus: regulator-12 { + compatible =3D "regulator-fixed"; + regulator-name =3D "USB0_EN_OC#"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&vcc_usb0_vbus_pins_default>; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpios =3D <&main_gpio1 50 GPIO_ACTIVE_HIGH>; + }; +}; + +&audio_refclk0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&audio_refclk0_pins_default>; + status =3D "disabled"; +}; + +&audio_refclk1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&audio_refclk1_pins_default>; + status =3D "disabled"; +}; + +&cpsw3g { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cpsw3g_pins_default>, <&rgmii1_pins_default>, + <&rgmii2_pins_default>; + status =3D "okay"; +}; + +&cpsw3g_mdio { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&cpsw3g_mdio_pins_default>; + status =3D "okay"; + + phy0: ethernet-phy@0 { + reg =3D <0>; + }; + + phy1: ethernet-phy@1 { + reg =3D <1>; + }; +}; + +&cpsw_port1 { + phy-connection-type =3D "rgmii-id"; + phy-handle =3D <&phy0>; + nvmem-cells =3D <&base_mac_address 0>; + nvmem-cell-names =3D "mac-address"; + status =3D "okay"; +}; + +&main_gpio0 { + gpio-line-names =3D + "", "", "", "", "", "", "", "SOC_SDIO_PWR_EN", "VSD_SEL", + "RESET_OUT#", "I2C_MUX_RST#", "SPI_FLASH_CS#", "QPSI_CS0#", + "QSPI_CS1#", "BOOT_SEL1", "BRDCFG0", "BRDCFG1", "BRDCFG2", + "BRDCFG3", "BRDCFG4", "", "BRDREV0", "BRDREV1", "", "", "", "", + "", "", "LCD0_BKLT_EN", "LCD0_VDD_EN", "GBE_INT#", "DSI0_TE", + "CHARGING#", "USB0_OTG_ID", "PMIC_INT#", "RTC_INT#", + "EDP_BRIDGE_EN", "EDP_BRIDGE_IRQ#", "", "CHARGER_PRSNT#", "", + "", "", "", "BOOT_SEL2#", "CAM2_RST#", "CAM2_PWR#", "", + "CAM3_RST#", "CAM3_PWR#", "GPIO0", "GPIO1", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "", "GPIO10", "GPIO11", + "SLEEP#", "LID#"; + + bootph-all; + status =3D "okay"; +}; + +&main_gpio1 { + gpio-line-names =3D + "", "", "", "", "", "", "", "GPIO6", "GPIO7", "", "", "", "", + "GPIO8", "GPIO9", "PCIE_A_RST#", "", "BATLOW#", "LCD1_BKLT_EN", + "LCD1_VDD_EN", "", "", "", "", "GPIO2", "GPIO3", "", "", + "GPIO4", "GPIO5", "CAM_S0_FAULT#", "BOOT_SEL0#", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", "", "", "SDIO_CD#", "", + "USB0_DRVVBUS", "USB1_DRVVBUS"; + + bootph-all; + status =3D "okay"; +}; + +/* I2C_LOCAL */ +&main_i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c0_pins_default>; + clock-frequency =3D <100000>; + status =3D "okay"; + bootph-all; + + tps652g1: pmic@44 { + compatible =3D "ti,tps652g1"; + reg =3D <0x44>; + ti,primary-pmic; + system-power-controller; + + gpio-controller; + #gpio-cells =3D <2>; + gpio-line-names =3D + "LPM_EN#", "EN_3V3_S0", "POWER_BTN#", "CARRIER_STBY#", + "EN_0V75_0V85_VCORE_S0", "PMIC_WAKEUP"; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_irq_pins_default>; + interrupts-extended =3D <&main_gpio0 35 IRQ_TYPE_EDGE_FALLING>; + + buck1-supply =3D <&vin_5p0>; + buck2-supply =3D <&vin_5p0>; + buck3-supply =3D <&vin_5p0>; + buck4-supply =3D <&vin_5p0>; + ldo1-supply =3D <&vin_5p0>; + ldo2-supply =3D <&vin_5p0>; + ldo3-supply =3D <&vin_5p0>; + + bootph-all; + + regulators { + vcc_0p85_s0: buck1 { + regulator-name =3D "V_0V85_S0"; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_1p1_s3: buck2 { + regulator-name =3D "V_1V1_S3"; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_1p8_s0: buck3 { + regulator-name =3D "V_1V8_S0"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_1p2_s0: buck4 { + regulator-name =3D "V_1V2_S0"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_1p8_vda_pll_s0: ldo1 { + regulator-name =3D "V_1V8_VDA_PLL_S0"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_1p8_s3: ldo2 { + regulator-name =3D "V_1V8_S3"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + vcc_1p8_ret_s5: ldo3 { + regulator-name =3D "V_1V8_RET_S5"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + + system-controller@4a { + compatible =3D "kontron,sa67mcu", "kontron,sl28cpld"; + reg =3D <0x4a>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + watchdog@4 { + compatible =3D "kontron,sl28cpld-wdt"; + reg =3D <0x4>; + kontron,assert-wdt-timeout-pin; + }; + + hwmon@8{ + compatible =3D "kontron,sa67mcu-hwmon"; + reg =3D <0x8>; + }; + }; + + rtc: rtc@51 { + compatible =3D "microcrystal,rv8263"; + reg =3D <0x51>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rtc_pins_default>; + interrupts-extended =3D <&main_gpio0 36 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +/* I2C_CAM */ +&main_i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c2_pins_default>; + clock-frequency =3D <100000>; + status =3D "okay"; + + i2c-mux@70 { + compatible =3D "nxp,pca9546"; + reg =3D <0x70>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c_mux_pins_default>; + + vdd-supply =3D <&vcc_1p8_s0>; + reset-gpios =3D <&main_gpio0 10 GPIO_ACTIVE_LOW>; + + i2c_cam0: i2c@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + }; + + i2c_cam1: i2c@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + }; + + i2c_cam2: i2c@2 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <2>; + }; + + i2c_cam3: i2c@3 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <3>; + }; + }; +}; + +/* I2C_LCD */ +&main_i2c3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_i2c3_pins_default>; + clock-frequency =3D <100000>; + status =3D "okay"; +}; + +&main_pmx0 { + audio_refclk0_pins_default: audio-refclk0-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x0c4, PIN_OUTPUT, 5) /* (W23) VOUT0_DATA3.AUDIO_EXT_REFCLK= 0 */ + >; + }; + + audio_refclk1_pins_default: audio-refclk1-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x0a0, PIN_OUTPUT, 1) /* (N24) GPMC0_WPn.AUDIO_EXT_REFCLK1 = */ + >; + }; + + cpsw3g_mdio_pins_default: cpsw3g-mdio-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x160, PIN_OUTPUT, 0) /* (AC24) MDIO0_MDC */ + J722S_IOPAD(0x15c, PIN_INPUT, 0) /* (AD25) MDIO0_MDIO */ + >; + }; + + cpsw3g_pins_default: cpsw3g-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x1b8, PIN_OUTPUT, 1) /* (C20) SPI0_CS1.CP_GEMAC_CPTS0_TS_C= OMP */ + >; + }; + + edp_bridge_pins_default: edp-bridge-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x098, PIN_OUTPUT, 7) /* (V21) GPMC0_WAIT0.GPIO0_37 */ + J722S_IOPAD(0x09c, PIN_INPUT, 7) /* (W26) GPMC0_WAIT1.GPIO0_38 */ + >; + }; + + i2c_mux_pins_default: i2c-mux-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x028, PIN_OUTPUT, 7) /* (M27) OSPI0_D7.GPIO0_10 */ + >; + }; + + lcd0_backlight_pins_default: lcd0-backlight-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x074, PIN_OUTPUT, 7) /* (V22) GPMC0_AD14.GPIO0_29 */ + J722S_IOPAD(0x110, PIN_OUTPUT, 4) /* (G27) MMC2_DAT1.EHRPWM1_A */ + >; + }; + + lcd1_backlight_pins_default: lcd1-backlight-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x1c0, PIN_OUTPUT, 7) /* (E19) SPI0_D0.GPIO1_18 */ + J722S_IOPAD(0x114, PIN_OUTPUT, 4) /* (G26) MMC2_DAT0.EHRPWM1_B */ + >; + }; + + main_i2c0_pins_default: main-i2c0-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x1e0, PIN_INPUT, 0) /* (D23) I2C0_SCL */ + J722S_IOPAD(0x1e4, PIN_INPUT, 0) /* (B22) I2C0_SDA */ + >; + bootph-all; + }; + + main_i2c2_pins_default: main-i2c2-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x0b0, PIN_INPUT, 1) /* (P22) GPMC0_CSn2.I2C2_SCL */ + J722S_IOPAD(0x0b4, PIN_INPUT, 1) /* (P23) GPMC0_CSn3.I2C2_SDA */ + >; + }; + + main_i2c3_pins_default: main-i2c3-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x1d0, PIN_INPUT, 2) /* (E22) UART0_CTSn.I2C3_SCL */ + J722S_IOPAD(0x1d4, PIN_INPUT, 2) /* (B21) UART0_RTSn.I2C3_SDA */ + >; + }; + + main_i2c4_pins_default: main-i2c4-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x0a8, PIN_INPUT, 1) /* (R27) GPMC0_CSn0.I2C4_SCL */ + J722S_IOPAD(0x0ac, PIN_INPUT, 1) /* (P21) GPMC0_CSn1.I2C4_SDA */ + >; + }; + + main_uart0_pins_default: main-uart0-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x1c8, PIN_INPUT, 0) /* (F19) UART0_RXD */ + J722S_IOPAD(0x1cc, PIN_OUTPUT, 0) /* (F20) UART0_TXD */ + >; + bootph-all; + }; + + main_uart5_pins_default: main-uart5-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x108, PIN_INPUT, 3) /* (J27) MMC2_DAT3.UART5_RXD */ + J722S_IOPAD(0x10c, PIN_OUTPUT, 3) /* (H27) MMC2_DAT2.UART5_TXD */ + J722S_IOPAD(0x008, PIN_INPUT, 5) /* (L22) OSPI0_DQS.UART5_CTSn */ + J722S_IOPAD(0x004, PIN_OUTPUT, 5) /* (L23) OSPI0_LBCLKO.UART5_RTSn */ + >; + }; + + mcasp0_pins_default: mcasp0-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x1a4, PIN_INPUT, 0) /* (D25) MCASP0_ACLKX */ + J722S_IOPAD(0x1a8, PIN_INPUT, 0) /* (C26) MCASP0_AFSX */ + J722S_IOPAD(0x1a0, PIN_INPUT, 0) /* (F23) MCASP0_AXR0 */ + J722S_IOPAD(0x19c, PIN_OUTPUT, 0) /* (B25) MCASP0_AXR1 */ + >; + }; + + mcasp2_pins_default: mcasp2-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x070, PIN_INPUT, 3) /* (V24) GPMC0_AD13.MCASP2_ACLKX */ + J722S_IOPAD(0x06c, PIN_INPUT, 3) /* (V26) GPMC0_AD12.MCASP2_AFSX */ + J722S_IOPAD(0x05c, PIN_INPUT, 3) /* (U27) GPMC0_AD8.MCASP2_AXR0 */ + J722S_IOPAD(0x060, PIN_OUTPUT, 3) /* (U26) GPMC0_AD9.MCASP2_AXR1 */ + >; + }; + + oldi0_pins_default: oldi0-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x260, PIN_OUTPUT, 0) /* (AF23) OLDI0_A0N */ + J722S_IOPAD(0x25c, PIN_OUTPUT, 0) /* (AG24) OLDI0_A0P */ + J722S_IOPAD(0x268, PIN_OUTPUT, 0) /* (AG22) OLDI0_A1N */ + J722S_IOPAD(0x264, PIN_OUTPUT, 0) /* (AG23) OLDI0_A1P */ + J722S_IOPAD(0x270, PIN_OUTPUT, 0) /* (AB20) OLDI0_A2N */ + J722S_IOPAD(0x26c, PIN_OUTPUT, 0) /* (AB21) OLDI0_A2P */ + J722S_IOPAD(0x278, PIN_OUTPUT, 0) /* (AG20) OLDI0_A3N */ + J722S_IOPAD(0x274, PIN_OUTPUT, 0) /* (AG21) OLDI0_A3P */ + J722S_IOPAD(0x2a0, PIN_OUTPUT, 0) /* (AF21) OLDI0_CLK0N */ + J722S_IOPAD(0x29c, PIN_OUTPUT, 0) /* (AE20) OLDI0_CLK0P */ + >; + }; + + oldi1_pins_default: oldi1-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x280, PIN_OUTPUT, 0) /* (AD21) OLDI0_A4N */ + J722S_IOPAD(0x27c, PIN_OUTPUT, 0) /* (AC21) OLDI0_A4P */ + J722S_IOPAD(0x288, PIN_OUTPUT, 0) /* (AF19) OLDI0_A5N */ + J722S_IOPAD(0x284, PIN_OUTPUT, 0) /* (AF18) OLDI0_A5P */ + J722S_IOPAD(0x290, PIN_OUTPUT, 0) /* (AG17) OLDI0_A6N */ + J722S_IOPAD(0x28c, PIN_OUTPUT, 0) /* (AG18) OLDI0_A6P */ + J722S_IOPAD(0x298, PIN_OUTPUT, 0) /* (AB19) OLDI0_A7N */ + J722S_IOPAD(0x294, PIN_OUTPUT, 0) /* (AA20) OLDI0_A7P */ + J722S_IOPAD(0x2a8, PIN_OUTPUT, 0) /* (AD20) OLDI0_CLK1N */ + J722S_IOPAD(0x2a4, PIN_OUTPUT, 0) /* (AE19) OLDI0_CLK1P */ + >; + }; + + ospi0_pins_default: ospi0-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x000, PIN_OUTPUT, 0) /* (L24) OSPI0_CLK */ + J722S_IOPAD(0x02c, PIN_OUTPUT, 0) /* (K26) OSPI0_CSn0 */ + J722S_IOPAD(0x030, PIN_OUTPUT, 0) /* (K23) OSPI0_CSn1 */ + J722S_IOPAD(0x034, PIN_OUTPUT, 0) /* (K22) OSPI0_CSn2 */ + J722S_IOPAD(0x00c, PIN_INPUT, 0) /* (K27) OSPI0_D0 */ + J722S_IOPAD(0x010, PIN_INPUT, 0) /* (L27) OSPI0_D1 */ + J722S_IOPAD(0x014, PIN_INPUT, 0) /* (L26) OSPI0_D2 */ + J722S_IOPAD(0x018, PIN_INPUT, 0) /* (L25) OSPI0_D3 */ + >; + bootph-all; + }; + + pcie0_rc_pins_default: pcie0-rc-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x2ac, PIN_OUTPUT, 0) /* (F25) PCIE0_CLKREQn */ + J722S_IOPAD(0x1b4, PIN_OUTPUT, 7) /* (B20) SPI0_CS0.GPIO1_15 */ + >; + }; + + pmic_irq_pins_default: pmic-irq-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x090, PIN_INPUT, 7) /* (P27) GPMC0_BE0n_CLE.GPIO0_35 */ + >; + }; + + rgmii1_pins_default: rgmii1-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x14c, PIN_INPUT, 0) /* (AC25) RGMII1_RD0 */ + J722S_IOPAD(0x150, PIN_INPUT, 0) /* (AD27) RGMII1_RD1 */ + J722S_IOPAD(0x154, PIN_INPUT, 0) /* (AE24) RGMII1_RD2 */ + J722S_IOPAD(0x158, PIN_INPUT, 0) /* (AE26) RGMII1_RD3 */ + J722S_IOPAD(0x148, PIN_INPUT, 0) /* (AE27) RGMII1_RXC */ + J722S_IOPAD(0x144, PIN_INPUT, 0) /* (AD23) RGMII1_RX_CTL */ + J722S_IOPAD(0x134, PIN_OUTPUT, 0) /* (AF27) RGMII1_TD0 */ + J722S_IOPAD(0x138, PIN_OUTPUT, 0) /* (AE23) RGMII1_TD1 */ + J722S_IOPAD(0x13c, PIN_OUTPUT, 0) /* (AG25) RGMII1_TD2 */ + J722S_IOPAD(0x140, PIN_OUTPUT, 0) /* (AF24) RGMII1_TD3 */ + J722S_IOPAD(0x130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */ + J722S_IOPAD(0x12c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */ + >; + }; + + rgmii2_pins_default: rgmii2-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x0f8, PIN_INPUT, 2) /* (AB24) VOUT0_HSYNC.RGMII2_RD0 */ + J722S_IOPAD(0x0fc, PIN_INPUT, 2) /* (AC27) VOUT0_DE.RGMII2_RD1 */ + J722S_IOPAD(0x100, PIN_INPUT, 2) /* (AB23) VOUT0_VSYNC.RGMII2_RD2 */ + J722S_IOPAD(0x104, PIN_INPUT, 2) /* (AC26) VOUT0_PCLK.RGMII2_RD3 */ + J722S_IOPAD(0x0f4, PIN_INPUT, 2) /* (AB27) VOUT0_DATA15.RGMII2_RXC */ + J722S_IOPAD(0x0f0, PIN_INPUT, 2) /* (AB26) VOUT0_DATA14.RGMII2_RX_CTL */ + J722S_IOPAD(0x0e0, PIN_OUTPUT, 2) /* (AA25) VOUT0_DATA10.RGMII2_TD0 */ + J722S_IOPAD(0x0e4, PIN_OUTPUT, 2) /* (AB25) VOUT0_DATA11.RGMII2_TD1 */ + J722S_IOPAD(0x0e8, PIN_OUTPUT, 2) /* (AA23) VOUT0_DATA12.RGMII2_TD2 */ + J722S_IOPAD(0x0ec, PIN_OUTPUT, 2) /* (AA22) VOUT0_DATA13.RGMII2_TD3 */ + J722S_IOPAD(0x0dc, PIN_OUTPUT, 2) /* (AA27) VOUT0_DATA9.RGMII2_TXC */ + J722S_IOPAD(0x0d8, PIN_OUTPUT, 2) /* (AA24) VOUT0_DATA8.RGMII2_TX_CTL */ + >; + }; + + rtc_pins_default: rtc-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x094, PIN_INPUT, 7) /* (P26) GPMC0_BE1n.GPIO0_36 */ + >; + }; + + sdhci1_pins_default: sdhci1-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x23c, PIN_INPUT, 0) /* (H22) MMC1_CMD */ + J722S_IOPAD(0x234, PIN_OUTPUT, 0) /* (H24) MMC1_CLK */ + J722S_IOPAD(0x230, PIN_INPUT, 0) /* (H23) MMC1_DAT0 */ + J722S_IOPAD(0x22c, PIN_INPUT, 0) /* (H20) MMC1_DAT1 */ + J722S_IOPAD(0x228, PIN_INPUT, 0) /* (J23) MMC1_DAT2 */ + J722S_IOPAD(0x224, PIN_INPUT, 0) /* (H25) MMC1_DAT3 */ + J722S_IOPAD(0x240, PIN_INPUT, 0) /* (B24) MMC1_SDCD */ + J722S_IOPAD(0x244, PIN_INPUT, 0) /* (A24) MMC1_SDWP */ + >; + bootph-all; + }; + + usb0_connector_pins_default: usb0-connector-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x08c, PIN_INPUT_PULLUP, 7) /* (N23) GPMC0_WEn.GPIO0_34 */ + >; + }; + + usb1_pins_default: usb1-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x258, PIN_OUTPUT, 0) /* (B27) USB1_DRVVBUS */ + >; + }; + + vcc_3p3_sd_s0_pins_default: vcc-3p3-sd-s0-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x01c, PIN_OUTPUT, 7) /* (L21) OSPI0_D4.GPIO0_7 */ + >; + bootph-all; + }; + + vcc_3p3_sd_vio_s0_pins_default: vcc-3p3-sd-vio-s0-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x020, PIN_OUTPUT, 7) /* (M26) OSPI0_D5.GPIO0_8 */ + >; + bootph-all; + }; + + vcc_3p3_cam_s0_pins_default: vcc-3p3-cam-s0-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x1f0, PIN_OUTPUT, 7) /* (A23) EXT_REFCLK1.GPIO1_30 */ + >; + }; + + vcc_lcd0_panel_pins_default: vcc-lcd0-panel-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x078, PIN_OUTPUT, 7) /* (V23) GPMC0_AD15.GPIO0_30 */ + >; + }; + + vcc_lcd1_panel_pins_default: vcc-lcd1-panel-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x1c4, PIN_OUTPUT, 7) /* (E20) SPI0_D1.GPIO1_19 */ + >; + }; + + vcc_usb0_vbus_pins_default: vcc-usb0-vbus-default-pins { + pinctrl-single,pins =3D < + J722S_IOPAD(0x254, PIN_OUTPUT, 7) /* (E25) USB0_DRVVBUS.GPIO1_50 */ + >; + }; +}; + +/* SER1 */ +&main_uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_uart0_pins_default>; + bootph-all; + status =3D "okay"; +}; + +/* SER2 */ +&main_uart5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&main_uart5_pins_default>; + bootph-all; + status =3D "okay"; +}; + +/* I2S0 */ +&mcasp0 { + #sound-dai-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcasp0_pins_default>; + op-mode =3D <0>; /* I2S */ + tdm-slots =3D <2>; + serial-dir =3D <2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; +}; + +/* I2S2 */ +&mcasp2 { + #sound-dai-cells =3D <0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcasp2_pins_default>; + op-mode =3D <0>; /* I2S */ + tdm-slots =3D <2>; + serial-dir =3D <2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; +}; + +/* CAN0 */ +&mcu_mcan0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_mcan0_pins_default>; + status =3D "okay"; +}; + +/* CAN1 */ +&mcu_mcan1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_mcan1_pins_default>; + status =3D "okay"; +}; + +&mcu_gpio0 { + gpio-line-names =3D + "", "", "", "", "", "", "", "", "", "", "", /* 10 */ "GPIO12", + "MCU_INT#", "", "", "", "", "", "", "", "", "", "", "GPIO13"; +}; + +/* I2C_GP */ +&mcu_i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_i2c0_pins_default>; + clock-frequency =3D <100000>; + status =3D "okay"; + + /* SMARC Module EEPROM */ + eeprom@50 { + compatible =3D "atmel,24c32"; + reg =3D <0x50>; + pagesize =3D <32>; + vcc-supply =3D <&vcc_1p8_s0>; + }; +}; + +&mcu_pmx0 { + mcu_i2c0_pins_default: mcu-i2c0-default-pins { + pinctrl-single,pins =3D < + J722S_MCU_IOPAD(0x044, PIN_INPUT, 0) /* (B13) MCU_I2C0_SCL */ + J722S_MCU_IOPAD(0x048, PIN_INPUT, 0) /* (E11) MCU_I2C0_SDA */ + >; + }; + mcu_mcan0_pins_default: mcu-mcan0-default-pins { + pinctrl-single,pins =3D < + J722S_MCU_IOPAD(0x038, PIN_INPUT, 0) /* (D8) MCU_MCAN0_RX */ + J722S_MCU_IOPAD(0x034, PIN_OUTPUT, 0) /* (B2) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-default-pins { + pinctrl-single,pins =3D < + J722S_MCU_IOPAD(0x040, PIN_INPUT, 0) /* (B1) MCU_MCAN1_RX */ + J722S_MCU_IOPAD(0x03C, PIN_OUTPUT, 0) /* (C1) MCU_MCAN1_TX */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-default-pins { + pinctrl-single,pins =3D < + J722S_MCU_IOPAD(0x014, PIN_INPUT, 0) /* (B8) MCU_UART0_RXD */ + J722S_MCU_IOPAD(0x018, PIN_OUTPUT, 0) /* (B4) MCU_UART0_TXD */ + J722S_MCU_IOPAD(0x01c, PIN_INPUT, 0) /* (B5) MCU_UART0_CTSn */ + J722S_MCU_IOPAD(0x020, PIN_OUTPUT, 0) /* (C5) MCU_UART0_RTSn */ + >; + bootph-all; + }; + + mcu_spi0_pins_default: mcu-spi0-default-pins { + pinctrl-single,pins =3D < + J722S_MCU_IOPAD(0x008, PIN_OUTPUT, 0) /* (A9) MCU_SPI0_CLK */ + J722S_MCU_IOPAD(0x000, PIN_OUTPUT, 0) /* (C12) MCU_SPI0_CS0 */ + J722S_MCU_IOPAD(0x004, PIN_OUTPUT, 0) /* (A10) MCU_SPI0_CS1 */ + J722S_MCU_IOPAD(0x00c, PIN_INPUT, 0) /* (B12) MCU_SPI0_D0 */ + J722S_MCU_IOPAD(0x010, PIN_OUTPUT, 0) /* (C11) MCU_SPI0_D1 */ + >; + }; + + wkup_uart0_pins_default: wkup-uart0-default-pins { + pinctrl-single,pins =3D < + J722S_MCU_IOPAD(0x024, PIN_INPUT, 0) /* (B3) WKUP_UART0_RXD */ + J722S_MCU_IOPAD(0x028, PIN_OUTPUT, 0) /* (C8) WKUP_UART0_TXD */ + >; + bootph-all; + }; + + wkup_i2c0_pins_default: wkup-i2c0-default-pins { + pinctrl-single,pins =3D < + J722S_MCU_IOPAD(0x04c, PIN_INPUT, 0) /* (B9) WKUP_I2C0_SCL */ + J722S_MCU_IOPAD(0x050, PIN_INPUT, 0) /* (D11) WKUP_I2C0_SDA */ + >; + }; +}; + +/* SPI0 */ +&mcu_spi0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_spi0_pins_default>; + status =3D "disabled"; +}; + +/* SER0 */ +&mcu_uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mcu_uart0_pins_default>; + bootph-all; + status =3D "okay"; +}; + +/* QSPI0 */ +&ospi0 { + pinctrl-0 =3D <&ospi0_pins_default>; + pinctrl-names =3D "default"; + status =3D "okay"; + + flash@0 { + compatible =3D "jedec,spi-nor"; + reg =3D <0>; + spi-max-frequency =3D <104000000>; + spi-rx-bus-width =3D <2>; + spi-tx-bus-width =3D <2>; + m25p,fast-read; + cdns,tshsl-ns =3D <60>; + cdns,tsd2d-ns =3D <60>; + cdns,tchsh-ns =3D <60>; + cdns,tslch-ns =3D <60>; + cdns,read-delay =3D <3>; + vcc-supply =3D <&vcc_1p8_s0>; + bootph-all; + + partitions { + compatible =3D "fixed-partitions"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + partition@0 { + reg =3D <0x000000 0x400000>; + label =3D "failsafe bootloader"; + read-only; + }; + }; + + otp-1 { + compatible =3D "user-otp"; + + nvmem-layout { + compatible =3D "kontron,sa67-vpd", "kontron,sl28-vpd"; + + serial_number: serial-number { + }; + + base_mac_address: base-mac-address { + #nvmem-cell-cells =3D <1>; + }; + }; + }; + }; +}; + +&pcie0_rc { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie0_rc_pins_default>; + + /* + * This is low active, but the driver itself is broken and already + * inverts the logic. + */ + reset-gpios =3D <&main_gpio1 15 GPIO_ACTIVE_HIGH>; + phys =3D <&serdes1_pcie>; + phy-names =3D "pcie-phy"; + status =3D "okay"; +}; + +&sdhci0 { + disable-wp; + bootph-all; + ti,driver-strength-ohm =3D <50>; + status =3D "okay"; +}; + +/* SDIO */ +&sdhci1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&sdhci1_pins_default>; + vmmc-supply =3D <&vcc_3p3_sd_s0>; + vqmmc-supply =3D <&vcc_3p3_sd_vio_s0>; + bootph-all; + cd-gpios =3D <&main_gpio1 48 GPIO_ACTIVE_LOW>; + cd-debounce-delay-ms =3D <100>; + ti,fails-without-test-cd; + ti,driver-strength-ohm =3D <50>; + status =3D "okay"; +}; + +&serdes_ln_ctrl { + idle-states =3D , + ; +}; + +&serdes_wiz0 { + status =3D "okay"; +}; + +&serdes_wiz1 { + status =3D "okay"; +}; + +&serdes0 { + serdes0_usb3: phy@0 { + reg =3D <0>; + #phy-cells =3D <0>; + resets =3D <&serdes_wiz0 1>; + cdns,num-lanes =3D <1>; + cdns,phy-type =3D ; + }; +}; + +&serdes1 { + serdes1_pcie: phy@0 { + reg =3D <0>; + #phy-cells =3D <0>; + resets =3D <&serdes_wiz1 1>; + cdns,num-lanes =3D <1>; + cdns,phy-type =3D ; + }; +}; + +&usb0 { + /* dual role is implemented but not a full featured OTG */ + adp-disable; + hnp-disable; + srp-disable; + dr_mode =3D "otg"; + usb-role-switch; + role-switch-default-mode =3D "peripheral"; + status =3D "okay"; + + port { + usb0_hc: endpoint { + remote-endpoint =3D <&usb0_connector>; + }; + }; +}; + +&usb1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb1_pins_default>; + + dr_mode =3D "host"; + maximum-speed =3D "super-speed"; + phys =3D <&serdes0_usb3>; + phy-names =3D "cdns3,usb3-phy"; +}; + +&usbss0 { + ti,vbus-divider; + status =3D "okay"; +}; + +&usbss1 { + ti,vbus-divider; + status =3D "okay"; +}; + +/* I2C_PM */ +&wkup_i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wkup_i2c0_pins_default>; + clock-frequency =3D <100000>; + status =3D "okay"; +}; + +/* SER3 */ +&wkup_uart0 { + /* WKUP UART0 is used by Device Manager firmware */ + pinctrl-names =3D "default"; + pinctrl-0 =3D <&wkup_uart0_pins_default>; + bootph-all; + status =3D "reserved"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso b/arch/= arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso new file mode 100644 index 000000000000..4e9eb7998f38 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-gbe1.dtso @@ -0,0 +1,19 @@ +/dts-v1/; +/plugin/; + +&cpsw3g_mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + phy1: ethernet-phy@1 { + reg =3D <1>; + }; +}; + +&cpsw_port2 { + phy-connection-type =3D "rgmii-id"; + phy-handle =3D <&phy1>; + nvmem-cells =3D <&base_mac_address 1>; + nvmem-cell-names =3D "mac-address"; + status =3D "okay"; +}; diff --git a/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso b= /arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso new file mode 100644 index 000000000000..c9aa15269c92 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am67a-kontron-sa67-rtc-rv8263.dtso @@ -0,0 +1,24 @@ +/dts-v1/; +/plugin/; + +#include + +&{/} { + aliases { + rtc0 =3D "/bus@f0000/i2c@20000000/rtc@51"; /* &rtc */ + rtc1 =3D "/bus@f0000/bus@b00000/rtc@2b1f0000"; /* &wkup_rtc0 */ + }; +}; + +&main_i2c0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + + rtc: rtc@51 { + compatible =3D "microcrystal,rv8263"; + reg =3D <0x51>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rtc_pins_default>; + interrupts-extended =3D <&main_gpio0 36 IRQ_TYPE_EDGE_FALLING>; + }; +}; --=20 2.39.5