From nobody Sat Oct 4 00:32:10 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EAC842FF156; Fri, 22 Aug 2025 12:53:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755867236; cv=none; b=K496oOqj2FiAMZ8hw8kDN9RYDn3Ui/pgNDqgImjyvTadPJ0xUPgQmMO+oxNEgZr85mYgZ5ADkOu4riCfWZ4p9kiBdEt+ATszjNTIsZn87Srx75YUfw9VgU8gaj0T5raGpyZbc9S2/9gPYcQ4+QU+bVgpvKkzjbswmbGdLq5P3gk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755867236; c=relaxed/simple; bh=npCLNuVeW2g61UocZVSIrIYmmyD2YYqBAY94mYnkBNc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ZwNzkW/CQPGF91XgSW3Qs8RN05fPEe8XTgPDDJ6mtHp+B0B0322tzErULzQCiOoVQLMS/cCaZLeRuXWAk3AVE+cZH/l2UN5WBMNkOLr6pm9AQKO0PHVW/0IxqnhbnIrDFuCgmt2+E9Lpm8kS6HIvqhV+nALf4QnrHhXCowQAGSo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=VMZCNx5v; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="VMZCNx5v" X-UUID: 0b20dbbc7f5711f0b33aeb1e7f16c2b6-20250822 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=x1MC0J/CH71gw9M2V/Ivb0lmPyN1JeqasB+bZz5cmp0=; b=VMZCNx5vpXDxsx2JVDzQ7S3HPT0UVckZ0CX9ExsHbmUOArfMBfyASLE/u+CplzRztr+BRVEFbWA8Kw74ihD2hMOd6cseHs0yVgxRnNJYBfEFqtcMWKkaxnzeKnnLPmltTP3H7TFG71dwYsluC9v5NNYxCfU6F6igGeDg3eEodEM=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.3,REQID:fb9f874f-85ad-446e-97ae-a0357e53f9a3,IP:0,UR L:25,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:0 X-CID-META: VersionHash:f1326cf,CLOUDID:80f7c344-18c5-4075-a135-4c0afe29f9d6,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:-5,Content:0|15|50,EDM: -3,IP:nil,URL:11|97|99|83|106|1,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,CO L:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 0b20dbbc7f5711f0b33aeb1e7f16c2b6-20250822 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 169179805; Fri, 22 Aug 2025 20:53:47 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Fri, 22 Aug 2025 20:53:45 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Fri, 22 Aug 2025 20:53:43 +0800 From: Darren.Ye To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jaroslav Kysela , Takashi Iwai , Linus Walleij , Bartosz Golaszewski CC: , , , , , , Darren Ye , Krzysztof Kozlowski Subject: [PATCH v7 08/10] ASoC: dt-bindings: mediatek,mt8196-afe: add audio AFE Date: Fri, 22 Aug 2025 20:52:37 +0800 Message-ID: <20250822125301.12333-9-darren.ye@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250822125301.12333-1-darren.ye@mediatek.com> References: <20250822125301.12333-1-darren.ye@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-MTK: N Content-Type: text/plain; charset="utf-8" From: Darren Ye Add mt8196 audio AFE. Signed-off-by: Darren Ye Reviewed-by: Krzysztof Kozlowski --- .../bindings/sound/mediatek,mt8196-afe.yaml | 113 ++++++++++++++++++ 1 file changed, 113 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/mediatek,mt8196= -afe.yaml diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8196-afe.ya= ml b/Documentation/devicetree/bindings/sound/mediatek,mt8196-afe.yaml new file mode 100644 index 000000000000..949f8622baf9 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mediatek,mt8196-afe.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mediatek,mt8196-afe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Audio Front End PCM controller for MT8196 + +maintainers: + - Darren Ye + +properties: + compatible: + const: mediatek,mt8196-afe + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + memory-region: + maxItems: 1 + + power-domains: + maxItems: 1 + + clocks: + items: + - description: mux for audio intbus + - description: mux for audio engen1 + - description: mux for audio engen2 + - description: mux for audio h + - description: audio apll1 clock + - description: audio apll2 clock + - description: audio apll12 divide for i2sin0 + - description: audio apll12 divide for i2sin1 + - description: audio apll12 divide for fmi2s + - description: audio apll12 divide for tdmout mck + - description: audio apll12 divide for tdmout bck + - description: mux for adsp clock + + clock-names: + items: + - const: top_aud_intbus + - const: top_aud_eng1 + - const: top_aud_eng2 + - const: top_aud_h + - const: apll1 + - const: apll2 + - const: apll12_div_i2sin0 + - const: apll12_div_i2sin1 + - const: apll12_div_fmi2s + - const: apll12_div_tdmout_m + - const: apll12_div_tdmout_b + - const: top_adsp + +required: + - compatible + - reg + - interrupts + - memory-region + - power-domains + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + afe@1a110000 { + compatible =3D "mediatek,mt8196-afe"; + reg =3D <0 0x1a110000 0 0x9000>; + interrupts =3D ; + memory-region =3D <&afe_dma_mem_reserved>; + power-domains =3D <&scpsys 14>; //MT8196_POWER_DOMAIN_AUDIO + pinctrl-names =3D "default"; + pinctrl-0 =3D <&aud_pins_default>; + clocks =3D <&vlp_cksys_clk 40>, //CLK_VLP_CK_AUD_INTBUS_SEL + <&vlp_cksys_clk 38>, //CLK_VLP_CK_AUD_ENGEN1_SEL + <&vlp_cksys_clk 39>, //CLK_VLP_CK_AUD_ENGEN2_SEL + <&vlp_cksys_clk 37>, //CLK_VLP_CK_AUDIO_H_SEL + <&vlp_cksys_clk 0>, //CLK_VLP_CK_VLP_APLL1 + <&vlp_cksys_clk 1>, //CLK_VLP_CK_VLP_APLL2 + <&cksys_clk 80>, //CLK_CK_APLL12_CK_DIV_I2SIN0 + <&cksys_clk 81>, //CLK_CK_APLL12_CK_DIV_I2SIN1 + <&cksys_clk 92>, //CLK_CK_APLL12_CK_DIV_FMI2S + <&cksys_clk 93>, //CLK_CK_APLL12_CK_DIV_TDMOUT_M + <&cksys_clk 94>, //CLK_CK_APLL12_CK_DIV_TDMOUT_B + <&cksys_clk 45>; //CLK_CK_ADSP_SEL + clock-names =3D "top_aud_intbus", + "top_aud_eng1", + "top_aud_eng2", + "top_aud_h", + "apll1", + "apll2", + "apll12_div_i2sin0", + "apll12_div_i2sin1", + "apll12_div_fmi2s", + "apll12_div_tdmout_m", + "apll12_div_tdmout_b", + "top_adsp"; + }; + }; + +... --=20 2.45.2