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charset="utf-8" Refactor register macros for consistency and clarity and remove redundant definitions and update naming for better alignment. Update copyright to include Qualcomm Technologies, Inc. Signed-off-by: Viken Dadhaniya --- drivers/soc/qcom/qcom-geni-se.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-s= e.c index 3c3b796333a6..e8ab2833815e 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -1,5 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ =20 /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO trac= es */ #define __DISABLE_TRACE_MMIO__ @@ -110,22 +113,20 @@ struct geni_se_desc { static const char * const icc_path_names[] =3D {"qup-core", "qup-config", "qup-memory"}; =20 -#define QUP_HW_VER_REG 0x4 +/* Common QUPV3 registers */ +#define QUPV3_HW_VER_REG 0x4 =20 /* Common SE registers */ -#define GENI_INIT_CFG_REVISION 0x0 -#define GENI_S_INIT_CFG_REVISION 0x4 -#define GENI_OUTPUT_CTRL 0x24 -#define GENI_CGC_CTRL 0x28 -#define GENI_CLK_CTRL_RO 0x60 -#define GENI_FW_S_REVISION_RO 0x6c +#define SE_GENI_INIT_CFG_REVISION 0x0 +#define SE_GENI_S_INIT_CFG_REVISION 0x4 +#define SE_GENI_CGC_CTRL 0x28 +#define SE_GENI_CLK_CTRL_RO 0x60 +#define SE_GENI_FW_S_REVISION_RO 0x6c #define SE_GENI_BYTE_GRAN 0x254 #define SE_GENI_TX_PACKING_CFG0 0x260 #define SE_GENI_TX_PACKING_CFG1 0x264 #define SE_GENI_RX_PACKING_CFG0 0x284 #define SE_GENI_RX_PACKING_CFG1 0x288 -#define SE_GENI_M_GP_LENGTH 0x910 -#define SE_GENI_S_GP_LENGTH 0x914 #define SE_DMA_TX_PTR_L 0xc30 #define SE_DMA_TX_PTR_H 0xc34 #define SE_DMA_TX_ATTR 0xc38 @@ -142,7 +143,6 @@ static const char * const icc_path_names[] =3D {"qup-co= re", "qup-config", #define SE_DMA_RX_IRQ_EN 0xd48 #define SE_DMA_RX_IRQ_EN_SET 0xd4c #define SE_DMA_RX_IRQ_EN_CLR 0xd50 -#define SE_DMA_RX_LEN_IN 0xd54 #define SE_DMA_RX_MAX_BURST 0xd5c #define SE_DMA_RX_FLUSH 0xd60 #define SE_GSI_EVENT_EN 0xe18 @@ -179,7 +179,7 @@ static const char * const icc_path_names[] =3D {"qup-co= re", "qup-config", /* SE_DMA_GENERAL_CFG */ #define DMA_RX_CLK_CGC_ON BIT(0) #define DMA_TX_CLK_CGC_ON BIT(1) -#define DMA_AHB_SLV_CFG_ON BIT(2) +#define DMA_AHB_SLV_CLK_CGC_ON BIT(2) #define AHB_SEC_SLV_CLK_CGC_ON BIT(3) #define DUMMY_RX_NON_BUFFERABLE BIT(4) #define RX_DMA_ZERO_PADDING_EN BIT(5) @@ -196,7 +196,7 @@ u32 geni_se_get_qup_hw_version(struct geni_se *se) { struct geni_wrapper *wrapper =3D se->wrapper; =20 - return readl_relaxed(wrapper->base + QUP_HW_VER_REG); + return readl_relaxed(wrapper->base + QUPV3_HW_VER_REG); } EXPORT_SYMBOL_GPL(geni_se_get_qup_hw_version); =20 @@ -220,12 +220,12 @@ static void geni_se_io_init(void __iomem *base) { u32 val; =20 - val =3D readl_relaxed(base + GENI_CGC_CTRL); + val =3D readl_relaxed(base + SE_GENI_CGC_CTRL); val |=3D DEFAULT_CGC_EN; - writel_relaxed(val, base + GENI_CGC_CTRL); + writel_relaxed(val, base + SE_GENI_CGC_CTRL); =20 val =3D readl_relaxed(base + SE_DMA_GENERAL_CFG); - val |=3D AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON; + val |=3D AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CLK_CGC_ON; val |=3D DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON; writel_relaxed(val, base + SE_DMA_GENERAL_CFG); =20 --=20 2.34.1