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charset="utf-8" Introduce a new YAML schema for QUP-supported peripherals. Define common properties used across QUP-supported peripherals. Add property `qcom,enable-gsi-dma` to configure the Serial Engine (SE) for QCOM GPI DMA mode. Reference the common schema YAML in the GENI I2C, SPI, and SERIAL YAML files. Reviewed-by: Krzysztof Kozlowski Co-developed-by: Mukesh Kumar Savaliya Signed-off-by: Mukesh Kumar Savaliya Signed-off-by: Viken Dadhaniya --- v5 -> v6: - No change. v5 Link: https://lore.kernel.org/linux-i2c/20250624095102.1587580-2-viken.d= adhaniya@oss.qualcomm.com/ v4 -> v5: - Add Reviewed-by tag. - Update the email domain from 'quic' to 'oss'. v4 Link: https://lore.kernel.org/all/20250503111029.3583807-2-quic_vdadhani= @quicinc.com/ v3 -> v4: - Update qcom,gsi-dma-allowed property name to qcom,enable-gsi-dma. - Remove full stop form title. - Add reference of common schema YAML in the I2C, SPI, and SERIAL YAML file= s. v3 Link: https://lore.kernel.org/linux-arm-msm/20250303124349.3474185-3-qui= c_vdadhani@quicinc.com/ --- --- .../bindings/i2c/qcom,i2c-geni-qcom.yaml | 1 + .../serial/qcom,serial-geni-qcom.yaml | 1 + .../soc/qcom/qcom,se-common-props.yaml | 26 +++++++++++++++++++ .../bindings/spi/qcom,spi-geni-qcom.yaml | 1 + 4 files changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,se-comm= on-props.yaml diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml = b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml index 9f66a3bb1f80..51534953a69c 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml @@ -75,6 +75,7 @@ required: =20 allOf: - $ref: /schemas/i2c/i2c-controller.yaml# + - $ref: /schemas/soc/qcom/qcom,se-common-props.yaml# - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom= .yaml b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml index dd33794b3534..ed7b3909d87d 100644 --- a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml +++ b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml @@ -12,6 +12,7 @@ maintainers: =20 allOf: - $ref: /schemas/serial/serial.yaml# + - $ref: /schemas/soc/qcom/qcom,se-common-props.yaml# =20 properties: compatible: diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,se-common-prop= s.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,se-common-props.ya= ml new file mode 100644 index 000000000000..6a34f05a07e8 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,se-common-props.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,se-common-props.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QUP Peripheral-specific properties for I2C, SPI and SERIAL bus + +description: + The Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) is + a programmable module that supports a wide range of serial interfaces + such as UART, SPI, I2C, I3C, etc. This defines the common properties used + across QUP-supported peripherals. + +maintainers: + - Mukesh Kumar Savaliya + - Viken Dadhaniya + +properties: + qcom,enable-gsi-dma: + $ref: /schemas/types.yaml#/definitions/flag + description: + Configure the Serial Engine (SE) to transfer data in QCOM GPI DMA mo= de. + By default, FIFO mode (PIO/CPU DMA) will be selected. + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml = b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml index 2e20ca313ec1..d12c5a060ed0 100644 --- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml +++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml @@ -25,6 +25,7 @@ description: =20 allOf: - $ref: /schemas/spi/spi-controller.yaml# + - $ref: /schemas/soc/qcom/qcom,se-common-props.yaml# =20 properties: compatible: --=20 2.34.1 From nobody Sat Oct 4 00:28:04 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F321B2E9EBE for ; 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charset="utf-8" Refactor register macros for consistency and clarity and remove redundant definitions and update naming for better alignment. Update copyright to include Qualcomm Technologies, Inc. Signed-off-by: Viken Dadhaniya --- drivers/soc/qcom/qcom-geni-se.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-s= e.c index 3c3b796333a6..e8ab2833815e 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -1,5 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 -// Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +/* + * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ =20 /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO trac= es */ #define __DISABLE_TRACE_MMIO__ @@ -110,22 +113,20 @@ struct geni_se_desc { static const char * const icc_path_names[] =3D {"qup-core", "qup-config", "qup-memory"}; =20 -#define QUP_HW_VER_REG 0x4 +/* Common QUPV3 registers */ +#define QUPV3_HW_VER_REG 0x4 =20 /* Common SE registers */ -#define GENI_INIT_CFG_REVISION 0x0 -#define GENI_S_INIT_CFG_REVISION 0x4 -#define GENI_OUTPUT_CTRL 0x24 -#define GENI_CGC_CTRL 0x28 -#define GENI_CLK_CTRL_RO 0x60 -#define GENI_FW_S_REVISION_RO 0x6c +#define SE_GENI_INIT_CFG_REVISION 0x0 +#define SE_GENI_S_INIT_CFG_REVISION 0x4 +#define SE_GENI_CGC_CTRL 0x28 +#define SE_GENI_CLK_CTRL_RO 0x60 +#define SE_GENI_FW_S_REVISION_RO 0x6c #define SE_GENI_BYTE_GRAN 0x254 #define SE_GENI_TX_PACKING_CFG0 0x260 #define SE_GENI_TX_PACKING_CFG1 0x264 #define SE_GENI_RX_PACKING_CFG0 0x284 #define SE_GENI_RX_PACKING_CFG1 0x288 -#define SE_GENI_M_GP_LENGTH 0x910 -#define SE_GENI_S_GP_LENGTH 0x914 #define SE_DMA_TX_PTR_L 0xc30 #define SE_DMA_TX_PTR_H 0xc34 #define SE_DMA_TX_ATTR 0xc38 @@ -142,7 +143,6 @@ static const char * const icc_path_names[] =3D {"qup-co= re", "qup-config", #define SE_DMA_RX_IRQ_EN 0xd48 #define SE_DMA_RX_IRQ_EN_SET 0xd4c #define SE_DMA_RX_IRQ_EN_CLR 0xd50 -#define SE_DMA_RX_LEN_IN 0xd54 #define SE_DMA_RX_MAX_BURST 0xd5c #define SE_DMA_RX_FLUSH 0xd60 #define SE_GSI_EVENT_EN 0xe18 @@ -179,7 +179,7 @@ static const char * const icc_path_names[] =3D {"qup-co= re", "qup-config", /* SE_DMA_GENERAL_CFG */ #define DMA_RX_CLK_CGC_ON BIT(0) #define DMA_TX_CLK_CGC_ON BIT(1) -#define DMA_AHB_SLV_CFG_ON BIT(2) +#define DMA_AHB_SLV_CLK_CGC_ON BIT(2) #define AHB_SEC_SLV_CLK_CGC_ON BIT(3) #define DUMMY_RX_NON_BUFFERABLE BIT(4) #define RX_DMA_ZERO_PADDING_EN BIT(5) @@ -196,7 +196,7 @@ u32 geni_se_get_qup_hw_version(struct geni_se *se) { struct geni_wrapper *wrapper =3D se->wrapper; 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charset="utf-8" In Qualcomm SoCs, firmware loading for Serial Engines (SE) within the QUP hardware has traditionally been managed by TrustZone (TZ). This restriction poses a significant challenge for developers, as it limits their ability to enable various protocols on any of the SEs from the Linux side, reducing flexibility. Load the firmware to QUP SE based on the 'firmware-name' property specified in devicetree at bootup time. Co-developed-by: Mukesh Kumar Savaliya Signed-off-by: Mukesh Kumar Savaliya Signed-off-by: Viken Dadhaniya --- v5 -> v6: - Moved contents of qup-fw-load.h into qcom-geni-se.c. - Specified endianness for all members of the se_fw_hdr structure. - Changed the return type and arguments of the geni_read_elf function. - Renamed geni_read_elf to geni_find_protocol_fw for clarity. - Added error logging for corrupt firmware. - Passed SE mode and protocol type explicitly to all relevant functions. - Replaced writel_relaxed with writel for stricter memory ordering. - Renamed variable reg_val to reg for consistency. - Moved firmware length validation logic into geni_find_protocol_fw. - Updated function documentation for clarity and accuracy. - Removed redundant firmware length check. - Inlined the qup_fw_load function and removed its definition. - Removed the MAX_PROTOCOL macro. - Dropped mode and protocol fields from the geni_se structure. - Moved unrelated firmware loading code into a separate patch. v5 Link: https://lore.kernel.org/linux-i2c/20250624095102.1587580-3-viken.d= adhaniya@oss.qualcomm.com/ v4 -> v5: - Resolved kernel test robot error by including the missing bitfield header= file. - Updated the SE firmware ELF structure name for consistency. - Specified _leb4 format for the magic number definition. - Updated the email domain from 'quic' to 'oss'. v4 Link: https://lore.kernel.org/all/20250503111029.3583807-3-quic_vdadhani= @quicinc.com/ v3 -> v4: - Update the commit message. - Resolve kernel test robot warnings. - Add a multiline comment in the Copyright section. - Remove valid_seg_size and geni_config_common_control functions, and add t= he code inline. - Rename read_elf function to geni_read_elf. - Add a firmware size check. - Assign *pelfseg after finding a match. - Break one large condition check into multiple checks to improve code read= ability. - Remove return type documentation for void functions. - Update error messages to be more descriptive. - Correct indentation. - Rename geni_flash_fw_revision function to geni_write_fw_revision. - Remove __func__ from all print statements. - Move resource_on to the appropriate section after parsing the firmware fi= le. - Update variable names and function arguments as suggested. - Use FIELD_GET, FIELD_PREP, and GENMASK. - Use memcpy_toio() instead of memcpy. - Remove duplicate registers and bitmask macros. - Remove rsc struct and add required variables in geni_se struct. v3 Link: https://lore.kernel.org/linux-arm-msm/20250303124349.3474185-7-qui= c_vdadhani@quicinc.com/ v2 -> v3: - Remove code related to the 'qcom,xfer-mode' property. - Add logic to read the boolean property 'qcom,gsi-dma-allowed' and select = the transfer mode. - Hardcode FIFO mode for the serial driver as GSI mode is currently not sup= ported. - Update function descriptions as suggested. - Enhance error handling and remove redundant if conditions. - Drop the ternary operator. v2 Link: https://lore.kernel.org/linux-arm-msm/20250124105309.295769-6-quic= _vdadhani@quicinc.com/ v1 -> v2: - Remove the fixed firmware path and add logic to read the path from the de= vice tree. - Remove code related to the 'qcom,load-firmware' property. - Resolve kernel test robot warnings. - Update the commit message. - Update Copyright year. v1 Link: https://lore.kernel.org/linux-kernel/20241204150326.1470749-5-quic= _vdadhani@quicinc.com/ --- --- drivers/soc/qcom/qcom-geni-se.c | 461 ++++++++++++++++++++++++++++++- include/linux/soc/qcom/geni-se.h | 4 + 2 files changed, 462 insertions(+), 3 deletions(-) diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-s= e.c index e8ab2833815e..d40b6d0395d0 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -8,7 +8,9 @@ #define __DISABLE_TRACE_MMIO__ =20 #include +#include #include +#include #include #include #include @@ -113,8 +115,80 @@ struct geni_se_desc { static const char * const icc_path_names[] =3D {"qup-core", "qup-config", "qup-memory"}; =20 +static const char * const protocol_name[] =3D { "None", "SPI", "UART", "I2= C", "I3C", "SPI SLAVE" }; + +/** + * struct se_fw_hdr - Serial Engine firmware configuration header + * + * This structure defines the SE firmware header, which together with the + * firmware payload is stored in individual ELF segments. + * + * @magic: Set to 'SEFW'. + * @version: Structure version number. + * @core_version: QUPV3 hardware version. + * @serial_protocol: Encoded in GENI_FW_REVISION. + * @fw_version: Firmware version, from GENI_FW_REVISION. + * @cfg_version: Configuration version, from GENI_INIT_CFG_REVISION. + * @fw_size_in_items: Number of 32-bit words in GENI_FW_RAM. + * @fw_offset: Byte offset to GENI_FW_RAM array. + * @cfg_size_in_items: Number of GENI_FW_CFG index/value pairs. + * @cfg_idx_offset: Byte offset to GENI_FW_CFG index array. + * @cfg_val_offset: Byte offset to GENI_FW_CFG values array. + */ +struct se_fw_hdr { + __le32 magic; + __le32 version; + __le32 core_version; + __le16 serial_protocol; + __le16 fw_version; + __le16 cfg_version; + __le16 fw_size_in_items; + __le16 fw_offset; + __le16 cfg_size_in_items; + __le16 cfg_idx_offset; + __le16 cfg_val_offset; +}; + +/*Magic numbers*/ +#define SE_MAGIC_NUM 0x57464553 + +#define MAX_GENI_CFG_RAMn_CNT 455 + +#define MI_PBT_NON_PAGED_SEGMENT 0x0 +#define MI_PBT_HASH_SEGMENT 0x2 +#define MI_PBT_NOTUSED_SEGMENT 0x3 +#define MI_PBT_SHARED_SEGMENT 0x4 + +#define MI_PBT_FLAG_PAGE_MODE BIT(20) +#define MI_PBT_FLAG_SEGMENT_TYPE GENMASK(26, 24) +#define MI_PBT_FLAG_ACCESS_TYPE GENMASK(23, 21) + +#define MI_PBT_PAGE_MODE_VALUE(x) FIELD_GET(MI_PBT_FLAG_PAGE_MODE, x) + +#define MI_PBT_SEGMENT_TYPE_VALUE(x) FIELD_GET(MI_PBT_FLAG_SEGMENT_TYPE, x) + +#define MI_PBT_ACCESS_TYPE_VALUE(x) FIELD_GET(MI_PBT_FLAG_ACCESS_TYPE, x) + +#define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \ + M_IO_DATA_DEASSERT_EN | \ + M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \ + M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \ + M_TX_FIFO_WR_ERR_EN) + /* Common QUPV3 registers */ #define QUPV3_HW_VER_REG 0x4 +#define QUPV3_SE_AHB_M_CFG 0x118 +#define QUPV3_COMMON_CFG 0x120 +#define QUPV3_COMMON_CGC_CTRL 0x21c + +/* QUPV3_COMMON_CFG fields */ +#define FAST_SWITCH_TO_HIGH_DISABLE BIT(0) + +/* QUPV3_SE_AHB_M_CFG fields */ +#define AHB_M_CLK_CGC_ON BIT(0) + +/* QUPV3_COMMON_CGC_CTRL fields */ +#define COMMON_CSR_SLV_CLK_CGC_ON BIT(0) =20 /* Common SE registers */ #define SE_GENI_INIT_CFG_REVISION 0x0 @@ -122,11 +196,13 @@ static const char * const icc_path_names[] =3D {"qup-= core", "qup-config", #define SE_GENI_CGC_CTRL 0x28 #define SE_GENI_CLK_CTRL_RO 0x60 #define SE_GENI_FW_S_REVISION_RO 0x6c +#define SE_GENI_CFG_REG0 0x100 #define SE_GENI_BYTE_GRAN 0x254 #define SE_GENI_TX_PACKING_CFG0 0x260 #define SE_GENI_TX_PACKING_CFG1 0x264 #define SE_GENI_RX_PACKING_CFG0 0x284 #define SE_GENI_RX_PACKING_CFG1 0x288 +#define SE_GENI_S_IRQ_ENABLE 0x644 #define SE_DMA_TX_PTR_L 0xc30 #define SE_DMA_TX_PTR_H 0xc34 #define SE_DMA_TX_ATTR 0xc38 @@ -148,6 +224,15 @@ static const char * const icc_path_names[] =3D {"qup-c= ore", "qup-config", #define SE_GSI_EVENT_EN 0xe18 #define SE_IRQ_EN 0xe1c #define SE_DMA_GENERAL_CFG 0xe30 +#define SE_GENI_FW_REVISION 0x1000 +#define SE_GENI_S_FW_REVISION 0x1004 +#define SE_GENI_CFG_RAMN 0x1010 +#define SE_GENI_CLK_CTRL 0x2000 +#define SE_DMA_IF_EN 0x2004 +#define SE_FIFO_IF_DISABLE 0x2008 + +/* GENI_FW_REVISION_RO fields */ +#define FW_REV_VERSION_MSK GENMASK(7, 0) =20 /* GENI_OUTPUT_CTRL fields */ #define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0) @@ -186,6 +271,15 @@ static const char * const icc_path_names[] =3D {"qup-c= ore", "qup-config", #define RX_DMA_IRQ_DELAY_MSK GENMASK(8, 6) #define RX_DMA_IRQ_DELAY_SHFT 6 =20 +/* GENI_CLK_CTRL fields */ +#define SER_CLK_SEL BIT(0) + +/* GENI_DMA_IF_EN fields */ +#define DMA_IF_EN BIT(0) + +#define geni_setbits32(_addr, _v) writel(readl(_addr) | (_v), _addr) +#define geni_clrbits32(_addr, _v) writel(readl(_addr) & ~(_v), _addr) + /** * geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version * @se: Pointer to the corresponding serial engine. @@ -658,9 +752,12 @@ int geni_se_clk_freq_match(struct geni_se *se, unsigne= d long req_freq, } EXPORT_SYMBOL_GPL(geni_se_clk_freq_match); =20 -#define GENI_SE_DMA_DONE_EN BIT(0) -#define GENI_SE_DMA_EOT_EN BIT(1) -#define GENI_SE_DMA_AHB_ERR_EN BIT(2) +#define GENI_SE_DMA_DONE_EN BIT(0) +#define GENI_SE_DMA_EOT_EN BIT(1) +#define GENI_SE_DMA_AHB_ERR_EN BIT(2) +#define GENI_SE_DMA_RESET_DONE_EN BIT(3) +#define GENI_SE_DMA_FLUSH_DONE BIT(4) + #define GENI_SE_DMA_EOT_BUF BIT(0) =20 /** @@ -891,6 +988,364 @@ int geni_icc_disable(struct geni_se *se) } EXPORT_SYMBOL_GPL(geni_icc_disable); =20 +/** + * geni_find_protocol_fw() - Locate and validate SE firmware for a protoco= l. + * @dev: Pointer to the device structure. + * @fw: Pointer to the firmware image. + * @protocol: Expected serial engine protocol type. + * + * Identifies the appropriate firmware image or configuration required for= a + * specific communication protocol instance running on a Qualcomm GENI + * controller. + * + * Return: pointer to a valid 'struct se_fw_hdr' if found, or NULL otherwi= se. + */ +static struct se_fw_hdr *geni_find_protocol_fw(struct device *dev, const s= truct firmware *fw, + enum geni_se_protocol_type protocol) +{ + const struct elf32_hdr *ehdr; + const struct elf32_phdr *phdrs; + const struct elf32_phdr *phdr; + struct se_fw_hdr *sefw; + int i; + + if (!fw || fw->size < sizeof(struct elf32_hdr)) + return NULL; + + ehdr =3D (const struct elf32_hdr *)fw->data; + phdrs =3D (const struct elf32_phdr *)(fw->data + ehdr->e_phoff); + + /* + * The firmware is expected to have at least two program headers (segment= s). + * One for metadata and the other for the actual protocol-specific firmwa= re. + */ + if (ehdr->e_phnum < 2) { + dev_err(dev, "Invalid firmware: less than 2 program headers\n"); + return NULL; + } + + for (i =3D 0; i < ehdr->e_phnum; i++) { + phdr =3D &phdrs[i]; + + if (fw->size < phdr->p_offset + phdr->p_filesz) { + dev_err(dev, "Firmware size (%zu) is smaller than expected offset + siz= e (%u + %u)\n", + fw->size, phdr->p_offset, phdr->p_filesz); + return NULL; + } + + if (phdr->p_type !=3D PT_LOAD || !phdr->p_memsz) + continue; + + if (MI_PBT_PAGE_MODE_VALUE(phdr->p_flags) !=3D MI_PBT_NON_PAGED_SEGMENT = || + MI_PBT_SEGMENT_TYPE_VALUE(phdr->p_flags) =3D=3D MI_PBT_HASH_SEGMENT = || + MI_PBT_ACCESS_TYPE_VALUE(phdr->p_flags) =3D=3D MI_PBT_NOTUSED_SEGMEN= T || + MI_PBT_ACCESS_TYPE_VALUE(phdr->p_flags) =3D=3D MI_PBT_SHARED_SEGMENT) + continue; + + if (phdr->p_filesz < sizeof(struct se_fw_hdr)) + continue; + + sefw =3D (struct se_fw_hdr *)(fw->data + phdr->p_offset); + + if (le32_to_cpu(sefw->magic) !=3D SE_MAGIC_NUM || le32_to_cpu(sefw->vers= ion) !=3D 1) + continue; + + if (le32_to_cpu(sefw->serial_protocol) !=3D protocol) + continue; + + if (sefw->fw_size_in_items % 2 !=3D 0) + sefw->fw_size_in_items++; + + if (sefw->fw_size_in_items >=3D MAX_GENI_CFG_RAMn_CNT) { + dev_err(dev, "Corrupt firmware: fw_size_in_items (%u) exceeds max allow= ed RAMn count (%u)\n", + sefw->fw_size_in_items, MAX_GENI_CFG_RAMn_CNT); + continue; + } + + if (sefw->fw_offset + sefw->fw_size_in_items * sizeof(u32) > phdr->p_fil= esz || + sefw->cfg_idx_offset + sefw->cfg_size_in_items * sizeof(u8) > phdr->= p_filesz || + sefw->cfg_val_offset + sefw->cfg_size_in_items * sizeof(u32) > phdr-= >p_filesz) { + dev_err(dev, "Truncated or corrupt SE FW segment found at index %d\n", = i); + continue; + } + + return sefw; + } + + dev_err(dev, "Failed to get %s protocol firmware\n", protocol_name[protoc= ol]); + return NULL; +} + +/** + * geni_configure_xfer_mode() - Set the transfer mode. + * @se: Pointer to the concerned serial engine. + * @mode: SE data transfer mode. + * + * Set the transfer mode to either FIFO or DMA according to the mode speci= fied + * by the protocol driver. + * + * Return: 0 if successful, otherwise return an error value. + */ +static int geni_configure_xfer_mode(struct geni_se *se, enum geni_se_xfer_= mode mode) +{ + /* Configure SE FIFO, DMA or GSI mode. */ + switch (mode) { + case GENI_GPI_DMA: + geni_setbits32(se->base + SE_GENI_DMA_MODE_EN, GENI_DMA_MODE_EN); + writel(0x0, se->base + SE_IRQ_EN); + writel(DMA_RX_EVENT_EN | DMA_TX_EVENT_EN | GENI_M_EVENT_EN | GENI_S_EVEN= T_EN, + se->base + SE_GSI_EVENT_EN); + break; + + case GENI_SE_FIFO: + geni_clrbits32(se->base + SE_GENI_DMA_MODE_EN, GENI_DMA_MODE_EN); + writel(DMA_RX_IRQ_EN | DMA_TX_IRQ_EN | GENI_M_IRQ_EN | GENI_S_IRQ_EN, + se->base + SE_IRQ_EN); + writel(0x0, se->base + SE_GSI_EVENT_EN); + break; + + case GENI_SE_DMA: + geni_setbits32(se->base + SE_GENI_DMA_MODE_EN, GENI_DMA_MODE_EN); + writel(DMA_RX_IRQ_EN | DMA_TX_IRQ_EN | GENI_M_IRQ_EN | GENI_S_IRQ_EN, + se->base + SE_IRQ_EN); + writel(0x0, se->base + SE_GSI_EVENT_EN); + break; + + default: + dev_err(se->dev, "Invalid geni-se transfer mode: %d\n", mode); + return -EINVAL; + } + return 0; +} + +/** + * geni_enable_interrupts() - Enable interrupts. + * @se: Pointer to the concerned serial engine. + * + * Enable the required interrupts during the firmware load process. + */ +static void geni_enable_interrupts(struct geni_se *se) +{ + u32 val; + + /* Enable required interrupts. */ + writel(M_COMMON_GENI_M_IRQ_EN, se->base + SE_GENI_M_IRQ_EN); + + val =3D S_CMD_OVERRUN_EN | S_ILLEGAL_CMD_EN | S_CMD_CANCEL_EN | S_CMD_ABO= RT_EN | + S_GP_IRQ_0_EN | S_GP_IRQ_1_EN | S_GP_IRQ_2_EN | S_GP_IRQ_3_EN | + S_RX_FIFO_WR_ERR_EN | S_RX_FIFO_RD_ERR_EN; + writel(val, se->base + SE_GENI_S_IRQ_ENABLE); + + /* DMA mode configuration. */ + val =3D GENI_SE_DMA_RESET_DONE_EN | GENI_SE_DMA_AHB_ERR_EN | GENI_SE_DMA_= DONE_EN; + writel(val, se->base + SE_DMA_TX_IRQ_EN_SET); + val =3D GENI_SE_DMA_FLUSH_DONE | GENI_SE_DMA_RESET_DONE_EN | GENI_SE_DMA_= AHB_ERR_EN | + GENI_SE_DMA_DONE_EN; + writel(val, se->base + SE_DMA_RX_IRQ_EN_SET); +} + +/** + * geni_write_fw_revision() - Write the firmware revision. + * @se: Pointer to the concerned serial engine. + * @serial_protocol: serial protocol type. + * @fw_version: QUP firmware version. + * + * Write the firmware revision and protocol into the respective register. + */ +static void geni_write_fw_revision(struct geni_se *se, u16 serial_protocol= , u16 fw_version) +{ + u32 reg; + + reg =3D FIELD_PREP(FW_REV_PROTOCOL_MSK, serial_protocol); + reg |=3D FIELD_PREP(FW_REV_VERSION_MSK, fw_version); + + writel(reg, se->base + SE_GENI_FW_REVISION); + writel(reg, se->base + SE_GENI_S_FW_REVISION); +} + +/** + * geni_load_se_fw() - Load Serial Engine specific firmware. + * @se: Pointer to the concerned serial engine. + * @fw: Pointer to the firmware structure. + * @mode: SE data transfer mode. + * @protocol: Protocol type to be used with the SE (e.g., UART, SPI, I2C). + * + * Load the protocol firmware into the IRAM of the Serial Engine. + * + * Return: 0 if successful, otherwise return an error value. + */ +static int geni_load_se_fw(struct geni_se *se, const struct firmware *fw, + enum geni_se_xfer_mode mode, enum geni_se_protocol_type protocol) +{ + const u32 *fw_data, *cfg_val_arr; + const u8 *cfg_idx_arr; + u32 i, reg_value; + int ret; + struct se_fw_hdr *hdr; + + hdr =3D geni_find_protocol_fw(se->dev, fw, protocol); + if (!hdr) + return -EINVAL; + + fw_data =3D (const u32 *)((u8 *)hdr + le16_to_cpu(hdr->fw_offset)); + cfg_idx_arr =3D (const u8 *)hdr + le16_to_cpu(hdr->cfg_idx_offset); + cfg_val_arr =3D (const u32 *)((u8 *)hdr + le16_to_cpu(hdr->cfg_val_offset= )); + + ret =3D geni_icc_set_bw(se); + if (ret) + return ret; + + ret =3D geni_icc_enable(se); + if (ret) + return ret; + + ret =3D geni_se_resources_on(se); + if (ret) + goto out_icc_disable; + + /* + * Disable high-priority interrupts until all currently executing + * low-priority interrupts have been fully handled. + */ + geni_setbits32(se->wrapper->base + QUPV3_COMMON_CFG, FAST_SWITCH_TO_HIGH_= DISABLE); + + /* Set AHB_M_CLK_CGC_ON to indicate hardware controls se-wrapper cgc cloc= k. */ + geni_setbits32(se->wrapper->base + QUPV3_SE_AHB_M_CFG, AHB_M_CLK_CGC_ON); + + /* Let hardware to control common cgc. */ + geni_setbits32(se->wrapper->base + QUPV3_COMMON_CGC_CTRL, COMMON_CSR_SLV_= CLK_CGC_ON); + + /* + * Setting individual bits in GENI_OUTPUT_CTRL activates corresponding ou= tput lines, + * allowing the hardware to drive data as configured. + */ + writel(0x0, se->base + GENI_OUTPUT_CTRL); + + /* Set SCLK and HCLK to program RAM */ + geni_setbits32(se->base + SE_GENI_CGC_CTRL, PROG_RAM_SCLK_OFF | PROG_RAM_= HCLK_OFF); + writel(0x0, se->base + SE_GENI_CLK_CTRL); + geni_clrbits32(se->base + SE_GENI_CGC_CTRL, PROG_RAM_SCLK_OFF | PROG_RAM_= HCLK_OFF); + + /* Enable required clocks for DMA CSR, TX and RX. */ + reg_value =3D AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CLK_CGC_ON | + DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON; + geni_setbits32(se->base + SE_DMA_GENERAL_CFG, reg_value); + + /* Let hardware control CGC by default. */ + writel(DEFAULT_CGC_EN, se->base + SE_GENI_CGC_CTRL); + + /* Set version of the configuration register part of firmware. */ + writel(hdr->cfg_version, se->base + SE_GENI_INIT_CFG_REVISION); + writel(hdr->cfg_version, se->base + SE_GENI_S_INIT_CFG_REVISION); + + /* Configure GENI primitive table. */ + for (i =3D 0; i < le16_to_cpu(hdr->cfg_size_in_items); i++) + writel(cfg_val_arr[i], + se->base + SE_GENI_CFG_REG0 + (cfg_idx_arr[i] * sizeof(u32))); + + /* Configure condition for assertion of RX_RFR_WATERMARK condition. */ + reg_value =3D geni_se_get_rx_fifo_depth(se); + writel(reg_value - 2, se->base + SE_GENI_RX_RFR_WATERMARK_REG); + + /* Let hardware control CGC */ + geni_setbits32(se->base + GENI_OUTPUT_CTRL, DEFAULT_IO_OUTPUT_CTRL_MSK); + + ret =3D geni_configure_xfer_mode(se, mode); + if (ret) + goto out_resources_off; + + geni_enable_interrupts(se); + + geni_write_fw_revision(se, le16_to_cpu(hdr->serial_protocol), le16_to_cpu= (hdr->fw_version)); + + /* Program RAM address space. */ + memcpy_toio(se->base + SE_GENI_CFG_RAMN, fw_data, + le16_to_cpu(hdr->fw_size_in_items) * sizeof(u32)); + + /* Put default values on GENI's output pads. */ + writel_relaxed(0x1, se->base + GENI_FORCE_DEFAULT_REG); + + /* Toggle SCLK/HCLK from high to low to finalize RAM programming and appl= y config. */ + geni_setbits32(se->base + SE_GENI_CGC_CTRL, PROG_RAM_SCLK_OFF | PROG_RAM_= HCLK_OFF); + geni_setbits32(se->base + SE_GENI_CLK_CTRL, SER_CLK_SEL); + geni_clrbits32(se->base + SE_GENI_CGC_CTRL, PROG_RAM_SCLK_OFF | PROG_RAM_= HCLK_OFF); + + /* Serial engine DMA interface is enabled. */ + geni_setbits32(se->base + SE_DMA_IF_EN, DMA_IF_EN); + + /* Enable or disable FIFO interface of the serial engine. */ + if (mode =3D=3D GENI_SE_FIFO) + geni_clrbits32(se->base + SE_FIFO_IF_DISABLE, FIFO_IF_DISABLE); + else + geni_setbits32(se->base + SE_FIFO_IF_DISABLE, FIFO_IF_DISABLE); + +out_resources_off: + geni_se_resources_off(se); + +out_icc_disable: + geni_icc_disable(se); + return ret; +} + +/** + * geni_load_se_firmware() - Load firmware for SE based on protocol + * @se: Pointer to the concerned serial engine. + * @protocol: Protocol type to be used with the SE (e.g., UART, SPI, I2C). + * + * Retrieves the firmware name from device properties and sets the transfe= r mode + * (FIFO or GSI DMA) based on device tree configuration. Enforces FIFO mod= e for + * UART protocol due to lack of GSI DMA support. Requests the firmware and= loads + * it into the SE. + * + * Return: 0 on success, negative error code on failure. + */ +int geni_load_se_firmware(struct geni_se *se, enum geni_se_protocol_type p= rotocol) +{ + const char *fw_name; + const struct firmware *fw; + enum geni_se_xfer_mode mode =3D GENI_SE_FIFO; + int ret; + + if (protocol >=3D ARRAY_SIZE(protocol_name)) { + dev_err(se->dev, "Invalid geni-se protocol: %d", protocol); + return -EINVAL; + } + + ret =3D device_property_read_string(se->wrapper->dev, "firmware-name", &f= w_name); + if (ret) { + dev_err(se->dev, "Failed to read firmware-name property: %d\n", ret); + return -EINVAL; + } + + if (of_property_read_bool(se->dev->of_node, "qcom,enable-gsi-dma")) + mode =3D GENI_GPI_DMA; + + /* GSI mode is not supported by the UART driver; therefore, setting FIFO = mode */ + if (protocol =3D=3D GENI_SE_UART) + mode =3D GENI_SE_FIFO; + + ret =3D request_firmware(&fw, fw_name, se->dev); + if (ret) { + dev_err(se->dev, "Failed to request firmware '%s' for protocol %d: ret: = %d\n", + fw_name, protocol, ret); + return ret; + } + + ret =3D geni_load_se_fw(se, fw, mode, protocol); + release_firmware(fw); + + if (ret) { + dev_err(se->dev, "Failed to load SE firmware for protocol %d: ret: %d\n", + protocol, ret); + return ret; + } + + dev_dbg(se->dev, "Firmware load for %s protocol is successful for xfer mo= de: %d\n", + protocol_name[protocol], mode); + return 0; +} +EXPORT_SYMBOL_GPL(geni_load_se_firmware); + static int geni_se_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni= -se.h index 2996a3c28ef3..0a984e2579fe 100644 --- a/include/linux/soc/qcom/geni-se.h +++ b/include/linux/soc/qcom/geni-se.h @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2017-2018, The Linux Foundation. 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charset="utf-8" Add provision to load firmware of Serial engine for I2C protocol from Linux Execution Environment on running on APPS processor. Acked-by: Andi Shyti Co-developed-by: Mukesh Kumar Savaliya Signed-off-by: Mukesh Kumar Savaliya Signed-off-by: Viken Dadhaniya --- Dependencies: This patch depends on patch 3 of this series. v5 -> v6: - Added Acked-by tag. v5 Link: https://lore.kernel.org/linux-i2c/20250624095102.1587580-4-viken.d= adhaniya@oss.qualcomm.com/ v4 -> v5: - Updated the email domain from 'quic' to 'oss'. v4 Link: https://lore.kernel.org/all/20250503111029.3583807-4-quic_vdadhani= @quicinc.com/ v3 - >v4: - Add a patch dependency note. v3 Link: https://lore.kernel.org/linux-arm-msm/20250303124349.3474185-8-qui= c_vdadhani@quicinc.com/ v2 -> v3: - Load firmware only if the protocol is invalid. v2 Link: https://lore.kernel.org/linux-arm-msm/20250124105309.295769-7-quic= _vdadhani@quicinc.com/ v1 -> v2: - No change. v1 Link: https://lore.kernel.org/linux-arm-msm/20241204150326.1470749-6-qui= c_vdadhani@quicinc.com/ --- --- drivers/i2c/busses/i2c-qcom-geni.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/i2c/busses/i2c-qcom-geni.c b/drivers/i2c/busses/i2c-qc= om-geni.c index ff2289b52c84..95a577764d5c 100644 --- a/drivers/i2c/busses/i2c-qcom-geni.c +++ b/drivers/i2c/busses/i2c-qcom-geni.c @@ -870,7 +870,13 @@ static int geni_i2c_probe(struct platform_device *pdev) goto err_clk; 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charset="utf-8" Add provision to load firmware of Serial engine for SPI protocol from Linux Execution Environment on running on APPS processor. Co-developed-by: Mukesh Kumar Savaliya Signed-off-by: Mukesh Kumar Savaliya Signed-off-by: Viken Dadhaniya --- Dependencies: This patch depends on patch 3 of this series. v5 -> v6: - No change. v5 Link: https://lore.kernel.org/linux-i2c/20250624095102.1587580-5-viken.d= adhaniya@oss.qualcomm.com/ v4 -> v5: - Updated the email domain from 'quic' to 'oss'. v4 Link: https://lore.kernel.org/all/20250503111029.3583807-5-quic_vdadhani= @quicinc.com/ v3 -> v4: - Add a patch dependency note. v3 Link: https://lore.kernel.org/linux-arm-msm/20250303124349.3474185-9-qui= c_vdadhani@quicinc.com/ v2 -> v3: - Load firmware only if the protocol is invalid. v2 Link: https://lore.kernel.org/linux-arm-msm/20250124105309.295769-8-quic= _vdadhani@quicinc.com/ v1 -> v2: - No change. v1 Link: https://lore.kernel.org/linux-arm-msm/20241204150326.1470749-7-qui= c_vdadhani@quicinc.com/ --- --- drivers/spi/spi-geni-qcom.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c index 768d7482102a..a0d8d3425c6c 100644 --- a/drivers/spi/spi-geni-qcom.c +++ b/drivers/spi/spi-geni-qcom.c @@ -671,6 +671,12 @@ static int spi_geni_init(struct spi_geni_master *mas) goto out_pm; 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charset="utf-8" Add provision to load firmware of Serial engine for UART protocol from Linux Execution Environment on running on APPS processor. Co-developed-by: Mukesh Kumar Savaliya Signed-off-by: Mukesh Kumar Savaliya Signed-off-by: Viken Dadhaniya --- Dependencies: This patch depends on patch 3 of this series. v5 -> v6: - No change. v5 Link: https://lore.kernel.org/linux-i2c/20250624095102.1587580-6-viken.d= adhaniya@oss.qualcomm.com/ v4 -> v5: - Updated the email domain from 'quic' to 'oss'. v4 Link: https://lore.kernel.org/all/20250503111029.3583807-6-quic_vdadhani= @quicinc.com/ v3 -> v4: - Add a patch dependency note. v3 Link: https://lore.kernel.org/linux-arm-msm/20250303124349.3474185-10-qu= ic_vdadhani@quicinc.com/ v2 -> v3: - Load firmware only if the protocol is invalid. v2 Link: https://lore.kernel.org/linux-arm-msm/20250124105309.295769-9-quic= _vdadhani@quicinc.com/ v1 -> v2: - No change. v1 Link: https://lore.kernel.org/linux-arm-msm/20241204150326.1470749-8-qui= c_vdadhani@quicinc.com/ --- --- drivers/tty/serial/qcom_geni_serial.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/qcom_geni_serial.c b/drivers/tty/serial/qco= m_geni_serial.c index 9c7b1cea7cfe..eba225be9b38 100644 --- a/drivers/tty/serial/qcom_geni_serial.c +++ b/drivers/tty/serial/qcom_geni_serial.c @@ -1179,7 +1179,13 @@ static int qcom_geni_serial_port_setup(struct uart_p= ort *uport) int ret; =20 proto =3D geni_se_read_proto(&port->se); - if (proto !=3D GENI_SE_UART) { + if (proto =3D=3D GENI_SE_INVALID_PROTO) { + ret =3D geni_load_se_firmware(&port->se, GENI_SE_UART); + if (ret) { + dev_err(uport->dev, "UART firmware load failed ret: %d\n", ret); + return ret; + } + } else if (proto !=3D GENI_SE_UART) { dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto); return -ENXIO; } --=20 2.34.1