From nobody Sat Oct 4 01:39:24 2025 Received: from szxga01-in.huawei.com (szxga01-in.huawei.com [45.249.212.187]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C68422F74E; Fri, 22 Aug 2025 03:40:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.187 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755834008; cv=none; b=JB+4sBM6uemZUtoh0wZgTjFufk1lblC+hLEAnbyj+5rjpJ+zeoxtJ1KFj4izTCGMbohhsd53NAMeUmBoXx6OQ3FLkUu29TRQsOn21MXJAaLOLaiEZVr3OwmYfkpahXFnkRsMlY8+eFmdNRNXmJCLPfswtgDb0qNTGkklZdtQzjs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755834008; c=relaxed/simple; bh=8CBD+ofFcWSQllEJ2EbjzdAgpR1iEW+k2AnNO+4Wh50=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=FZyf3YIoeV/XS+TtQWNbYuloqT+efurlLdkKLd46xly2heVmQz6ggD9NtEUiUDBJTdEdasdIWCgLWt6WTV/VTOEE0PqxuXX55c+/5AeCu//aFneMte01zEXzZZBTUr5twDcvLh5dUr+A/LUtd9o8f1cpCaz8bQrj4x6kk8YnX/4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.187 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.174]) by szxga01-in.huawei.com (SkyGuard) with ESMTP id 4c7QtR395wz14MR8; Fri, 22 Aug 2025 11:39:59 +0800 (CST) Received: from dggpemf500011.china.huawei.com (unknown [7.185.36.131]) by mail.maildlp.com (Postfix) with ESMTPS id 03FF31402DF; Fri, 22 Aug 2025 11:40:04 +0800 (CST) Received: from huawei.com (10.67.174.55) by dggpemf500011.china.huawei.com (7.185.36.131) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Fri, 22 Aug 2025 11:40:03 +0800 From: Jinjie Ruan To: , , , , , , , , , CC: Subject: [PATCH v5.15 RESEND 2/2] x86/irq: Plug vector setup race Date: Fri, 22 Aug 2025 03:36:08 +0000 Message-ID: <20250822033608.1096607-3-ruanjinjie@huawei.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250822033608.1096607-1-ruanjinjie@huawei.com> References: <20250822033608.1096607-1-ruanjinjie@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems500002.china.huawei.com (7.221.188.17) To dggpemf500011.china.huawei.com (7.185.36.131) Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner commit ce0b5eedcb753697d43f61dd2e27d68eb5d3150f upstream. Hogan reported a vector setup race, which overwrites the interrupt descriptor in the per CPU vector array resulting in a disfunctional device. CPU0 CPU1 interrupt is raised in APIC IRR but not handled free_irq() per_cpu(vector_irq, CPU1)[vector] =3D VECTOR_SHUTDOWN; request_irq() common_interrupt() d =3D this_cpu_read(vector_irq[vector]); per_cpu(vector_irq, CPU1)[vector] =3D desc; if (d =3D=3D VECTOR_SHUTDOWN) this_cpu_write(vector_irq[vector], VECTOR_UNUSED); free_irq() cannot observe the pending vector in the CPU1 APIC as there is no way to query the remote CPUs APIC IRR. This requires that request_irq() uses the same vector/CPU as the one which was freed, but this also can be triggered by a spurious interrupt. Interestingly enough this problem managed to be hidden for more than a decade. Prevent this by reevaluating vector_irq under the vector lock, which is held by the interrupt activation code when vector_irq is updated. To avoid ifdeffery or IS_ENABLED() nonsense, move the [un]lock_vector_lock() declarations out under the CONFIG_IRQ_DOMAIN_HIERARCHY guard as it's only provided when CONFIG_X86_LOCAL_APIC=3Dy. The current CONFIG_IRQ_DOMAIN_HIERARCHY guard is selected by CONFIG_X86_LOCAL_APIC, but can also be selected by other parts of the Kconfig system, which makes 32-bit UP builds with CONFIG_X86_LOCAL_APIC=3Dn fail. Can we just get rid of this !APIC nonsense once and forever? Fixes: 9345005f4eed ("x86/irq: Fix do_IRQ() interrupt warning for cpu hotpl= ug retriggered irqs") Cc: stable@vger.kernel.org#5.15.x Cc: gregkh@linuxfoundation.org Reported-by: Hogan Wang Signed-off-by: Thomas Gleixner Tested-by: Hogan Wang Link: https://lore.kernel.org/all/draft-87ikjhrhhh.ffs@tglx [ Conflicts in arch/x86/kernel/irq.c because call_irq_handler() has been refactored to do apic_eoi() according to the return value. Conflicts in arch/x86/include/asm/hw_irq.h because (un)lock_vector_lock() are already controlled by CONFIG_X86_LOCAL_APIC. ] Signed-off-by: Jinjie Ruan --- arch/x86/kernel/irq.c | 65 +++++++++++++++++++++++++++++++++---------- 1 file changed, 51 insertions(+), 14 deletions(-) diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c index 11d7233397df..065251fa3e40 100644 --- a/arch/x86/kernel/irq.c +++ b/arch/x86/kernel/irq.c @@ -235,24 +235,59 @@ static __always_inline void handle_irq(struct irq_des= c *desc, __handle_irq(desc, regs); } =20 -static __always_inline void call_irq_handler(int vector, struct pt_regs *r= egs) +static struct irq_desc *reevaluate_vector(int vector) { - struct irq_desc *desc; + struct irq_desc *desc =3D __this_cpu_read(vector_irq[vector]); + + if (!IS_ERR_OR_NULL(desc)) + return desc; + + if (desc =3D=3D VECTOR_UNUSED) + pr_emerg_ratelimited("No irq handler for %d.%u\n", smp_processor_id(), v= ector); + else + __this_cpu_write(vector_irq[vector], VECTOR_UNUSED); + return NULL; +} + +static __always_inline bool call_irq_handler(int vector, struct pt_regs *r= egs) +{ + struct irq_desc *desc =3D __this_cpu_read(vector_irq[vector]); =20 - desc =3D __this_cpu_read(vector_irq[vector]); if (likely(!IS_ERR_OR_NULL(desc))) { handle_irq(desc, regs); - } else { - ack_APIC_irq(); - - if (desc =3D=3D VECTOR_UNUSED) { - pr_emerg_ratelimited("%s: %d.%u No irq handler for vector\n", - __func__, smp_processor_id(), - vector); - } else { - __this_cpu_write(vector_irq[vector], VECTOR_UNUSED); - } + return true; } + + /* + * Reevaluate with vector_lock held to prevent a race against + * request_irq() setting up the vector: + * + * CPU0 CPU1 + * interrupt is raised in APIC IRR + * but not handled + * free_irq() + * per_cpu(vector_irq, CPU1)[vector] =3D VECTOR_SHUTDOWN; + * + * request_irq() common_interrupt() + * d =3D this_cpu_read(vector_irq[vector]); + * + * per_cpu(vector_irq, CPU1)[vector] =3D desc; + * + * if (d =3D=3D VECTOR_SHUTDOWN) + * this_cpu_write(vector_irq[vector], VECTOR_UNUSED); + * + * This requires that the same vector on the same target CPU is + * handed out or that a spurious interrupt hits that CPU/vector. + */ + lock_vector_lock(); + desc =3D reevaluate_vector(vector); + unlock_vector_lock(); + + if (!desc) + return false; + + handle_irq(desc, regs); + return true; } =20 /* @@ -266,7 +301,9 @@ DEFINE_IDTENTRY_IRQ(common_interrupt) /* entry code tells RCU that we're not quiescent. Check it. */ RCU_LOCKDEP_WARN(!rcu_is_watching(), "IRQ failed to wake up RCU"); =20 - call_irq_handler(vector, regs); + if (unlikely(!call_irq_handler(vector, regs))) + ack_APIC_irq(); + set_irq_regs(old_regs); } =20 --=20 2.34.1