From nobody Sat Oct 4 00:26:51 2025 Received: from smtpbg154.qq.com (smtpbg154.qq.com [15.184.224.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A00C6126C1E for ; Fri, 22 Aug 2025 02:36:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=15.184.224.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755830195; cv=none; b=Ax1/EZR71fDtManFwoR6hI4f2+O/eCd9eN1dffYDaU3aZtAGZTDE9yGzbF5kNLiDrodVHs8rtGeiWAzpl5mKRH07F9PJBIswriE6UgLeKSIlDgsVgOzoGvy7/NRPFP9/BhygiyaMzpSxnCe5sz0BwGF2YrWWL5OP725/SlNoaZk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755830195; c=relaxed/simple; bh=HKBAA4VxEZOqZL2o1kfwFuJ3K3FL2NnQlqRYQJt8ZxQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=TUrNg8bWYqKacx+jk2wgpTDyQdlqMVc09fZv0BUhQHRTx9lV/rNZX1l6ENRc52DJ0z5Xngwk3piYnhcUE1D4RJ/BvVDdzKPwS3BBls9IYZ7/fUnivcYAu4ceQv4b4IQdJvsvy04zUiV6IG64ySUdT0yc5l2RyWMSxTtFUnckPJ0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=mucse.com; spf=pass smtp.mailfrom=mucse.com; arc=none smtp.client-ip=15.184.224.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=mucse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mucse.com X-QQ-mid: esmtpgz14t1755830107t4edccde3 X-QQ-Originating-IP: HYT3rhxQHNIHzE/tIfp5+ErUvu05+1Dictwf46FIXqQ= Received: from localhost.localdomain ( [203.174.112.180]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 22 Aug 2025 10:35:05 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 17238093899132926662 EX-QQ-RecipientCnt: 26 From: Dong Yibo To: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, horms@kernel.org, corbet@lwn.net, gur.stavi@huawei.com, maddy@linux.ibm.com, mpe@ellerman.id.au, danishanwar@ti.com, lee@trager.us, gongfan1@huawei.com, lorenzo@kernel.org, geert+renesas@glider.be, Parthiban.Veerasooran@microchip.com, lukas.bulwahn@redhat.com, alexanderduyck@fb.com, richardcochran@gmail.com, kees@kernel.org, gustavoars@kernel.org Cc: netdev@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, dong100@mucse.com Subject: [PATCH net-next v7 1/5] net: rnpgbe: Add build support for rnpgbe Date: Fri, 22 Aug 2025 10:34:49 +0800 Message-Id: <20250822023453.1910972-2-dong100@mucse.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250822023453.1910972-1-dong100@mucse.com> References: <20250822023453.1910972-1-dong100@mucse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:mucse.com:qybglogicsvrgz:qybglogicsvrgz8a-1 X-QQ-XMAILINFO: M8e5kblytUZRDrCHYeiPs/LUVdynDCC8/Y/3yy2T1YS9P3TS2I4sPOJB NfwgXZECNCq6LfO8uPHJP3RoumR/2PIhhWhLF4ldyIoeAjBSQthvY4mTB2Meh2nFW8SuGfz DwDh8TUJvwqHk/loBcekSgemvvM75BAw8jO2NS07YqNQ5iXrXld77m+DvVN6ZDK8n9MocZf LyVLupRJm1zHki+6jdAzXdTeMQIUlQ5fkm+2zKqTMFQ/ywpyHwdIiDic5zBG7lJAbMYjB5T p+HljtI2cgYVtWTCACWpMXTrC1Zc8+YZoGV4b8GSGdVNrw4Yd9GOX5A3LrCH0uZRO8bWCvC +eGGMcT2+aDUj4iKXszSJFdMW+nzL3mqW5CDwa6chmun2uaUGFEdU9orsq3/raOrEKfksSw 7APZbTVV3WsslQ/llVo6bIgt4wdNncdi4528dnnBJcEdB8f6EIZyV36gcsS7lbkNm26Iq3Q LgsSXuFPxLa2ncnO+fNBD/zAb1AQo4Qe3t/0fsRTeb4QZKG/u/Zfb8WeenEzKBwoFK6F0g1 Af+liBghOuDfU++hlhH+Ok6hJjReAn7lUS3y2sBGbrVpTzJQYSe7ZRr3wkKPAE5bRKsFdKG Rg71FJfuO76jBJ0EG6iVba/Xf3B+96mVs+/JCuilRStKQBql0dcZGOeOCKxHaT6YhdEtetL LY4XwsWH6seTB/8+nVFsPLANXw3XQb0rfjXFXxtNZz4YRhVJYd2T31RayGCiz90Hopkapgc VJgNavA6uNieqUJd2eHOzyB9QvghzWcgz0izF5IhS3jkzcmy95vL/Fct8FwDAYAp33UuLTR AMZraIWZIU/d43SABleXGEw3Hp4RL6PuF0eItf3mozj5h3W1SBjSq6U4JmI5jS+UE9VW/7Z RA0smxJI/WuU7/FaIDhdcmr3YUkuJKaUUjH85h1fhQfDkE1Bqhi7+BTniSL4nK5kgAx6tIX xlTI529zL5Cxa3bFGmv2Xz76voAo8lSFylhrnbb/WFjWwj711x9mwE20//zhMWv8a8lMHdl k10hEpXpWnRHAmrF3bod5QTRm37CCvPoqD99HsHySwPCUCXUx9bVQUhVQUA3775qgryqIzR itMSITdUeRnqSmN/EtLyMk= X-QQ-XMRINFO: MSVp+SPm3vtS1Vd6Y4Mggwc= X-QQ-RECHKSPAM: 0 Content-Type: text/plain; charset="utf-8" Add build options and doc for mucse. Initialize pci device access for MUCSE devices. Signed-off-by: Dong Yibo --- .../device_drivers/ethernet/index.rst | 1 + .../device_drivers/ethernet/mucse/rnpgbe.rst | 21 +++ MAINTAINERS | 8 ++ drivers/net/ethernet/Kconfig | 1 + drivers/net/ethernet/Makefile | 1 + drivers/net/ethernet/mucse/Kconfig | 34 +++++ drivers/net/ethernet/mucse/Makefile | 7 + drivers/net/ethernet/mucse/rnpgbe/Makefile | 8 ++ drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h | 24 ++++ .../net/ethernet/mucse/rnpgbe/rnpgbe_main.c | 120 ++++++++++++++++++ 10 files changed, 225 insertions(+) create mode 100644 Documentation/networking/device_drivers/ethernet/mucse/= rnpgbe.rst create mode 100644 drivers/net/ethernet/mucse/Kconfig create mode 100644 drivers/net/ethernet/mucse/Makefile create mode 100644 drivers/net/ethernet/mucse/rnpgbe/Makefile create mode 100644 drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h create mode 100644 drivers/net/ethernet/mucse/rnpgbe/rnpgbe_main.c diff --git a/Documentation/networking/device_drivers/ethernet/index.rst b/D= ocumentation/networking/device_drivers/ethernet/index.rst index 0b0a3eef6aae..41ff2152b7aa 100644 --- a/Documentation/networking/device_drivers/ethernet/index.rst +++ b/Documentation/networking/device_drivers/ethernet/index.rst @@ -47,6 +47,7 @@ Contents: mellanox/mlx5/index meta/fbnic microsoft/netvsc + mucse/rnpgbe neterion/s2io netronome/nfp pensando/ionic diff --git a/Documentation/networking/device_drivers/ethernet/mucse/rnpgbe.= rst b/Documentation/networking/device_drivers/ethernet/mucse/rnpgbe.rst new file mode 100644 index 000000000000..7562fb6b8f61 --- /dev/null +++ b/Documentation/networking/device_drivers/ethernet/mucse/rnpgbe.rst @@ -0,0 +1,21 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Linux Base Driver for MUCSE(R) Gigabit PCI Express Adapters +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +MUCSE Gigabit Linux driver. +Copyright (c) 2020 - 2025 MUCSE Co.,Ltd. + +Identifying Your Adapter +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +The driver is compatible with devices based on the following: + + * MUCSE(R) Ethernet Controller N500 series + * MUCSE(R) Ethernet Controller N210 series + +Support +=3D=3D=3D=3D=3D=3D=3D + If you have problems with the software or hardware, please contact our + customer support team via email at techsupport@mucse.com or check our + website at https://www.mucse.com/en/ diff --git a/MAINTAINERS b/MAINTAINERS index bce96dd254b8..00b73e3631b4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17276,6 +17276,14 @@ T: git git://linuxtv.org/media.git F: Documentation/devicetree/bindings/media/i2c/aptina,mt9v111.yaml F: drivers/media/i2c/mt9v111.c =20 +MUCSE ETHERNET DRIVER +M: Yibo Dong +L: netdev@vger.kernel.org +S: Maintained +W: https://www.mucse.com/en/ +F: Documentation/networking/device_drivers/ethernet/mucse/ +F: drivers/net/ethernet/mucse/ + MULTIFUNCTION DEVICES (MFD) M: Lee Jones S: Maintained diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig index f86d4557d8d7..167388f9c744 100644 --- a/drivers/net/ethernet/Kconfig +++ b/drivers/net/ethernet/Kconfig @@ -129,6 +129,7 @@ source "drivers/net/ethernet/microchip/Kconfig" source "drivers/net/ethernet/mscc/Kconfig" source "drivers/net/ethernet/microsoft/Kconfig" source "drivers/net/ethernet/moxa/Kconfig" +source "drivers/net/ethernet/mucse/Kconfig" source "drivers/net/ethernet/myricom/Kconfig" =20 config FEALNX diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile index 67182339469a..1b8c4df3f594 100644 --- a/drivers/net/ethernet/Makefile +++ b/drivers/net/ethernet/Makefile @@ -65,6 +65,7 @@ obj-$(CONFIG_NET_VENDOR_MICREL) +=3D micrel/ obj-$(CONFIG_NET_VENDOR_MICROCHIP) +=3D microchip/ obj-$(CONFIG_NET_VENDOR_MICROSEMI) +=3D mscc/ obj-$(CONFIG_NET_VENDOR_MOXART) +=3D moxa/ +obj-$(CONFIG_NET_VENDOR_MUCSE) +=3D mucse/ obj-$(CONFIG_NET_VENDOR_MYRI) +=3D myricom/ obj-$(CONFIG_FEALNX) +=3D fealnx.o obj-$(CONFIG_NET_VENDOR_NATSEMI) +=3D natsemi/ diff --git a/drivers/net/ethernet/mucse/Kconfig b/drivers/net/ethernet/mucs= e/Kconfig new file mode 100644 index 000000000000..be0fdf268484 --- /dev/null +++ b/drivers/net/ethernet/mucse/Kconfig @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Mucse network device configuration +# + +config NET_VENDOR_MUCSE + bool "Mucse devices" + default y + help + If you have a network (Ethernet) card from Mucse(R), say Y. + + Note that the answer to this question doesn't directly affect the + kernel: saying N will just cause the configurator to skip all + the questions about Mucse(R) cards. If you say Y, you will + be asked for your specific card in the following questions. + +if NET_VENDOR_MUCSE + +config MGBE + tristate "Mucse(R) 1GbE PCI Express adapters support" + depends on PCI + select PAGE_POOL + help + This driver supports Mucse(R) 1GbE PCI Express family of + adapters. + + More specific information on configuring the driver is in + . + + To compile this driver as a module, choose M here. The module + will be called rnpgbe. + +endif # NET_VENDOR_MUCSE + diff --git a/drivers/net/ethernet/mucse/Makefile b/drivers/net/ethernet/muc= se/Makefile new file mode 100644 index 000000000000..675173fa05f7 --- /dev/null +++ b/drivers/net/ethernet/mucse/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright(c) 2020 - 2025 MUCSE Corporation. +# +# Makefile for the MUCSE(R) network device drivers +# + +obj-$(CONFIG_MGBE) +=3D rnpgbe/ diff --git a/drivers/net/ethernet/mucse/rnpgbe/Makefile b/drivers/net/ether= net/mucse/rnpgbe/Makefile new file mode 100644 index 000000000000..9df536f0d04c --- /dev/null +++ b/drivers/net/ethernet/mucse/rnpgbe/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright(c) 2020 - 2025 MUCSE Corporation. +# +# Makefile for the MUCSE(R) 1GbE PCI Express ethernet driver +# + +obj-$(CONFIG_MGBE) +=3D rnpgbe.o +rnpgbe-objs :=3D rnpgbe_main.o diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h b/drivers/net/ether= net/mucse/rnpgbe/rnpgbe.h new file mode 100644 index 000000000000..64b2c093bc6e --- /dev/null +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2020 - 2025 Mucse Corporation. */ + +#ifndef _RNPGBE_H +#define _RNPGBE_H + +enum rnpgbe_boards { + board_n500, + board_n210, + board_n210L, +}; + +struct mucse { + struct net_device *netdev; + struct pci_dev *pdev; +}; + +/* Device IDs */ +#define PCI_VENDOR_ID_MUCSE 0x8848 +#define PCI_DEVICE_ID_N500_QUAD_PORT 0x8308 +#define PCI_DEVICE_ID_N500_DUAL_PORT 0x8318 +#define PCI_DEVICE_ID_N210 0x8208 +#define PCI_DEVICE_ID_N210L 0x820a +#endif /* _RNPGBE_H */ diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_main.c b/drivers/net/= ethernet/mucse/rnpgbe/rnpgbe_main.c new file mode 100644 index 000000000000..b4a9c5c66af6 --- /dev/null +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_main.c @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2020 - 2025 Mucse Corporation. */ + +#include +#include +#include + +#include "rnpgbe.h" + +static const char rnpgbe_driver_name[] =3D "rnpgbe"; + +/* rnpgbe_pci_tbl - PCI Device ID Table + * + * { PCI_DEVICE(Vendor ID, Device ID), + * driver_data (used for different hw chip) } + */ +static struct pci_device_id rnpgbe_pci_tbl[] =3D { + { PCI_DEVICE(PCI_VENDOR_ID_MUCSE, PCI_DEVICE_ID_N500_QUAD_PORT), + .driver_data =3D board_n500}, + { PCI_DEVICE(PCI_VENDOR_ID_MUCSE, PCI_DEVICE_ID_N500_DUAL_PORT), + .driver_data =3D board_n500}, + { PCI_DEVICE(PCI_VENDOR_ID_MUCSE, PCI_DEVICE_ID_N210), + .driver_data =3D board_n210}, + { PCI_DEVICE(PCI_VENDOR_ID_MUCSE, PCI_DEVICE_ID_N210L), + .driver_data =3D board_n210L}, + /* required last entry */ + {0, }, +}; + +/** + * rnpgbe_probe - Device initialization routine + * @pdev: PCI device information struct + * @id: entry in rnpgbe_pci_tbl + * + * rnpgbe_probe initializes a PF adapter identified by a pci_dev + * structure. + * + * @return: 0 on success, negative on failure + **/ +static int rnpgbe_probe(struct pci_dev *pdev, const struct pci_device_id *= id) +{ + int err; + + err =3D pci_enable_device_mem(pdev); + if (err) + return err; + + err =3D dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(56)); + if (err) { + dev_err(&pdev->dev, + "No usable DMA configuration, aborting %d\n", err); + goto err_dma; + } + + err =3D pci_request_mem_regions(pdev, rnpgbe_driver_name); + if (err) { + dev_err(&pdev->dev, + "pci_request_selected_regions failed 0x%x\n", err); + goto err_dma; + } + + pci_set_master(pdev); + pci_save_state(pdev); + + return 0; +err_dma: + pci_disable_device(pdev); + return err; +} + +/** + * rnpgbe_remove - Device removal routine + * @pdev: PCI device information struct + * + * rnpgbe_remove is called by the PCI subsystem to alert the driver + * that it should release a PCI device. This could be caused by a + * Hot-Plug event, or because the driver is going to be removed from + * memory. + **/ +static void rnpgbe_remove(struct pci_dev *pdev) +{ + pci_release_mem_regions(pdev); + pci_disable_device(pdev); +} + +/** + * rnpgbe_dev_shutdown - Device shutdown routine + * @pdev: PCI device information struct + **/ +static void rnpgbe_dev_shutdown(struct pci_dev *pdev) +{ + pci_disable_device(pdev); +} + +/** + * rnpgbe_shutdown - Device shutdown routine + * @pdev: PCI device information struct + * + * rnpgbe_shutdown is called by the PCI subsystem to alert the driver + * that os shutdown. Device should setup wakeup state here. + **/ +static void rnpgbe_shutdown(struct pci_dev *pdev) +{ + rnpgbe_dev_shutdown(pdev); +} + +static struct pci_driver rnpgbe_driver =3D { + .name =3D rnpgbe_driver_name, + .id_table =3D rnpgbe_pci_tbl, + .probe =3D rnpgbe_probe, + .remove =3D rnpgbe_remove, + .shutdown =3D rnpgbe_shutdown, +}; + +module_pci_driver(rnpgbe_driver); + +MODULE_DEVICE_TABLE(pci, rnpgbe_pci_tbl); +MODULE_AUTHOR("Mucse Corporation, "); +MODULE_DESCRIPTION("Mucse(R) 1 Gigabit PCI Express Network Driver"); +MODULE_LICENSE("GPL"); --=20 2.25.1 From nobody Sat Oct 4 00:26:51 2025 Received: from smtpbgjp3.qq.com (smtpbgjp3.qq.com [54.92.39.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADA1119D07A for ; Fri, 22 Aug 2025 02:36:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.92.39.34 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755830210; cv=none; b=rimUKZd6TJjWpmTOXYfv5KNbbU3Qwmf8RweO2kQ+2nbUePomRsgR6Xl+8LD+Qv2wg1zWugG2urltFymgw7kSzZUWn2DiEujVvAnwoBBpL9bwE4UP10mRjlxEhOQRvt0Xw0tmEAF6ZZ4+4Z9/uhtf9fWokRjcBUlpV/lom6Lwmxs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755830210; c=relaxed/simple; bh=Z7pB7pna9G5PTy8KbAbKEChXLRTnidIdLycFFB+/FOE=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=M+yKAtt2yiJ+XB6A1TGSUiWgHK13Tnti+HqqwcDfZhcgyJZTAw0ze01K8ahUSlIFK2kE1Rvv/CHeg/Rrlj9h3plws9IMOffBosc4WLe/5hHepCN223CSjYfONuVVd/wwo/FQv4Qx7DdDKIbljwpeF+sDu8TkbK/Q7mLoCvK2W2g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=mucse.com; spf=pass smtp.mailfrom=mucse.com; arc=none smtp.client-ip=54.92.39.34 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=mucse.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mucse.com X-QQ-mid: esmtpgz14t1755830112tbea72c99 X-QQ-Originating-IP: kpt1Iol6Fb1B69QZkrndSDD+UnTL/TRpbZ74en0A+eY= Received: from localhost.localdomain ( [203.174.112.180]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 22 Aug 2025 10:35:09 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 14820152475783932875 EX-QQ-RecipientCnt: 26 From: Dong Yibo To: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, horms@kernel.org, corbet@lwn.net, gur.stavi@huawei.com, maddy@linux.ibm.com, mpe@ellerman.id.au, danishanwar@ti.com, lee@trager.us, gongfan1@huawei.com, lorenzo@kernel.org, geert+renesas@glider.be, Parthiban.Veerasooran@microchip.com, lukas.bulwahn@redhat.com, alexanderduyck@fb.com, richardcochran@gmail.com, kees@kernel.org, gustavoars@kernel.org Cc: netdev@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, dong100@mucse.com Subject: [PATCH net-next v7 2/5] net: rnpgbe: Add n500/n210 chip support Date: Fri, 22 Aug 2025 10:34:50 +0800 Message-Id: <20250822023453.1910972-3-dong100@mucse.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250822023453.1910972-1-dong100@mucse.com> References: <20250822023453.1910972-1-dong100@mucse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:mucse.com:qybglogicsvrgz:qybglogicsvrgz8a-1 X-QQ-XMAILINFO: M8mbr1QaauXGPJyxYY3copZ4McFtYiP6k+gKSNBaTSIKMZyv1mNm/CUz CfALZ0emoozDMUfzITbBteFRF1V4UYhg1LWnEnINoIn/V5apAi/3Az8OWplXSfrBGGxUjod 5SMxtFm+W2m+wcKCJArEb7bmZRw4TTgcg30hGxu1qlzcPX4wv/pDB6x2/CkbiWPz5JlYYJP qrOPui7CQdkkyKSkGgJDFvLQVD2pPuz6yUWwpQd3ml6AzlJBqb73R88J7hjsrGzIy9sTt8u 0U4Yc+f/F09bsDgnp988j4kHo9Y7UsaeWqB7MmRKTIl+mg9BjIrCoQfO7o6r/K0rVtx7Mpq VjMKIF+9XxAaElbGStoQcv3Z4HvQzB8StbPrqsfQw0fVa3WvTWZJ+x8lPBVPWHJl/D0KsHq ELtdMZw7KAW0iv8MyDxTyhS9zgDGqF1Z3r9guUYgA/tfch68WN3gkYMwkDIAu+DmwhkCnR9 H/+lnPwJG+jnpw766ZAHIr94otFBUGWRbu4fTwTHU4O3BER3zpwZyAUD8SUPsUfl4eHUfij qMWDXM5FE+yRlZsnYkczcIYRUvnNDqVd/pawe3q/kAsncJsUfA+dp9qUgrh6VpIVco1UR2r 7VL9vHqq0DsCveW57Ft57hA7rGRPARrhduEUQ6kRWix+GZoy9yFANPQ+0TknImWWrxnIMiD 2epO5apGXp2zlw1sisJjWWuoQg6Xgrwzhd+H9JWsWvZ5W/+BatwJ4tB3gTFFbkKL4SyTlrQ yfdRfeNLnlxdVzZMuetyfPL4tXNg6nyTM8L5ux2jlbmL5xuQh2KsAly1hHdPDYJh41cTJje UjgJ6oFjUdAcWVze9r+u1N670oujqLtOgsWqS8zdd+XuY5RqQg+U5XZtJ1x3DHqGLrb4jqE RbpYxEca5bVs4RSx45BwpVPNJ0z99qpZgT17f5Zt663ytbD9EDgDFkhjcb3/2KDQ1v9RbBZ bqcOzr8A1aouGsm6mNkBxfWNeC7BzLBUs+sjpa1+Sr4rqo2KT/5V9DS7OQxqJYN3TyV/FyZ uqvckTvDv/m3Rm745BDggt4aWbOMxXdeC1N+8ReG5XdpGzryzWD4jkxjAli3UYlYlN/BsE0 NCiczQNnMwJgJW4KOg7M0U= X-QQ-XMRINFO: MSVp+SPm3vtS1Vd6Y4Mggwc= X-QQ-RECHKSPAM: 0 Content-Type: text/plain; charset="utf-8" Initialize n500/n210 chip bar resource map and dma, eth, mbx ... info for future use. Signed-off-by: Dong Yibo --- drivers/net/ethernet/mucse/rnpgbe/Makefile | 3 +- drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h | 34 ++++++++ .../net/ethernet/mucse/rnpgbe/rnpgbe_chip.c | 68 +++++++++++++++ drivers/net/ethernet/mucse/rnpgbe/rnpgbe_hw.h | 16 ++++ .../net/ethernet/mucse/rnpgbe/rnpgbe_main.c | 87 +++++++++++++++++++ 5 files changed, 207 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ethernet/mucse/rnpgbe/rnpgbe_chip.c create mode 100644 drivers/net/ethernet/mucse/rnpgbe/rnpgbe_hw.h diff --git a/drivers/net/ethernet/mucse/rnpgbe/Makefile b/drivers/net/ether= net/mucse/rnpgbe/Makefile index 9df536f0d04c..42c359f459d9 100644 --- a/drivers/net/ethernet/mucse/rnpgbe/Makefile +++ b/drivers/net/ethernet/mucse/rnpgbe/Makefile @@ -5,4 +5,5 @@ # =20 obj-$(CONFIG_MGBE) +=3D rnpgbe.o -rnpgbe-objs :=3D rnpgbe_main.o +rnpgbe-objs :=3D rnpgbe_main.o\ + rnpgbe_chip.o diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h b/drivers/net/ether= net/mucse/rnpgbe/rnpgbe.h index 64b2c093bc6e..9a86e67d6395 100644 --- a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h @@ -4,15 +4,49 @@ #ifndef _RNPGBE_H #define _RNPGBE_H =20 +#include + +extern const struct rnpgbe_info rnpgbe_n500_info; +extern const struct rnpgbe_info rnpgbe_n210_info; +extern const struct rnpgbe_info rnpgbe_n210L_info; + enum rnpgbe_boards { board_n500, board_n210, board_n210L, }; =20 +enum rnpgbe_hw_type { + rnpgbe_hw_n500 =3D 0, + rnpgbe_hw_n210, + rnpgbe_hw_n210L, + rnpgbe_hw_unknown +}; + +struct mucse_mbx_info { + /* fw <--> pf mbx */ + u32 fw_pf_shm_base; + u32 pf2fw_mbox_ctrl; + u32 fw_pf_mbox_mask; + u32 fw2pf_mbox_vec; +}; + +struct mucse_hw { + void __iomem *hw_addr; + struct pci_dev *pdev; + enum rnpgbe_hw_type hw_type; + struct mucse_mbx_info mbx; +}; + struct mucse { struct net_device *netdev; struct pci_dev *pdev; + struct mucse_hw hw; +}; + +struct rnpgbe_info { + enum rnpgbe_hw_type hw_type; + void (*init)(struct mucse_hw *hw); }; =20 /* Device IDs */ diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_chip.c b/drivers/net/= ethernet/mucse/rnpgbe/rnpgbe_chip.c new file mode 100644 index 000000000000..179621ea09f3 --- /dev/null +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_chip.c @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2020 - 2025 Mucse Corporation. */ + +#include "rnpgbe.h" +#include "rnpgbe_hw.h" + +/** + * rnpgbe_init_common - Setup common attribute + * @hw: hw information structure + **/ +static void rnpgbe_init_common(struct mucse_hw *hw) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + + mbx->pf2fw_mbox_ctrl =3D GBE_PF2FW_MBX_MASK_OFFSET; + mbx->fw_pf_mbox_mask =3D GBE_FWPF_MBX_MASK; +} + +/** + * rnpgbe_init_n500 - Setup n500 hw info + * @hw: hw information structure + * + * rnpgbe_init_n500 initializes all private + * structure, such as dma, eth, mac and mbx base on + * hw->hw_addr for n500 + **/ +static void rnpgbe_init_n500(struct mucse_hw *hw) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + + rnpgbe_init_common(hw); + + mbx->fw2pf_mbox_vec =3D N500_FW2PF_MBX_VEC_OFFSET; + mbx->fw_pf_shm_base =3D N500_FWPF_SHM_BASE_OFFSET; +} + +/** + * rnpgbe_init_n210 - Setup n210 hw info + * @hw: hw information structure + * + * rnpgbe_init_n210 initializes all private + * structure, such as dma, eth, mac and mbx base on + * hw->hw_addr for n210 + **/ +static void rnpgbe_init_n210(struct mucse_hw *hw) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + + rnpgbe_init_common(hw); + + mbx->fw2pf_mbox_vec =3D N210_FW2PF_MBX_VEC_OFFSET; + mbx->fw_pf_shm_base =3D N210_FWPF_SHM_BASE_OFFSET; +} + +const struct rnpgbe_info rnpgbe_n500_info =3D { + .hw_type =3D rnpgbe_hw_n500, + .init =3D &rnpgbe_init_n500, +}; + +const struct rnpgbe_info rnpgbe_n210_info =3D { + .hw_type =3D rnpgbe_hw_n210, + .init =3D &rnpgbe_init_n210, +}; + +const struct rnpgbe_info rnpgbe_n210L_info =3D { + .hw_type =3D rnpgbe_hw_n210L, + .init =3D &rnpgbe_init_n210, +}; diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_hw.h b/drivers/net/et= hernet/mucse/rnpgbe/rnpgbe_hw.h new file mode 100644 index 000000000000..746dca78f1df --- /dev/null +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_hw.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2020 - 2025 Mucse Corporation. */ + +#ifndef _RNPGBE_HW_H +#define _RNPGBE_HW_H + +/**************** MBX Resource ****************************/ +#define N500_FW2PF_MBX_VEC_OFFSET 0x28b00 +#define N500_FWPF_SHM_BASE_OFFSET 0x2d000 +#define GBE_PF2FW_MBX_MASK_OFFSET 0x5500 +#define GBE_FWPF_MBX_MASK 0x5700 +#define N210_FW2PF_MBX_VEC_OFFSET 0x29400 +#define N210_FWPF_SHM_BASE_OFFSET 0x2d900 +/**************** CHIP Resource ****************************/ +#define RNPGBE_MAX_QUEUES 8 +#endif /* _RNPGBE_HW_H */ diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_main.c b/drivers/net/= ethernet/mucse/rnpgbe/rnpgbe_main.c index b4a9c5c66af6..6992a3c0e58a 100644 --- a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_main.c +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_main.c @@ -4,10 +4,18 @@ #include #include #include +#include +#include =20 #include "rnpgbe.h" +#include "rnpgbe_hw.h" =20 static const char rnpgbe_driver_name[] =3D "rnpgbe"; +static const struct rnpgbe_info *rnpgbe_info_tbl[] =3D { + [board_n500] =3D &rnpgbe_n500_info, + [board_n210] =3D &rnpgbe_n210_info, + [board_n210L] =3D &rnpgbe_n210L_info, +}; =20 /* rnpgbe_pci_tbl - PCI Device ID Table * @@ -27,6 +35,56 @@ static struct pci_device_id rnpgbe_pci_tbl[] =3D { {0, }, }; =20 +/** + * rnpgbe_add_adapter - Add netdev for this pci_dev + * @pdev: PCI device information structure + * @info: chip info structure + * + * rnpgbe_add_adapter initializes a netdev for this pci_dev + * structure. Initializes Bar map, private structure, and a + * hardware reset occur. + * + * @return: 0 on success, negative on failure + **/ +static int rnpgbe_add_adapter(struct pci_dev *pdev, + const struct rnpgbe_info *info) +{ + struct net_device *netdev; + void __iomem *hw_addr; + struct mucse *mucse; + struct mucse_hw *hw; + int err; + + netdev =3D alloc_etherdev_mq(sizeof(struct mucse), RNPGBE_MAX_QUEUES); + if (!netdev) + return -ENOMEM; + + SET_NETDEV_DEV(netdev, &pdev->dev); + mucse =3D netdev_priv(netdev); + mucse->netdev =3D netdev; + mucse->pdev =3D pdev; + pci_set_drvdata(pdev, mucse); + + hw =3D &mucse->hw; + hw->hw_type =3D info->hw_type; + hw->pdev =3D pdev; + hw_addr =3D devm_ioremap(&pdev->dev, + pci_resource_start(pdev, 2), + pci_resource_len(pdev, 2)); + if (!hw_addr) { + err =3D -EIO; + goto err_free_net; + } + + hw->hw_addr =3D hw_addr; + info->init(hw); + return 0; + +err_free_net: + free_netdev(netdev); + return err; +} + /** * rnpgbe_probe - Device initialization routine * @pdev: PCI device information struct @@ -39,6 +97,7 @@ static struct pci_device_id rnpgbe_pci_tbl[] =3D { **/ static int rnpgbe_probe(struct pci_dev *pdev, const struct pci_device_id *= id) { + const struct rnpgbe_info *info =3D rnpgbe_info_tbl[id->driver_data]; int err; =20 err =3D pci_enable_device_mem(pdev); @@ -61,13 +120,36 @@ static int rnpgbe_probe(struct pci_dev *pdev, const st= ruct pci_device_id *id) =20 pci_set_master(pdev); pci_save_state(pdev); + err =3D rnpgbe_add_adapter(pdev, info); + if (err) + goto err_regions; =20 return 0; +err_regions: + pci_release_mem_regions(pdev); err_dma: pci_disable_device(pdev); return err; } =20 +/** + * rnpgbe_rm_adapter - Remove netdev for this mucse structure + * @pdev: PCI device information struct + * + * rnpgbe_rm_adapter remove a netdev for this mucse structure + **/ +static void rnpgbe_rm_adapter(struct pci_dev *pdev) +{ + struct mucse *mucse =3D pci_get_drvdata(pdev); + struct net_device *netdev; + + if (!mucse) + return; + netdev =3D mucse->netdev; + mucse->netdev =3D NULL; + free_netdev(netdev); +} + /** * rnpgbe_remove - Device removal routine * @pdev: PCI device information struct @@ -79,6 +161,7 @@ static int rnpgbe_probe(struct pci_dev *pdev, const stru= ct pci_device_id *id) **/ static void rnpgbe_remove(struct pci_dev *pdev) { + rnpgbe_rm_adapter(pdev); pci_release_mem_regions(pdev); pci_disable_device(pdev); } @@ -89,6 +172,10 @@ static void rnpgbe_remove(struct pci_dev *pdev) **/ static void rnpgbe_dev_shutdown(struct pci_dev *pdev) { + struct mucse *mucse =3D pci_get_drvdata(pdev); + struct net_device *netdev =3D mucse->netdev; + + netif_device_detach(netdev); pci_disable_device(pdev); } =20 --=20 2.25.1 From nobody Sat Oct 4 00:26:51 2025 Received: from smtpbgsg2.qq.com (smtpbgsg2.qq.com [54.254.200.128]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8B3F419CC11 for ; Fri, 22 Aug 2025 02:36:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.254.200.128 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755830209; cv=none; b=cIe5lvPJJgo2xBmxHgWKHKmbaG4aZnUv6AKsEavrtU0CSl7Bl7EdRlagdZ5xdcVgcKurhiiFCmDIcctAs9iJMg2G5muKP+ABBVz1dnLWPaSDDnMfMGvQbAI4De8zfyVJfTk9jQJy8AdFC01QTsc8VSsiqh5OnyeD0G9pg/fWZgs= ARC-Message-Signature: i=1; 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charset="utf-8" Initialize basic mbx function. Signed-off-by: Dong Yibo --- drivers/net/ethernet/mucse/rnpgbe/Makefile | 3 +- drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h | 17 + .../net/ethernet/mucse/rnpgbe/rnpgbe_chip.c | 3 + .../net/ethernet/mucse/rnpgbe/rnpgbe_mbx.c | 395 ++++++++++++++++++ .../net/ethernet/mucse/rnpgbe/rnpgbe_mbx.h | 25 ++ 5 files changed, 442 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx.c create mode 100644 drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx.h diff --git a/drivers/net/ethernet/mucse/rnpgbe/Makefile b/drivers/net/ether= net/mucse/rnpgbe/Makefile index 42c359f459d9..5fc878ada4b1 100644 --- a/drivers/net/ethernet/mucse/rnpgbe/Makefile +++ b/drivers/net/ethernet/mucse/rnpgbe/Makefile @@ -6,4 +6,5 @@ =20 obj-$(CONFIG_MGBE) +=3D rnpgbe.o rnpgbe-objs :=3D rnpgbe_main.o\ - rnpgbe_chip.o + rnpgbe_chip.o\ + rnpgbe_mbx.o diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h b/drivers/net/ether= net/mucse/rnpgbe/rnpgbe.h index 9a86e67d6395..67e28a4667e7 100644 --- a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h @@ -5,6 +5,7 @@ #define _RNPGBE_H =20 #include +#include =20 extern const struct rnpgbe_info rnpgbe_n500_info; extern const struct rnpgbe_info rnpgbe_n210_info; @@ -23,7 +24,23 @@ enum rnpgbe_hw_type { rnpgbe_hw_unknown }; =20 +struct mucse_mbx_stats { + u32 msgs_tx; + u32 msgs_rx; + u32 acks; + u32 reqs; +}; + struct mucse_mbx_info { + struct mucse_mbx_stats stats; + u32 timeout; + u32 usec_delay; + u16 size; + u16 fw_req; + u16 fw_ack; + /* lock for only one use mbx */ + struct mutex lock; + bool irq_enabled; /* fw <--> pf mbx */ u32 fw_pf_shm_base; u32 pf2fw_mbox_ctrl; diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_chip.c b/drivers/net/= ethernet/mucse/rnpgbe/rnpgbe_chip.c index 179621ea09f3..f38daef752a3 100644 --- a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_chip.c +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_chip.c @@ -1,8 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 /* Copyright(c) 2020 - 2025 Mucse Corporation. */ =20 +#include + #include "rnpgbe.h" #include "rnpgbe_hw.h" +#include "rnpgbe_mbx.h" =20 /** * rnpgbe_init_common - Setup common attribute diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx.c b/drivers/net/e= thernet/mucse/rnpgbe/rnpgbe_mbx.c new file mode 100644 index 000000000000..e02563b994c2 --- /dev/null +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx.c @@ -0,0 +1,395 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2022 - 2025 Mucse Corporation. */ + +#include +#include +#include +#include + +#include "rnpgbe.h" +#include "rnpgbe_mbx.h" +#include "rnpgbe_hw.h" + +/** + * mbx_data_rd32 - Reads reg with base mbx->fw_pf_shm_base + * @mbx: pointer to the MBX structure + * @reg: register offset + * + * @return: register value + **/ +static u32 mbx_data_rd32(struct mucse_mbx_info *mbx, u32 reg) +{ + struct mucse_hw *hw =3D container_of(mbx, struct mucse_hw, mbx); + + return readl(hw->hw_addr + mbx->fw_pf_shm_base + reg); +} + +/** + * mbx_data_wr32 - Writes value to reg with base mbx->fw_pf_shm_base + * @mbx: pointer to the MBX structure + * @reg: register offset + * @value: value to be written + * + **/ +static void mbx_data_wr32(struct mucse_mbx_info *mbx, u32 reg, u32 value) +{ + struct mucse_hw *hw =3D container_of(mbx, struct mucse_hw, mbx); + + writel(value, hw->hw_addr + mbx->fw_pf_shm_base + reg); +} + +/** + * mbx_ctrl_rd32 - Reads reg with base mbx->fw2pf_mbox_vec + * @mbx: pointer to the MBX structure + * @reg: register offset + * + * @return: register value + **/ +static u32 mbx_ctrl_rd32(struct mucse_mbx_info *mbx, u32 reg) +{ + struct mucse_hw *hw =3D container_of(mbx, struct mucse_hw, mbx); + + return readl(hw->hw_addr + mbx->fw2pf_mbox_vec + reg); +} + +/** + * mbx_ctrl_wr32 - Writes value to reg with base mbx->fw2pf_mbox_vec + * @mbx: pointer to the MBX structure + * @reg: register offset + * @value: value to be written + * + **/ +static void mbx_ctrl_wr32(struct mucse_mbx_info *mbx, u32 reg, u32 value) +{ + struct mucse_hw *hw =3D container_of(mbx, struct mucse_hw, mbx); + + writel(value, hw->hw_addr + mbx->fw2pf_mbox_vec + reg); +} + +/** + * mucse_mbx_get_fwreq - Read fw req from reg + * @mbx: pointer to the mbx structure + * + * @return: the req value + **/ +static u16 mucse_mbx_get_fwreq(struct mucse_mbx_info *mbx) +{ + return mbx_data_rd32(mbx, MBX_FW2PF_COUNTER) & GENMASK_U32(15, 0); +} + +/** + * mucse_mbx_get_fwack - Read fw ack from reg + * @mbx: pointer to the MBX structure + * + * @return: the ack value + **/ +static u16 mucse_mbx_get_fwack(struct mucse_mbx_info *mbx) +{ + return (mbx_data_rd32(mbx, MBX_FW2PF_COUNTER) >> 16); +} + +/** + * mucse_mbx_inc_pf_req - Increase req + * @hw: pointer to the HW structure + * + * mucse_mbx_inc_pf_req read pf_req from hw, then write + * new value back after increase + **/ +static void mucse_mbx_inc_pf_req(struct mucse_hw *hw) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + u16 req; + u32 v; + + v =3D mbx_data_rd32(mbx, MBX_PF2FW_COUNTER); + req =3D (v & GENMASK_U32(15, 0)); + req++; + v &=3D GENMASK_U32(31, 16); + v |=3D req; + mbx_data_wr32(mbx, MBX_PF2FW_COUNTER, v); + hw->mbx.stats.msgs_tx++; +} + +/** + * mucse_mbx_inc_pf_ack - Increase ack + * @hw: pointer to the HW structure + * + * mucse_mbx_inc_pf_ack read pf_ack from hw, then write + * new value back after increase + **/ +static void mucse_mbx_inc_pf_ack(struct mucse_hw *hw) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + u16 ack; + u32 v; + + v =3D mbx_data_rd32(mbx, MBX_PF2FW_COUNTER); + ack =3D (v >> 16) & GENMASK_U32(15, 0); + ack++; + v &=3D GENMASK_U32(15, 0); + v |=3D (ack << 16); + mbx_data_wr32(mbx, MBX_PF2FW_COUNTER, v); + hw->mbx.stats.msgs_rx++; +} + +/** + * mucse_check_for_msg_pf - Check to see if the fw has sent mail + * @hw: pointer to the HW structure + * + * @return: 0 if the fw has set the Status bit or else + * -EIO + **/ +static int mucse_check_for_msg_pf(struct mucse_hw *hw) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + u16 hw_req_count =3D 0; + + hw_req_count =3D mucse_mbx_get_fwreq(mbx); + /* chip's register is reset to 0 when rc send reset + * mbx command. This causes 'hw_req_count !=3D hw->mbx.fw_req' + * be TRUE before fw really reply. Driver must wait fw reset + * done reply before using chip, we must check no-zero. + **/ + if (hw_req_count !=3D 0 && hw_req_count !=3D hw->mbx.fw_req) { + hw->mbx.stats.reqs++; + return 0; + } + + return -EIO; +} + +/** + * mucse_poll_for_msg - Wait for message notification + * @hw: pointer to the HW structure + * + * @return: 0 on success, negative on failure + **/ +static int mucse_poll_for_msg(struct mucse_hw *hw) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + int countdown =3D mbx->timeout; + int val; + + return read_poll_timeout(mucse_check_for_msg_pf, + val, val =3D=3D 0, mbx->usec_delay, + countdown * mbx->usec_delay, + false, hw); +} + +/** + * mucse_check_for_ack_pf - Check to see if the VF has ACKed + * @hw: pointer to the HW structure + * + * @return: 0 if the fw has set the Status bit or else + * -EIO + **/ +static int mucse_check_for_ack_pf(struct mucse_hw *hw) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + u16 hw_fw_ack; + + hw_fw_ack =3D mucse_mbx_get_fwack(mbx); + /* chip's register is reset to 0 when rc send reset + * mbx command. This causes 'hw_fw_ack !=3D hw->mbx.fw_ack' + * be TRUE before fw really reply. Driver must wait fw reset + * done reply before using chip, we must check no-zero. + **/ + if (hw_fw_ack !=3D 0 && hw_fw_ack !=3D hw->mbx.fw_ack) { + hw->mbx.stats.acks++; + return 0; + } + + return -EIO; +} + +/** + * mucse_poll_for_ack - Wait for message acknowledgment + * @hw: pointer to the HW structure + * + * @return: 0 if it successfully received a message acknowledgment + **/ +static int mucse_poll_for_ack(struct mucse_hw *hw) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + int countdown =3D mbx->timeout; + int val; + + return read_poll_timeout(mucse_check_for_ack_pf, + val, val =3D=3D 0, mbx->usec_delay, + countdown * mbx->usec_delay, + false, hw); +} + +/** + * mucse_obtain_mbx_lock_pf - Obtain mailbox lock + * @hw: pointer to the HW structure + * + * This function maybe used in an irq handler. + * + * @return: 0 if we obtained the mailbox lock + **/ +static int mucse_obtain_mbx_lock_pf(struct mucse_hw *hw) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + int try_cnt =3D 5000; + u32 reg; + + reg =3D PF2FW_MBOX_CTRL(mbx); + while (try_cnt-- > 0) { + mbx_ctrl_wr32(mbx, reg, MBOX_PF_HOLD); + /* force write back before check */ + wmb(); + if (mbx_ctrl_rd32(mbx, reg) & MBOX_PF_HOLD) + return 0; + udelay(100); + } + return -EIO; +} + +/** + * mucse_read_mbx_pf - Read a message from the mailbox + * @hw: pointer to the HW structure + * @msg: the message buffer + * @size: length of buffer + * + * This function copies a message from the mailbox buffer to the caller's + * memory buffer. The presumption is that the caller knows that there was + * a message due to a fw request so no polling for message is needed. + * + * @return: 0 on success, negative on failure + **/ +static int mucse_read_mbx_pf(struct mucse_hw *hw, u32 *msg, u16 size) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + int size_inwords =3D size / 4; + u32 ctrl_reg; + int ret; + int i; + + ctrl_reg =3D PF2FW_MBOX_CTRL(mbx); + + ret =3D mucse_obtain_mbx_lock_pf(hw); + if (ret) + return ret; + for (i =3D 0; i < size_inwords; i++) + msg[i] =3D mbx_data_rd32(mbx, MBX_FW_PF_SHM_DATA + 4 * i); + /* Hw need write data_reg at last */ + mbx_data_wr32(mbx, MBX_FW_PF_SHM_DATA, 0); + hw->mbx.fw_req =3D mucse_mbx_get_fwreq(mbx); + mucse_mbx_inc_pf_ack(hw); + mbx_ctrl_wr32(mbx, ctrl_reg, 0); + + return 0; +} + +/** + * mucse_read_posted_mbx - Wait for message notification and receive messa= ge + * @hw: pointer to the HW structure + * @msg: the message buffer + * @size: length of buffer + * + * @return: 0 if it successfully received a message notification and + * copied it into the receive buffer. + **/ +int mucse_read_posted_mbx(struct mucse_hw *hw, u32 *msg, u16 size) +{ + int ret; + + ret =3D mucse_poll_for_msg(hw); + if (ret) + return ret; + + return mucse_read_mbx_pf(hw, msg, size); +} + +/** + * mucse_mbx_reset - Reset mbx info, sync info from regs + * @hw: pointer to the HW structure + * + * This function reset all mbx variables to default. + **/ +static void mucse_mbx_reset(struct mucse_hw *hw) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + u32 v; + + v =3D mbx_data_rd32(mbx, MBX_FW2PF_COUNTER); + hw->mbx.fw_req =3D v & GENMASK_U32(15, 0); + hw->mbx.fw_ack =3D (v >> 16) & GENMASK_U32(15, 0); + mbx_ctrl_wr32(mbx, PF2FW_MBOX_CTRL(mbx), 0); + mbx_ctrl_wr32(mbx, FW_PF_MBOX_MASK(mbx), GENMASK_U32(31, 16)); +} + +/** + * mucse_init_mbx_params_pf - Set initial values for pf mailbox + * @hw: pointer to the HW structure + * + * Initializes the hw->mbx struct to correct values for pf mailbox + */ +void mucse_init_mbx_params_pf(struct mucse_hw *hw) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + + mbx->usec_delay =3D 100; + mbx->timeout =3D (4 * USEC_PER_SEC) / mbx->usec_delay; + mbx->stats.msgs_tx =3D 0; + mbx->stats.msgs_rx =3D 0; + mbx->stats.reqs =3D 0; + mbx->stats.acks =3D 0; + mbx->size =3D MUCSE_MAILBOX_BYTES; + mutex_init(&mbx->lock); + mucse_mbx_reset(hw); +} + +/** + * mucse_write_mbx_pf - Place a message in the mailbox + * @hw: pointer to the HW structure + * @msg: the message buffer + * @size: length of buffer + * + * This function maybe used in an irq handler. + * + * @return: 0 if it successfully copied message into the buffer + **/ +int mucse_write_mbx_pf(struct mucse_hw *hw, u32 *msg, u16 size) +{ + struct mucse_mbx_info *mbx =3D &hw->mbx; + int size_inwords =3D size / 4; + u32 ctrl_reg; + int ret; + int i; + + ctrl_reg =3D PF2FW_MBOX_CTRL(mbx); + ret =3D mucse_obtain_mbx_lock_pf(hw); + if (ret) + return ret; + + for (i =3D 0; i < size_inwords; i++) + mbx_data_wr32(mbx, MBX_FW_PF_SHM_DATA + i * 4, msg[i]); + + /* flush msg and acks as we are overwriting the message buffer */ + hw->mbx.fw_ack =3D mucse_mbx_get_fwack(mbx); + mucse_mbx_inc_pf_req(hw); + mbx_ctrl_wr32(mbx, ctrl_reg, MBOX_CTRL_REQ); + + return 0; +} + +/** + * mucse_write_posted_mbx - Write a message to the mailbox, wait for ack + * @hw: pointer to the HW structure + * @msg: the message buffer + * @size: length of buffer + * + * @return: 0 if it successfully copied message into the buffer and + * received an ack to that message within delay * timeout period + **/ +int mucse_write_posted_mbx(struct mucse_hw *hw, u32 *msg, u16 size) +{ + int ret; + + ret =3D mucse_write_mbx_pf(hw, msg, size); + if (ret) + return ret; + return mucse_poll_for_ack(hw); +} diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx.h b/drivers/net/e= thernet/mucse/rnpgbe/rnpgbe_mbx.h new file mode 100644 index 000000000000..110c1ee025ba --- /dev/null +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2020 - 2025 Mucse Corporation. */ + +#ifndef _RNPGBE_MBX_H +#define _RNPGBE_MBX_H + +#include "rnpgbe.h" + +#define MUCSE_MAILBOX_BYTES 56 +#define MBX_FW2PF_COUNTER 0 +#define MBX_PF2FW_COUNTER 4 +#define MBX_FW_PF_SHM_DATA 8 +#define FW2PF_MBOX_VEC 0 +#define PF2FW_MBOX_CTRL(mbx) ((mbx)->pf2fw_mbox_ctrl) +#define FW_PF_MBOX_MASK(mbx) ((mbx)->fw_pf_mbox_mask) +#define MBOX_CTRL_REQ BIT(0) +#define MBOX_PF_HOLD BIT(3) +#define MBOX_IRQ_EN 0 +#define MBOX_IRQ_DISABLE 1 + +int mucse_write_mbx_pf(struct mucse_hw *hw, u32 *msg, u16 size); +int mucse_write_posted_mbx(struct mucse_hw *hw, u32 *msg, u16 size); +void mucse_init_mbx_params_pf(struct mucse_hw *hw); +int mucse_read_posted_mbx(struct mucse_hw *hw, u32 *msg, u16 size); +#endif /* _RNPGBE_MBX_H */ --=20 2.25.1 From nobody Sat Oct 4 00:26:51 2025 Received: from smtpbgsg2.qq.com (smtpbgsg2.qq.com [54.254.200.128]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF4A1140E5F for ; Fri, 22 Aug 2025 02:36:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.254.200.128 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755830194; cv=none; b=TdG595u0/6pmG9JG39rfq4jxQ4rs5jTmfV0g+/1bMYgsf/FS/DhdVC99pfNZt8CLZ9H7dPg+2jfaxqk9ExzDZC+TH1tjv4wVZzfBR71NO1eQuaz4cnfaChvK0cpsG/fAD4i1B1IyA8tznY8X7Xrbl/T8Ct/G/gnuAeZ9m72iiyI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755830194; 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charset="utf-8" Initialize basic mbx_fw ops, such as get_capability, reset phy and so on. Signed-off-by: Dong Yibo --- drivers/net/ethernet/mucse/rnpgbe/Makefile | 3 +- drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h | 1 + .../net/ethernet/mucse/rnpgbe/rnpgbe_mbx_fw.c | 333 ++++++++++++++++++ .../net/ethernet/mucse/rnpgbe/rnpgbe_mbx_fw.h | 152 ++++++++ 4 files changed, 488 insertions(+), 1 deletion(-) create mode 100644 drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx_fw.c create mode 100644 drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx_fw.h diff --git a/drivers/net/ethernet/mucse/rnpgbe/Makefile b/drivers/net/ether= net/mucse/rnpgbe/Makefile index 5fc878ada4b1..de8bcb7772ab 100644 --- a/drivers/net/ethernet/mucse/rnpgbe/Makefile +++ b/drivers/net/ethernet/mucse/rnpgbe/Makefile @@ -7,4 +7,5 @@ obj-$(CONFIG_MGBE) +=3D rnpgbe.o rnpgbe-objs :=3D rnpgbe_main.o\ rnpgbe_chip.o\ - rnpgbe_mbx.o + rnpgbe_mbx.o\ + rnpgbe_mbx_fw.o diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h b/drivers/net/ether= net/mucse/rnpgbe/rnpgbe.h index 67e28a4667e7..a32419a34d75 100644 --- a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h @@ -52,6 +52,7 @@ struct mucse_hw { void __iomem *hw_addr; struct pci_dev *pdev; enum rnpgbe_hw_type hw_type; + u8 pfvfnum; struct mucse_mbx_info mbx; }; =20 diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx_fw.c b/drivers/ne= t/ethernet/mucse/rnpgbe/rnpgbe_mbx_fw.c new file mode 100644 index 000000000000..84570763cf79 --- /dev/null +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx_fw.c @@ -0,0 +1,333 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Copyright(c) 2020 - 2025 Mucse Corporation. */ + +#include +#include + +#include "rnpgbe.h" +#include "rnpgbe_hw.h" +#include "rnpgbe_mbx.h" +#include "rnpgbe_mbx_fw.h" + +/** + * mucse_fw_send_cmd_wait - Send cmd req and wait for response + * @hw: pointer to the HW structure + * @req: pointer to the cmd req structure + * @reply: pointer to the fw reply structure + * + * mucse_fw_send_cmd_wait sends req to pf-fw mailbox and wait + * reply from fw. + * + * @return: 0 on success, negative on failure + **/ +static int mucse_fw_send_cmd_wait(struct mucse_hw *hw, + struct mbx_fw_cmd_req *req, + struct mbx_fw_cmd_reply *reply) +{ + int len =3D le16_to_cpu(req->datalen); + int retry_cnt =3D 3; + int err; + + err =3D mutex_lock_interruptible(&hw->mbx.lock); + if (err) + return err; + err =3D mucse_write_posted_mbx(hw, (u32 *)req, len); + if (err) + goto out; + do { + err =3D mucse_read_posted_mbx(hw, (u32 *)reply, + sizeof(*reply)); + if (err) + goto out; + /* mucse_write_posted_mbx return 0 means fw has + * received request, wait for the expect opcode + * reply with 'retry_cnt' times. + */ + } while (--retry_cnt >=3D 0 && reply->opcode !=3D req->opcode); +out: + mutex_unlock(&hw->mbx.lock); + if (!err && retry_cnt < 0) + return -ETIMEDOUT; + if (!err && reply->error_code) + return -EIO; + return err; +} + +/** + * build_phy_abilities_req - build req with get_phy_ability opcode + * @req: pointer to the cmd req structure + **/ +static void build_phy_abilities_req(struct mbx_fw_cmd_req *req) +{ + req->flags =3D 0; + req->opcode =3D cpu_to_le16(GET_PHY_ABILITY); + req->datalen =3D cpu_to_le16(MBX_REQ_HDR_LEN); + req->reply_lo =3D 0; + req->reply_hi =3D 0; +} + +/** + * mucse_fw_get_capability - Get hw abilities from fw + * @hw: pointer to the HW structure + * @abil: pointer to the hw_abilities structure + * + * mucse_fw_get_capability tries to get hw abilities from + * hw. + * + * @return: 0 on success, negative on failure + **/ +static int mucse_fw_get_capability(struct mucse_hw *hw, + struct hw_abilities *abil) +{ + struct mbx_fw_cmd_reply reply =3D {}; + struct mbx_fw_cmd_req req =3D {}; + int err; + + build_phy_abilities_req(&req); + err =3D mucse_fw_send_cmd_wait(hw, &req, &reply); + if (!err) + memcpy(abil, &reply.hw_abilities, sizeof(*abil)); + return err; +} + +/** + * mucse_mbx_get_capability - Get hw abilities from fw + * @hw: pointer to the HW structure + * + * mucse_mbx_get_capability tries to get capabities from + * hw. Many retrys will do if it is failed. + * + * @return: 0 on success, negative on failure + **/ +int mucse_mbx_get_capability(struct mucse_hw *hw) +{ + struct hw_abilities ability =3D {}; + int try_cnt =3D 3; + int err =3D -EIO; + + while (try_cnt--) { + err =3D mucse_fw_get_capability(hw, &ability); + if (err) + continue; + hw->pfvfnum =3D le16_to_cpu(ability.pfnum) & GENMASK_U16(7, 0); + return 0; + } + return err; +} + +/** + * mbx_cookie_zalloc - Alloc a cookie structure + * @priv_len: private length for this cookie + * + * @return: cookie structure on success + **/ +static struct mbx_req_cookie *mbx_cookie_zalloc(int priv_len) +{ + struct mbx_req_cookie *cookie; + + cookie =3D kzalloc(struct_size(cookie, priv, priv_len), GFP_KERNEL); + if (cookie) { + cookie->timeout_jiffies =3D 30 * HZ; + cookie->magic =3D COOKIE_MAGIC; + cookie->priv_len =3D priv_len; + } + return cookie; +} + +/** + * mucse_mbx_fw_post_req - Posts a mbx req to firmware and wait reply + * @hw: pointer to the HW structure + * @req: pointer to the cmd req structure + * @cookie: pointer to the req cookie + * + * mucse_mbx_fw_post_req posts a mbx req to firmware and wait for the + * reply. cookie->wait will be set in irq handler. + * + * @return: 0 on success, negative on failure + **/ +static int mucse_mbx_fw_post_req(struct mucse_hw *hw, + struct mbx_fw_cmd_req *req, + struct mbx_req_cookie *cookie) +{ + int len =3D le16_to_cpu(req->datalen); + int err; + + cookie->errcode =3D 0; + cookie->done =3D 0; + init_waitqueue_head(&cookie->wait); + err =3D mutex_lock_interruptible(&hw->mbx.lock); + if (err) + return err; + err =3D mucse_write_mbx_pf(hw, (u32 *)req, len); + if (err) + goto out; + /* if write succeeds, we must wait for firmware response or + * timeout to avoid using the already freed cookie->wait + */ + err =3D wait_event_timeout(cookie->wait, + cookie->done =3D=3D 1, + cookie->timeout_jiffies); + + if (!err) + err =3D -ETIMEDOUT; + else + err =3D 0; + if (!err && cookie->errcode) + err =3D cookie->errcode; +out: + mutex_unlock(&hw->mbx.lock); + return err; +} + +/** + * build_ifinsmod - build req with insmod opcode + * @req: pointer to the cmd req structure + * @status: true for insmod, false for rmmod + **/ +static void build_ifinsmod(struct mbx_fw_cmd_req *req, + int status) +{ + req->flags =3D 0; + req->opcode =3D cpu_to_le16(DRIVER_INSMOD); + req->datalen =3D cpu_to_le16(sizeof(req->ifinsmod) + + MBX_REQ_HDR_LEN); + req->cookie =3D NULL; + req->reply_lo =3D 0; + req->reply_hi =3D 0; +#define FIXED_VERSION 0xFFFFFFFF + req->ifinsmod.version =3D cpu_to_le32(FIXED_VERSION); + req->ifinsmod.status =3D cpu_to_le32(status); +} + +/** + * mucse_mbx_ifinsmod - Echo driver insmod status to hw + * @hw: pointer to the HW structure + * @status: true for insmod, false for rmmod + * + * @return: 0 on success, negative on failure + **/ +int mucse_mbx_ifinsmod(struct mucse_hw *hw, int status) +{ + struct mbx_fw_cmd_req req =3D {}; + int len; + int err; + + build_ifinsmod(&req, status); + len =3D le16_to_cpu(req.datalen); + err =3D mutex_lock_interruptible(&hw->mbx.lock); + if (err) + return err; + + if (status) { + err =3D mucse_write_posted_mbx(hw, (u32 *)&req, + len); + } else { + err =3D mucse_write_mbx_pf(hw, (u32 *)&req, + len); + } + + mutex_unlock(&hw->mbx.lock); + return err; +} + +/** + * build_reset_phy_req - build req with reset_phy opcode + * @req: pointer to the cmd req structure + * @cookie: pointer of cookie for this cmd + **/ +static void build_reset_phy_req(struct mbx_fw_cmd_req *req, + void *cookie) +{ + req->flags =3D 0; + req->opcode =3D cpu_to_le16(RESET_PHY); + req->datalen =3D cpu_to_le16(MBX_REQ_HDR_LEN); + req->reply_lo =3D 0; + req->reply_hi =3D 0; + req->cookie =3D cookie; +} + +/** + * mucse_mbx_fw_reset_phy - Posts a mbx req to reset hw + * @hw: pointer to the HW structure + * + * mucse_mbx_fw_reset_phy posts a mbx req to firmware to reset hw. + * It uses mucse_fw_send_cmd_wait if no irq, and mucse_mbx_fw_post_req + * if other irq is registered. + * + * @return: 0 on success, negative on failure + **/ +int mucse_mbx_fw_reset_phy(struct mucse_hw *hw) +{ + struct mbx_fw_cmd_reply reply =3D {}; + struct mbx_fw_cmd_req req =3D {}; + int ret; + + if (hw->mbx.irq_enabled) { + struct mbx_req_cookie *cookie =3D mbx_cookie_zalloc(0); + + if (!cookie) + return -ENOMEM; + + build_reset_phy_req(&req, cookie); + ret =3D mucse_mbx_fw_post_req(hw, &req, cookie); + kfree(cookie); + return ret; + } + + build_reset_phy_req(&req, &req); + return mucse_fw_send_cmd_wait(hw, &req, &reply); +} + +/** + * build_get_macaddress_req - build req with get_mac opcode + * @req: pointer to the cmd req structure + * @port_mask: port valid for this cmd + * @pfvfnum: pfvfnum for this cmd + * @cookie: pointer of cookie for this cmd + **/ +static void build_get_macaddress_req(struct mbx_fw_cmd_req *req, + int port_mask, int pfvfnum, + void *cookie) +{ + req->flags =3D 0; + req->opcode =3D cpu_to_le16(GET_MAC_ADDRES); + req->datalen =3D cpu_to_le16(sizeof(req->get_mac_addr) + + MBX_REQ_HDR_LEN); + req->cookie =3D cookie; + req->reply_lo =3D 0; + req->reply_hi =3D 0; + req->get_mac_addr.port_mask =3D cpu_to_le32(port_mask); + req->get_mac_addr.pfvf_num =3D cpu_to_le32(pfvfnum); +} + +/** + * mucse_fw_get_macaddr - Posts a mbx req to request macaddr + * @hw: pointer to the HW structure + * @pfvfnum: index of pf/vf num + * @mac_addr: pointer to store mac_addr + * @port: port index + * + * mucse_fw_get_macaddr posts a mbx req to firmware to get mac_addr. + * It uses mucse_fw_send_cmd_wait if no irq, and mucse_mbx_fw_post_req + * if other irq is registered. + * + * @return: 0 on success, negative on failure + **/ +int mucse_fw_get_macaddr(struct mucse_hw *hw, int pfvfnum, + u8 *mac_addr, + int port) +{ + struct mbx_fw_cmd_reply reply =3D {}; + struct mbx_fw_cmd_req req =3D {}; + int err; + + build_get_macaddress_req(&req, BIT(port), pfvfnum, &req); + err =3D mucse_fw_send_cmd_wait(hw, &req, &reply); + if (err) + return err; + if (le32_to_cpu(reply.mac_addr.ports) & BIT(port)) + memcpy(mac_addr, reply.mac_addr.addrs[port].mac, ETH_ALEN); + else + return -ENODATA; + return 0; +} diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx_fw.h b/drivers/ne= t/ethernet/mucse/rnpgbe/rnpgbe_mbx_fw.h new file mode 100644 index 000000000000..b73238d0e848 --- /dev/null +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_mbx_fw.h @@ -0,0 +1,152 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright(c) 2020 - 2025 Mucse Corporation. */ + +#ifndef _RNPGBE_MBX_FW_H +#define _RNPGBE_MBX_FW_H + +#include +#include +#include + +#include "rnpgbe.h" + +#define MBX_REQ_HDR_LEN 24 + +struct mbx_fw_cmd_reply; +typedef void (*cookie_cb)(struct mbx_fw_cmd_reply *reply, void *priv); + +struct mbx_req_cookie { + int magic; +#define COOKIE_MAGIC 0xCE + cookie_cb cb; + int timeout_jiffies; + int errcode; + wait_queue_head_t wait; + int done; + int priv_len; + char priv[] __counted_by(priv_len); +}; + +enum MUCSE_FW_CMD { + GET_PHY_ABILITY =3D 0x0601, + GET_MAC_ADDRES =3D 0x0602, + RESET_PHY =3D 0x0603, + DRIVER_INSMOD =3D 0x0803, +}; + +struct hw_abilities { + u8 link_stat; + u8 port_mask; + __le32 speed; + __le16 phy_type; + __le16 nic_mode; + __le16 pfnum; + __le32 fw_version; + __le32 axi_mhz; + union { + u8 port_id[4]; + __le32 port_ids; + }; + __le32 bd_uid; + __le32 phy_id; + __le32 wol_status; + union { + __le32 ext_ability; + struct { + u32 valid : 1; + u32 wol_en : 1; + u32 pci_preset_runtime_en : 1; + u32 smbus_en : 1; + u32 ncsi_en : 1; + u32 rpu_en : 1; + u32 v2 : 1; + u32 pxe_en : 1; + u32 mctp_en : 1; + u32 yt8614 : 1; + u32 pci_ext_reset : 1; + u32 rpu_availble : 1; + u32 fw_lldp_ability : 1; + u32 lldp_enabled : 1; + u32 only_1g : 1; + u32 force_down_en: 1; + } e_host; + }; +} __packed; + +/* FW stores extended ability information in 'ext_ability' as a 32-bit + * little-endian value. To make these flags easily accessible in the + * kernel (via named 'bitfields' instead of raw bitmask operations), + * we use the union's 'e_host' struct, which provides named bits + * (e.g., 'wol_en', 'smbus_en') + */ +static inline void ability_update_host_endian(struct hw_abilities *abi) +{ + u32 host_val =3D le32_to_cpu(abi->ext_ability); + + abi->e_host =3D *(typeof(abi->e_host) *)&host_val; +} + +#define FLAGS_DD BIT(0) +#define FLAGS_ERR BIT(2) + +struct mbx_fw_cmd_req { + __le16 flags; + __le16 opcode; + __le16 datalen; + __le16 ret_value; + union { + struct { + __le32 cookie_lo; + __le32 cookie_hi; + }; + + void *cookie; + }; + __le32 reply_lo; + __le32 reply_hi; + union { + u8 data[32]; + struct { + __le32 version; + __le32 status; + } ifinsmod; + struct { + __le32 port_mask; + __le32 pfvf_num; + } get_mac_addr; + }; +} __packed; + +struct mbx_fw_cmd_reply { + __le16 flags; + __le16 opcode; + __le16 error_code; + __le16 datalen; + union { + struct { + __le32 cookie_lo; + __le32 cookie_hi; + }; + void *cookie; + }; + union { + u8 data[40]; + struct mac_addr { + __le32 ports; + struct _addr { + /* for macaddr:01:02:03:04:05:06 + * mac-hi=3D0x01020304 mac-lo=3D0x05060000 + */ + u8 mac[8]; + } addrs[4]; + } mac_addr; + struct hw_abilities hw_abilities; + }; +} __packed; + +int mucse_mbx_get_capability(struct mucse_hw *hw); +int mucse_mbx_ifinsmod(struct mucse_hw *hw, int status); +int mucse_mbx_fw_reset_phy(struct mucse_hw *hw); +int mucse_fw_get_macaddr(struct mucse_hw *hw, int pfvfnum, + u8 *mac_addr, int port); +#endif /* _RNPGBE_MBX_FW_H */ --=20 2.25.1 From nobody Sat Oct 4 00:26:51 2025 Received: from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E8E719C558 for ; Fri, 22 Aug 2025 02:36:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=54.206.16.166 ARC-Seal: i=1; a=rsa-sha256; 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Fri, 22 Aug 2025 10:35:21 +0800 (CST) X-QQ-SSF: 0000000000000000000000000000000 X-QQ-GoodBg: 0 X-BIZMAIL-ID: 4022437291746701167 EX-QQ-RecipientCnt: 26 From: Dong Yibo To: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, horms@kernel.org, corbet@lwn.net, gur.stavi@huawei.com, maddy@linux.ibm.com, mpe@ellerman.id.au, danishanwar@ti.com, lee@trager.us, gongfan1@huawei.com, lorenzo@kernel.org, geert+renesas@glider.be, Parthiban.Veerasooran@microchip.com, lukas.bulwahn@redhat.com, alexanderduyck@fb.com, richardcochran@gmail.com, kees@kernel.org, gustavoars@kernel.org Cc: netdev@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-hardening@vger.kernel.org, dong100@mucse.com Subject: [PATCH net-next v7 5/5] net: rnpgbe: Add register_netdev Date: Fri, 22 Aug 2025 10:34:53 +0800 Message-Id: <20250822023453.1910972-6-dong100@mucse.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250822023453.1910972-1-dong100@mucse.com> References: <20250822023453.1910972-1-dong100@mucse.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-QQ-SENDSIZE: 520 Feedback-ID: esmtpgz:mucse.com:qybglogicsvrgz:qybglogicsvrgz8a-1 X-QQ-XMAILINFO: MtRooIZ2Z9ixY7xGSZv4bzUYjqpRuVUukQcjE1JJ1W2z8Ifkb/aNreFu b4KE/RyoHyhYQ2ixYDTTHPIULTQLIBL45Us27o68WclD2jlXx/d5nOumYgtXJA3vieGoCDW E/U+nG6e8fnvTq8hl6Sb3F5TE7dUtIY6ZgPxqhTUGXJPW9hGamsqBlUlV0mIOOOyv09zMmR 8/TVJNmFW1DLE8nwONnQe58VNQR0W0OoljLeEZEZP0CcuXiUAb4C28eQ+mfemtEqvo1symw kpL87dWZ+7EW/A943Tp2SCL7NrGbAFt//Z19ZVNOhTv/7tqz7EjKxqur9MDf4KoKY8y95Eb yC5agk+Wtr1Ic1QH5p0o/zog918Dt0lHeMAXo0jSOu3svZW88UO94tRREftOaFNXEUlUECV nfxebfYP2ojK6GgUMLRBV9Xrq63uZ3LnenlokoUndkovrxlH9Ubsc1VKrWOehY0Ro2KOmlx s2k/hLHgSE/KxApN6g2XQI6Hov/lBBJhTG56J8Z98Cq58Ll5YqTmJlZzHjdxv76GGgj0XQ/ yjvlfiWQ/k+6JQaHaOsRGZKS56hDDmMyGZnWedEmoJx4MRG5JrsLMN6wNGXsoAX7xghB+n6 1USUACfCwwFJQwacAure7B3aTchV04cdNjLJEPVmEnZ/fAO1NdNtvOhTgjGnnnBbComP77Q zPdGbYj5QK7mDqScYfYUt1OK0bsd9mnkTgmEX6AaUVZAreJWLwMcUPX0+cRJoBAEcAVxX1Y RTsoevlb3DnGwJIiTf2Umqo7Zs7x/KQOKtmsOOmzCnOUChxvbQiFdHAhH0+V5YrVfZhQLZH WanGuTirRVZbKs2sT5YQhkMTwAa4tSpQVX4q/9eP2fH4eyX7LH4rq2XLLXHlMzFLjchOH4f aet1n1LXZFW1SczvXDfj6j5CVbp+cDXPNmS9QALJhq10eFLYIGFtfczW5h0LaUz17bYtRDj icYEvNSQh7QvoLY5gcmNwhHB51xHXu9zXgYud8Rf4+N+nsMGqvX30jbfbGIzcRaLulMe/JV j3h2scU1C9J4IKKFyhJPLyG3KoUcJcT+JJRHpwYLNloyfRJbe99SVNlcmdzrQWZtcNTFoYE Iwy3wEumqK4 X-QQ-XMRINFO: NI4Ajvh11aEj8Xl/2s1/T8w= X-QQ-RECHKSPAM: 0 Content-Type: text/plain; charset="utf-8" Initialize get mac from hw, register the netdev. Signed-off-by: Dong Yibo --- drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h | 23 ++++++ .../net/ethernet/mucse/rnpgbe/rnpgbe_chip.c | 82 +++++++++++++++++++ drivers/net/ethernet/mucse/rnpgbe/rnpgbe_hw.h | 2 + .../net/ethernet/mucse/rnpgbe/rnpgbe_main.c | 75 +++++++++++++++++ 4 files changed, 182 insertions(+) diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h b/drivers/net/ether= net/mucse/rnpgbe/rnpgbe.h index a32419a34d75..44b581b8d45c 100644 --- a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe.h @@ -6,6 +6,7 @@ =20 #include #include +#include =20 extern const struct rnpgbe_info rnpgbe_n500_info; extern const struct rnpgbe_info rnpgbe_n210_info; @@ -24,6 +25,10 @@ enum rnpgbe_hw_type { rnpgbe_hw_unknown }; =20 +struct mucse_dma_info { + void __iomem *dma_base_addr; +}; + struct mucse_mbx_stats { u32 msgs_tx; u32 msgs_rx; @@ -48,12 +53,27 @@ struct mucse_mbx_info { u32 fw2pf_mbox_vec; }; =20 +struct mucse_hw; + +struct mucse_hw_operations { + int (*reset_hw)(struct mucse_hw *hw); + void (*driver_status)(struct mucse_hw *hw, bool enable, int mode); +}; + +enum { + mucse_driver_insmod, +}; + struct mucse_hw { void __iomem *hw_addr; struct pci_dev *pdev; enum rnpgbe_hw_type hw_type; u8 pfvfnum; + const struct mucse_hw_operations *ops; + struct mucse_dma_info dma; struct mucse_mbx_info mbx; + int port; + u8 perm_addr[ETH_ALEN]; }; =20 struct mucse { @@ -73,4 +93,7 @@ struct rnpgbe_info { #define PCI_DEVICE_ID_N500_DUAL_PORT 0x8318 #define PCI_DEVICE_ID_N210 0x8208 #define PCI_DEVICE_ID_N210L 0x820a + +#define rnpgbe_dma_wr32(dma, reg, val) \ + writel((val), (dma)->dma_base_addr + (reg)) #endif /* _RNPGBE_H */ diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_chip.c b/drivers/net/= ethernet/mucse/rnpgbe/rnpgbe_chip.c index f38daef752a3..40c29411fe09 100644 --- a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_chip.c +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_chip.c @@ -1,11 +1,87 @@ // SPDX-License-Identifier: GPL-2.0 /* Copyright(c) 2020 - 2025 Mucse Corporation. */ =20 +#include #include +#include =20 #include "rnpgbe.h" #include "rnpgbe_hw.h" #include "rnpgbe_mbx.h" +#include "rnpgbe_mbx_fw.h" + +/** + * rnpgbe_get_permanent_mac - Get permanent mac + * @hw: hw information structure + * @mac_addr: pointer to store mac + * + * rnpgbe_get_permanent_mac tries to get mac from hw. + * It use eth_random_addr if failed. + * + * @return: 0 on success, negative on failure + **/ +static int rnpgbe_get_permanent_mac(struct mucse_hw *hw, + u8 *mac_addr) +{ + struct device *dev =3D &hw->pdev->dev; + int err; + + err =3D mucse_fw_get_macaddr(hw, hw->pfvfnum, mac_addr, hw->port); + if (err) { + dev_err(dev, "Failed to get MAC from FW %d\n", err); + return err; + } + + if (!is_valid_ether_addr(mac_addr)) { + dev_err(dev, "Failed to get valid MAC from FW\n"); + return -EINVAL; + } + + return 0; +} + +/** + * rnpgbe_reset_hw_ops - Do a hardware reset + * @hw: hw information structure + * + * rnpgbe_reset_hw_ops calls fw to do a hardware + * reset, and cleans some regs to default. + * + * @return: 0 on success, negative on failure + **/ +static int rnpgbe_reset_hw_ops(struct mucse_hw *hw) +{ + struct mucse_dma_info *dma =3D &hw->dma; + int err; + + rnpgbe_dma_wr32(dma, RNPGBE_DMA_AXI_EN, 0); + err =3D mucse_mbx_fw_reset_phy(hw); + if (err) + return err; + return rnpgbe_get_permanent_mac(hw, hw->perm_addr); +} + +/** + * rnpgbe_driver_status_hw_ops - Echo driver status to hw + * @hw: hw information structure + * @enable: true or false status + * @mode: status mode + **/ +static void rnpgbe_driver_status_hw_ops(struct mucse_hw *hw, + bool enable, + int mode) +{ + switch (mode) { + case mucse_driver_insmod: + mucse_mbx_ifinsmod(hw, enable); + break; + } +} + +static const struct mucse_hw_operations rnpgbe_hw_ops =3D { + .reset_hw =3D &rnpgbe_reset_hw_ops, + .driver_status =3D &rnpgbe_driver_status_hw_ops, +}; =20 /** * rnpgbe_init_common - Setup common attribute @@ -13,10 +89,16 @@ **/ static void rnpgbe_init_common(struct mucse_hw *hw) { + struct mucse_dma_info *dma =3D &hw->dma; struct mucse_mbx_info *mbx =3D &hw->mbx; =20 + dma->dma_base_addr =3D hw->hw_addr; + mbx->pf2fw_mbox_ctrl =3D GBE_PF2FW_MBX_MASK_OFFSET; mbx->fw_pf_mbox_mask =3D GBE_FWPF_MBX_MASK; + + hw->ops =3D &rnpgbe_hw_ops; + hw->port =3D 0; } =20 /** diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_hw.h b/drivers/net/et= hernet/mucse/rnpgbe/rnpgbe_hw.h index 746dca78f1df..0ab2c328c9e9 100644 --- a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_hw.h +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_hw.h @@ -11,6 +11,8 @@ #define GBE_FWPF_MBX_MASK 0x5700 #define N210_FW2PF_MBX_VEC_OFFSET 0x29400 #define N210_FWPF_SHM_BASE_OFFSET 0x2d900 +/**************** DMA Registers ****************************/ +#define RNPGBE_DMA_AXI_EN 0x0010 /**************** CHIP Resource ****************************/ #define RNPGBE_MAX_QUEUES 8 #endif /* _RNPGBE_HW_H */ diff --git a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_main.c b/drivers/net/= ethernet/mucse/rnpgbe/rnpgbe_main.c index 6992a3c0e58a..947d0ca2101d 100644 --- a/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_main.c +++ b/drivers/net/ethernet/mucse/rnpgbe/rnpgbe_main.c @@ -9,6 +9,8 @@ =20 #include "rnpgbe.h" #include "rnpgbe_hw.h" +#include "rnpgbe_mbx.h" +#include "rnpgbe_mbx_fw.h" =20 static const char rnpgbe_driver_name[] =3D "rnpgbe"; static const struct rnpgbe_info *rnpgbe_info_tbl[] =3D { @@ -35,6 +37,55 @@ static struct pci_device_id rnpgbe_pci_tbl[] =3D { {0, }, }; =20 +/** + * rnpgbe_open - Called when a network interface is made active + * @netdev: network interface device structure + * + * The open entry point is called when a network interface is made + * active by the system (IFF_UP). + * + * @return: 0 on success, negative value on failure + **/ +static int rnpgbe_open(struct net_device *netdev) +{ + return 0; +} + +/** + * rnpgbe_close - Disables a network interface + * @netdev: network interface device structure + * + * The close entry point is called when an interface is de-activated + * by the OS. + * + * @return: 0, this is not allowed to fail + **/ +static int rnpgbe_close(struct net_device *netdev) +{ + return 0; +} + +/** + * rnpgbe_xmit_frame - Send a skb to driver + * @skb: skb structure to be sent + * @netdev: network interface device structure + * + * @return: NETDEV_TX_OK or NETDEV_TX_BUSY + **/ +static netdev_tx_t rnpgbe_xmit_frame(struct sk_buff *skb, + struct net_device *netdev) +{ + dev_kfree_skb_any(skb); + netdev->stats.tx_dropped++; + return NETDEV_TX_OK; +} + +static const struct net_device_ops rnpgbe_netdev_ops =3D { + .ndo_open =3D rnpgbe_open, + .ndo_stop =3D rnpgbe_close, + .ndo_start_xmit =3D rnpgbe_xmit_frame, +}; + /** * rnpgbe_add_adapter - Add netdev for this pci_dev * @pdev: PCI device information structure @@ -78,6 +129,27 @@ static int rnpgbe_add_adapter(struct pci_dev *pdev, =20 hw->hw_addr =3D hw_addr; info->init(hw); + mucse_init_mbx_params_pf(hw); + /* echo fw driver insmod to control hw */ + hw->ops->driver_status(hw, true, mucse_driver_insmod); + err =3D mucse_mbx_get_capability(hw); + if (err) { + dev_err(&pdev->dev, + "mucse_mbx_get_capability failed! %d\n", + err); + goto err_free_net; + } + netdev->netdev_ops =3D &rnpgbe_netdev_ops; + netdev->watchdog_timeo =3D 5 * HZ; + err =3D hw->ops->reset_hw(hw); + if (err) { + dev_err(&pdev->dev, "Hw reset failed %d\n", err); + goto err_free_net; + } + eth_hw_addr_set(netdev, hw->perm_addr); + err =3D register_netdev(netdev); + if (err) + goto err_free_net; return 0; =20 err_free_net: @@ -141,12 +213,15 @@ static int rnpgbe_probe(struct pci_dev *pdev, const s= truct pci_device_id *id) static void rnpgbe_rm_adapter(struct pci_dev *pdev) { struct mucse *mucse =3D pci_get_drvdata(pdev); + struct mucse_hw *hw =3D &mucse->hw; struct net_device *netdev; =20 if (!mucse) return; netdev =3D mucse->netdev; + unregister_netdev(netdev); mucse->netdev =3D NULL; + hw->ops->driver_status(hw, false, mucse_driver_insmod); free_netdev(netdev); } =20 --=20 2.25.1