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Thu, 21 Aug 2025 20:06:58 -0700 (PDT) From: Guodong Xu Date: Fri, 22 Aug 2025 11:06:31 +0800 Subject: [PATCH v5 5/8] dmaengine: mmp_pdma: Add SpacemiT K1 PDMA support with 64-bit addressing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250822-working_dma_0701_v2-v5-5-f5c0eda734cc@riscstar.com> References: <20250822-working_dma_0701_v2-v5-0-f5c0eda734cc@riscstar.com> In-Reply-To: <20250822-working_dma_0701_v2-v5-0-f5c0eda734cc@riscstar.com> To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , duje@dujemihanovic.xyz Cc: Alex Elder , Vivian Wang , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Guodong Xu , Troy Mitchell X-Mailer: b4 0.14.2 Add support for SpacemiT K1 PDMA controller which features 64-bit addressing capabilities. The SpacemiT K1 PDMA extends the descriptor format with additional 32-bit words for high address bits, enabling access to memory beyond 4GB boundaries. The new spacemit_k1_pdma_ops provides necessary 64-bit address handling functions and k1 specific controller configurations. Key changes: - Add ARCH_SPACEMIT dependency to Kconfig - Define new high 32-bit address registers (DDADRH, DSADRH, DTADRH) - Add DCSR_LPAEEN bit for Long Physical Address Extension Enable - Implement 64-bit operations for SpacemiT K1 PDMA Signed-off-by: Guodong Xu --- v5: No change. v4: No change. v3: No change. v2: New patch. - Implement 64-bit addrssing support to mmp_pdma - Add support for SpacemiT K1 PDMA - Extend the MMP_PDMA entry in Kconfig to depend on ARCH_SPACEMIT --- drivers/dma/Kconfig | 2 +- drivers/dma/mmp_pdma.c | 81 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 82 insertions(+), 1 deletion(-) diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 05c7c7d9e5a4e52a8ad7ada8c8b9b1a6f9d875f6..b8a74b1798ba1d44b2655399042= 8c065de6fc535 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -450,7 +450,7 @@ config MILBEAUT_XDMAC =20 config MMP_PDMA tristate "MMP PDMA support" - depends on ARCH_MMP || ARCH_PXA || COMPILE_TEST + depends on ARCH_MMP || ARCH_PXA || ARCH_SPACEMIT || COMPILE_TEST select DMA_ENGINE help Support the MMP PDMA engine for PXA and MMP platform. diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c index 38d1a4cdfd0e92e53c77b61caa1133559ef40dbd..d07229a748868b8115892c63c54= c16130d88e326 100644 --- a/drivers/dma/mmp_pdma.c +++ b/drivers/dma/mmp_pdma.c @@ -28,6 +28,9 @@ #define DDADR(n) (0x0200 + ((n) << 4)) #define DSADR(n) (0x0204 + ((n) << 4)) #define DTADR(n) (0x0208 + ((n) << 4)) +#define DDADRH(n) (0x0300 + ((n) << 4)) +#define DSADRH(n) (0x0304 + ((n) << 4)) +#define DTADRH(n) (0x0308 + ((n) << 4)) #define DCMD 0x020c =20 #define DCSR_RUN BIT(31) /* Run Bit (read / write) */ @@ -44,6 +47,7 @@ #define DCSR_EORSTOPEN BIT(26) /* STOP on an EOR */ #define DCSR_SETCMPST BIT(25) /* Set Descriptor Compare Status */ #define DCSR_CLRCMPST BIT(24) /* Clear Descriptor Compare Status */ +#define DCSR_LPAEEN BIT(21) /* Long Physical Address Extension Enable */ #define DCSR_CMPST BIT(10) /* The Descriptor Compare Status */ #define DCSR_EORINTR BIT(9) /* The end of Receive */ =20 @@ -76,6 +80,16 @@ struct mmp_pdma_desc_hw { u32 dsadr; /* DSADR value for the current transfer */ u32 dtadr; /* DTADR value for the current transfer */ u32 dcmd; /* DCMD value for the current transfer */ + /* + * The following 32-bit words are only used in the 64-bit, ie. + * LPAE (Long Physical Address Extension) mode. + * They are used to specify the high 32 bits of the descriptor's + * addresses. + */ + u32 ddadrh; /* High 32-bit of DDADR */ + u32 dsadrh; /* High 32-bit of DSADR */ + u32 dtadrh; /* High 32-bit of DTADR */ + u32 rsvd; /* reserved */ } __aligned(32); =20 struct mmp_pdma_desc_sw { @@ -222,6 +236,57 @@ static u64 get_desc_dst_addr_32(const struct mmp_pdma_= desc_hw *desc) return desc->dtadr; } =20 +/* For 64-bit PDMA */ +static void write_next_addr_64(struct mmp_pdma_phy *phy, dma_addr_t addr) +{ + writel(lower_32_bits(addr), phy->base + DDADR(phy->idx)); + writel(upper_32_bits(addr), phy->base + DDADRH(phy->idx)); +} + +static u64 read_src_addr_64(struct mmp_pdma_phy *phy) +{ + u32 low =3D readl(phy->base + DSADR(phy->idx)); + u32 high =3D readl(phy->base + DSADRH(phy->idx)); + + return ((u64)high << 32) | low; +} + +static u64 read_dst_addr_64(struct mmp_pdma_phy *phy) +{ + u32 low =3D readl(phy->base + DTADR(phy->idx)); + u32 high =3D readl(phy->base + DTADRH(phy->idx)); + + return ((u64)high << 32) | low; +} + +static void set_desc_next_addr_64(struct mmp_pdma_desc_hw *desc, dma_addr_= t addr) +{ + desc->ddadr =3D lower_32_bits(addr); + desc->ddadrh =3D upper_32_bits(addr); +} + +static void set_desc_src_addr_64(struct mmp_pdma_desc_hw *desc, dma_addr_t= addr) +{ + desc->dsadr =3D lower_32_bits(addr); + desc->dsadrh =3D upper_32_bits(addr); +} + +static void set_desc_dst_addr_64(struct mmp_pdma_desc_hw *desc, dma_addr_t= addr) +{ + desc->dtadr =3D lower_32_bits(addr); + desc->dtadrh =3D upper_32_bits(addr); +} + +static u64 get_desc_src_addr_64(const struct mmp_pdma_desc_hw *desc) +{ + return ((u64)desc->dsadrh << 32) | desc->dsadr; +} + +static u64 get_desc_dst_addr_64(const struct mmp_pdma_desc_hw *desc) +{ + return ((u64)desc->dtadrh << 32) | desc->dtadr; +} + static int mmp_pdma_config_write(struct dma_chan *dchan, struct dma_slave_config *cfg, enum dma_transfer_direction direction); @@ -1110,10 +1175,26 @@ static const struct mmp_pdma_ops marvell_pdma_v1_op= s =3D { .dma_mask =3D 0, /* let OF/platform set DMA mask */ }; =20 +static const struct mmp_pdma_ops spacemit_k1_pdma_ops =3D { + .write_next_addr =3D write_next_addr_64, + .read_src_addr =3D read_src_addr_64, + .read_dst_addr =3D read_dst_addr_64, + .set_desc_next_addr =3D set_desc_next_addr_64, + .set_desc_src_addr =3D set_desc_src_addr_64, + .set_desc_dst_addr =3D set_desc_dst_addr_64, + .get_desc_src_addr =3D get_desc_src_addr_64, + .get_desc_dst_addr =3D get_desc_dst_addr_64, + .run_bits =3D (DCSR_RUN | DCSR_LPAEEN), + .dma_mask =3D DMA_BIT_MASK(64), /* force 64-bit DMA addr capability */ +}; + static const struct of_device_id mmp_pdma_dt_ids[] =3D { { .compatible =3D "marvell,pdma-1.0", .data =3D &marvell_pdma_v1_ops + }, { + .compatible =3D "spacemit,k1-pdma", + .data =3D &spacemit_k1_pdma_ops }, { /* sentinel */ } --=20 2.43.0