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Thu, 21 Aug 2025 20:06:40 -0700 (PDT) From: Guodong Xu Date: Fri, 22 Aug 2025 11:06:27 +0800 Subject: [PATCH v5 1/8] dt-bindings: dma: Add SpacemiT K1 PDMA controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250822-working_dma_0701_v2-v5-1-f5c0eda734cc@riscstar.com> References: <20250822-working_dma_0701_v2-v5-0-f5c0eda734cc@riscstar.com> In-Reply-To: <20250822-working_dma_0701_v2-v5-0-f5c0eda734cc@riscstar.com> To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , duje@dujemihanovic.xyz Cc: Alex Elder , Vivian Wang , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Guodong Xu , Troy Mitchell X-Mailer: b4 0.14.2 Add device tree binding documentation for the SpacemiT K1 PDMA controller. Signed-off-by: Guodong Xu Reviewed-by: Rob Herring (Arm) Tested-by: Troy Mitchell --- v5: No change. v4: Add Rob's reviewed-by. v3: New patch. --- .../devicetree/bindings/dma/spacemit,k1-pdma.yaml | 68 ++++++++++++++++++= ++++ 1 file changed, 68 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml b/= Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml new file mode 100644 index 0000000000000000000000000000000000000000..ec06235baf5ca3ecffe7dba9bb4= 25b242985660e --- /dev/null +++ b/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/spacemit,k1-pdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 PDMA Controller + +maintainers: + - Guodong Xu + +allOf: + - $ref: dma-controller.yaml# + +properties: + compatible: + const: spacemit,k1-pdma + + reg: + maxItems: 1 + + interrupts: + description: Shared interrupt for all DMA channels + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + dma-channels: + maximum: 16 + + '#dma-cells': + const: 1 + description: + The DMA request number for the peripheral device. + +required: + - compatible + - reg + - interrupts + - clocks + - resets + - dma-channels + - '#dma-cells' + +unevaluatedProperties: false + +examples: + - | + #include + + soc { + #address-cells =3D <2>; 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Thu, 21 Aug 2025 20:06:45 -0700 (PDT) Received: from [127.0.1.1] ([222.71.237.178]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b47769afc1bsm2756777a12.19.2025.08.21.20.06.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Aug 2025 20:06:44 -0700 (PDT) From: Guodong Xu Date: Fri, 22 Aug 2025 11:06:28 +0800 Subject: [PATCH v5 2/8] dmaengine: mmp_pdma: Add clock support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250822-working_dma_0701_v2-v5-2-f5c0eda734cc@riscstar.com> References: <20250822-working_dma_0701_v2-v5-0-f5c0eda734cc@riscstar.com> In-Reply-To: <20250822-working_dma_0701_v2-v5-0-f5c0eda734cc@riscstar.com> To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , duje@dujemihanovic.xyz Cc: Alex Elder , Vivian Wang , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Guodong Xu , Troy Mitchell X-Mailer: b4 0.14.2 Add support for retrieving and enabling an optional clock during mmp_pdma_probe(). It is optional because in Marvell devices such as "marvell,pdma-1.0" the clocks property is not a required property. But in SpacemiT K1 PDMA, "spacemit,k1-pdma" as the dt binding schema file stated, clocks is required. Signed-off-by: Guodong Xu Tested-by: Troy Mitchell --- v5: No change. v4: Update the commit message, no source code change. v3: No change. v2: No change. --- drivers/dma/mmp_pdma.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c index a95d31103d3063a1d11177a1a37b89ac2fd213e9..4a6dbf55823722d26cc69379d22= aaa88fbe19313 100644 --- a/drivers/dma/mmp_pdma.c +++ b/drivers/dma/mmp_pdma.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include =20 @@ -1019,6 +1020,7 @@ static int mmp_pdma_probe(struct platform_device *op) { struct mmp_pdma_device *pdev; struct mmp_dma_platdata *pdata =3D dev_get_platdata(&op->dev); + struct clk *clk; int i, ret, irq =3D 0; int dma_channels =3D 0, irq_num =3D 0; const enum dma_slave_buswidth widths =3D @@ -1037,6 +1039,10 @@ static int mmp_pdma_probe(struct platform_device *op) if (IS_ERR(pdev->base)) return PTR_ERR(pdev->base); =20 + clk =3D devm_clk_get_optional_enabled(pdev->dev, NULL); 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Thu, 21 Aug 2025 20:06:49 -0700 (PDT) Received: from [127.0.1.1] ([222.71.237.178]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b47769afc1bsm2756777a12.19.2025.08.21.20.06.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Aug 2025 20:06:49 -0700 (PDT) From: Guodong Xu Date: Fri, 22 Aug 2025 11:06:29 +0800 Subject: [PATCH v5 3/8] dmaengine: mmp_pdma: Add reset controller support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250822-working_dma_0701_v2-v5-3-f5c0eda734cc@riscstar.com> References: <20250822-working_dma_0701_v2-v5-0-f5c0eda734cc@riscstar.com> In-Reply-To: <20250822-working_dma_0701_v2-v5-0-f5c0eda734cc@riscstar.com> To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , duje@dujemihanovic.xyz Cc: Alex Elder , Vivian Wang , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Guodong Xu , Troy Mitchell X-Mailer: b4 0.14.2 Add support to acquire and deassert an optional hardware reset controller during mmp_pdma_probe(). It is optional because in Marvell devices such as "marvell,pdma-1.0" the resets property is not a required property. But in SpacemiT K1 PDMA, "spacemit,k1-pdma" as the dt binding schema file stated, resets is required. Signed-off-by: Guodong Xu Tested-by: Troy Mitchell --- v5: No change. v4: Updated the commit message, no source code change. v3: No change. v2: No change. --- drivers/dma/mmp_pdma.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c index 4a6dbf55823722d26cc69379d22aaa88fbe19313..fe627efeaff07436647f86ab5ec= 5333144a3c92d 100644 --- a/drivers/dma/mmp_pdma.c +++ b/drivers/dma/mmp_pdma.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include =20 @@ -1021,6 +1022,7 @@ static int mmp_pdma_probe(struct platform_device *op) struct mmp_pdma_device *pdev; struct mmp_dma_platdata *pdata =3D dev_get_platdata(&op->dev); struct clk *clk; + struct reset_control *rst; int i, ret, irq =3D 0; int dma_channels =3D 0, irq_num =3D 0; const enum dma_slave_buswidth widths =3D @@ -1043,6 +1045,11 @@ static int mmp_pdma_probe(struct platform_device *op) if (IS_ERR(clk)) return PTR_ERR(clk); =20 + rst =3D devm_reset_control_get_optional_exclusive_deasserted(pdev->dev, + NULL); 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Thu, 21 Aug 2025 20:06:54 -0700 (PDT) Received: from [127.0.1.1] ([222.71.237.178]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b47769afc1bsm2756777a12.19.2025.08.21.20.06.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Aug 2025 20:06:53 -0700 (PDT) From: Guodong Xu Date: Fri, 22 Aug 2025 11:06:30 +0800 Subject: [PATCH v5 4/8] dmaengine: mmp_pdma: Add operations structure for controller abstraction Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250822-working_dma_0701_v2-v5-4-f5c0eda734cc@riscstar.com> References: <20250822-working_dma_0701_v2-v5-0-f5c0eda734cc@riscstar.com> In-Reply-To: <20250822-working_dma_0701_v2-v5-0-f5c0eda734cc@riscstar.com> To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , duje@dujemihanovic.xyz Cc: Alex Elder , Vivian Wang , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Guodong Xu , Troy Mitchell , Dan Carpenter X-Mailer: b4 0.14.2 Introduce mmp_pdma_ops structure to abstract 32-bit addressing operations and enable support for different controller variants. This prepares for adding 64-bit addressing support. The ops structure includes: - Hardware register operations (read/write DDADR, DSADR, DTADR) - Descriptor memory operations (manipulate descriptor structs) - Controller configuration (run bits, DMA mask) Convert existing 32-bit operations to use the new abstraction layer while maintaining backward compatibility. Cc: Dan Carpenter Signed-off-by: Guodong Xu Tested-by: Troy Mitchell --- v5: Fixed dereference warnings reported by kernel test bot and Dan Carpenter. v4: No change. v3: No change. v2: New patch, introduce mmp_pdma_ops for 32-bit addressing operations. --- drivers/dma/mmp_pdma.c | 195 ++++++++++++++++++++++++++++++++++++++++-----= ---- 1 file changed, 160 insertions(+), 35 deletions(-) diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c index fe627efeaff07436647f86ab5ec5333144a3c92d..38d1a4cdfd0e92e53c77b61caa1= 133559ef40dbd 100644 --- a/drivers/dma/mmp_pdma.c +++ b/drivers/dma/mmp_pdma.c @@ -25,7 +25,7 @@ #define DCSR 0x0000 #define DALGN 0x00a0 #define DINT 0x00f0 -#define DDADR 0x0200 +#define DDADR(n) (0x0200 + ((n) << 4)) #define DSADR(n) (0x0204 + ((n) << 4)) #define DTADR(n) (0x0208 + ((n) << 4)) #define DCMD 0x020c @@ -120,12 +120,55 @@ struct mmp_pdma_phy { struct mmp_pdma_chan *vchan; }; =20 +/** + * struct mmp_pdma_ops - Operations for the MMP PDMA controller + * + * Hardware Register Operations (read/write hardware registers): + * @write_next_addr: Function to program address of next descriptor into + * DDADR/DDADRH + * @read_src_addr: Function to read the source address from DSADR/DSADRH + * @read_dst_addr: Function to read the destination address from DTADR/DTA= DRH + * + * Descriptor Memory Operations (manipulate descriptor structs in memory): + * @set_desc_next_addr: Function to set next descriptor address in descrip= tor + * @set_desc_src_addr: Function to set the source address in descriptor + * @set_desc_dst_addr: Function to set the destination address in descript= or + * @get_desc_src_addr: Function to get the source address from descriptor + * @get_desc_dst_addr: Function to get the destination address from descri= ptor + * + * Controller Configuration: + * @run_bits: Control bits in DCSR register for channel start/stop + * @dma_mask: DMA addressing capability of controller. 0 to use OF/platf= orm + * settings, or explicit mask like DMA_BIT_MASK(32/64) + */ +struct mmp_pdma_ops { + /* Hardware Register Operations */ + void (*write_next_addr)(struct mmp_pdma_phy *phy, dma_addr_t addr); + u64 (*read_src_addr)(struct mmp_pdma_phy *phy); + u64 (*read_dst_addr)(struct mmp_pdma_phy *phy); + + /* Descriptor Memory Operations */ + void (*set_desc_next_addr)(struct mmp_pdma_desc_hw *desc, + dma_addr_t addr); + void (*set_desc_src_addr)(struct mmp_pdma_desc_hw *desc, + dma_addr_t addr); + void (*set_desc_dst_addr)(struct mmp_pdma_desc_hw *desc, + dma_addr_t addr); + u64 (*get_desc_src_addr)(const struct mmp_pdma_desc_hw *desc); + u64 (*get_desc_dst_addr)(const struct mmp_pdma_desc_hw *desc); + + /* Controller Configuration */ + u32 run_bits; + u64 dma_mask; +}; + struct mmp_pdma_device { int dma_channels; void __iomem *base; struct device *dev; struct dma_device device; struct mmp_pdma_phy *phy; + const struct mmp_pdma_ops *ops; spinlock_t phy_lock; /* protect alloc/free phy channels */ }; =20 @@ -138,24 +181,61 @@ struct mmp_pdma_device { #define to_mmp_pdma_dev(dmadev) \ container_of(dmadev, struct mmp_pdma_device, device) =20 -static int mmp_pdma_config_write(struct dma_chan *dchan, - struct dma_slave_config *cfg, - enum dma_transfer_direction direction); +/* For 32-bit PDMA */ +static void write_next_addr_32(struct mmp_pdma_phy *phy, dma_addr_t addr) +{ + writel(addr, phy->base + DDADR(phy->idx)); +} + +static u64 read_src_addr_32(struct mmp_pdma_phy *phy) +{ + return readl(phy->base + DSADR(phy->idx)); +} + +static u64 read_dst_addr_32(struct mmp_pdma_phy *phy) +{ + return readl(phy->base + DTADR(phy->idx)); +} + +static void set_desc_next_addr_32(struct mmp_pdma_desc_hw *desc, dma_addr_= t addr) +{ + desc->ddadr =3D addr; +} + +static void set_desc_src_addr_32(struct mmp_pdma_desc_hw *desc, dma_addr_t= addr) +{ + desc->dsadr =3D addr; +} =20 -static void set_desc(struct mmp_pdma_phy *phy, dma_addr_t addr) +static void set_desc_dst_addr_32(struct mmp_pdma_desc_hw *desc, dma_addr_t= addr) { - u32 reg =3D (phy->idx << 4) + DDADR; + desc->dtadr =3D addr; +} =20 - writel(addr, phy->base + reg); +static u64 get_desc_src_addr_32(const struct mmp_pdma_desc_hw *desc) +{ + return desc->dsadr; } =20 +static u64 get_desc_dst_addr_32(const struct mmp_pdma_desc_hw *desc) +{ + return desc->dtadr; +} + +static int mmp_pdma_config_write(struct dma_chan *dchan, + struct dma_slave_config *cfg, + enum dma_transfer_direction direction); + static void enable_chan(struct mmp_pdma_phy *phy) { u32 reg, dalgn; + struct mmp_pdma_device *pdev; =20 if (!phy->vchan) return; =20 + pdev =3D to_mmp_pdma_dev(phy->vchan->chan.device); + reg =3D DRCMR(phy->vchan->drcmr); writel(DRCMR_MAPVLD | phy->idx, phy->base + reg); =20 @@ -167,18 +247,29 @@ static void enable_chan(struct mmp_pdma_phy *phy) writel(dalgn, phy->base + DALGN); =20 reg =3D (phy->idx << 2) + DCSR; - writel(readl(phy->base + reg) | DCSR_RUN, phy->base + reg); + writel(readl(phy->base + reg) | pdev->ops->run_bits, + phy->base + reg); } =20 static void disable_chan(struct mmp_pdma_phy *phy) { - u32 reg; + u32 reg, dcsr; =20 if (!phy) return; =20 reg =3D (phy->idx << 2) + DCSR; - writel(readl(phy->base + reg) & ~DCSR_RUN, phy->base + reg); + dcsr =3D readl(phy->base + reg); + + if (phy->vchan) { + struct mmp_pdma_device *pdev; + + pdev =3D to_mmp_pdma_dev(phy->vchan->chan.device); + writel(dcsr & ~pdev->ops->run_bits, phy->base + reg); + } else { + /* If no vchan, just clear the RUN bit */ + writel(dcsr & ~DCSR_RUN, phy->base + reg); + } } =20 static int clear_chan_irq(struct mmp_pdma_phy *phy) @@ -297,6 +388,7 @@ static void mmp_pdma_free_phy(struct mmp_pdma_chan *pch= an) static void start_pending_queue(struct mmp_pdma_chan *chan) { struct mmp_pdma_desc_sw *desc; + struct mmp_pdma_device *pdev =3D to_mmp_pdma_dev(chan->chan.device); =20 /* still in running, irq will start the pending list */ if (!chan->idle) { @@ -331,7 +423,7 @@ static void start_pending_queue(struct mmp_pdma_chan *c= han) * Program the descriptor's address into the DMA controller, * then start the DMA transaction */ - set_desc(chan->phy, desc->async_tx.phys); + pdev->ops->write_next_addr(chan->phy, desc->async_tx.phys); enable_chan(chan->phy); chan->idle =3D false; } @@ -447,15 +539,14 @@ mmp_pdma_prep_memcpy(struct dma_chan *dchan, size_t len, unsigned long flags) { struct mmp_pdma_chan *chan; + struct mmp_pdma_device *pdev; struct mmp_pdma_desc_sw *first =3D NULL, *prev =3D NULL, *new; size_t copy =3D 0; =20 - if (!dchan) - return NULL; - - if (!len) + if (!dchan || !len) return NULL; =20 + pdev =3D to_mmp_pdma_dev(dchan->device); chan =3D to_mmp_pdma_chan(dchan); chan->byte_align =3D false; =20 @@ -478,13 +569,14 @@ mmp_pdma_prep_memcpy(struct dma_chan *dchan, chan->byte_align =3D true; =20 new->desc.dcmd =3D chan->dcmd | (DCMD_LENGTH & copy); - new->desc.dsadr =3D dma_src; - new->desc.dtadr =3D dma_dst; + pdev->ops->set_desc_src_addr(&new->desc, dma_src); + pdev->ops->set_desc_dst_addr(&new->desc, dma_dst); =20 if (!first) first =3D new; else - prev->desc.ddadr =3D new->async_tx.phys; + pdev->ops->set_desc_next_addr(&prev->desc, + new->async_tx.phys); =20 new->async_tx.cookie =3D 0; async_tx_ack(&new->async_tx); @@ -528,6 +620,7 @@ mmp_pdma_prep_slave_sg(struct dma_chan *dchan, struct s= catterlist *sgl, unsigned long flags, void *context) { struct mmp_pdma_chan *chan =3D to_mmp_pdma_chan(dchan); + struct mmp_pdma_device *pdev =3D to_mmp_pdma_dev(dchan->device); struct mmp_pdma_desc_sw *first =3D NULL, *prev =3D NULL, *new =3D NULL; size_t len, avail; struct scatterlist *sg; @@ -559,17 +652,18 @@ mmp_pdma_prep_slave_sg(struct dma_chan *dchan, struct= scatterlist *sgl, =20 new->desc.dcmd =3D chan->dcmd | (DCMD_LENGTH & len); if (dir =3D=3D DMA_MEM_TO_DEV) { - new->desc.dsadr =3D addr; + pdev->ops->set_desc_src_addr(&new->desc, addr); new->desc.dtadr =3D chan->dev_addr; } else { new->desc.dsadr =3D chan->dev_addr; - new->desc.dtadr =3D addr; + pdev->ops->set_desc_dst_addr(&new->desc, addr); } =20 if (!first) first =3D new; else - prev->desc.ddadr =3D new->async_tx.phys; + pdev->ops->set_desc_next_addr(&prev->desc, + new->async_tx.phys); =20 new->async_tx.cookie =3D 0; async_tx_ack(&new->async_tx); @@ -609,12 +703,15 @@ mmp_pdma_prep_dma_cyclic(struct dma_chan *dchan, unsigned long flags) { struct mmp_pdma_chan *chan; + struct mmp_pdma_device *pdev; struct mmp_pdma_desc_sw *first =3D NULL, *prev =3D NULL, *new; dma_addr_t dma_src, dma_dst; =20 if (!dchan || !len || !period_len) return NULL; =20 + pdev =3D to_mmp_pdma_dev(dchan->device); + /* the buffer length must be a multiple of period_len */ if (len % period_len !=3D 0) return NULL; @@ -651,13 +748,14 @@ mmp_pdma_prep_dma_cyclic(struct dma_chan *dchan, =20 new->desc.dcmd =3D (chan->dcmd | DCMD_ENDIRQEN | (DCMD_LENGTH & period_len)); - new->desc.dsadr =3D dma_src; - new->desc.dtadr =3D dma_dst; + pdev->ops->set_desc_src_addr(&new->desc, dma_src); + pdev->ops->set_desc_dst_addr(&new->desc, dma_dst); =20 if (!first) first =3D new; else - prev->desc.ddadr =3D new->async_tx.phys; + pdev->ops->set_desc_next_addr(&prev->desc, + new->async_tx.phys); =20 new->async_tx.cookie =3D 0; async_tx_ack(&new->async_tx); @@ -678,7 +776,7 @@ mmp_pdma_prep_dma_cyclic(struct dma_chan *dchan, first->async_tx.cookie =3D -EBUSY; =20 /* make the cyclic link */ - new->desc.ddadr =3D first->async_tx.phys; + pdev->ops->set_desc_next_addr(&new->desc, first->async_tx.phys); chan->cyclic_first =3D first; =20 return &first->async_tx; @@ -764,7 +862,9 @@ static unsigned int mmp_pdma_residue(struct mmp_pdma_ch= an *chan, dma_cookie_t cookie) { struct mmp_pdma_desc_sw *sw; - u32 curr, residue =3D 0; + struct mmp_pdma_device *pdev =3D to_mmp_pdma_dev(chan->chan.device); + u64 curr; + u32 residue =3D 0; bool passed =3D false; bool cyclic =3D chan->cyclic_first !=3D NULL; =20 @@ -776,17 +876,18 @@ static unsigned int mmp_pdma_residue(struct mmp_pdma_= chan *chan, return 0; =20 if (chan->dir =3D=3D DMA_DEV_TO_MEM) - curr =3D readl(chan->phy->base + DTADR(chan->phy->idx)); + curr =3D pdev->ops->read_dst_addr(chan->phy); else - curr =3D readl(chan->phy->base + DSADR(chan->phy->idx)); + curr =3D pdev->ops->read_src_addr(chan->phy); =20 list_for_each_entry(sw, &chan->chain_running, node) { - u32 start, end, len; + u64 start, end; + u32 len; =20 if (chan->dir =3D=3D DMA_DEV_TO_MEM) - start =3D sw->desc.dtadr; + start =3D pdev->ops->get_desc_dst_addr(&sw->desc); else - start =3D sw->desc.dsadr; + start =3D pdev->ops->get_desc_src_addr(&sw->desc); =20 len =3D sw->desc.dcmd & DCMD_LENGTH; end =3D start + len; @@ -802,7 +903,7 @@ static unsigned int mmp_pdma_residue(struct mmp_pdma_ch= an *chan, if (passed) { residue +=3D len; } else if (curr >=3D start && curr <=3D end) { - residue +=3D end - curr; + residue +=3D (u32)(end - curr); passed =3D true; } =20 @@ -996,9 +1097,26 @@ static int mmp_pdma_chan_init(struct mmp_pdma_device = *pdev, int idx, int irq) return 0; } =20 +static const struct mmp_pdma_ops marvell_pdma_v1_ops =3D { + .write_next_addr =3D write_next_addr_32, + .read_src_addr =3D read_src_addr_32, + .read_dst_addr =3D read_dst_addr_32, + .set_desc_next_addr =3D set_desc_next_addr_32, + .set_desc_src_addr =3D set_desc_src_addr_32, + .set_desc_dst_addr =3D set_desc_dst_addr_32, + .get_desc_src_addr =3D get_desc_src_addr_32, + .get_desc_dst_addr =3D get_desc_dst_addr_32, + .run_bits =3D (DCSR_RUN), + .dma_mask =3D 0, /* let OF/platform set DMA mask */ +}; + static const struct of_device_id mmp_pdma_dt_ids[] =3D { - { .compatible =3D "marvell,pdma-1.0", }, - {} + { + .compatible =3D "marvell,pdma-1.0", + .data =3D &marvell_pdma_v1_ops + }, { + /* sentinel */ + } }; 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Thu, 21 Aug 2025 20:06:59 -0700 (PDT) Received: from [127.0.1.1] ([222.71.237.178]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b47769afc1bsm2756777a12.19.2025.08.21.20.06.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Aug 2025 20:06:58 -0700 (PDT) From: Guodong Xu Date: Fri, 22 Aug 2025 11:06:31 +0800 Subject: [PATCH v5 5/8] dmaengine: mmp_pdma: Add SpacemiT K1 PDMA support with 64-bit addressing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250822-working_dma_0701_v2-v5-5-f5c0eda734cc@riscstar.com> References: <20250822-working_dma_0701_v2-v5-0-f5c0eda734cc@riscstar.com> In-Reply-To: <20250822-working_dma_0701_v2-v5-0-f5c0eda734cc@riscstar.com> To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , duje@dujemihanovic.xyz Cc: Alex Elder , Vivian Wang , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Guodong Xu , Troy Mitchell X-Mailer: b4 0.14.2 Add support for SpacemiT K1 PDMA controller which features 64-bit addressing capabilities. The SpacemiT K1 PDMA extends the descriptor format with additional 32-bit words for high address bits, enabling access to memory beyond 4GB boundaries. The new spacemit_k1_pdma_ops provides necessary 64-bit address handling functions and k1 specific controller configurations. Key changes: - Add ARCH_SPACEMIT dependency to Kconfig - Define new high 32-bit address registers (DDADRH, DSADRH, DTADRH) - Add DCSR_LPAEEN bit for Long Physical Address Extension Enable - Implement 64-bit operations for SpacemiT K1 PDMA Signed-off-by: Guodong Xu Tested-by: Troy Mitchell --- v5: No change. v4: No change. v3: No change. v2: New patch. - Implement 64-bit addrssing support to mmp_pdma - Add support for SpacemiT K1 PDMA - Extend the MMP_PDMA entry in Kconfig to depend on ARCH_SPACEMIT --- drivers/dma/Kconfig | 2 +- drivers/dma/mmp_pdma.c | 81 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 82 insertions(+), 1 deletion(-) diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 05c7c7d9e5a4e52a8ad7ada8c8b9b1a6f9d875f6..b8a74b1798ba1d44b2655399042= 8c065de6fc535 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -450,7 +450,7 @@ config MILBEAUT_XDMAC =20 config MMP_PDMA tristate "MMP PDMA support" - depends on ARCH_MMP || ARCH_PXA || COMPILE_TEST + depends on ARCH_MMP || ARCH_PXA || ARCH_SPACEMIT || COMPILE_TEST select DMA_ENGINE help Support the MMP PDMA engine for PXA and MMP platform. diff --git a/drivers/dma/mmp_pdma.c b/drivers/dma/mmp_pdma.c index 38d1a4cdfd0e92e53c77b61caa1133559ef40dbd..d07229a748868b8115892c63c54= c16130d88e326 100644 --- a/drivers/dma/mmp_pdma.c +++ b/drivers/dma/mmp_pdma.c @@ -28,6 +28,9 @@ #define DDADR(n) (0x0200 + ((n) << 4)) #define DSADR(n) (0x0204 + ((n) << 4)) #define DTADR(n) (0x0208 + ((n) << 4)) +#define DDADRH(n) (0x0300 + ((n) << 4)) +#define DSADRH(n) (0x0304 + ((n) << 4)) +#define DTADRH(n) (0x0308 + ((n) << 4)) #define DCMD 0x020c =20 #define DCSR_RUN BIT(31) /* Run Bit (read / write) */ @@ -44,6 +47,7 @@ #define DCSR_EORSTOPEN BIT(26) /* STOP on an EOR */ #define DCSR_SETCMPST BIT(25) /* Set Descriptor Compare Status */ #define DCSR_CLRCMPST BIT(24) /* Clear Descriptor Compare Status */ +#define DCSR_LPAEEN BIT(21) /* Long Physical Address Extension Enable */ #define DCSR_CMPST BIT(10) /* The Descriptor Compare Status */ #define DCSR_EORINTR BIT(9) /* The end of Receive */ =20 @@ -76,6 +80,16 @@ struct mmp_pdma_desc_hw { u32 dsadr; /* DSADR value for the current transfer */ u32 dtadr; /* DTADR value for the current transfer */ u32 dcmd; /* DCMD value for the current transfer */ + /* + * The following 32-bit words are only used in the 64-bit, ie. + * LPAE (Long Physical Address Extension) mode. + * They are used to specify the high 32 bits of the descriptor's + * addresses. + */ + u32 ddadrh; /* High 32-bit of DDADR */ + u32 dsadrh; /* High 32-bit of DSADR */ + u32 dtadrh; /* High 32-bit of DTADR */ + u32 rsvd; /* reserved */ } __aligned(32); =20 struct mmp_pdma_desc_sw { @@ -222,6 +236,57 @@ static u64 get_desc_dst_addr_32(const struct mmp_pdma_= desc_hw *desc) return desc->dtadr; } =20 +/* For 64-bit PDMA */ +static void write_next_addr_64(struct mmp_pdma_phy *phy, dma_addr_t addr) +{ + writel(lower_32_bits(addr), phy->base + DDADR(phy->idx)); + writel(upper_32_bits(addr), phy->base + DDADRH(phy->idx)); +} + +static u64 read_src_addr_64(struct mmp_pdma_phy *phy) +{ + u32 low =3D readl(phy->base + DSADR(phy->idx)); + u32 high =3D readl(phy->base + DSADRH(phy->idx)); + + return ((u64)high << 32) | low; +} + +static u64 read_dst_addr_64(struct mmp_pdma_phy *phy) +{ + u32 low =3D readl(phy->base + DTADR(phy->idx)); + u32 high =3D readl(phy->base + DTADRH(phy->idx)); + + return ((u64)high << 32) | low; +} + +static void set_desc_next_addr_64(struct mmp_pdma_desc_hw *desc, dma_addr_= t addr) +{ + desc->ddadr =3D lower_32_bits(addr); + desc->ddadrh =3D upper_32_bits(addr); +} + +static void set_desc_src_addr_64(struct mmp_pdma_desc_hw *desc, dma_addr_t= addr) +{ + desc->dsadr =3D lower_32_bits(addr); + desc->dsadrh =3D upper_32_bits(addr); +} + +static void set_desc_dst_addr_64(struct mmp_pdma_desc_hw *desc, dma_addr_t= addr) +{ + desc->dtadr =3D lower_32_bits(addr); + desc->dtadrh =3D upper_32_bits(addr); +} + +static u64 get_desc_src_addr_64(const struct mmp_pdma_desc_hw *desc) +{ + return ((u64)desc->dsadrh << 32) | desc->dsadr; +} + +static u64 get_desc_dst_addr_64(const struct mmp_pdma_desc_hw *desc) +{ + return ((u64)desc->dtadrh << 32) | desc->dtadr; +} + static int mmp_pdma_config_write(struct dma_chan *dchan, struct dma_slave_config *cfg, enum dma_transfer_direction direction); @@ -1110,10 +1175,26 @@ static const struct mmp_pdma_ops marvell_pdma_v1_op= s =3D { .dma_mask =3D 0, /* let OF/platform set DMA mask */ }; =20 +static const struct mmp_pdma_ops spacemit_k1_pdma_ops =3D { + .write_next_addr =3D write_next_addr_64, + .read_src_addr =3D read_src_addr_64, + .read_dst_addr =3D read_dst_addr_64, + .set_desc_next_addr =3D set_desc_next_addr_64, + .set_desc_src_addr =3D set_desc_src_addr_64, + .set_desc_dst_addr =3D set_desc_dst_addr_64, + .get_desc_src_addr =3D get_desc_src_addr_64, + .get_desc_dst_addr =3D get_desc_dst_addr_64, + .run_bits =3D (DCSR_RUN | DCSR_LPAEEN), + .dma_mask =3D DMA_BIT_MASK(64), /* force 64-bit DMA addr capability */ +}; + static const struct of_device_id mmp_pdma_dt_ids[] =3D { { .compatible =3D "marvell,pdma-1.0", .data =3D &marvell_pdma_v1_ops + }, { + .compatible =3D "spacemit,k1-pdma", + .data =3D &spacemit_k1_pdma_ops }, { /* sentinel */ } --=20 2.43.0 From nobody Sat Oct 4 00:33:15 2025 Received: from mail-pf1-f177.google.com (mail-pf1-f177.google.com [209.85.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6423827EC7C for ; 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Thu, 21 Aug 2025 20:07:03 -0700 (PDT) Received: from [127.0.1.1] ([222.71.237.178]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b47769afc1bsm2756777a12.19.2025.08.21.20.06.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Aug 2025 20:07:03 -0700 (PDT) From: Guodong Xu Date: Fri, 22 Aug 2025 11:06:32 +0800 Subject: [PATCH v5 6/8] riscv: dts: spacemit: Add PDMA node for K1 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250822-working_dma_0701_v2-v5-6-f5c0eda734cc@riscstar.com> References: <20250822-working_dma_0701_v2-v5-0-f5c0eda734cc@riscstar.com> In-Reply-To: <20250822-working_dma_0701_v2-v5-0-f5c0eda734cc@riscstar.com> To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , duje@dujemihanovic.xyz Cc: Alex Elder , Vivian Wang , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Guodong Xu , Troy Mitchell X-Mailer: b4 0.14.2 Add PDMA dma-controller node under dma_bus for SpacemiT K1 SoC. The PDMA node is marked as disabled by default, allowing board-specific device trees to enable it as needed. Signed-off-by: Guodong Xu Reviewed-by: Troy Mitchell Tested-by: Troy Mitchell --- v5: - Add reviewed-by from Troy. v4: - Rename the node from pdma0 to pdma - For consistnecy, put the "interrupts" after "clocks" and "resets" v3: - Adjust pdma0 position, ordering by device address - Update properties according to the newly created schema binding v2: - Updated the compatible string. - Rebased. Part of the changes in v1 is now in this patchset: - "riscv: dts: spacemit: Add DMA translation buses for K1" - Link: https://lore.kernel.org/all/20250623-k1-dma-buses-rfc-wip-v1-0-c= 0144082061f@iscas.ac.cn/ --- arch/riscv/boot/dts/spacemit/k1.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spa= cemit/k1.dtsi index abde8bb07c95c5a745736a2dd6f0c0e0d7c696e4..861f0fe18083fa158da51bd3be2= 808609f6233f4 100644 --- a/arch/riscv/boot/dts/spacemit/k1.dtsi +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi @@ -660,6 +660,17 @@ dma-bus { dma-ranges =3D <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>, <0x1 0x00000000 0x1 0x80000000 0x3 0x00000000>; =20 + pdma: dma-controller@d4000000 { + compatible =3D "spacemit,k1-pdma"; + reg =3D <0x0 0xd4000000 0x0 0x4000>; + clocks =3D <&syscon_apmu CLK_DMA>; + resets =3D <&syscon_apmu RESET_DMA>; + interrupts =3D <72>; + dma-channels =3D <16>; + #dma-cells=3D <1>; + status =3D "disabled"; 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Signed-off-by: Guodong Xu Tested-by: Troy Mitchell --- v5: No change. v4: Rename the node from pdma0 to pdma v3: Adjust pdma0 position, ordering by name alphabetic v2: Added pdma0 enablement on Milkv Jupiter --- arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 4 ++++ arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/b= oot/dts/spacemit/k1-bananapi-f3.dts index fe22c747c5012fe56d42ac8a7efdbbdb694f31b6..6013be25854283a95e630098c1f= de55e33e08018 100644 --- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts @@ -40,6 +40,10 @@ &emmc { status =3D "okay"; }; =20 +&pdma { + status =3D "okay"; +}; + &uart0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&uart0_2_cfg>; diff --git a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts b/arch/riscv= /boot/dts/spacemit/k1-milkv-jupiter.dts index 4483192141049caa201c093fb206b6134a064f42..c615fcadbd333adc749b758f7f8= 14126783f87fb 100644 --- a/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts +++ b/arch/riscv/boot/dts/spacemit/k1-milkv-jupiter.dts @@ -20,6 +20,10 @@ chosen { }; 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Thu, 21 Aug 2025 20:07:13 -0700 (PDT) Received: from [127.0.1.1] ([222.71.237.178]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b47769afc1bsm2756777a12.19.2025.08.21.20.07.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Aug 2025 20:07:12 -0700 (PDT) From: Guodong Xu Date: Fri, 22 Aug 2025 11:06:34 +0800 Subject: [PATCH v5 8/8] riscv: defconfig: Enable MMP_PDMA support for SpacemiT K1 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250822-working_dma_0701_v2-v5-8-f5c0eda734cc@riscstar.com> References: <20250822-working_dma_0701_v2-v5-0-f5c0eda734cc@riscstar.com> In-Reply-To: <20250822-working_dma_0701_v2-v5-0-f5c0eda734cc@riscstar.com> To: Vinod Koul , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , duje@dujemihanovic.xyz Cc: Alex Elder , Vivian Wang , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Guodong Xu , Troy Mitchell X-Mailer: b4 0.14.2 Enable CONFIG_MMP_PDMA in the riscv defconfig for SpacemiT K1 SoC boards. Signed-off-by: Guodong Xu Tested-by: Troy Mitchell --- v5: No change. v4: No change. v3: No change. v2: Rebased. Part of the modification in v1 is now in this patch: - "riscv: defconfig: run savedefconfig to reorder it" , which has been merged into riscv/linux.git (for-next) - Link: https://git.kernel.org/riscv/c/d958097bdf88 --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index f25394d088d0d3cbee41fa9fb553c71e495036fd..b9ef2da15fb22f08bdb5ee5d1bb= a9f6eed49ff97 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -241,6 +241,7 @@ CONFIG_RTC_DRV_SUN6I=3Dy CONFIG_DMADEVICES=3Dy CONFIG_DMA_SUN6I=3Dm CONFIG_DW_AXI_DMAC=3Dy +CONFIG_MMP_PDMA=3Dm CONFIG_VIRTIO_PCI=3Dy CONFIG_VIRTIO_BALLOON=3Dy CONFIG_VIRTIO_INPUT=3Dy --=20 2.43.0