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To enable this feature increase configuration space size to 256MB. If the config space is increased, the BAR space needs to be truncated as it resides in the same location. To avoid the bar space truncation move config space, DBI, ELBI, iATU to upper PCIe region and use lower PCIe iregion entirely for BAR region. This depends on the commit: '10ba0854c5e6 ("PCI: qcom: Disable mirroring of DBI and iATU register space in BAR region")' Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 64a2abd3010018e94eb50c534a509d6b4cf2473b..36afeb2e45937f8ad301c55caf2= 96babdb499820 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2202,11 +2202,11 @@ wifi: wifi@17a10040 { =20 pcie1: pcie@1c08000 { compatible =3D "qcom,pcie-sc7280"; - reg =3D <0 0x01c08000 0 0x3000>, - <0 0x40000000 0 0xf1d>, - <0 0x40000f20 0 0xa8>, - <0 0x40001000 0 0x1000>, - <0 0x40100000 0 0x100000>; + reg =3D <0x0 0x01c08000 0 0x3000>, + <0x4 0x10001000 0 0xf1d>, + <0x4 0x10001f20 0 0xa8>, + <0x4 0x10000000 0 0x1000>, + <0x4 0x00000000 0 0x10000000>; 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Since ELBI register space is applicable for all DWC based controllers, move the resource get code to DWC core and make it optional. Suggested-by: Manivannan Sadhasivam Reviewed-by: Manivannan Sadhasivam Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware.c | 9 +++++++++ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 10 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 89aad5a08928cc29870ab258d33bee9ff8f83143..4684c671a81bee468f686a83cc9= 92433b38af59d 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -167,6 +167,15 @@ int dw_pcie_get_resources(struct dw_pcie *pci) } } =20 + if (!pci->elbi_base) { + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi"); + if (res) { + pci->elbi_base =3D devm_ioremap_resource(pci->dev, res); + if (IS_ERR(pci->elbi_base)) + return PTR_ERR(pci->elbi_base); + } + } + /* LLDD is supposed to manually switch the clocks and resets state */ if (dw_pcie_cap_is(pci, REQ_RES)) { ret =3D dw_pcie_get_clocks(pci); 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Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 294babe1816e4d0c2b2343fe22d89af72afcd6cd..5092752de23866ef95036bb3f8f= ae9bb06e8ea1e 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -276,7 +276,6 @@ struct qcom_pcie_port { struct qcom_pcie { struct dw_pcie *pci; void __iomem *parf; /* DT parf */ - void __iomem *elbi; /* DT elbi */ void __iomem *mhi; union qcom_pcie_resources res; struct phy *phy; @@ -414,12 +413,17 @@ static void qcom_pcie_configure_dbi_atu_base(struct q= com_pcie *pcie) =20 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie) { + struct dw_pcie *pci =3D pcie->pci; u32 val; =20 + if (!pci->elbi_base) { + dev_err(pci->dev, "ELBI is not present\n"); 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Designware databook 5.20a, section 3.10.10.3 says about CFG Shift Feature, which shifts/maps the BDF (bits [31:16] of the third header DWORD, which would be matched against the Base and Limit addresses) of the incoming CfgRd0/CfgWr0 down to bits[27:12]of the translated address. Configuring iATU in config shift feature enables ECAM feature to access the config space, which avoids iATU configuration for every config access. Add "ctrl2" into struct dw_pcie_ob_atu_cfg to enable config shift feature. As DBI comes under config space, this avoids remapping of DBI space separately. Instead, it uses the mapped config space address returned from ECAM initialization. Change the order of dw_pcie_get_resources() execution to achieve this. Enable the ECAM feature if the config space size is equal to size required to represent number of buses in the bus range property. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/Kconfig | 1 + drivers/pci/controller/dwc/pcie-designware-host.c | 131 ++++++++++++++++++= +--- drivers/pci/controller/dwc/pcie-designware.c | 2 +- drivers/pci/controller/dwc/pcie-designware.h | 5 + 4 files changed, 124 insertions(+), 15 deletions(-) diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dw= c/Kconfig index ff6b6d9e18ecfa44273e87931551f9e63fbe3cba..a0e7ad3fb5afec63b0f919732a5= 0147229623186 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -20,6 +20,7 @@ config PCIE_DW_HOST bool select PCIE_DW select IRQ_MSI_LIB + select PCI_HOST_COMMON =20 config PCIE_DW_EP bool diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 952f8594b501254d2b2de5d5e056e16d2aa8d4b7..abb93265a19fd62d3fecc64f29f= 37baf67291b40 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -413,6 +413,81 @@ static void dw_pcie_host_request_msg_tlp_res(struct dw= _pcie_rp *pp) } } =20 +static int dw_pcie_config_ecam_iatu(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct dw_pcie_ob_atu_cfg atu =3D {0}; + resource_size_t bus_range_max; + struct resource_entry *bus; + int ret; + + bus =3D resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS); + + /* + * Root bus under the host bridge doesn't require any iATU configuration + * as DBI region will be used to access root bus config space. + * Immediate bus under Root Bus, needs type 0 iATU configuration and + * remaining buses need type 1 iATU configuration. + */ + atu.index =3D 0; + atu.type =3D PCIE_ATU_TYPE_CFG0; + atu.parent_bus_addr =3D pp->cfg0_base + SZ_1M; + /* 1MiB is to cover 1 (bus) * 32 (devices) * 8 (functions) */ + atu.size =3D SZ_1M; + atu.ctrl2 =3D PCIE_ATU_CFG_SHIFT_MODE_ENABLE; + ret =3D dw_pcie_prog_outbound_atu(pci, &atu); + if (ret) + return ret; + + bus_range_max =3D resource_size(bus->res); + + if (bus_range_max < 2) + return 0; + + /* Configure remaining buses in type 1 iATU configuration */ + atu.index =3D 1; + atu.type =3D PCIE_ATU_TYPE_CFG1; + atu.parent_bus_addr =3D pp->cfg0_base + SZ_2M; + atu.size =3D (SZ_1M * bus_range_max) - SZ_2M; + atu.ctrl2 =3D PCIE_ATU_CFG_SHIFT_MODE_ENABLE; + + return dw_pcie_prog_outbound_atu(pci, &atu); +} + +static int dw_pcie_create_ecam_window(struct dw_pcie_rp *pp, struct resour= ce *res) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct device *dev =3D pci->dev; + struct resource_entry *bus; + + bus =3D resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS); + if (!bus) + return -ENODEV; + + pp->cfg =3D pci_ecam_create(dev, res, bus->res, &pci_generic_ecam_ops); + if (IS_ERR(pp->cfg)) + return PTR_ERR(pp->cfg); + + pci->dbi_base =3D pp->cfg->win; + pci->dbi_phys_addr =3D res->start; + + return 0; +} + +static bool dw_pcie_ecam_enabled(struct dw_pcie_rp *pp, struct resource *c= onfig_res) +{ + struct resource *bus_range; + u64 nr_buses; + + bus_range =3D resource_list_first_type(&pp->bridge->windows, IORESOURCE_B= US)->res; + if (!bus_range) + return false; + + nr_buses =3D resource_size(config_res) >> PCIE_ECAM_BUS_SHIFT; + + return !!(nr_buses >=3D resource_size(bus_range)); +} + static int dw_pcie_host_get_resources(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); @@ -422,10 +497,6 @@ static int dw_pcie_host_get_resources(struct dw_pcie_r= p *pp) struct resource *res; int ret; =20 - ret =3D dw_pcie_get_resources(pci); - if (ret) - return ret; - res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); if (!res) { dev_err(dev, "Missing \"config\" reg space\n"); @@ -435,9 +506,32 @@ static int dw_pcie_host_get_resources(struct dw_pcie_r= p *pp) pp->cfg0_size =3D resource_size(res); pp->cfg0_base =3D res->start; =20 - pp->va_cfg0_base =3D devm_pci_remap_cfg_resource(dev, res); - if (IS_ERR(pp->va_cfg0_base)) - return PTR_ERR(pp->va_cfg0_base); + pp->ecam_enabled =3D dw_pcie_ecam_enabled(pp, res); + if (pp->ecam_enabled) { + ret =3D dw_pcie_create_ecam_window(pp, res); + if (ret) + return ret; + + pp->bridge->ops =3D (struct pci_ops *)&pci_generic_ecam_ops.pci_ops; + pp->bridge->sysdata =3D pp->cfg; + pp->cfg->priv =3D pp; + } else { + pp->va_cfg0_base =3D devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(pp->va_cfg0_base)) + return PTR_ERR(pp->va_cfg0_base); + + /* Set default bus ops */ + pp->bridge->ops =3D &dw_pcie_ops; + pp->bridge->child_ops =3D &dw_child_pcie_ops; + pp->bridge->sysdata =3D pp; + } + + ret =3D dw_pcie_get_resources(pci); + if (ret) { + if (pp->cfg) + pci_ecam_free(pp->cfg); + return ret; + } =20 /* Get the I/O range from DT */ win =3D resource_list_first_type(&pp->bridge->windows, IORESOURCE_IO); @@ -476,14 +570,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) if (ret) return ret; =20 - /* Set default bus ops */ - bridge->ops =3D &dw_pcie_ops; - bridge->child_ops =3D &dw_child_pcie_ops; - if (pp->ops->init) { ret =3D pp->ops->init(pp); if (ret) - return ret; + goto err_free_ecam; } =20 if (pci_msi_enabled()) { @@ -525,6 +615,14 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) if (ret) goto err_free_msi; =20 + if (pp->ecam_enabled) { + ret =3D dw_pcie_config_ecam_iatu(pp); + if (ret) { + dev_err(dev, "Failed to configure iATU in ECAM mode\n"); + goto err_free_msi; + } + } + /* * Allocate the resource for MSG TLP before programming the iATU * outbound window in dw_pcie_setup_rc(). Since the allocation depends @@ -560,8 +658,6 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) /* Ignore errors, the link may come up later */ dw_pcie_wait_for_link(pci); =20 - bridge->sysdata =3D pp; - ret =3D pci_host_probe(bridge); if (ret) goto err_stop_link; @@ -587,6 +683,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) if (pp->ops->deinit) pp->ops->deinit(pp); =20 +err_free_ecam: + if (pp->cfg) + pci_ecam_free(pp->cfg); + return ret; } EXPORT_SYMBOL_GPL(dw_pcie_host_init); @@ -609,6 +709,9 @@ void dw_pcie_host_deinit(struct dw_pcie_rp *pp) =20 if (pp->ops->deinit) pp->ops->deinit(pp); + + if (pp->cfg) + pci_ecam_free(pp->cfg); } EXPORT_SYMBOL_GPL(dw_pcie_host_deinit); =20 diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 4684c671a81bee468f686a83cc992433b38af59d..6826ddb9478d41227fa011018cf= fa8d2242336a9 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -576,7 +576,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, val =3D dw_pcie_enable_ecrc(val); dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val); =20 - val =3D PCIE_ATU_ENABLE; + val =3D PCIE_ATU_ENABLE | atu->ctrl2; if (atu->type =3D=3D PCIE_ATU_TYPE_MSG) { /* The data-less messages only for now */ val |=3D PCIE_ATU_INHIBIT_PAYLOAD | atu->code; diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index ceb022506c3191cd8fe580411526e20cc3758fed..f770e160ce7c538e0835e7cf80b= ae9ed099f906c 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -20,6 +20,7 @@ #include #include #include +#include #include =20 #include @@ -169,6 +170,7 @@ #define PCIE_ATU_REGION_CTRL2 0x004 #define PCIE_ATU_ENABLE BIT(31) #define PCIE_ATU_BAR_MODE_ENABLE BIT(30) +#define PCIE_ATU_CFG_SHIFT_MODE_ENABLE BIT(28) #define PCIE_ATU_INHIBIT_PAYLOAD BIT(22) #define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19) #define PCIE_ATU_LOWER_BASE 0x008 @@ -387,6 +389,7 @@ struct dw_pcie_ob_atu_cfg { u8 func_no; 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Fri, 22 Aug 2025 02:28:13 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE7VrExFnDlGbeOR1PxrtvPDRrJOKWRFkczToKjKFje2jrXPwafW08yHjZroWItQyC6aiaimQ== X-Received: by 2002:a17:90b:278b:b0:323:7e7f:b8f4 with SMTP id 98e67ed59e1d1-32518b80cfamr3394041a91.37.1755854893306; Fri, 22 Aug 2025 02:28:13 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-32525205d1csm549417a91.4.2025.08.22.02.28.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Aug 2025 02:28:12 -0700 (PDT) From: Krishna Chaitanya Chundru Date: Fri, 22 Aug 2025 14:57:33 +0530 Subject: [PATCH v7 5/5] PCI: qcom: Add support for ECAM feature Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250822-ecam_v4-v7-5-098fb4ca77c1@oss.qualcomm.com> References: <20250822-ecam_v4-v7-0-098fb4ca77c1@oss.qualcomm.com> In-Reply-To: <20250822-ecam_v4-v7-0-098fb4ca77c1@oss.qualcomm.com> To: cros-qcom-dts-watchers@chromium.org, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , Manivannan Sadhasivam , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Bjorn Helgaas , Jingoo Han Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, quic_vpernami@quicinc.com, mmareddy@quicinc.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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So override ELBI with the offset from PARF_SLV_DBI_ELBI and cfg win to map these regions. On root bus, we have only the root port. Any access other than that should not go out of the link and should return all F's. Since the iATU is configured for the buses which starts after root bus, block the transactions starting from function 1 of the root bus to the end of the root bus (i.e from dbi_base + 4kb to dbi_base + 1MB) from going outside the link through ECAM blocker through PARF registers. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 70 ++++++++++++++++++++++++++++++= ++++ 1 file changed, 70 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 5092752de23866ef95036bb3f8fae9bb06e8ea1e..8f3c86c77e2604fd7826083f63b= 66b4cb62a341d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -55,6 +55,7 @@ #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 #define PARF_Q2A_FLUSH 0x1ac #define PARF_LTSSM 0x1b0 +#define PARF_SLV_DBI_ELBI 0x1b4 #define PARF_INT_ALL_STATUS 0x224 #define PARF_INT_ALL_CLEAR 0x228 #define PARF_INT_ALL_MASK 0x22c @@ -64,6 +65,16 @@ #define PARF_DBI_BASE_ADDR_V2_HI 0x354 #define PARF_SLV_ADDR_SPACE_SIZE_V2 0x358 #define PARF_SLV_ADDR_SPACE_SIZE_V2_HI 0x35c +#define PARF_BLOCK_SLV_AXI_WR_BASE 0x360 +#define PARF_BLOCK_SLV_AXI_WR_BASE_HI 0x364 +#define PARF_BLOCK_SLV_AXI_WR_LIMIT 0x368 +#define PARF_BLOCK_SLV_AXI_WR_LIMIT_HI 0x36c +#define PARF_BLOCK_SLV_AXI_RD_BASE 0x370 +#define PARF_BLOCK_SLV_AXI_RD_BASE_HI 0x374 +#define PARF_BLOCK_SLV_AXI_RD_LIMIT 0x378 +#define PARF_BLOCK_SLV_AXI_RD_LIMIT_HI 0x37c +#define PARF_ECAM_BASE 0x380 +#define PARF_ECAM_BASE_HI 0x384 #define PARF_NO_SNOOP_OVERRIDE 0x3d4 #define PARF_ATU_BASE_ADDR 0x634 #define PARF_ATU_BASE_ADDR_HI 0x638 @@ -87,6 +98,7 @@ =20 /* PARF_SYS_CTRL register fields */ #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29) +#define PCIE_ECAM_BLOCKER_EN BIT(26) #define MST_WAKEUP_EN BIT(13) #define SLV_WAKEUP_EN BIT(12) #define MSTR_ACLK_CGC_DIS BIT(10) @@ -134,6 +146,9 @@ /* PARF_LTSSM register fields */ #define LTSSM_EN BIT(8) =20 +/* PARF_SLV_DBI_ELBI */ +#define SLV_DBI_ELBI_ADDR_BASE GENMASK(11, 0) + /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */ #define PARF_INT_ALL_LINK_UP BIT(13) #define PARF_INT_MSI_DEV_0_7 GENMASK(30, 23) @@ -317,6 +332,48 @@ static void qcom_ep_reset_deassert(struct qcom_pcie *p= cie) qcom_perst_assert(pcie, false); } =20 +static void qcom_pci_config_ecam(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct qcom_pcie *pcie =3D to_qcom_pcie(pci); + u64 addr, addr_end; + u32 val; + + /* Set the ECAM base */ + writel_relaxed(lower_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_= BASE); + writel_relaxed(upper_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_= BASE_HI); + + /* + * The only device on root bus is the Root Port. Any access to the PCIe + * region will go outside the PCIe link. As part of enumeration the PCI + * sw can try to read to vendor ID & device ID with different device + * number and function number under root bus. As any access other than + * root bus, device 0, function 0, should not go out of the link and + * should return all F's. Since the iATU is configured for the buses + * which starts after root bus, block the transactions starting from + * function 1 of the root bus to the end of the root bus (i.e from + * dbi_base + 4kb to dbi_base + 1MB) from going outside the link. + */ + addr =3D pci->dbi_phys_addr + SZ_4K; + writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BA= SE); + writel_relaxed(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BA= SE_HI); + + writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BA= SE); + writel_relaxed(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BA= SE_HI); + + addr_end =3D pci->dbi_phys_addr + SZ_1M - 1; + + writel_relaxed(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_W= R_LIMIT); + writel_relaxed(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_W= R_LIMIT_HI); + + writel_relaxed(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_R= D_LIMIT); + writel_relaxed(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_R= D_LIMIT_HI); + + val =3D readl_relaxed(pcie->parf + PARF_SYS_CTRL); + val |=3D PCIE_ECAM_BLOCKER_EN; + writel_relaxed(val, pcie->parf + PARF_SYS_CTRL); +} + static int qcom_pcie_start_link(struct dw_pcie *pci) { struct qcom_pcie *pcie =3D to_qcom_pcie(pci); @@ -326,6 +383,9 @@ static int qcom_pcie_start_link(struct dw_pcie *pci) qcom_pcie_common_set_16gt_lane_margining(pci); } =20 + if (pci->pp.ecam_enabled) + qcom_pci_config_ecam(&pci->pp); + /* Enable Link Training state machine */ if (pcie->cfg->ops->ltssm_enable) pcie->cfg->ops->ltssm_enable(pcie); @@ -1314,6 +1374,7 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); struct qcom_pcie *pcie =3D to_qcom_pcie(pci); + u16 offset; int ret; =20 qcom_ep_reset_assert(pcie); @@ -1322,6 +1383,15 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) if (ret) return ret; =20 + if (pp->ecam_enabled) { + /* + * Override ELBI when ECAM is enabled, as when ECAM + * is enabled ELBI moves along with the dbi config space. + */ + offset =3D FIELD_GET(SLV_DBI_ELBI_ADDR_BASE, readl(pcie->parf + PARF_SLV= _DBI_ELBI)); + pci->elbi_base =3D pci->dbi_base + offset; + } + ret =3D qcom_pcie_phy_power_on(pcie); if (ret) goto err_deinit; --=20 2.34.1