From nobody Sat Oct 4 00:19:14 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37347214232; Fri, 22 Aug 2025 14:38:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755873520; cv=none; b=TaAwcdQLay3ghwQRnmM94BDnfJKlQtQa03XK24TWH09dA8afr3JoUvp2kff4qvCdrh/U8Ox69u925ki8WULIxEfMVvWy0ewQZUq+6G5VOb7WAzYByI/ujshfgK4NRwqD3zkrUdP6xnvKd9wasBABAFlL7nhXAeMsdPiapIjODcA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755873520; c=relaxed/simple; bh=FD7f8ChAXPmotgCiHjbPUthmhaXnVq4zbyjwyn+HzF4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=ssyMtd6RARUnXFwW0Oo0oc5IDdPRjrCxhoDv2DIT5MDcjTPYHxUoiDxCpLA+Tt0VPLCs3MC/PL6k/E72mUMYPgfTSMsBqGrtZpZr5FE5Tz/bCW1Vug9rJobAs89nSbK7kc6TVWdeeOp9djzQkCXyEQ9MjY/fKW/HxGvRhas66/Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=UOjjXn3m; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="UOjjXn3m" Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57MEW3dA017575; Fri, 22 Aug 2025 16:38:25 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= tb63wGgl66XJrSdpJFzgbrvT8Sty+d5zvKlUcKZpBbE=; b=UOjjXn3mr+r4BTJe 2hmSh6Pnm7bVn8X8bPOH7gPr1k5VG5wtyYWE0JQz9TRNChgq79/OPyp7/cKjAuse XUas3xwgwbHIXPgAaj6qy7PFJi5oSNtX+hAEXRUFpJYMozskIS5JOJmES1ZDSOrs 1znbq2yTI8LWJG6oDkUzO6XT3I3+AFDUt4N9M4KKVI49NNEdGwwlBlov0S8+B1Yj AEmcfwLevVtPFOKRzxVX8NdO3x3JOazQi0xEaMsHyGmiF5304bOZaaJHo0xCS5GX M3GtgM9tOwxE5wXqOero0snKRrDlmjTFLoxdgFJT+APjp1x0xMdYmLtEJZkd8UyU 9Z8g6w== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 48nd5xshmu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Aug 2025 16:38:25 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 5FBC54004A; Fri, 22 Aug 2025 16:36:55 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 0FD39726F18; Fri, 22 Aug 2025 16:35:54 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 22 Aug 2025 16:35:53 +0200 From: Raphael Gallais-Pou Date: Fri, 22 Aug 2025 16:34:17 +0200 Subject: [PATCH v5 08/13] drm/stm: ltdc: handle lvds pixel clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250822-drm-misc-next-v5-8-9c825e28f733@foss.st.com> References: <20250822-drm-misc-next-v5-0-9c825e28f733@foss.st.com> In-Reply-To: <20250822-drm-misc-next-v5-0-9c825e28f733@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Maxime Coquelin" , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-22_04,2025-08-20_03,2025-03-28_01 From: Yannick Fertre Handle LVDS pixel clock. The LTDC operates with multiple clock domains for register access, requiring all clocks to be provided during read/write operations. This imposes a dependency between the LVDS and LTDC to access correctly all LTDC registers. And because both IPs' pixel rates must be synchronized, the LTDC has to handle the LVDS clock. Signed-off-by: Yannick Fertre Acked-by: Yannick Fertre Signed-off-by: Raphael Gallais-Pou Acked-by: Philippe Cornu --- drivers/gpu/drm/stm/ltdc.c | 22 +++++++++++++++++++++- drivers/gpu/drm/stm/ltdc.h | 1 + 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index 17548dd3484a0a3e1015c58c752b80f8892a0ff7..f84a9a8590f0653e422798ff618= 04d7c3966caef 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -837,6 +837,12 @@ ltdc_crtc_mode_valid(struct drm_crtc *crtc, int target_max =3D target + CLK_TOLERANCE_HZ; int result; =20 + if (ldev->lvds_clk) { + result =3D clk_round_rate(ldev->lvds_clk, target); + drm_dbg_driver(crtc->dev, "lvds pixclk rate target %d, available %d\n", + target, result); + } + result =3D clk_round_rate(ldev->pixel_clk, target); =20 DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result); @@ -1878,6 +1884,8 @@ void ltdc_suspend(struct drm_device *ddev) clk_disable_unprepare(ldev->pixel_clk); if (ldev->bus_clk) clk_disable_unprepare(ldev->bus_clk); + if (ldev->lvds_clk) + clk_disable_unprepare(ldev->lvds_clk); } =20 int ltdc_resume(struct drm_device *ddev) @@ -1895,8 +1903,16 @@ int ltdc_resume(struct drm_device *ddev) =20 if (ldev->bus_clk) { ret =3D clk_prepare_enable(ldev->bus_clk); - if (ret) + if (ret) { drm_err(ddev, "failed to enable bus clock (%d)\n", ret); + return ret; + } + } + + if (ldev->lvds_clk) { + ret =3D clk_prepare_enable(ldev->lvds_clk); + if (ret) + drm_err(ddev, "failed to prepare lvds clock\n"); } =20 return ret; @@ -1981,6 +1997,10 @@ int ltdc_load(struct drm_device *ddev) } } =20 + ldev->lvds_clk =3D devm_clk_get(dev, "lvds"); + if (IS_ERR(ldev->lvds_clk)) + ldev->lvds_clk =3D NULL; + rstc =3D devm_reset_control_get_exclusive(dev, NULL); =20 mutex_init(&ldev->err_lock); diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h index ddfa8ae61a7ba5dc446fae647562d0ec8e6953e1..17b51a7ce28eee5de6d24ca943c= a3b1f48695dfd 100644 --- a/drivers/gpu/drm/stm/ltdc.h +++ b/drivers/gpu/drm/stm/ltdc.h @@ -48,6 +48,7 @@ struct ltdc_device { void __iomem *regs; struct regmap *regmap; struct clk *pixel_clk; /* lcd pixel clock */ + struct clk *lvds_clk; /* lvds pixel clock */ struct clk *bus_clk; /* bus clock */ struct mutex err_lock; /* protecting error_status */ struct ltdc_caps caps; --=20 2.25.1