From nobody Fri Oct 3 23:02:52 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 320393054F4; Fri, 22 Aug 2025 14:38:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755873502; cv=none; b=bsca1QCw4Z98idf/9LWLpyGFhxBT/Jf81hRbUI7Fb7wHQwxvzX+0OsddI3i2CmM8rj0ZRyel/Qqtq+yGDIjP0Q8ifj3m+EVhX2ZFncqBbtA2LkOTawcwe0UBA+Fpot7ImPtdTii3tBpaVTGgvCfKC2o2Yp6GbNWRS49zbYdp+Xc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755873502; c=relaxed/simple; bh=MXPe2LGtvWgtIXzuXImiBeNnO3kSJn60L1tgMiATbS0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=gSggbmAHk7YciotgzQIxJJLQa1tUcXMJzUihmqXO/qwaHjrIcEqYuv5cVDAwABz8QQL8Lm8A7bFroiGrgPT9owPUtU4cOzxc+9lapWMws2q5A8OQURfZsn8vhsx5hG8XLW5TbIwjMFJON5Pcn/NuQ6ZhIppjpxHiWNaaGgv/qD4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=rYljASOn; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="rYljASOn" Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57MEUQMT026394; Fri, 22 Aug 2025 16:38:02 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= 0/DWalJdpRTzR41GI/7nr5IgJdjyXkVRYmOi2yrQ+OU=; b=rYljASOn2oBk5+sC T4oMYk1DxLu7f/HUgIgi1M1Z5TlJvH3MDSkM7JmI0Y+p/5rB/jPVrG0cU/YEoFkh gN9dy45R1g4IAMlmpRwnAPY9qp/cCZUoU1UAf41dQI2R7sW7xkQ+lapYyTjoLECZ i4NNVr6RIiKLr/EdxpO65Wj5YsERo0E2XE51bdEI/nXyFXaY4rTyvpYztLLVuUYE gq4MkYVhcbVyg8miTYiXMlE9pN5FczI6Zij6nN72B//ptRjESsGbsa9QYCAvRaZq L2RSeJsPSP7kQwuZLeZZIUOBK7KJQPMKi9HqkYQpRKAzo/v/5ZaRwZG/FRp91f9U ax9Jfg== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 48np7n7hna-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 22 Aug 2025 16:38:01 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 9AC204002D; Fri, 22 Aug 2025 16:36:47 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id C2C26726C8B; Fri, 22 Aug 2025 16:35:49 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 22 Aug 2025 16:35:49 +0200 From: Raphael Gallais-Pou Date: Fri, 22 Aug 2025 16:34:10 +0200 Subject: [PATCH v5 01/13] dt-bindings: display: st: add two new compatibles to LTDC device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250822-drm-misc-next-v5-1-9c825e28f733@foss.st.com> References: <20250822-drm-misc-next-v5-0-9c825e28f733@foss.st.com> In-Reply-To: <20250822-drm-misc-next-v5-0-9c825e28f733@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Maxime Coquelin" , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-22_04,2025-08-20_03,2025-03-28_01 The new STMicroelectronics SoC features a display controller similar to the one used in previous SoCs. Because there is additional registers, and different mandatory clocks it is incompatible with existing IPs. On STM32MP251, the device only needs two clocks while on STM32MP255 it needs four. Add the new names to the list of compatible string and handle each quirks accordingly. Signed-off-by: Raphael Gallais-Pou Acked-by: Philippe Cornu Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/display/st,stm32-ltdc.yaml | 52 ++++++++++++++++++= +++- 1 file changed, 50 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml b= /Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml index d6ea4d62a2cfae26353c9f20a326a4329fed3a2f..1233345a16307532ea08d3686d1= 94b486f897ea9 100644 --- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml @@ -12,7 +12,10 @@ maintainers: =20 properties: compatible: - const: st,stm32-ltdc + enum: + - st,stm32-ltdc + - st,stm32mp251-ltdc + - st,stm32mp255-ltdc =20 reg: maxItems: 1 @@ -24,11 +27,16 @@ properties: minItems: 1 =20 clocks: - maxItems: 1 + minItems: 1 + maxItems: 4 =20 clock-names: items: - const: lcd + - const: bus + - const: ref + - const: lvds + minItems: 1 =20 resets: maxItems: 1 @@ -51,6 +59,46 @@ required: - resets - port =20 +allOf: + - if: + properties: + compatible: + contains: + enum: + - st,stm32-ltdc + then: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp251-ltdc + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + minItems: 2 + maxItems: 2 + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp255-ltdc + then: + properties: + clocks: + minItems: 4 + clock-names: + minItems: 4 + additionalProperties: false =20 examples: --=20 2.25.1 From nobody Fri Oct 3 23:02:52 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6369B305E0D; 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Fri, 22 Aug 2025 16:38:01 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 9AC5D40044; Fri, 22 Aug 2025 16:36:47 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 5EF79726F09; Fri, 22 Aug 2025 16:35:50 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 22 Aug 2025 16:35:50 +0200 From: Raphael Gallais-Pou Date: Fri, 22 Aug 2025 16:34:11 +0200 Subject: [PATCH v5 02/13] dt-bindings: display: st,stm32-ltdc: add access-controllers property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250822-drm-misc-next-v5-2-9c825e28f733@foss.st.com> References: <20250822-drm-misc-next-v5-0-9c825e28f733@foss.st.com> In-Reply-To: <20250822-drm-misc-next-v5-0-9c825e28f733@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Maxime Coquelin" , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-22_04,2025-08-20_03,2025-03-28_01 access-controllers is an optional property that allows a peripheral to refer to one or more domain access controller(s). This property is added when the peripheral is under the STM32 firewall controller. It allows an accurate representation of the hardware, where the peripheral is connected to a firewall bus. The firewall can then check the peripheral accesses before allowing its device to probe. Acked-by: Rob Herring (Arm) Acked-by: Yannick Fertre Signed-off-by: Raphael Gallais-Pou --- Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml b= /Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml index 1233345a16307532ea08d3686d194b486f897ea9..77058a5ccf682832b923d3e0c5c= e0cdf1f0b85f4 100644 --- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml @@ -41,6 +41,9 @@ properties: resets: maxItems: 1 =20 + access-controllers: + maxItems: 1 + port: $ref: /schemas/graph.yaml#/properties/port description: | --=20 2.25.1 From nobody Fri Oct 3 23:02:52 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AEF16214232; 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Fri, 22 Aug 2025 16:38:17 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id B25FD40049; Fri, 22 Aug 2025 16:36:51 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id F3A98726CAC; Fri, 22 Aug 2025 16:35:50 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 22 Aug 2025 16:35:50 +0200 From: Raphael Gallais-Pou Date: Fri, 22 Aug 2025 16:34:12 +0200 Subject: [PATCH v5 03/13] dt-bindings: display: st: add new compatible to LVDS device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250822-drm-misc-next-v5-3-9c825e28f733@foss.st.com> References: <20250822-drm-misc-next-v5-0-9c825e28f733@foss.st.com> In-Reply-To: <20250822-drm-misc-next-v5-0-9c825e28f733@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Maxime Coquelin" , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-22_04,2025-08-20_03,2025-03-28_01 Update the compatible to accept both "st,stm32mp255-lvds" and st,stm32mp25-lvds" respectively. Default will fall back to "st,stm32mp25-lvds". Acked-by: Krzysztof Kozlowski Acked-by: Yannick Fertre Signed-off-by: Raphael Gallais-Pou --- Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml | 7 +++++= +- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.ya= ml b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml index 6736f93256b5cebb558cda5250369ec4b1b3033c..74e61d95370c299130410cdaae8= 33514324c3e8f 100644 --- a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml @@ -31,7 +31,12 @@ description: | =20 properties: compatible: - const: st,stm32mp25-lvds + oneOf: + - items: + - enum: + - st,stm32mp255-lvds + - const: st,stm32mp25-lvds + - const: st,stm32mp25-lvds =20 "#clock-cells": const: 0 --=20 2.25.1 From nobody Fri Oct 3 23:02:52 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 63620305E05; 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Fri, 22 Aug 2025 16:38:01 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 9F0AE40045; Fri, 22 Aug 2025 16:36:47 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 97A76726F0D; Fri, 22 Aug 2025 16:35:51 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 22 Aug 2025 16:35:51 +0200 From: Raphael Gallais-Pou Date: Fri, 22 Aug 2025 16:34:13 +0200 Subject: [PATCH v5 04/13] dt-bindings: display: st,stm32mp25-lvds: add access-controllers property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250822-drm-misc-next-v5-4-9c825e28f733@foss.st.com> References: <20250822-drm-misc-next-v5-0-9c825e28f733@foss.st.com> In-Reply-To: <20250822-drm-misc-next-v5-0-9c825e28f733@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Maxime Coquelin" , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-22_04,2025-08-20_03,2025-03-28_01 access-controllers is an optional property that allows a peripheral to refer to one or more domain access controller(s). This property is added when the peripheral is under the STM32 firewall controller. It allows an accurate representation of the hardware, where the peripheral is connected to a firewall bus. The firewall can then check the peripheral accesses before allowing its device to probe. Acked-by: Rob Herring (Arm) Acked-by: Yannick Fertre Signed-off-by: Raphael Gallais-Pou --- Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.ya= ml b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml index 74e61d95370c299130410cdaae833514324c3e8f..05a73bbc246a8994b6aabf7c2cd= 9dca773232be4 100644 --- a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml @@ -59,6 +59,9 @@ properties: resets: maxItems: 1 =20 + access-controllers: + maxItems: 1 + ports: $ref: /schemas/graph.yaml#/properties/ports =20 --=20 2.25.1 From nobody Fri Oct 3 23:02:52 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E32A303CB6; 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Fri, 22 Aug 2025 16:38:01 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id E24B540046; Fri, 22 Aug 2025 16:36:47 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 382BF726F13; Fri, 22 Aug 2025 16:35:52 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 22 Aug 2025 16:35:51 +0200 From: Raphael Gallais-Pou Date: Fri, 22 Aug 2025 16:34:14 +0200 Subject: [PATCH v5 05/13] dt-bindings: display: st,stm32mp25-lvds: add power-domains property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250822-drm-misc-next-v5-5-9c825e28f733@foss.st.com> References: <20250822-drm-misc-next-v5-0-9c825e28f733@foss.st.com> In-Reply-To: <20250822-drm-misc-next-v5-0-9c825e28f733@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Maxime Coquelin" , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-22_04,2025-08-20_03,2025-03-28_01 STM32 LVDS peripheral may be in a power domain. Allow an optional single 'power-domains' entry for STM32 LVDS devices. Acked-by: Rob Herring (Arm) Acked-by: Yannick Fertre Signed-off-by: Raphael Gallais-Pou --- Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.ya= ml b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml index 05a73bbc246a8994b6aabf7c2cd9dca773232be4..14e042156179cb2f2d906422eaf= f6840da3c91ea 100644 --- a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml @@ -62,6 +62,9 @@ properties: access-controllers: maxItems: 1 =20 + power-domains: + maxItems: 1 + ports: $ref: /schemas/graph.yaml#/properties/ports =20 --=20 2.25.1 From nobody Fri Oct 3 23:02:52 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3146309DA4; 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Fri, 22 Aug 2025 16:38:25 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 8D84540047; Fri, 22 Aug 2025 16:36:50 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id D04F6726F12; Fri, 22 Aug 2025 16:35:52 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 22 Aug 2025 16:35:52 +0200 From: Raphael Gallais-Pou Date: Fri, 22 Aug 2025 16:34:15 +0200 Subject: [PATCH v5 06/13] dt-bindings: arm: stm32: add required #clock-cells property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250822-drm-misc-next-v5-6-9c825e28f733@foss.st.com> References: <20250822-drm-misc-next-v5-0-9c825e28f733@foss.st.com> In-Reply-To: <20250822-drm-misc-next-v5-0-9c825e28f733@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Maxime Coquelin" , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-22_04,2025-08-20_03,2025-03-28_01 On STM32MP25 SoC, the syscfg peripheral provides a clock to the display subsystem through a multiplexer. Since it only provides a single clock, the cell value is 0. Doing so allows the clock consumers to reach the peripheral and gate the clock accordingly. Reviewed-by: Rob Herring (Arm) Reviewed-by: Yannick Fertre Signed-off-by: Raphael Gallais-Pou Acked-by: Christophe Roullier --- .../bindings/arm/stm32/st,stm32-syscon.yaml | 31 +++++++++++++++---= ---- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.ya= ml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index ed97652c84922813e94b1818c07fe8714891c089..95d2319afe235fa86974d80f89c= 9deeae2275232 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -36,20 +36,31 @@ properties: clocks: maxItems: 1 =20 + "#clock-cells": + const: 0 + required: - compatible - reg =20 -if: - properties: - compatible: - contains: - enum: - - st,stm32mp157-syscfg - - st,stm32f4-gcan -then: - required: - - clocks +allOf: + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp157-syscfg + - st,stm32f4-gcan + then: + required: + - clocks + - if: + properties: + compatible: + const: st,stm32mp25-syscfg + then: + required: + - "#clock-cells" =20 additionalProperties: false =20 --=20 2.25.1 From nobody Fri Oct 3 23:02:52 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 97C093126D6; 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Fri, 22 Aug 2025 16:38:25 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 64EDF4004B; Fri, 22 Aug 2025 16:36:54 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 72483726F14; Fri, 22 Aug 2025 16:35:53 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 22 Aug 2025 16:35:53 +0200 From: Raphael Gallais-Pou Date: Fri, 22 Aug 2025 16:34:16 +0200 Subject: [PATCH v5 07/13] drm/stm: ltdc: support new hardware version for STM32MP25 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250822-drm-misc-next-v5-7-9c825e28f733@foss.st.com> References: <20250822-drm-misc-next-v5-0-9c825e28f733@foss.st.com> In-Reply-To: <20250822-drm-misc-next-v5-0-9c825e28f733@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Maxime Coquelin" , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-22_04,2025-08-20_03,2025-03-28_01 From: Yannick Fertre STM32MP25 SoC features a new version of the LTDC IP. Add its compatible to the list of device to probe and implement its quirks. This hardware supports a pad frequency of 150MHz and a peripheral bus clock. Signed-off-by: Yannick Fertre Acked-by: Yannick Fertre Signed-off-by: Raphael Gallais-Pou Acked-by: Philippe Cornu --- drivers/gpu/drm/stm/drv.c | 12 +++++++++++- drivers/gpu/drm/stm/ltdc.c | 38 +++++++++++++++++++++++++++++++++++--- drivers/gpu/drm/stm/ltdc.h | 5 +++++ 3 files changed, 51 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/stm/drv.c b/drivers/gpu/drm/stm/drv.c index 8ebcaf953782d806a738d5a41ff1f428b0ccff78..ab00d1a6140cc32e71e10abc82f= 7956328b518e3 100644 --- a/drivers/gpu/drm/stm/drv.c +++ b/drivers/gpu/drm/stm/drv.c @@ -236,8 +236,18 @@ static void stm_drm_platform_shutdown(struct platform_= device *pdev) drm_atomic_helper_shutdown(platform_get_drvdata(pdev)); } =20 +static struct ltdc_plat_data stm_drm_plat_data =3D { + .pad_max_freq_hz =3D 90000000, +}; + +static struct ltdc_plat_data stm_drm_plat_data_mp25 =3D { + .pad_max_freq_hz =3D 150000000, +}; + static const struct of_device_id drv_dt_ids[] =3D { - { .compatible =3D "st,stm32-ltdc"}, + { .compatible =3D "st,stm32-ltdc", .data =3D &stm_drm_plat_data, }, + { .compatible =3D "st,stm32mp251-ltdc", .data =3D &stm_drm_plat_data_mp25= , }, + { .compatible =3D "st,stm32mp255-ltdc", .data =3D &stm_drm_plat_data_mp25= , }, { /* end node */ }, }; MODULE_DEVICE_TABLE(of, drv_dt_ids); diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index ba315c66a04d72758b9d3cfcd842432877f66d3a..17548dd3484a0a3e1015c58c752= b80f8892a0ff7 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -51,6 +52,7 @@ #define HWVER_10300 0x010300 #define HWVER_20101 0x020101 #define HWVER_40100 0x040100 +#define HWVER_40101 0x040101 =20 /* * The address of some registers depends on the HW version: such registers= have @@ -1779,6 +1781,7 @@ static int ltdc_get_caps(struct drm_device *ddev) { struct ltdc_device *ldev =3D ddev->dev_private; u32 bus_width_log2, lcr, gc2r; + const struct ltdc_plat_data *pdata =3D of_device_get_match_data(ddev->dev= ); =20 /* * at least 1 layer must be managed & the number of layers @@ -1794,6 +1797,8 @@ static int ltdc_get_caps(struct drm_device *ddev) ldev->caps.bus_width =3D 8 << bus_width_log2; regmap_read(ldev->regmap, LTDC_IDR, &ldev->caps.hw_version); =20 + ldev->caps.pad_max_freq_hz =3D pdata->pad_max_freq_hz; + switch (ldev->caps.hw_version) { case HWVER_10200: case HWVER_10300: @@ -1811,7 +1816,6 @@ static int ltdc_get_caps(struct drm_device *ddev) * does not work on 2nd layer. */ ldev->caps.non_alpha_only_l1 =3D true; - ldev->caps.pad_max_freq_hz =3D 90000000; if (ldev->caps.hw_version =3D=3D HWVER_10200) ldev->caps.pad_max_freq_hz =3D 65000000; ldev->caps.nb_irq =3D 2; @@ -1842,6 +1846,7 @@ static int ltdc_get_caps(struct drm_device *ddev) ldev->caps.fifo_threshold =3D false; break; case HWVER_40100: + case HWVER_40101: ldev->caps.layer_ofs =3D LAY_OFS_1; ldev->caps.layer_regs =3D ltdc_layer_regs_a2; ldev->caps.pix_fmt_hw =3D ltdc_pix_fmt_a2; @@ -1849,7 +1854,6 @@ static int ltdc_get_caps(struct drm_device *ddev) ldev->caps.pix_fmt_nb =3D ARRAY_SIZE(ltdc_drm_fmt_a2); ldev->caps.pix_fmt_flex =3D true; ldev->caps.non_alpha_only_l1 =3D false; - ldev->caps.pad_max_freq_hz =3D 90000000; ldev->caps.nb_irq =3D 2; ldev->caps.ycbcr_input =3D true; ldev->caps.ycbcr_output =3D true; @@ -1872,6 +1876,8 @@ void ltdc_suspend(struct drm_device *ddev) =20 DRM_DEBUG_DRIVER("\n"); clk_disable_unprepare(ldev->pixel_clk); + if (ldev->bus_clk) + clk_disable_unprepare(ldev->bus_clk); } =20 int ltdc_resume(struct drm_device *ddev) @@ -1887,7 +1893,13 @@ int ltdc_resume(struct drm_device *ddev) return ret; } =20 - return 0; + if (ldev->bus_clk) { + ret =3D clk_prepare_enable(ldev->bus_clk); + if (ret) + drm_err(ddev, "failed to enable bus clock (%d)\n", ret); + } + + return ret; } =20 int ltdc_load(struct drm_device *ddev) @@ -1922,6 +1934,20 @@ int ltdc_load(struct drm_device *ddev) return -ENODEV; } =20 + if (of_device_is_compatible(np, "st,stm32mp251-ltdc") || + of_device_is_compatible(np, "st,stm32mp255-ltdc")) { + ldev->bus_clk =3D devm_clk_get(dev, "bus"); + if (IS_ERR(ldev->bus_clk)) + return dev_err_probe(dev, PTR_ERR(ldev->bus_clk), + "Unable to get bus clock\n"); + + ret =3D clk_prepare_enable(ldev->bus_clk); + if (ret) { + drm_err(ddev, "Unable to prepare bus clock\n"); + return ret; + } + } + /* Get endpoints if any */ for (i =3D 0; i < nb_endpoints; i++) { ret =3D drm_of_find_panel_or_bridge(np, 0, i, &panel, &bridge); @@ -2034,6 +2060,9 @@ int ltdc_load(struct drm_device *ddev) =20 clk_disable_unprepare(ldev->pixel_clk); =20 + if (ldev->bus_clk) + clk_disable_unprepare(ldev->bus_clk); + pinctrl_pm_select_sleep_state(ddev->dev); =20 pm_runtime_enable(ddev->dev); @@ -2042,6 +2071,9 @@ int ltdc_load(struct drm_device *ddev) err: clk_disable_unprepare(ldev->pixel_clk); =20 + if (ldev->bus_clk) + clk_disable_unprepare(ldev->bus_clk); + return ret; } =20 diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h index 9d488043ffdbc652deeede71c9d57d45fb89d3c6..ddfa8ae61a7ba5dc446fae64756= 2d0ec8e6953e1 100644 --- a/drivers/gpu/drm/stm/ltdc.h +++ b/drivers/gpu/drm/stm/ltdc.h @@ -40,10 +40,15 @@ struct fps_info { ktime_t last_timestamp; }; =20 +struct ltdc_plat_data { + int pad_max_freq_hz; /* max frequency supported by pad */ +}; + struct ltdc_device { void __iomem *regs; struct regmap *regmap; struct clk *pixel_clk; /* lcd pixel clock */ + struct clk *bus_clk; /* bus clock */ struct mutex err_lock; /* protecting error_status */ struct ltdc_caps caps; u32 irq_status; --=20 2.25.1 From nobody Fri Oct 3 23:02:53 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37347214232; Fri, 22 Aug 2025 14:38:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755873520; cv=none; b=TaAwcdQLay3ghwQRnmM94BDnfJKlQtQa03XK24TWH09dA8afr3JoUvp2kff4qvCdrh/U8Ox69u925ki8WULIxEfMVvWy0ewQZUq+6G5VOb7WAzYByI/ujshfgK4NRwqD3zkrUdP6xnvKd9wasBABAFlL7nhXAeMsdPiapIjODcA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755873520; c=relaxed/simple; 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Fri, 22 Aug 2025 16:36:55 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 0FD39726F18; Fri, 22 Aug 2025 16:35:54 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 22 Aug 2025 16:35:53 +0200 From: Raphael Gallais-Pou Date: Fri, 22 Aug 2025 16:34:17 +0200 Subject: [PATCH v5 08/13] drm/stm: ltdc: handle lvds pixel clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250822-drm-misc-next-v5-8-9c825e28f733@foss.st.com> References: <20250822-drm-misc-next-v5-0-9c825e28f733@foss.st.com> In-Reply-To: <20250822-drm-misc-next-v5-0-9c825e28f733@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Maxime Coquelin" , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-22_04,2025-08-20_03,2025-03-28_01 From: Yannick Fertre Handle LVDS pixel clock. The LTDC operates with multiple clock domains for register access, requiring all clocks to be provided during read/write operations. This imposes a dependency between the LVDS and LTDC to access correctly all LTDC registers. And because both IPs' pixel rates must be synchronized, the LTDC has to handle the LVDS clock. Signed-off-by: Yannick Fertre Acked-by: Yannick Fertre Signed-off-by: Raphael Gallais-Pou Acked-by: Philippe Cornu --- drivers/gpu/drm/stm/ltdc.c | 22 +++++++++++++++++++++- drivers/gpu/drm/stm/ltdc.h | 1 + 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index 17548dd3484a0a3e1015c58c752b80f8892a0ff7..f84a9a8590f0653e422798ff618= 04d7c3966caef 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -837,6 +837,12 @@ ltdc_crtc_mode_valid(struct drm_crtc *crtc, int target_max =3D target + CLK_TOLERANCE_HZ; int result; =20 + if (ldev->lvds_clk) { + result =3D clk_round_rate(ldev->lvds_clk, target); + drm_dbg_driver(crtc->dev, "lvds pixclk rate target %d, available %d\n", + target, result); + } + result =3D clk_round_rate(ldev->pixel_clk, target); =20 DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result); @@ -1878,6 +1884,8 @@ void ltdc_suspend(struct drm_device *ddev) clk_disable_unprepare(ldev->pixel_clk); if (ldev->bus_clk) clk_disable_unprepare(ldev->bus_clk); + if (ldev->lvds_clk) + clk_disable_unprepare(ldev->lvds_clk); } =20 int ltdc_resume(struct drm_device *ddev) @@ -1895,8 +1903,16 @@ int ltdc_resume(struct drm_device *ddev) =20 if (ldev->bus_clk) { ret =3D clk_prepare_enable(ldev->bus_clk); - if (ret) + if (ret) { drm_err(ddev, "failed to enable bus clock (%d)\n", ret); + return ret; + } + } + + if (ldev->lvds_clk) { + ret =3D clk_prepare_enable(ldev->lvds_clk); + if (ret) + drm_err(ddev, "failed to prepare lvds clock\n"); } =20 return ret; @@ -1981,6 +1997,10 @@ int ltdc_load(struct drm_device *ddev) } } =20 + ldev->lvds_clk =3D devm_clk_get(dev, "lvds"); + if (IS_ERR(ldev->lvds_clk)) + ldev->lvds_clk =3D NULL; + rstc =3D devm_reset_control_get_exclusive(dev, NULL); =20 mutex_init(&ldev->err_lock); diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h index ddfa8ae61a7ba5dc446fae647562d0ec8e6953e1..17b51a7ce28eee5de6d24ca943c= a3b1f48695dfd 100644 --- a/drivers/gpu/drm/stm/ltdc.h +++ b/drivers/gpu/drm/stm/ltdc.h @@ -48,6 +48,7 @@ struct ltdc_device { void __iomem *regs; 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It provides a parallel digital RGB flow to be used by display interfaces. Add the LTDC node. Acked-by: Yannick Fertre Signed-off-by: Raphael Gallais-Pou --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 303abf915b8e489671b51a8c832041c14a42ecb8..372a99d9cc5c3730e8fbeddeb61= 34a3b18d938b6 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1576,6 +1576,18 @@ dcmipp: dcmipp@48030000 { status =3D "disabled"; }; =20 + ltdc: display-controller@48010000 { + compatible =3D "st,stm32mp251-ltdc"; + reg =3D <0x48010000 0x400>; + interrupts =3D , + ; + clocks =3D <&rcc CK_KER_LTDC>, <&rcc CK_BUS_LTDC>; + clock-names =3D "lcd", "bus"; + resets =3D <&rcc LTDC_R>; + access-controllers =3D <&rifsc 80>; + status =3D "disabled"; + }; + combophy: phy@480c0000 { compatible =3D "st,stm32mp25-combophy"; reg =3D <0x480c0000 0x1000>; --=20 2.25.1 From nobody Fri Oct 3 23:02:53 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 097D53126C0; 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While having this flag is semantically correct, it for now leads to an improper setting of the clock rate. The ck_ker_ltdc parent clock is the flexgen 27, which does not support changing rates yet. To overcome this issue, a fixed clock can be used for the kernel clock. Acked-by: Yannick Fertre Signed-off-by: Raphael Gallais-Pou --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 6 ++++++ arch/arm64/boot/dts/st/stm32mp255.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 372a99d9cc5c3730e8fbeddeb6134a3b18d938b6..b44ff221e0da968be104ff8195f= 9bef79c90c57a 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -52,6 +52,12 @@ clk_rcbsec: clk-rcbsec { compatible =3D "fixed-clock"; clock-frequency =3D <64000000>; }; + + clk_flexgen_27_fixed: clk-54000000 { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <54000000>; + }; }; =20 firmware { diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/s= t/stm32mp255.dtsi index f689b47c5010033120146cf1954d6624c0270045..48a95af1741c42300195b753b71= 0e714abc60d96 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -5,6 +5,12 @@ */ #include "stm32mp253.dtsi" =20 +<dc { + compatible =3D "st,stm32mp255-ltdc"; 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Fri, 22 Aug 2025 16:37:02 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id E6BA6726F1E; Fri, 22 Aug 2025 16:35:55 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 22 Aug 2025 16:35:55 +0200 From: Raphael Gallais-Pou Date: Fri, 22 Aug 2025 16:34:20 +0200 Subject: [PATCH v5 11/13] arm64: dts: st: add lvds support on stm32mp255 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250822-drm-misc-next-v5-11-9c825e28f733@foss.st.com> References: <20250822-drm-misc-next-v5-0-9c825e28f733@foss.st.com> In-Reply-To: <20250822-drm-misc-next-v5-0-9c825e28f733@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Maxime Coquelin" , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-22_04,2025-08-20_03,2025-03-28_01 The LVDS is used on STM32MP2 as a display interface. Add the LVDS node. Acked-by: Yannick Fertre Signed-off-by: Raphael Gallais-Pou --- arch/arm64/boot/dts/st/stm32mp255.dtsi | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/s= t/stm32mp255.dtsi index 48a95af1741c42300195b753b710e714abc60d96..433a0aabe72e5a449ec03fb984a= 8684c5d5d75a2 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -12,6 +12,18 @@ <dc { }; =20 &rifsc { + lvds: lvds@48060000 { + compatible =3D "st,stm32mp255-lvds", "st,stm32mp25-lvds"; + #clock-cells =3D <0>; + reg =3D <0x48060000 0x2000>; + clocks =3D <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>; + clock-names =3D "pclk", "ref"; + resets =3D <&rcc LVDS_R>; + access-controllers =3D <&rifsc 84>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + }; + vdec: vdec@480d0000 { compatible =3D "st,stm32mp25-vdec"; reg =3D <0x480d0000 0x3c8>; @@ -28,4 +40,4 @@ venc: venc@480e0000 { clocks =3D <&rcc CK_BUS_VENC>; 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Acked-by: Yannick Fertre Signed-off-by: Raphael Gallais-Pou --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index b44ff221e0da968be104ff8195f9bef79c90c57a..24823bbfee31f15e813573ad1a0= c4f67a125ce51 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1874,6 +1874,7 @@ exti1: interrupt-controller@44220000 { syscfg: syscon@44230000 { compatible =3D "st,stm32mp25-syscfg", "syscon"; reg =3D <0x44230000 0x10000>; + #clock-cells =3D <0>; }; =20 pinctrl: pinctrl@44240000 { --=20 2.25.1 From nobody Fri Oct 3 23:02:53 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B905312837; Fri, 22 Aug 2025 14:40:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Fri, 22 Aug 2025 16:39:55 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id BACB74005D; Fri, 22 Aug 2025 16:38:41 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 21C3A726F1A; Fri, 22 Aug 2025 16:35:57 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Fri, 22 Aug 2025 16:35:56 +0200 From: Raphael Gallais-Pou Date: Fri, 22 Aug 2025 16:34:22 +0200 Subject: [PATCH v5 13/13] arm64: dts: st: enable display support on stm32mp257f-ev1 board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250822-drm-misc-next-v5-13-9c825e28f733@foss.st.com> References: <20250822-drm-misc-next-v5-0-9c825e28f733@foss.st.com> In-Reply-To: <20250822-drm-misc-next-v5-0-9c825e28f733@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Maxime Coquelin" , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-22_04,2025-08-20_03,2025-03-28_01 Enable the following IPs on stm32mp257f-ev1 in order to get display: * LTDC * LVDS * WSVGA LVDS panel (1024x600) * Panel LVDS backlight as GPIO backlight * ILI2511 i2c touchscreen Acked-by: Yannick Fertre Signed-off-by: Raphael Gallais-Pou --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 79 ++++++++++++++++++++++++++= ++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/d= ts/st/stm32mp257f-ev1.dts index 836b1958ce65fb72c99d634a92af3efaf9844d76..2958ad413b0675575d84942e193= a16f80197b88e 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -86,6 +86,43 @@ mm_ospi1: mm-ospi@60000000 { no-map; }; }; + + panel_lvds: display { + compatible =3D "edt,etml0700z9ndha", "panel-lvds"; + enable-gpios =3D <&gpiog 15 GPIO_ACTIVE_HIGH>; + backlight =3D <&panel_lvds_backlight>; + power-supply =3D <&scmi_v3v3>; + status =3D "okay"; + + width-mm =3D <156>; + height-mm =3D <92>; + data-mapping =3D "vesa-24"; + + panel-timing { + clock-frequency =3D <54000000>; + hactive =3D <1024>; + vactive =3D <600>; + hfront-porch =3D <150>; + hback-porch =3D <150>; + hsync-len =3D <21>; + vfront-porch =3D <24>; + vback-porch =3D <24>; + vsync-len =3D <21>; + }; + + port { + lvds_panel_in: endpoint { + remote-endpoint =3D <&lvds_out0>; + }; + }; + }; + + panel_lvds_backlight: backlight { + compatible =3D "gpio-backlight"; + gpios =3D <&gpioi 5 GPIO_ACTIVE_HIGH>; + default-on; + status =3D "okay"; + }; }; =20 &arm_wdt { @@ -183,6 +220,15 @@ imx335_ep: endpoint { }; }; }; + + ili2511: ili2511@41 { + compatible =3D "ilitek,ili251x"; + reg =3D <0x41>; + interrupt-parent =3D <&gpioi>; + interrupts =3D <13 IRQ_TYPE_EDGE_FALLING>; + reset-gpios =3D <&gpiog 14 GPIO_ACTIVE_LOW>; + status =3D "okay"; + }; }; =20 &i2c8 { @@ -230,6 +276,39 @@ timer { }; }; =20 +<dc { + status =3D "okay"; + + port { + ltdc_ep0_out: endpoint { + remote-endpoint =3D <&lvds_in>; + }; + }; +}; + +&lvds { + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + lvds_in: endpoint { + remote-endpoint =3D <<dc_ep0_out>; + }; + }; + + port@1 { + reg =3D <1>; + lvds_out0: endpoint { + remote-endpoint =3D <&lvds_panel_in>; + }; + }; + }; +}; + &rtc { status =3D "okay"; }; --=20 2.25.1