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Signed-off-by: Wenmeng Liu --- drivers/media/platform/qcom/camss/Makefile | 1 + .../media/platform/qcom/camss/camss-csid-gen3.c | 17 ++ drivers/media/platform/qcom/camss/camss-tpg-gen1.c | 219 +++++++++++++++++= ++++ drivers/media/platform/qcom/camss/camss.c | 78 ++++++++ 4 files changed, 315 insertions(+) diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/pla= tform/qcom/camss/Makefile index e4cf3033b8798cf0ffeff85409ae4ed3559879c1..274fa1e8fef3ce972a94e735565= 1c3801bc1dddc 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -25,5 +25,6 @@ qcom-camss-objs +=3D \ camss-video.o \ camss-format.o \ camss-tpg.o \ + camss-tpg-gen1.o \ =20 obj-$(CONFIG_VIDEO_QCOM_CAMSS) +=3D qcom-camss.o diff --git a/drivers/media/platform/qcom/camss/camss-csid-gen3.c b/drivers/= media/platform/qcom/camss/camss-csid-gen3.c index 664245cf6eb0cac662b02f8b920cd1c72db0aeb2..8e0b0cbaa0010f4b4a156877ac2= fe805e5c4422e 100644 --- a/drivers/media/platform/qcom/camss/camss-csid-gen3.c +++ b/drivers/media/platform/qcom/camss/camss-csid-gen3.c @@ -66,6 +66,8 @@ #define CSI2_RX_CFG0_VC_MODE 3 #define CSI2_RX_CFG0_DL0_INPUT_SEL 4 #define CSI2_RX_CFG0_PHY_NUM_SEL 20 +#define CSI2_RX_CFG0_TPG_NUM_EN 27 +#define CSI2_RX_CFG0_TPG_NUM_SEL 28 =20 #define CSID_CSI2_RX_CFG1 0x204 #define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0) @@ -109,11 +111,26 @@ static void __csid_configure_rx(struct csid_device *c= sid, struct csid_phy_config *phy, int vc) { int val; + struct camss *camss; + struct tpg_device *tpg; =20 + camss =3D csid->camss; val =3D (phy->lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; val |=3D phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; val |=3D (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) << CSI2_RX_CFG0= _PHY_NUM_SEL; =20 + if (camss->tpg) { + tpg =3D &camss->tpg[phy->csiphy_id]; + + if (tpg->testgen.mode > 0) { + val |=3D (phy->csiphy_id + 1) << CSI2_RX_CFG0_TPG_NUM_SEL; + val |=3D 1 << CSI2_RX_CFG0_TPG_NUM_EN; + } else { + val |=3D 0 << CSI2_RX_CFG0_TPG_NUM_SEL; + val |=3D 0 << CSI2_RX_CFG0_TPG_NUM_EN; + } + } + writel(val, csid->base + CSID_CSI2_RX_CFG0); =20 val =3D CSI2_RX_CFG1_ECC_CORRECTION_EN; diff --git a/drivers/media/platform/qcom/camss/camss-tpg-gen1.c b/drivers/m= edia/platform/qcom/camss/camss-tpg-gen1.c new file mode 100644 index 0000000000000000000000000000000000000000..e498e4065d53eca7982590a057c= 2532eaa12ac68 --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-tpg-gen1.c @@ -0,0 +1,219 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * + * Qualcomm MSM Camera Subsystem - TPG (Test Patter Generator) Module + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include +#include + +#include "camss-tpg.h" +#include "camss.h" + +#define TPG_HW_VERSION 0x0 +#define HW_VERSION_STEPPING 0 +#define HW_VERSION_REVISION 16 +#define HW_VERSION_GENERATION 28 + +#define TPG_HW_STATUS 0x4 + +#define TPG_VC_n_GAIN_CFG(n) (0x60 + (n) * 0x60) + +#define TPG_CTRL 0x64 +#define TPG_CTRL_TEST_EN 0 +#define TPG_CTRL_PHY_SEL 3 +#define TPG_CTRL_NUM_ACTIVE_LANES 4 +#define TPG_CTRL_VC_DT_PATTERN_ID 6 +#define TPG_CTRL_OVERLAP_SHDR_EN 10 +#define TPG_CTRL_NUM_ACTIVE_VC 30 +#define NUM_ACTIVE_VC_0_ENABLED 0 +#define NUM_ACTIVE_VC_0_1_ENABLED 1 +#define NUM_ACTIVE_VC_0_1_2_ENABLED 2 +#define NUM_ACTIVE_VC_0_1_3_ENABLED 3 + +#define TPG_VC_n_CFG0(n) (0x68 + (n) * 0x60) +#define TPG_VC_n_CFG0_VC_NUM 0 +#define TPG_VC_n_CFG0_NUM_ACTIVE_DT 8 +#define NUM_ACTIVE_SLOTS_0_ENABLED 0 +#define NUM_ACTIVE_SLOTS_0_1_ENABLED 1 +#define NUM_ACTIVE_SLOTS_0_1_2_ENABLED 2 +#define NUM_ACTIVE_SLOTS_0_1_3_ENABLED 3 +#define TPG_VC_n_CFG0_NUM_BATCH 12 +#define TPG_VC_n_CFG0_NUM_FRAMES 16 + +#define TPG_VC_n_LSFR_SEED(n) (0x6C + (n) * 0x60) + +#define TPG_VC_n_HBI_CFG(n) (0x70 + (n) * 0x60) + +#define TPG_VC_n_VBI_CFG(n) (0x74 + (n) * 0x60) + +#define TPG_VC_n_COLOR_BARS_CFG(n) (0x78 + (n) * 0x60) +#define TPG_VC_n_COLOR_BARS_CFG_PIX_PATTERN 0 +#define TPG_VC_n_COLOR_BARS_CFG_QCFA_EN 3 +#define TPG_VC_n_COLOR_BARS_CFG_SPLIT_EN 4 +#define TPG_VC_n_COLOR_BARS_CFG_NOISE_EN 5 +#define TPG_VC_n_COLOR_BARS_CFG_ROTATE_PERIOD 8 +#define TPG_VC_n_COLOR_BARS_CFG_XCFA_EN 16 +#define TPG_VC_n_COLOR_BARS_CFG_SIZE_X 24 +#define TPG_VC_n_COLOR_BARS_CFG_SIZE_Y 28 + +#define TPG_VC_m_DT_n_CFG_0(m, n) (0x7C + (m) * 0x60 + (n) * 0xC) +#define TPG_VC_m_DT_n_CFG_0_FRAME_HEIGHT 0 +#define TPG_VC_m_DT_n_CFG_0_FRAME_WIDTH 16 + +#define TPG_VC_m_DT_n_CFG_1(m, n) (0x80 + (m) * 0x60 + (n) * 0xC) +#define TPG_VC_m_DT_n_CFG_1_DATA_TYPE 0 +#define TPG_VC_m_DT_n_CFG_1_ECC_XOR_MASK 8 +#define TPG_VC_m_DT_n_CFG_1_CRC_XOR_MASK 16 + +#define TPG_VC_m_DT_n_CFG_2(m, n) (0x84 + (m) * 0x60 + (n) * 0xC) +#define TPG_VC_m_DT_n_CFG_2_PAYLOAD_MODE 0 +#define TPG_VC_m_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD 4 +#define TPG_VC_m_DT_n_CFG_2_ENCODE_FORMAT 28 + +#define TPG_VC_n_COLOR_BAR_CFA_COLOR0(n) (0xB0 + (n) * 0x60) +#define TPG_VC_n_COLOR_BAR_CFA_COLOR1(n) (0xB4 + (n) * 0x60) +#define TPG_VC_n_COLOR_BAR_CFA_COLOR2(n) (0xB8 + (n) * 0x60) +#define TPG_VC_n_COLOR_BAR_CFA_COLOR3(n) (0xBC + (n) * 0x60) + +/* Line offset between VC(n) and VC(n-1), n form 1 to 3 */ +#define TPG_VC_n_SHDR_CFG (0x84 + (n) * 0x60) + +#define TPG_CLEAR 0x1F4 + +#define TPG_USER_SPECIFIED_PAYLOAD_DEFAULT 0xBE +#define TPG_HBI_CFG_DEFAULT 0x4701 +#define TPG_VBI_CFG_DEFAULT 0x438 +#define TPG_LFSR_SEED_DEFAULT 0x12345678 +#define TPG_COLOR_BARS_CFG_STANDARD \ + (0xA << TPG_VC_n_COLOR_BARS_CFG_ROTATE_PERIOD) + +static int tpg_stream_on(struct tpg_device *tpg) +{ + struct tpg_testgen_config *tg =3D &tpg->testgen; + struct v4l2_mbus_framefmt *input_format; + const struct tpg_format_info *format; + u8 lane_cnt =3D tpg->res->lane_cnt; + u8 dt_cnt =3D 0; + u8 i; + u32 val; + + /* Loop through all enabled VCs and configure stream for each */ + for (i =3D 0; i < tpg->res->vc_cnt; i++) { + input_format =3D &tpg->fmt[MSM_TPG_PAD_SRC + i]; + format =3D tpg_get_fmt_entry(tpg, + tpg->res->formats->formats, + tpg->res->formats->nformats, + input_format->code); + + val =3D (input_format->height & 0xffff) << TPG_VC_m_DT_n_CFG_0_FRAME_HEI= GHT; + val |=3D (input_format->width & 0xffff) << TPG_VC_m_DT_n_CFG_0_FRAME_WID= TH; + writel(val, tpg->base + TPG_VC_m_DT_n_CFG_0(i, dt_cnt)); + + val =3D format->data_type << TPG_VC_m_DT_n_CFG_1_DATA_TYPE; + writel(val, tpg->base + TPG_VC_m_DT_n_CFG_1(i, dt_cnt)); + + val =3D (tg->mode - 1) << TPG_VC_m_DT_n_CFG_2_PAYLOAD_MODE; + val |=3D TPG_USER_SPECIFIED_PAYLOAD_DEFAULT << + TPG_VC_m_DT_n_CFG_2_USER_SPECIFIED_PAYLOAD; + val |=3D format->encode_format << TPG_VC_m_DT_n_CFG_2_ENCODE_FORMAT; + writel(val, tpg->base + TPG_VC_m_DT_n_CFG_2(i, dt_cnt)); + + writel(TPG_COLOR_BARS_CFG_STANDARD, tpg->base + TPG_VC_n_COLOR_BARS_CFG(= i)); + + writel(TPG_HBI_CFG_DEFAULT, tpg->base + TPG_VC_n_HBI_CFG(i)); + writel(TPG_VBI_CFG_DEFAULT, tpg->base + TPG_VC_n_VBI_CFG(i)); + + writel(TPG_LFSR_SEED_DEFAULT, tpg->base + TPG_VC_n_LSFR_SEED(i)); + + /* configure one DT, infinite frames */ + val =3D i << TPG_VC_n_CFG0_VC_NUM; + val |=3D 0 << TPG_VC_n_CFG0_NUM_FRAMES; + writel(val, tpg->base + TPG_VC_n_CFG0(i)); + } + + val =3D 1 << TPG_CTRL_TEST_EN; + val |=3D 0 << TPG_CTRL_PHY_SEL; + val |=3D (lane_cnt - 1) << TPG_CTRL_NUM_ACTIVE_LANES; + val |=3D 0 << TPG_CTRL_VC_DT_PATTERN_ID; + val |=3D (tpg->res->vc_cnt - 1) << TPG_CTRL_NUM_ACTIVE_VC; + writel(val, tpg->base + TPG_CTRL); + + return 0; +} + +static void tpg_stream_off(struct tpg_device *tpg) +{ + writel(0, tpg->base + TPG_CTRL); + writel(1, tpg->base + TPG_CLEAR); +} + +static void tpg_configure_stream(struct tpg_device *tpg, u8 enable) +{ + if (enable) + tpg_stream_on(tpg); + else + tpg_stream_off(tpg); +} + +static int tpg_configure_testgen_pattern(struct tpg_device *tpg, s32 val) +{ + if (val > 0 && val <=3D TPG_PAYLOAD_MODE_COLOR_BARS) + tpg->testgen.mode =3D val; + + return 0; +} + +/* + * tpg_hw_version - tpg hardware version query + * @tpg: tpg device + * + * Return HW version or error + */ +static u32 tpg_hw_version(struct tpg_device *tpg) +{ + u32 hw_version; + u32 hw_gen; + u32 hw_rev; + u32 hw_step; + + hw_version =3D readl(tpg->base + TPG_HW_VERSION); + hw_gen =3D FIELD_GET(0xF << HW_VERSION_GENERATION, hw_version); + hw_rev =3D FIELD_GET(0xFFF << HW_VERSION_REVISION, hw_version); + hw_step =3D FIELD_GET(0xFFFF << HW_VERSION_STEPPING, hw_version); + dev_dbg_once(tpg->camss->dev, "tpg HW Version =3D %u.%u.%u\n", + hw_gen, hw_rev, hw_step); + + return hw_version; +} + +/* + * tpg_reset - Trigger reset on tpg module and wait to complete + * @tpg: tpg device + * + * Return 0 on success or a negative error code otherwise + */ +static int tpg_reset(struct tpg_device *tpg) +{ + writel(0, tpg->base + TPG_CTRL); + writel(1, tpg->base + TPG_CLEAR); + + return 0; +} + +static void tpg_subdev_init(struct tpg_device *tpg) +{ + tpg->testgen.modes =3D testgen_payload_modes; + tpg->testgen.nmodes =3D TPG_PAYLOAD_MODE_NUM_SUPPORTED_GEN1; +} + +const struct tpg_hw_ops tpg_ops_gen1 =3D { + .configure_stream =3D tpg_configure_stream, + .configure_testgen_pattern =3D tpg_configure_testgen_pattern, + .hw_version =3D tpg_hw_version, + .reset =3D tpg_reset, + .subdev_init =3D tpg_subdev_init, +}; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/plat= form/qcom/camss/camss.c index 53477a97dcba8385611398dfd07d41653e6ebaf9..3bdd8427fe6d6f1768a65204518= 075dd8a09ca08 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -2611,6 +2611,62 @@ static const struct camss_subdev_resources csiphy_re= s_8775p[] =3D { }, }; =20 +static const struct camss_subdev_resources tpg_res_8775p[] =3D { + /* TPG0 */ + { + .regulators =3D { }, + .clock =3D { "csiphy_rx", "camnoc_axi" }, + .clock_rate =3D { + { 400000000 }, + { 400000000 }, + }, + .reg =3D { "tpg0" }, + .interrupt =3D { "tpg0" }, + .tpg =3D { + .lane_cnt =3D 4, + .vc_cnt =3D 1, + .formats =3D &tpg_formats_gen1, + .hw_ops =3D &tpg_ops_gen1 + } + }, + + /* TPG1 */ + { + .regulators =3D { }, + .clock =3D { "csiphy_rx", "camnoc_axi" }, + .clock_rate =3D { + { 400000000 }, + { 400000000 }, + }, + .reg =3D { "tpg1" }, + .interrupt =3D { "tpg1" }, + .tpg =3D { + .lane_cnt =3D 4, + .vc_cnt =3D 1, + .formats =3D &tpg_formats_gen1, + .hw_ops =3D &tpg_ops_gen1 + } + }, + + /* TPG2 */ + { + .regulators =3D { }, + .clock =3D { "csiphy_rx", "camnoc_axi" }, + .clock_rate =3D { + { 400000000 }, + { 400000000 }, + }, + .reg =3D { "tpg2" }, + .interrupt =3D { "tpg2" }, + .tpg =3D { + .lane_cnt =3D 4, + .vc_cnt =3D 1, + .formats =3D &tpg_formats_gen1, + .hw_ops =3D &tpg_ops_gen1 + } + }, +}; + static const struct camss_subdev_resources csid_res_8775p[] =3D { /* CSID0 */ { @@ -4088,6 +4144,13 @@ static int camss_probe(struct platform_device *pdev) if (!camss->csiphy) return -ENOMEM; =20 + if (camss->res->tpg_num > 0) { + camss->tpg =3D devm_kcalloc(dev, camss->res->tpg_num, + sizeof(*camss->tpg), GFP_KERNEL); + if (!camss->tpg) + return -ENOMEM; + } + camss->csid =3D devm_kcalloc(dev, camss->res->csid_num, sizeof(*camss->cs= id), GFP_KERNEL); if (!camss->csid) @@ -4234,6 +4297,7 @@ static const struct camss_resources msm8916_resources= =3D { .ispif_res =3D &ispif_res_8x16, .vfe_res =3D vfe_res_8x16, .csiphy_num =3D ARRAY_SIZE(csiphy_res_8x16), + .tpg_num =3D 0, .csid_num =3D ARRAY_SIZE(csid_res_8x16), .vfe_num =3D ARRAY_SIZE(vfe_res_8x16), .link_entities =3D camss_link_entities @@ -4248,6 +4312,7 @@ static const struct camss_resources msm8953_resources= =3D { .ispif_res =3D &ispif_res_8x53, .vfe_res =3D vfe_res_8x53, .csiphy_num =3D ARRAY_SIZE(csiphy_res_8x96), + .tpg_num =3D 0, .csid_num =3D ARRAY_SIZE(csid_res_8x53), .vfe_num =3D ARRAY_SIZE(vfe_res_8x53), .link_entities =3D camss_link_entities @@ -4260,6 +4325,7 @@ static const struct camss_resources msm8996_resources= =3D { .ispif_res =3D &ispif_res_8x96, .vfe_res =3D vfe_res_8x96, .csiphy_num =3D ARRAY_SIZE(csiphy_res_8x96), + .tpg_num =3D 0, .csid_num =3D ARRAY_SIZE(csid_res_8x96), .vfe_num =3D ARRAY_SIZE(vfe_res_8x96), .link_entities =3D camss_link_entities @@ -4269,11 +4335,13 @@ static const struct camss_resources qcs8300_resourc= es =3D { .version =3D CAMSS_8300, .pd_name =3D "top", .csiphy_res =3D csiphy_res_8300, + .tpg_res =3D tpg_res_8775p, .csid_res =3D csid_res_8775p, .csid_wrapper_res =3D &csid_wrapper_res_sm8550, .vfe_res =3D vfe_res_8775p, .icc_res =3D icc_res_qcs8300, .csiphy_num =3D ARRAY_SIZE(csiphy_res_8300), + .tpg_num =3D ARRAY_SIZE(tpg_res_8775p), .csid_num =3D ARRAY_SIZE(csid_res_8775p), .vfe_num =3D ARRAY_SIZE(vfe_res_8775p), .icc_path_num =3D ARRAY_SIZE(icc_res_qcs8300), @@ -4284,11 +4352,13 @@ static const struct camss_resources sa8775p_resourc= es =3D { .version =3D CAMSS_8775P, .pd_name =3D "top", .csiphy_res =3D csiphy_res_8775p, + .tpg_res =3D tpg_res_8775p, .csid_res =3D csid_res_8775p, .csid_wrapper_res =3D &csid_wrapper_res_sm8550, .vfe_res =3D vfe_res_8775p, .icc_res =3D icc_res_sa8775p, .csiphy_num =3D ARRAY_SIZE(csiphy_res_8775p), + .tpg_num =3D ARRAY_SIZE(tpg_res_8775p), .csid_num =3D ARRAY_SIZE(csid_res_8775p), .vfe_num =3D ARRAY_SIZE(vfe_res_8775p), .icc_path_num =3D ARRAY_SIZE(icc_res_sa8775p), @@ -4302,6 +4372,7 @@ static const struct camss_resources sdm660_resources = =3D { .ispif_res =3D &ispif_res_660, .vfe_res =3D vfe_res_660, .csiphy_num =3D ARRAY_SIZE(csiphy_res_660), + .tpg_num =3D 0, .csid_num =3D ARRAY_SIZE(csid_res_660), .vfe_num =3D ARRAY_SIZE(vfe_res_660), .link_entities =3D camss_link_entities @@ -4313,6 +4384,7 @@ static const struct camss_resources sdm670_resources = =3D { .csid_res =3D csid_res_670, .vfe_res =3D vfe_res_670, .csiphy_num =3D ARRAY_SIZE(csiphy_res_670), + .tpg_num =3D 0, .csid_num =3D ARRAY_SIZE(csid_res_670), .vfe_num =3D ARRAY_SIZE(vfe_res_670), .link_entities =3D camss_link_entities @@ -4325,6 +4397,7 @@ static const struct camss_resources sdm845_resources = =3D { .csid_res =3D csid_res_845, .vfe_res =3D vfe_res_845, .csiphy_num =3D ARRAY_SIZE(csiphy_res_845), + .tpg_num =3D 0, .csid_num =3D ARRAY_SIZE(csid_res_845), .vfe_num =3D ARRAY_SIZE(vfe_res_845), .link_entities =3D camss_link_entities @@ -4339,6 +4412,7 @@ static const struct camss_resources sm8250_resources = =3D { .icc_res =3D icc_res_sm8250, .icc_path_num =3D ARRAY_SIZE(icc_res_sm8250), .csiphy_num =3D ARRAY_SIZE(csiphy_res_8250), + .tpg_num =3D 0, .csid_num =3D ARRAY_SIZE(csid_res_8250), .vfe_num =3D ARRAY_SIZE(vfe_res_8250), .link_entities =3D camss_link_entities @@ -4354,6 +4428,7 @@ static const struct camss_resources sc8280xp_resource= s =3D { .icc_res =3D icc_res_sc8280xp, .icc_path_num =3D ARRAY_SIZE(icc_res_sc8280xp), .csiphy_num =3D ARRAY_SIZE(csiphy_res_sc8280xp), + .tpg_num =3D 0, .csid_num =3D ARRAY_SIZE(csid_res_sc8280xp), .vfe_num =3D ARRAY_SIZE(vfe_res_sc8280xp), .link_entities =3D camss_link_entities @@ -4368,6 +4443,7 @@ static const struct camss_resources sc7280_resources = =3D { .icc_res =3D icc_res_sc7280, .icc_path_num =3D ARRAY_SIZE(icc_res_sc7280), .csiphy_num =3D ARRAY_SIZE(csiphy_res_7280), + .tpg_num =3D 0, .csid_num =3D ARRAY_SIZE(csid_res_7280), .vfe_num =3D ARRAY_SIZE(vfe_res_7280), .link_entities =3D camss_link_entities @@ -4383,6 +4459,7 @@ static const struct camss_resources sm8550_resources = =3D { .icc_res =3D icc_res_sm8550, .icc_path_num =3D ARRAY_SIZE(icc_res_sm8550), .csiphy_num =3D ARRAY_SIZE(csiphy_res_8550), + .tpg_num =3D 0, .csid_num =3D ARRAY_SIZE(csid_res_8550), .vfe_num =3D ARRAY_SIZE(vfe_res_8550), .link_entities =3D camss_link_entities @@ -4398,6 +4475,7 @@ static const struct camss_resources x1e80100_resource= s =3D { .icc_res =3D icc_res_x1e80100, .icc_path_num =3D ARRAY_SIZE(icc_res_x1e80100), .csiphy_num =3D ARRAY_SIZE(csiphy_res_x1e80100), + .tpg_num =3D 0, .csid_num =3D ARRAY_SIZE(csid_res_x1e80100), .vfe_num =3D ARRAY_SIZE(vfe_res_x1e80100), .link_entities =3D camss_link_entities --=20 2.34.1