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Fri, 22 Aug 2025 06:31:36 -0700 (PDT) From: Krzysztof Kozlowski Date: Fri, 22 Aug 2025 15:31:19 +0200 Subject: [PATCH 10/10] arm64: dts: imx8: Use GIC_SPI for interrupt-map for readability Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250822-b4-dts-interrupt-address-cells-imx-v1-10-f1b479da9340@linaro.org> References: <20250822-b4-dts-interrupt-address-cells-imx-v1-0-f1b479da9340@linaro.org> In-Reply-To: <20250822-b4-dts-interrupt-address-cells-imx-v1-0-f1b479da9340@linaro.org> To: Shawn Guo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, imx@lists.linux.dev, Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3812; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=ZgO6eUDKdzkFk380nvHSCOPF+LK4HXHq8MSxWowHtBQ=; b=owEBbAKT/ZANAwAKAcE3ZuaGi4PXAcsmYgBoqHEo8ebRuqypCpa68Mh2v7d5MUvPuEcsRySCX 9cVV2D5SWeJAjIEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaKhxKAAKCRDBN2bmhouD 12G3D/j2os04TAukiAzO4cVt0bZ4ODbfZ8ElQZZugArIYddeU7K0aLR9h7anhmfB246YsCfa3/C 5/XJ+YY/5EqzjywJxDY+IH1cSgK4UBy86W/JdbBkCLBkBxlu9qJp/LT8itKBaX6u1BwubCI0No1 tJXCN/v+RPVZCs00QXh9ej1sXS/U9bbR70h8TETqgmc1mZXdVGxXBRml0MJ5BfUnreCl+i1+uK6 Cp3MtFnsapo66aWskhohC+jcv//WLG/6LHJ2PKUzzrRI9YYG+09NPABlEwXy4PnoHMUjxXNm1Yx F8vCgZOmZ0dPAbxz2vZa7ibb9vV4JZz6RYC8OvZU5p9ZUTC07odvybnVT15f7m3kOMUIX6lE64b P5XCDPwwi40TIlKH/OKgAJmY/1gk9BU9BwD/8W2oSbaQseb/yPhhaRrJyKVoS5OeNduIsUjRkX/ oBaY0EREk9kNocGp7kQ0V62RzkaD3dmSUFZFjxpWh//WAdH4XCOvjNxOF6BdwKfW79i6nKULuXs 2plT0/ALA4dCbqEpE+9KQYQXPFRBAfp62NOFq2+vdDr/8qKyowWrbc/INq82kPAt4SCsNVVKPb0 E+36ERJGOKX3vyRKxiLDo2EIh4EypzaCmh6079MF0qHBrG0+5gfPi2B3fxPoKL30U8I/MB0IlMH 1XEuQclU7/FOi X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Decoding interrupt-map is tricky, because it consists of five components. Use known GIC_SPI define in final interrupt specifier component makes easier to read. Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi | 8 ++++---- arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi | 8 ++++---- arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi | 16 ++++++++-------- 3 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi b/arch/arm64/b= oot/dts/freescale/imx8-ss-hsio.dtsi index 9b8b1380c4c2bb25f691d72a0217915cf3824889..469de8b536b5866ea83cc054294= 1039996ae5f23 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi @@ -68,10 +68,10 @@ pcieb: pcie@5f010000 { clock-names =3D "dbi", "mstr", "slv"; bus-range =3D <0x00 0xff>; device_type =3D "pci"; - interrupt-map =3D <0 0 0 1 &gic 0 105 4>, - <0 0 0 2 &gic 0 106 4>, - <0 0 0 3 &gic 0 107 4>, - <0 0 0 4 &gic 0 108 4>; + interrupt-map =3D <0 0 0 1 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; interrupt-map-mask =3D <0 0 0 0x7>; num-lanes =3D <1>; num-viewport =3D <4>; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi b/arch/arm6= 4/boot/dts/freescale/imx8dxl-ss-hsio.dtsi index bbc6abb0fdf25b650dacb8dfcbbbe5dac9ed5cce..ec466e4d7df5467803243404795= a9a6a1da890b2 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi @@ -42,10 +42,10 @@ pcie0: pcie@5f010000 { #interrupt-cells =3D <1>; interrupts =3D ; interrupt-names =3D "msi"; - interrupt-map =3D <0 0 0 1 &gic 0 47 4>, - <0 0 0 2 &gic 0 48 4>, - <0 0 0 3 &gic 0 49 4>, - <0 0 0 4 &gic 0 50 4>; + interrupt-map =3D <0 0 0 1 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; interrupt-map-mask =3D <0 0 0 0x7>; }; =20 diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi b/arch/arm64= /boot/dts/freescale/imx8qm-ss-hsio.dtsi index 50c0f6b0f0bdc2bd6fd3a19e08d1b7a723353783..bd6e0aa27efe90d3489c16c705d= 508028b268ee7 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi @@ -30,10 +30,10 @@ pcie0: pciea: pcie@5f000000 { clock-names =3D "dbi", "mstr", "slv"; bus-range =3D <0x00 0xff>; device_type =3D "pci"; - interrupt-map =3D <0 0 0 1 &gic 0 73 4>, - <0 0 0 2 &gic 0 74 4>, - <0 0 0 3 &gic 0 75 4>, - <0 0 0 4 &gic 0 76 4>; + interrupt-map =3D <0 0 0 1 &gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; interrupt-map-mask =3D <0 0 0 0x7>; num-lanes =3D <1>; num-viewport =3D <4>; @@ -80,10 +80,10 @@ pcie1: pcieb: pcie@5f010000 { clock-names =3D "dbi", "mstr", "slv"; bus-range =3D <0x00 0xff>; device_type =3D "pci"; - interrupt-map =3D <0 0 0 1 &gic 0 105 4>, - <0 0 0 2 &gic 0 106 4>, - <0 0 0 3 &gic 0 107 4>, - <0 0 0 4 &gic 0 108 4>; + interrupt-map =3D <0 0 0 1 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; interrupt-map-mask =3D <0 0 0 0x7>; num-lanes =3D <1>; num-viewport =3D <4>; --=20 2.48.1