From nobody Sat Oct 4 00:28:11 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A5F41306D2B; Thu, 21 Aug 2025 17:24:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755797060; cv=none; b=a0A4exRA+23i+hTHrAuojJAWoIIeC1jp2otPtcC837S81mwZlR+QowpOauWiSUWStg4SFuwAZa78eg1QrP8yTTjkAt23EVQEg+zgkR9Z4zjEsIo+VtkqnSKgd3Q84I/cFMPHu0qdQgKfiXqj9i5+GsIOqrjDQ8xFJ85rXegS5tU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755797060; c=relaxed/simple; bh=GZS8B5riWrRAALkBlvJ27EMS9EH/NTGI1JAuqMGKfoY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=iCdE2BsEcqmB6HWWFMerUsI+TarA3bOO7QfECcGf/VQaTZbMwlqhkS0ny27HJ1wWZA+ulNZh/NFt4Nej4mRpnRW/9cuMc+4xtPvK8DjbNmo60bN2Zha0YoKNy3qzdgsiv1gc2x/WxjxYnPxBzMHFARPtu63z881YTMn2qmx70aw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D8FE0168F; Thu, 21 Aug 2025 10:24:09 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 89D5A3F59E; Thu, 21 Aug 2025 10:24:14 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, oliver.upton@linux.dev, anshuman.khandual@arm.com, robh@kernel.org, james.morse@arm.com, mark.rutland@arm.com, joey.gouly@arm.com, Dave.Martin@arm.com, ahmed.genidi@arm.com, kevin.brodsky@arm.com, scott@os.amperecomputing.com, mbenes@suse.cz, james.clark@linaro.org, frederic@kernel.org, rafael@kernel.org, pavel@kernel.org, ryan.roberts@arm.com, suzuki.poulose@arm.com, maz@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvmarm@lists.linux.dev, Yeoreum Yun Subject: [PATCH v4 1/5] arm64: make SCTLR2_EL1 accessible Date: Thu, 21 Aug 2025 18:24:04 +0100 Message-Id: <20250821172408.2101870-2-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250821172408.2101870-1-yeoreum.yun@arm.com> References: <20250821172408.2101870-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" When the kernel runs at EL1, and yet is booted at EL2, HCRX_EL2.SCTLR2En must be set to avoid trapping SCTLR2_EL1 accesses from EL1 to EL2. Ensure this bit is set at the point of initialising EL2. Signed-off-by: Yeoreum Yun Reviewed-by: Marc Zyngier --- arch/arm64/include/asm/el2_setup.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el= 2_setup.h index 46033027510c..d9529dfc4783 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -57,10 +57,16 @@ /* Enable GCS if supported */ mrs_s x1, SYS_ID_AA64PFR1_EL1 ubfx x1, x1, #ID_AA64PFR1_EL1_GCS_SHIFT, #4 - cbz x1, .Lset_hcrx_\@ + cbz x1, .Lskip_hcrx_GCSEn_\@ orr x0, x0, #HCRX_EL2_GCSEn =20 -.Lset_hcrx_\@: +.Lskip_hcrx_GCSEn_\@: + mrs_s x1, SYS_ID_AA64MMFR3_EL1 + ubfx x1, x1, #ID_AA64MMFR3_EL1_SCTLRX_SHIFT, #4 + cbz x1, .Lskip_hcrx_SCTLR2En\@ + orr x0, x0, #HCRX_EL2_SCTLR2En + +.Lskip_hcrx_SCTLR2En\@: msr_s SYS_HCRX_EL2, x0 .Lskip_hcrx_\@: .endm --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sat Oct 4 00:28:11 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B41CA30E0E4; Thu, 21 Aug 2025 17:24:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755797064; cv=none; b=aO5cXoyuj3wtztidQzkzi45NFX2E0nTgsrKH5MgMM3AT7PRGMK6kQTO2gRbIRYFmvmHjmeQPUSKX3nnpXFL/OieNg+DvjbA2uN+RrPuwZVfpq5iDuailMwIJ6myjBbKoklTmjptSrfG1Ycko7wIrRGSLPCpRX2UjRwbEMaOPay8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755797064; c=relaxed/simple; bh=8bUrJy8kFdsel6a29ezZOJv1OAbdONLJW21w+k8jdv4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=t67We/jVMbXPJHyoNuL03v3BQnvhiwJcWgMziYX3mFPi+2r91MLPo92Jv4rdnoOnoWIDraqfjyeR5jQh6vfsnLUqaSypY1d0LenkHEgNwzX68dHZgaK8ML2BTOolyQhRUG/UDf+0rFOFDAG8PJXTkBRiiVXr0BgElzyBuoBf7vU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id AD9AC152B; Thu, 21 Aug 2025 10:24:13 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 640C13F59E; Thu, 21 Aug 2025 10:24:18 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, oliver.upton@linux.dev, anshuman.khandual@arm.com, robh@kernel.org, james.morse@arm.com, mark.rutland@arm.com, joey.gouly@arm.com, Dave.Martin@arm.com, ahmed.genidi@arm.com, kevin.brodsky@arm.com, scott@os.amperecomputing.com, mbenes@suse.cz, james.clark@linaro.org, frederic@kernel.org, rafael@kernel.org, pavel@kernel.org, ryan.roberts@arm.com, suzuki.poulose@arm.com, maz@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvmarm@lists.linux.dev, Yeoreum Yun Subject: [PATCH v4 2/5] arm64: initialise SCTLR2_ELx register at boot time Date: Thu, 21 Aug 2025 18:24:05 +0100 Message-Id: <20250821172408.2101870-3-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250821172408.2101870-1-yeoreum.yun@arm.com> References: <20250821172408.2101870-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The value of the SCTLR2_ELx register is UNKNOWN after reset. If the firmware initializes these registers properly, no additional initialization is required. However, in cases where they are not initialized correctly, initialize the SCTLR2_ELx registers during CPU/vCPU boot to prevent unexpected system behavior caused by invalid values. Signed-off-by: Yeoreum Yun --- arch/arm64/include/asm/assembler.h | 15 +++++++++++++++ arch/arm64/include/asm/el2_setup.h | 7 +++++++ arch/arm64/include/asm/sysreg.h | 5 +++++ arch/arm64/kernel/head.S | 5 +++++ arch/arm64/kernel/hyp-stub.S | 10 ++++++++++ arch/arm64/kvm/hyp/nvhe/psci-relay.c | 3 +++ 6 files changed, 45 insertions(+) diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/as= sembler.h index 23be85d93348..c25c2aed5125 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -738,6 +738,21 @@ alternative_endif set_sctlr sctlr_el2, \reg .endm =20 +/* Set SCTLR2_ELx to the @reg value. */ +.macro set_sctlr2_elx, el, reg, tmp + mrs_s \tmp, SYS_ID_AA64MMFR3_EL1 + ubfx \tmp, \tmp, #ID_AA64MMFR3_EL1_SCTLRX_SHIFT, #4 + cbz \tmp, .Lskip_sctlr2_\@ + .if \el =3D=3D 2 + msr_s SYS_SCTLR2_EL2, \reg + .elseif \el =3D=3D 12 + msr_s SYS_SCTLR2_EL12, \reg + .else + msr_s SYS_SCTLR2_EL1, \reg + .endif +.Lskip_sctlr2_\@: +.endm + /* * Check whether asm code should yield as soon as it is able. This is * the case if we are currently running in task context, and the diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el= 2_setup.h index d9529dfc4783..2addf7c096fc 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -48,6 +48,12 @@ isb .endm =20 +.macro __init_sctlr2_el2 + mov_q x0, INIT_SCTLR2_EL2 + set_sctlr2_elx 2, x0, x1 + isb +.endm + .macro __init_el2_hcrx mrs x0, id_aa64mmfr1_el1 ubfx x0, x0, #ID_AA64MMFR1_EL1_HCX_SHIFT, #4 @@ -411,6 +417,7 @@ */ .macro init_el2_state __init_el2_sctlr + __init_sctlr2_el2 __init_el2_hcrx __init_el2_timers __init_el2_debug diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index d5b5f2ae1afa..0431b357b87b 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -868,6 +868,8 @@ #define INIT_SCTLR_EL2_MMU_OFF \ (SCTLR_EL2_RES1 | ENDIAN_SET_EL2) =20 +#define INIT_SCTLR2_EL2 UL(0) + /* SCTLR_EL1 specific flags. */ #ifdef CONFIG_CPU_BIG_ENDIAN #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE) @@ -888,6 +890,8 @@ SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS | \ SCTLR_EL1_TSCXT | SCTLR_EL1_EOS) =20 +#define INIT_SCTLR2_EL1 UL(0) + /* MAIR_ELx memory attributes (used by Linux) */ #define MAIR_ATTR_DEVICE_nGnRnE UL(0x00) #define MAIR_ATTR_DEVICE_nGnRE UL(0x04) @@ -1164,6 +1168,7 @@ msr hcr_el2, \reg #endif .endm + #else =20 #include diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index ca04b338cb0d..e42664246e15 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -276,6 +276,8 @@ SYM_INNER_LABEL(init_el1, SYM_L_LOCAL) mov_q x0, INIT_SCTLR_EL1_MMU_OFF pre_disable_mmu_workaround msr sctlr_el1, x0 + mov_q x0, INIT_SCTLR2_EL1 + set_sctlr2_elx 1, x0, x1 isb mov_q x0, INIT_PSTATE_EL1 msr spsr_el1, x0 @@ -308,6 +310,7 @@ SYM_INNER_LABEL(init_el2, SYM_L_LOCAL) isb =20 mov_q x1, INIT_SCTLR_EL1_MMU_OFF + mov_q x2, INIT_SCTLR2_EL1 =20 mrs x0, hcr_el2 and x0, x0, #HCR_E2H @@ -315,11 +318,13 @@ SYM_INNER_LABEL(init_el2, SYM_L_LOCAL) =20 /* Set a sane SCTLR_EL1, the VHE way */ msr_s SYS_SCTLR_EL12, x1 + set_sctlr2_elx 12, x2, x0 mov x2, #BOOT_CPU_FLAG_E2H b 3f =20 2: msr sctlr_el1, x1 + set_sctlr2_elx 1, x2, x0 mov x2, xzr 3: mov x0, #INIT_PSTATE_EL1 diff --git a/arch/arm64/kernel/hyp-stub.S b/arch/arm64/kernel/hyp-stub.S index 36e2d26b54f5..ac12f1b4f8e2 100644 --- a/arch/arm64/kernel/hyp-stub.S +++ b/arch/arm64/kernel/hyp-stub.S @@ -144,7 +144,17 @@ SYM_CODE_START_LOCAL(__finalise_el2) =20 .Lskip_indirection: .Lskip_tcr2: + mrs_s x1, SYS_ID_AA64MMFR3_EL1 + ubfx x1, x1, #ID_AA64MMFR3_EL1_SCTLRX_SHIFT, #4 + cbz x1, .Lskip_sctlr2 + mrs_s x1, SYS_SCTLR2_EL12 + msr_s SYS_SCTLR2_EL1, x1 =20 + // clean SCTLR2_EL1 + mov_q x1, INIT_SCTLR2_EL1 + msr_s SYS_SCTLR2_EL12, x1 + +.Lskip_sctlr2: isb =20 // Hack the exception return to stay at EL2 diff --git a/arch/arm64/kvm/hyp/nvhe/psci-relay.c b/arch/arm64/kvm/hyp/nvhe= /psci-relay.c index c3e196fb8b18..df1180cad7f8 100644 --- a/arch/arm64/kvm/hyp/nvhe/psci-relay.c +++ b/arch/arm64/kvm/hyp/nvhe/psci-relay.c @@ -4,6 +4,7 @@ * Author: David Brazdil */ =20 +#include #include #include #include @@ -219,6 +220,8 @@ asmlinkage void __noreturn __kvm_host_psci_cpu_entry(bo= ol is_cpu_on) release_boot_args(boot_args); =20 write_sysreg_el1(INIT_SCTLR_EL1_MMU_OFF, SYS_SCTLR); + if (cpus_have_final_cap(ARM64_HAS_SCTLR2)) + write_sysreg_el1(INIT_SCTLR2_EL1, SYS_SCTLR2); write_sysreg(INIT_PSTATE_EL1, SPSR_EL2); =20 __host_enter(host_ctxt); --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sat Oct 4 00:28:11 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2335233439F; Thu, 21 Aug 2025 17:24:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755797067; cv=none; b=LumCvcGe9Fe4xVQOzVyRs3vrK4LcadxnalS+QevioB3M4ofXTQ+zYZTgLwShDkfsMSudG1YoywL7vjgXhwIFTT5l3Loxg4OCe88gyg0YL3TkoAdqAU6JvQILPPQVQ+ghNy4lfjhpbQMtPTKlplH+hjLNUi/badWlRp6fXbTxTnc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755797067; c=relaxed/simple; bh=aM07tPTmulbFpd+C+lCNUoWkh3IHAjAlwjQKMQQd3ew=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=IM69K700WCcbMJ8WRa/U3H4ymxsiFEKuVbOUCNwuanlFOuYyC4XhM2Ukp94t0PnBbMyJ28RA6TJ59PmeywapOkNs8MtcLZUzbVCWcC9WvpZZ3Clp3ULWNSQlSybbWEwPDf13nqqVlN5F9v/K1Bv6dYDmkABZL+L8kduU2DWTg3E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7FBFA168F; Thu, 21 Aug 2025 10:24:17 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 369573F59E; Thu, 21 Aug 2025 10:24:22 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, oliver.upton@linux.dev, anshuman.khandual@arm.com, robh@kernel.org, james.morse@arm.com, mark.rutland@arm.com, joey.gouly@arm.com, Dave.Martin@arm.com, ahmed.genidi@arm.com, kevin.brodsky@arm.com, scott@os.amperecomputing.com, mbenes@suse.cz, james.clark@linaro.org, frederic@kernel.org, rafael@kernel.org, pavel@kernel.org, ryan.roberts@arm.com, suzuki.poulose@arm.com, maz@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvmarm@lists.linux.dev, Yeoreum Yun Subject: [PATCH v4 3/5] arm64: save/restore SCTLR2_EL1 when cpu_suspend()/resume() Date: Thu, 21 Aug 2025 18:24:06 +0100 Message-Id: <20250821172408.2101870-4-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250821172408.2101870-1-yeoreum.yun@arm.com> References: <20250821172408.2101870-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Save and restore the SCTLR2_EL1 value during cpu_suspend()/resume(), ensuring that the configured value remains consistent across suspend and resume. Signed-off-by: Yeoreum Yun --- arch/arm64/include/asm/suspend.h | 2 +- arch/arm64/mm/proc.S | 24 ++++++++++++++++-------- 2 files changed, 17 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/suspend.h b/arch/arm64/include/asm/susp= end.h index 0cde2f473971..eb60c9735553 100644 --- a/arch/arm64/include/asm/suspend.h +++ b/arch/arm64/include/asm/suspend.h @@ -2,7 +2,7 @@ #ifndef __ASM_SUSPEND_H #define __ASM_SUSPEND_H =20 -#define NR_CTX_REGS 13 +#define NR_CTX_REGS 14 #define NR_CALLEE_SAVED_REGS 12 =20 /* diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index 8c75965afc9e..a330d828270f 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -87,8 +87,12 @@ SYM_FUNC_START(cpu_do_suspend) mrs x9, mdscr_el1 mrs x10, oslsr_el1 mrs x11, sctlr_el1 - get_this_cpu_offset x12 - mrs x13, sp_el0 +alternative_if ARM64_HAS_SCTLR2 + mrs_s x12, SYS_SCTLR2_EL1 +alternative_else_nop_endif + get_this_cpu_offset x13 + mrs x14, sp_el0 + stp x2, x3, [x0] stp x4, x5, [x0, #16] stp x6, x7, [x0, #32] @@ -99,7 +103,7 @@ SYM_FUNC_START(cpu_do_suspend) * Save x18 as it may be used as a platform register, e.g. by shadow * call stack. */ - str x18, [x0, #96] + stp x14, x18, [x0, #96] ret SYM_FUNC_END(cpu_do_suspend) =20 @@ -120,8 +124,8 @@ SYM_FUNC_START(cpu_do_resume) * the buffer to minimize the risk of exposure when used for shadow * call stack. */ - ldr x18, [x0, #96] - str xzr, [x0, #96] + ldp x15, x18, [x0, #96] + str xzr, [x0, #104] msr tpidr_el0, x2 msr tpidrro_el0, x3 msr contextidr_el1, x4 @@ -136,8 +140,12 @@ SYM_FUNC_START(cpu_do_resume) msr mdscr_el1, x10 =20 msr sctlr_el1, x12 - set_this_cpu_offset x13 - msr sp_el0, x14 +alternative_if ARM64_HAS_SCTLR2 + msr_s SYS_SCTLR2_EL1, x13 +alternative_else_nop_endif + + set_this_cpu_offset x14 + msr sp_el0, x15 /* * Restore oslsr_el1 by writing oslar_el1 */ @@ -151,7 +159,7 @@ alternative_if ARM64_HAS_RAS_EXTN msr_s SYS_DISR_EL1, xzr alternative_else_nop_endif =20 - ptrauth_keys_install_kernel_nosync x14, x1, x2, x3 + ptrauth_keys_install_kernel_nosync x15, x1, x2, x3 isb ret SYM_FUNC_END(cpu_do_resume) --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sat Oct 4 00:28:11 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2341331813A; 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dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5B13C168F; Thu, 21 Aug 2025 10:24:21 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 0877B3F59E; Thu, 21 Aug 2025 10:24:25 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, oliver.upton@linux.dev, anshuman.khandual@arm.com, robh@kernel.org, james.morse@arm.com, mark.rutland@arm.com, joey.gouly@arm.com, Dave.Martin@arm.com, ahmed.genidi@arm.com, kevin.brodsky@arm.com, scott@os.amperecomputing.com, mbenes@suse.cz, james.clark@linaro.org, frederic@kernel.org, rafael@kernel.org, pavel@kernel.org, ryan.roberts@arm.com, suzuki.poulose@arm.com, maz@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvmarm@lists.linux.dev, Yeoreum Yun Subject: [PATCH v4 4/5] arm64: initialise SCTLR2_EL1 at cpu_soft_restart() Date: Thu, 21 Aug 2025 18:24:07 +0100 Message-Id: <20250821172408.2101870-5-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250821172408.2101870-1-yeoreum.yun@arm.com> References: <20250821172408.2101870-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Explicitly initialize the SCTLR2_ELx register before launching a new kernel via kexec() to avoid leaving SCTLR2_ELx with an arbitrary value when the new kernel runs. Signed-off-by: Yeoreum Yun --- arch/arm64/kernel/cpu-reset.S | 4 ++++ arch/arm64/kvm/hyp/nvhe/hyp-init.S | 3 +++ 2 files changed, 7 insertions(+) diff --git a/arch/arm64/kernel/cpu-reset.S b/arch/arm64/kernel/cpu-reset.S index c87445dde674..c8888891dc8d 100644 --- a/arch/arm64/kernel/cpu-reset.S +++ b/arch/arm64/kernel/cpu-reset.S @@ -37,6 +37,10 @@ SYM_TYPED_FUNC_START(cpu_soft_restart) * regime if HCR_EL2.E2H =3D=3D 1 */ msr sctlr_el1, x12 + + mov_q x12, INIT_SCTLR2_EL1 + set_sctlr2_elx 1, x12, x8 + isb =20 cbz x0, 1f // el2_switch? diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-init.S b/arch/arm64/kvm/hyp/nvhe/h= yp-init.S index aada42522e7b..cc569656fe35 100644 --- a/arch/arm64/kvm/hyp/nvhe/hyp-init.S +++ b/arch/arm64/kvm/hyp/nvhe/hyp-init.S @@ -255,6 +255,9 @@ SYM_CODE_START(__kvm_handle_stub_hvc) mov x0, xzr reset: /* Reset kvm back to the hyp stub. */ + mov_q x5, INIT_SCTLR2_EL2 + set_sctlr2_elx 2, x5, x4 + mov_q x5, INIT_SCTLR_EL2_MMU_OFF pre_disable_mmu_workaround msr sctlr_el2, x5 --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7} From nobody Sat Oct 4 00:28:11 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 041C031813A; Thu, 21 Aug 2025 17:24:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755797075; cv=none; b=qYR1JlKLY8vZy7kVDzjPiYmACt0SD5VObMHw0qfQJxTEDKCrPj3R5y42fAxt3eQyE/qAQWZFDos2GC+SEgAolCl7cOJL5HIlvDU0IsJLCR9H778ZWOKrxSY/WnlkIUQ/8QzLODP3LakCZjrRiBMkUKtt+5gT5p3kakvm20BH4f8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755797075; c=relaxed/simple; bh=jpG4OioajyvO9e69rzujynWFs3I89Xv/VGW/yDdnHLY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=FhYZEwUBZIEZF/nCL+JztY31E/f/mFz4iAQMuUTExw6XNCa2iB//oyOOx3/0KHLgn2m/HcFCb9SnxKnV9tnrN6pxpWDIbJqCCCFScrs7la72mKl+fAxFajpoeuYZafEp2w9XpQvAkyRvfIQmAN7o9lu4cK27bzByMneC2RRedBo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2C4A4152B; Thu, 21 Aug 2025 10:24:25 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id D7F023F59E; Thu, 21 Aug 2025 10:24:29 -0700 (PDT) From: Yeoreum Yun To: catalin.marinas@arm.com, will@kernel.org, broonie@kernel.org, oliver.upton@linux.dev, anshuman.khandual@arm.com, robh@kernel.org, james.morse@arm.com, mark.rutland@arm.com, joey.gouly@arm.com, Dave.Martin@arm.com, ahmed.genidi@arm.com, kevin.brodsky@arm.com, scott@os.amperecomputing.com, mbenes@suse.cz, james.clark@linaro.org, frederic@kernel.org, rafael@kernel.org, pavel@kernel.org, ryan.roberts@arm.com, suzuki.poulose@arm.com, maz@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, kvmarm@lists.linux.dev, Yeoreum Yun Subject: [PATCH v4 5/5] arm64: make the per-task SCTLR2_EL1 Date: Thu, 21 Aug 2025 18:24:08 +0100 Message-Id: <20250821172408.2101870-6-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250821172408.2101870-1-yeoreum.yun@arm.com> References: <20250821172408.2101870-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some bits in SCTLR2_EL1 that control system behavior can be configured on a per-task basis (e.g., fields related to FEAT_CPA2). To support future use of these fields, SCTLR2_EL1 is maintained per task. On platforms without FEAT_SCTLR2 support, there is no functional change and only minimal performance overhead. Signed-off-by: Yeoreum Yun --- arch/arm64/include/asm/processor.h | 3 +++ arch/arm64/kernel/process.c | 9 +++++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/pr= ocessor.h index 61d62bfd5a7b..e066116735c6 100644 --- a/arch/arm64/include/asm/processor.h +++ b/arch/arm64/include/asm/processor.h @@ -184,6 +184,7 @@ struct thread_struct { u64 mte_ctrl; #endif u64 sctlr_user; + u64 sctlr2_user; u64 svcr; u64 tpidr2_el0; u64 por_el0; @@ -258,6 +259,8 @@ static inline void task_set_sve_vl_onexec(struct task_s= truct *task, (SCTLR_ELx_ENIA | SCTLR_ELx_ENIB | SCTLR_ELx_ENDA | SCTLR_ELx_ENDB | \ SCTLR_EL1_TCF0_MASK) =20 +#define SCTLR2_USER_MASK (0) + static inline void arch_thread_struct_whitelist(unsigned long *offset, unsigned long *size) { diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 96482a1412c6..e54f192c0629 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -698,6 +698,11 @@ void update_sctlr_el1(u64 sctlr) isb(); } =20 +static void update_sctlr2_el1(u64 sctlr2) +{ + sysreg_clear_set_s(SYS_SCTLR2_EL1, SCTLR2_USER_MASK, sctlr2); +} + /* * Thread switching. */ @@ -737,6 +742,10 @@ struct task_struct *__switch_to(struct task_struct *pr= ev, if (prev->thread.sctlr_user !=3D next->thread.sctlr_user) update_sctlr_el1(next->thread.sctlr_user); =20 + if (alternative_has_cap_unlikely(ARM64_HAS_SCTLR2) && + prev->thread.sctlr2_user !=3D next->thread.sctlr2_user) + update_sctlr2_el1(next->thread.sctlr2_user); + /* the actual thread switch */ last =3D cpu_switch_to(prev, next); =20 --=20 LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}