From nobody Sat Oct 4 01:43:53 2025 Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9A8A02EC540; Thu, 21 Aug 2025 13:56:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.81 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755784577; cv=none; b=oUQAGEKuqpG+nQNO2USjNMVQzA3qwZggYk9dJR79tmEdBOt21WOgH0cpyoohKjMyiG5hTL6popN5Jz1+A25w+U+KHVjYbMF2llHkTtnLmuCNm09zqxR7wX/VbcCUlihDInOVu3wIW/al24/Htm2sX0dPyvES9xVvFBZC7lwZE4M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755784577; c=relaxed/simple; bh=phIJMcgQ6E84sL2C/Ac8Pje97s1BQGqkugomBSZrM8E=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=CjpnfIbs6h3u6+38lb80B6/gow+rI1oAK0KPeZK40/g59Y+a4rA0ESgNo1ak/sTVMxfQdp5cvv7gDjiUBOzL3EV1o8+HuNM6q72vSPZq2VW5gzHvlON4WhBuHl/WDQX1c7hN6sAT1q+EZktYt6CXHy6/W+wNk+w+WnMk8YjdfsQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=isrc.iscas.ac.cn; spf=pass smtp.mailfrom=isrc.iscas.ac.cn; arc=none smtp.client-ip=159.226.251.81 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=isrc.iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=isrc.iscas.ac.cn Received: from ROG.lan (unknown [118.251.176.166]) by APP-03 (Coremail) with SMTP id rQCowAAngIFZJadoCYkTDg--.22571S3; Thu, 21 Aug 2025 21:55:42 +0800 (CST) From: Pincheng Wang To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, anup@brainfault.org, pbonzini@redhat.com, shuah@kernel.org, cyan.yang@sifive.com, cleger@rivosinc.com, charlie@rivosinc.com, cuiyunhui@bytedance.com, samuel.holland@sifive.com, namcao@linutronix.de, jesse@rivosinc.com, inochiama@gmail.com, yongxuan.wang@sifive.com, ajones@ventanamicro.com, parri.andrea@gmail.com, mikisabate@gmail.com, yikming2222@gmail.com, thomas.weissschuh@linutronix.de Cc: linux-riscv@list.infradead.org, linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, pincheng.plct@isrc.iscas.ac.cn Subject: [PATCH 1/5] dt-bidings: riscv: add Zilsd and Zclsd extension descriptions Date: Thu, 21 Aug 2025 21:55:23 +0800 Message-Id: <20250821135527.224044-2-pincheng.plct@isrc.iscas.ac.cn> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250821135527.224044-1-pincheng.plct@isrc.iscas.ac.cn> References: <20250821135527.224044-1-pincheng.plct@isrc.iscas.ac.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: rQCowAAngIFZJadoCYkTDg--.22571S3 X-Coremail-Antispam: 1UD129KBjvJXoW7CF4ftF48uw17Ww1fCr15Jwb_yoW8tF1rpF s3GF1kKas0q3W3ur97tw4xuw15ZF1vqw45AFZFy34xKFZ0yry0qrWay3W5Z3WrCF4xAFyU ua1jgr17ZrsrAaDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUm214x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWUWVWUuwAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Jr0_JF4l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Jr0_Gr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4j6r4UJwAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Cr0_Gr1UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2ka0x kIwI1lc7CjxVAaw2AFwI0_GFv_Wryl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_ Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1V AY17CE14v26rWY6r4UJwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF 0xvE2Ix0cI8IcVCY1x0267AKxVWxJVW8Jr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMI IF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVF xhVjvjDU0xZFpf9x0JUjsj8UUUUU= X-CM-SenderInfo: pslquxhhqjh1xofwqxxvufhxpvfd2hldfou0/ Content-Type: text/plain; charset="utf-8" Add descriptions for the Zilsd (Load/Store pair instructions) and Zclsd (Compressed Load/Store pair instructions) ISA extensions which were ratified in commit f88abf1 ("Integrating load/store pair for RV32 with the main manual") of the riscv-isa-manual. Signed-off-by: Pincheng Wang --- .../devicetree/bindings/riscv/extensions.yaml | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index ede6a58ccf53..d72ffe8f6fa7 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -366,6 +366,20 @@ properties: guarantee on LR/SC sequences, as ratified in commit b1d806605f= 87 ("Updated to ratified state.") of the riscv profiles specifica= tion. =20 + - const: zilsd + description: + The standard Zilsd extension which provides support for aligned + register-pair load and store operations in 32-bit instruction + encodings, as ratified in commit f88abf1 ("Integrating + load/store pair for RV32 with the main manual") of riscv-isa-m= anual. + + - const: zclsd + description: + The Zclsd extension implements the compressed (16-bit) version= of the + Load/Store Pair for RV32. As with Zilsd, this extension was ra= tified + in commit f88abf1 ("Integrating load/store pair for RV32 with = the + main manual") of riscv-isa-manual. + - const: zk description: The standard Zk Standard Scalar cryptography extension as rati= fied @@ -847,6 +861,16 @@ properties: anyOf: - const: v - const: zve32x + # Zclsd depends on Zilsd and Zca + - if: + contains: + anyOf: + - const: zclsd + then: + contains: + anyOf: + - const: zilsd + - const: zca =20 allOf: # Zcf extension does not exist on rv64 @@ -864,6 +888,21 @@ allOf: not: contains: const: zcf + # Zilsd extension does not exist on rv64 + - if: + properties: + riscv,isa-extensions: + contains: + const: zilsd + riscv,isa-base: + contains: + const: rv64i + then: + properties: + riscv,isa-extensions: + not: + contains: + const: zilsd =20 additionalProperties: true ... --=20 2.39.5