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Thu, 21 Aug 2025 12:40:19 +0000 (GMT) From: Ravi Patel To: jesper.nilsson@axis.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, linus.walleij@linaro.org, tomasz.figa@gmail.com, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de Cc: ksk4725@coasia.com, kenkim@coasia.com, pjsin865@coasia.com, gwk1013@coasia.com, hgkim05@coasia.com, mingyoungbo@coasia.com, smn1196@coasia.com, pankaj.dubey@samsung.com, shradha.t@samsung.com, ravi.patel@samsung.com, inbaraj.e@samsung.com, swathi.ks@samsung.com, hrishikesh.d@samsung.com, dj76.yang@samsung.com, hypmean.kim@samsung.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@axis.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, soc@lists.linux.dev Subject: [PATCH v2 02/10] clk: samsung: Add clock PLL support for ARTPEC-8 SoC Date: Thu, 21 Aug 2025 18:02:46 +0530 Message-ID: <20250821123310.94089-3-ravi.patel@samsung.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250821123310.94089-1-ravi.patel@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250821124024epcas5p349dda3c9e0523cc07acf2889476beeb1 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250821124024epcas5p349dda3c9e0523cc07acf2889476beeb1 References: <20250710002047.1573841-1-ksk4725@coasia.com> <20250821123310.94089-1-ravi.patel@samsung.com> From: Hakyeong Kim Add below clock PLL support for Axis ARTPEC-8 SoC platform: - pll_1017x: Integer PLL with mid frequency FVCO (950 to 2400 MHz) This is used in ARTPEC-8 SoC for shared PLL - pll_1031x: Integer/Fractional PLL with mid frequency FVCO (600 to 1200 MHz) This is used in ARTPEC-8 SoC for Audio PLL FOUT calculation for pll_1017x and pll_1031x: FOUT =3D (MDIV x FIN)/(PDIV x 2^SDIV) for integer PLL FOUT =3D (((MDIV + KDIV)/65536) x FIN)/(PDIV x 2^SDIV) for fractional PLL Signed-off-by: Hakyeong Kim Signed-off-by: SeonGu Kang Signed-off-by: Ravi Patel --- drivers/clk/samsung/clk-pll.c | 128 +++++++++++++++++++++++++++++++++- drivers/clk/samsung/clk-pll.h | 2 + 2 files changed, 129 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index fe8abe442c51..614063396e23 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -273,7 +273,7 @@ static int samsung_pll35xx_set_rate(struct clk_hw *hw, = unsigned long drate, } =20 /* Set PLL lock time. */ - if (pll->type =3D=3D pll_142xx) + if (pll->type =3D=3D pll_142xx || pll->type =3D=3D pll_1017x) writel_relaxed(rate->pdiv * PLL142XX_LOCK_FACTOR, pll->lock_reg); else @@ -1325,6 +1325,125 @@ static const struct clk_ops samsung_pll531x_clk_ops= =3D { .recalc_rate =3D samsung_pll531x_recalc_rate, }; =20 +/* + * PLL1031x Clock Type + */ +#define PLL1031X_LOCK_FACTOR (500) + +#define PLL1031X_MDIV_MASK (0x3ff) +#define PLL1031X_PDIV_MASK (0x3f) +#define PLL1031X_SDIV_MASK (0x7) +#define PLL1031X_MDIV_SHIFT (16) +#define PLL1031X_PDIV_SHIFT (8) +#define PLL1031X_SDIV_SHIFT (0) + +#define PLL1031X_KDIV_MASK (0xffff) +#define PLL1031X_KDIV_SHIFT (0) +#define PLL1031X_MFR_MASK (0x3f) +#define PLL1031X_MRR_MASK (0x1f) +#define PLL1031X_MFR_SHIFT (16) +#define PLL1031X_MRR_SHIFT (24) + +static unsigned long samsung_pll1031x_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct samsung_clk_pll *pll =3D to_clk_pll(hw); + u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con3; + u64 fvco =3D parent_rate; + + pll_con0 =3D readl_relaxed(pll->con_reg); + pll_con3 =3D readl_relaxed(pll->con_reg + 0xc); + mdiv =3D (pll_con0 >> PLL1031X_MDIV_SHIFT) & PLL1031X_MDIV_MASK; + pdiv =3D (pll_con0 >> PLL1031X_PDIV_SHIFT) & PLL1031X_PDIV_MASK; + sdiv =3D (pll_con0 >> PLL1031X_SDIV_SHIFT) & PLL1031X_SDIV_MASK; + kdiv =3D (pll_con3 & PLL1031X_KDIV_MASK); + + fvco *=3D (mdiv << PLL1031X_MDIV_SHIFT) + kdiv; + do_div(fvco, (pdiv << sdiv)); + fvco >>=3D PLL1031X_MDIV_SHIFT; + + return (unsigned long)fvco; +} + +static bool samsung_pll1031x_mpk_change(u32 pll_con0, u32 pll_con3, + const struct samsung_pll_rate_table *rate) +{ + u32 old_mdiv, old_pdiv, old_kdiv; + + old_mdiv =3D (pll_con0 >> PLL1031X_MDIV_SHIFT) & PLL1031X_MDIV_MASK; + old_pdiv =3D (pll_con0 >> PLL1031X_PDIV_SHIFT) & PLL1031X_PDIV_MASK; + old_kdiv =3D (pll_con3 >> PLL1031X_KDIV_SHIFT) & PLL1031X_KDIV_MASK; + + return (old_mdiv !=3D rate->mdiv || old_pdiv !=3D rate->pdiv || + old_kdiv !=3D rate->kdiv); +} + +static int samsung_pll1031x_set_rate(struct clk_hw *hw, unsigned long drat= e, + unsigned long prate) +{ + struct samsung_clk_pll *pll =3D to_clk_pll(hw); + const struct samsung_pll_rate_table *rate; + u32 con0, con3; + + /* Get required rate settings from table */ + rate =3D samsung_get_pll_settings(pll, drate); + if (!rate) { + pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__, + drate, clk_hw_get_name(hw)); + return -EINVAL; + } + + con0 =3D readl_relaxed(pll->con_reg); + con3 =3D readl_relaxed(pll->con_reg + 0xc); + + if (!(samsung_pll1031x_mpk_change(con0, con3, rate))) { + /* If only s change, change just s value only */ + con0 &=3D ~(PLL1031X_SDIV_MASK << PLL1031X_SDIV_SHIFT); + con0 |=3D rate->sdiv << PLL1031X_SDIV_SHIFT; + writel_relaxed(con0, pll->con_reg); + + return 0; + } + + /* Set PLL lock time. */ + writel_relaxed(rate->pdiv * PLL1031X_LOCK_FACTOR, pll->lock_reg); + + /* Set PLL M, P, and S values. */ + con0 &=3D ~((PLL1031X_MDIV_MASK << PLL1031X_MDIV_SHIFT) | + (PLL1031X_PDIV_MASK << PLL1031X_PDIV_SHIFT) | + (PLL1031X_SDIV_MASK << PLL1031X_SDIV_SHIFT)); + + con0 |=3D (rate->mdiv << PLL1031X_MDIV_SHIFT) | + (rate->pdiv << PLL1031X_PDIV_SHIFT) | + (rate->sdiv << PLL1031X_SDIV_SHIFT); + + /* Set PLL K, MFR and MRR values. */ + con3 =3D readl_relaxed(pll->con_reg + 0xc); + con3 &=3D ~((PLL1031X_KDIV_MASK << PLL1031X_KDIV_SHIFT) | + (PLL1031X_MFR_MASK << PLL1031X_MFR_SHIFT) | + (PLL1031X_MRR_MASK << PLL1031X_MRR_SHIFT)); + con3 |=3D (rate->kdiv << PLL1031X_KDIV_SHIFT) | + (rate->mfr << PLL1031X_MFR_SHIFT) | + (rate->mrr << PLL1031X_MRR_SHIFT); + + /* Write configuration to PLL */ + writel_relaxed(con0, pll->con_reg); + writel_relaxed(con3, pll->con_reg + 0xc); + + /* Wait for PLL lock if the PLL is enabled */ + return samsung_pll_lock_wait(pll, BIT(pll->lock_offs)); +} + +static const struct clk_ops samsung_pll1031x_clk_ops =3D { + .recalc_rate =3D samsung_pll1031x_recalc_rate, + .round_rate =3D samsung_pll_round_rate, + .set_rate =3D samsung_pll1031x_set_rate, +}; + +static const struct clk_ops samsung_pll1031x_clk_min_ops =3D { + .recalc_rate =3D samsung_pll1031x_recalc_rate, +}; + static void __init _samsung_clk_register_pll(struct samsung_clk_provider *= ctx, const struct samsung_pll_clock *pll_clk) { @@ -1373,6 +1492,7 @@ static void __init _samsung_clk_register_pll(struct s= amsung_clk_provider *ctx, case pll_1451x: case pll_1452x: case pll_142xx: + case pll_1017x: pll->enable_offs =3D PLL35XX_ENABLE_SHIFT; pll->lock_offs =3D PLL35XX_LOCK_STAT_SHIFT; if (!pll->rate_table) @@ -1468,6 +1588,12 @@ static void __init _samsung_clk_register_pll(struct = samsung_clk_provider *ctx, case pll_4311: init.ops =3D &samsung_pll531x_clk_ops; break; + case pll_1031x: + if (!pll->rate_table) + init.ops =3D &samsung_pll1031x_clk_min_ops; + else + init.ops =3D &samsung_pll1031x_clk_ops; + break; default: pr_warn("%s: Unknown pll type for pll clk %s\n", __func__, pll_clk->name); diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index e9a5f8e0e0a3..6c8bb7f26da5 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -49,6 +49,8 @@ enum samsung_pll_type { pll_0718x, pll_0732x, pll_4311, + pll_1017x, + pll_1031x, }; =20 #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \ --=20 2.49.0